[deliverable/linux.git] / drivers / irqchip / irq-gic-v2m.c

/*
 * ARM GIC v2m MSI(-X) support
 * Support for Message Signaled Interrupts for systems that
 * implement ARM Generic Interrupt Controller: GICv2m.
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 *	    Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
 *	    Brandon Anderson <brandon.anderson@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#define pr_fmt(fmt) "GICv2m: " fmt

#include <linux/acpi.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irqchip/arm-gic.h>

/*
* MSI_TYPER:
*     [31:26] Reserved
*     [25:16] lowest SPI assigned to MSI
*     [15:10] Reserved
*     [9:0]   Numer of SPIs assigned to MSI
*/
#define V2M_MSI_TYPER		       0x008
#define V2M_MSI_TYPER_BASE_SHIFT       16
#define V2M_MSI_TYPER_BASE_MASK	       0x3FF
#define V2M_MSI_TYPER_NUM_MASK	       0x3FF
#define V2M_MSI_SETSPI_NS	       0x040
#define V2M_MIN_SPI		       32
#define V2M_MAX_SPI		       1019
#define V2M_MSI_IIDR		       0xFCC

#define V2M_MSI_TYPER_BASE_SPI(x)      \
	       (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)

#define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)

/* APM X-Gene with GICv2m MSI_IIDR register value */
#define XGENE_GICV2M_MSI_IIDR		0x06000170

/* Broadcom NS2 GICv2m MSI_IIDR register value */
#define BCM_NS2_GICV2M_MSI_IIDR		0x0000013f

/* List of flags for specific v2m implementation */
#define GICV2M_NEEDS_SPI_OFFSET		0x00000001

static LIST_HEAD(v2m_nodes);
static DEFINE_SPINLOCK(v2m_lock);

struct v2m_data {
	struct list_head entry;
	struct fwnode_handle *fwnode;
	struct resource res;	/* GICv2m resource */
	void __iomem *base;	/* GICv2m virt address */
	u32 spi_start;		/* The SPI number that MSIs start */
	u32 nr_spis;		/* The number of SPIs for MSIs */
	u32 spi_offset;		/* offset to be subtracted from SPI number */
	unsigned long *bm;	/* MSI vector bitmap */
	u32 flags;		/* v2m flags for specific implementation */
};

static void gicv2m_mask_msi_irq(struct irq_data *d)
{
	pci_msi_mask_irq(d);
	irq_chip_mask_parent(d);
}

static void gicv2m_unmask_msi_irq(struct irq_data *d)
{
	pci_msi_unmask_irq(d);
	irq_chip_unmask_parent(d);
}

static struct irq_chip gicv2m_msi_irq_chip = {
	.name			= "MSI",
	.irq_mask		= gicv2m_mask_msi_irq,
	.irq_unmask		= gicv2m_unmask_msi_irq,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
};

static struct msi_domain_info gicv2m_msi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
		   MSI_FLAG_PCI_MSIX),
	.chip	= &gicv2m_msi_irq_chip,
};

static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;

	msg->address_hi = upper_32_bits(addr);
	msg->address_lo = lower_32_bits(addr);
	msg->data = data->hwirq;

	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
		msg->data -= v2m->spi_offset;
}

static struct irq_chip gicv2m_irq_chip = {
	.name			= "GICv2m",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
	.irq_compose_msi_msg	= gicv2m_compose_msi_msg,
};

static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
				       unsigned int virq,
				       irq_hw_number_t hwirq)
{
	struct irq_fwspec fwspec;
	struct irq_data *d;
	int err;

	if (is_of_node(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 3;
		fwspec.param[0] = 0;
		fwspec.param[1] = hwirq - 32;
		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 2;
		fwspec.param[0] = hwirq;
		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
	} else {
		return -EINVAL;
	}

	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
	if (err)
		return err;

	/* Configure the interrupt line to be edge */
	d = irq_domain_get_irq_data(domain->parent, virq);
	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	return 0;
}

static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
{
	int pos;

	pos = hwirq - v2m->spi_start;
	if (pos < 0 || pos >= v2m->nr_spis) {
		pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
		return;
	}

	spin_lock(&v2m_lock);
	__clear_bit(pos, v2m->bm);
	spin_unlock(&v2m_lock);
}

static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *args)
{
	struct v2m_data *v2m = NULL, *tmp;
	int hwirq, offset, err = 0;

	spin_lock(&v2m_lock);
	list_for_each_entry(tmp, &v2m_nodes, entry) {
		offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
		if (offset < tmp->nr_spis) {
			__set_bit(offset, tmp->bm);
			v2m = tmp;
			break;
		}
	}
	spin_unlock(&v2m_lock);

	if (!v2m)
		return -ENOSPC;

	hwirq = v2m->spi_start + offset;

	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
	if (err) {
		gicv2m_unalloc_msi(v2m, hwirq);
		return err;
	}

	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
				      &gicv2m_irq_chip, v2m);

	return 0;
}

static void gicv2m_irq_domain_free(struct irq_domain *domain,
				   unsigned int virq, unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);

	BUG_ON(nr_irqs != 1);
	gicv2m_unalloc_msi(v2m, d->hwirq);
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops gicv2m_domain_ops = {
	.alloc			= gicv2m_irq_domain_alloc,
	.free			= gicv2m_irq_domain_free,
};

static bool is_msi_spi_valid(u32 base, u32 num)
{
	if (base < V2M_MIN_SPI) {
		pr_err("Invalid MSI base SPI (base:%u)\n", base);
		return false;
	}

	if ((num == 0) || (base + num > V2M_MAX_SPI)) {
		pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
		return false;
	}

	return true;
}

static struct irq_chip gicv2m_pmsi_irq_chip = {
	.name			= "pMSI",
};

static struct msi_domain_ops gicv2m_pmsi_ops = {
};

static struct msi_domain_info gicv2m_pmsi_domain_info = {
	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
	.ops	= &gicv2m_pmsi_ops,
	.chip	= &gicv2m_pmsi_irq_chip,
};

static void gicv2m_teardown(void)
{
	struct v2m_data *v2m, *tmp;

	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
		list_del(&v2m->entry);
		kfree(v2m->bm);
		iounmap(v2m->base);
		of_node_put(to_of_node(v2m->fwnode));
		if (is_fwnode_irqchip(v2m->fwnode))
			irq_domain_free_fwnode(v2m->fwnode);
		kfree(v2m);
	}
}

static int gicv2m_allocate_domains(struct irq_domain *parent)
{
	struct irq_domain *inner_domain, *pci_domain, *plat_domain;
	struct v2m_data *v2m;

	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!v2m)
		return 0;

	inner_domain = irq_domain_create_tree(v2m->fwnode,
					      &gicv2m_domain_ops, v2m);
	if (!inner_domain) {
		pr_err("Failed to create GICv2m domain\n");
		return -ENOMEM;
	}

	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	inner_domain->parent = parent;
	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
					       &gicv2m_msi_domain_info,
					       inner_domain);
	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
						     &gicv2m_pmsi_domain_info,
						     inner_domain);
	if (!pci_domain || !plat_domain) {
		pr_err("Failed to create MSI domains\n");
		if (plat_domain)
			irq_domain_remove(plat_domain);
		if (pci_domain)
			irq_domain_remove(pci_domain);
		irq_domain_remove(inner_domain);
		return -ENOMEM;
	}

	return 0;
}

static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
				  u32 spi_start, u32 nr_spis,
				  struct resource *res)
{
	int ret;
	struct v2m_data *v2m;

	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	if (!v2m) {
		pr_err("Failed to allocate struct v2m_data.\n");
		return -ENOMEM;
	}

	INIT_LIST_HEAD(&v2m->entry);
	v2m->fwnode = fwnode;

	memcpy(&v2m->res, res, sizeof(struct resource));

	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	if (!v2m->base) {
		pr_err("Failed to map GICv2m resource\n");
		ret = -ENOMEM;
		goto err_free_v2m;
	}

	if (spi_start && nr_spis) {
		v2m->spi_start = spi_start;
		v2m->nr_spis = nr_spis;
	} else {
		u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);

		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	}

	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
		ret = -EINVAL;
		goto err_iounmap;
	}

	/*
	 * APM X-Gene GICv2m implementation has an erratum where
	 * the MSI data needs to be the offset from the spi_start
	 * in order to trigger the correct MSI interrupt. This is
	 * different from the standard GICv2m implementation where
	 * the MSI data is the absolute value within the range from
	 * spi_start to (spi_start + num_spis).
	 *
	 * Broadom NS2 GICv2m implementation has an erratum where the MSI data
	 * is 'spi_number - 32'
	 */
	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
	case XGENE_GICV2M_MSI_IIDR:
		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
		v2m->spi_offset = v2m->spi_start;
		break;
	case BCM_NS2_GICV2M_MSI_IIDR:
		v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
		v2m->spi_offset = 32;
		break;
	}

	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
			  GFP_KERNEL);
	if (!v2m->bm) {
		ret = -ENOMEM;
		goto err_iounmap;
	}

	list_add_tail(&v2m->entry, &v2m_nodes);

	pr_info("range%pR, SPI[%d:%d]\n", res,
		v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
	return 0;

err_iounmap:
	iounmap(v2m->base);
err_free_v2m:
	kfree(v2m);
	return ret;
}

static struct of_device_id gicv2m_device_id[] = {
	{	.compatible	= "arm,gic-v2m-frame",	},
	{},
};

static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
				 struct irq_domain *parent)
{
	int ret = 0;
	struct device_node *node = to_of_node(parent_handle);
	struct device_node *child;

	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	     child = of_find_matching_node(child, gicv2m_device_id)) {
		u32 spi_start = 0, nr_spis = 0;
		struct resource res;

		if (!of_find_property(child, "msi-controller", NULL))
			continue;

		ret = of_address_to_resource(child, 0, &res);
		if (ret) {
			pr_err("Failed to allocate v2m resource.\n");
			break;
		}

		if (!of_property_read_u32(child, "arm,msi-base-spi",
					  &spi_start) &&
		    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
				spi_start, nr_spis);

		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
		if (ret) {
			of_node_put(child);
			break;
		}
	}

	if (!ret)
		ret = gicv2m_allocate_domains(parent);
	if (ret)
		gicv2m_teardown();
	return ret;
}

#ifdef CONFIG_ACPI
static int acpi_num_msi;

static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
{
	struct v2m_data *data;

	if (WARN_ON(acpi_num_msi <= 0))
		return NULL;

	/* We only return the fwnode of the first MSI frame. */
	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	if (!data)
		return NULL;

	return data->fwnode;
}

static int __init
acpi_parse_madt_msi(struct acpi_subtable_header *header,
		    const unsigned long end)
{
	int ret;
	struct resource res;
	u32 spi_start = 0, nr_spis = 0;
	struct acpi_madt_generic_msi_frame *m;
	struct fwnode_handle *fwnode;

	m = (struct acpi_madt_generic_msi_frame *)header;
	if (BAD_MADT_ENTRY(m, end))
		return -EINVAL;

	res.start = m->base_address;
	res.end = m->base_address + SZ_4K - 1;
	res.flags = IORESOURCE_MEM;

	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
		spi_start = m->spi_base;
		nr_spis = m->spi_count;

		pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
			spi_start, nr_spis);
	}

	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	if (!fwnode) {
		pr_err("Unable to allocate GICv2m domain token\n");
		return -EINVAL;
	}

	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	if (ret)
		irq_domain_free_fwnode(fwnode);

	return ret;
}

static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	int ret;

	if (acpi_num_msi > 0)
		return 0;

	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
				      acpi_parse_madt_msi, 0);

	if (acpi_num_msi <= 0)
		goto err_out;

	ret = gicv2m_allocate_domains(parent);
	if (ret)
		goto err_out;

	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);

	return 0;

err_out:
	gicv2m_teardown();
	return -EINVAL;
}
#else /* CONFIG_ACPI */
static int __init gicv2m_acpi_init(struct irq_domain *parent)
{
	return -EINVAL;
}
#endif /* CONFIG_ACPI */

int __init gicv2m_init(struct fwnode_handle *parent_handle,
		       struct irq_domain *parent)
{
	if (is_of_node(parent_handle))
		return gicv2m_of_init(parent_handle, parent);

	return gicv2m_acpi_init(parent);
}
Commit	Line	Data
853a33ce SS	1	/*
	2	* ARM GIC v2m MSI(-X) support
	3	* Support for Message Signaled Interrupts for systems that
	4	* implement ARM Generic Interrupt Controller: GICv2m.
	5	*
	6	* Copyright (C) 2014 Advanced Micro Devices, Inc.
	7	* Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
	8	* Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
	9	* Brandon Anderson <brandon.anderson@amd.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published
	13	* by the Free Software Foundation.
	14	*/
	15
	16	#define pr_fmt(fmt) "GICv2m: " fmt
	17
0644b3da	18	#include <linux/acpi.h>
853a33ce SS	19	#include <linux/irq.h>
	20	#include <linux/irqdomain.h>
	21	#include <linux/kernel.h>
0644b3da	22	#include <linux/msi.h>
853a33ce SS	23	#include <linux/of_address.h>
	24	#include <linux/of_pci.h>
	25	#include <linux/slab.h>
	26	#include <linux/spinlock.h>
7c034f16	27	#include <linux/irqchip/arm-gic.h>
853a33ce SS	28
	29	/*
	30	* MSI_TYPER:
	31	* [31:26] Reserved
	32	* [25:16] lowest SPI assigned to MSI
	33	* [15:10] Reserved
	34	* [9:0] Numer of SPIs assigned to MSI
	35	*/
	36	#define V2M_MSI_TYPER 0x008
	37	#define V2M_MSI_TYPER_BASE_SHIFT 16
	38	#define V2M_MSI_TYPER_BASE_MASK 0x3FF
	39	#define V2M_MSI_TYPER_NUM_MASK 0x3FF
	40	#define V2M_MSI_SETSPI_NS 0x040
	41	#define V2M_MIN_SPI 32
	42	#define V2M_MAX_SPI 1019
ee5f7d64	43	#define V2M_MSI_IIDR 0xFCC
853a33ce SS	44
	45	#define V2M_MSI_TYPER_BASE_SPI(x) \
	46	(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
	47
	48	#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
	49
ee5f7d64 DD	50	/* APM X-Gene with GICv2m MSI_IIDR register value */
	51	#define XGENE_GICV2M_MSI_IIDR 0x06000170
	52
74c967aa RJ	53	/* Broadcom NS2 GICv2m MSI_IIDR register value */
	54	#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
	55
ee5f7d64 DD	56	/* List of flags for specific v2m implementation */
	57	#define GICV2M_NEEDS_SPI_OFFSET 0x00000001
	58
a71225e2 MZ	59	static LIST_HEAD(v2m_nodes);
	60	static DEFINE_SPINLOCK(v2m_lock);
	61
853a33ce	62	struct v2m_data {
a71225e2	63	struct list_head entry;
4266ab1a	64	struct fwnode_handle *fwnode;
853a33ce SS	65	struct resource res; /* GICv2m resource */
	66	void __iomem base; / GICv2m virt address */
	67	u32 spi_start; /* The SPI number that MSIs start */
	68	u32 nr_spis; /* The number of SPIs for MSIs */
74c967aa	69	u32 spi_offset; /* offset to be subtracted from SPI number */
853a33ce	70	unsigned long bm; / MSI vector bitmap */
ee5f7d64	71	u32 flags; /* v2m flags for specific implementation */
853a33ce SS	72	};
	73
	74	static void gicv2m_mask_msi_irq(struct irq_data *d)
	75	{
	76	pci_msi_mask_irq(d);
	77	irq_chip_mask_parent(d);
	78	}
	79
	80	static void gicv2m_unmask_msi_irq(struct irq_data *d)
	81	{
	82	pci_msi_unmask_irq(d);
	83	irq_chip_unmask_parent(d);
	84	}
	85
	86	static struct irq_chip gicv2m_msi_irq_chip = {
	87	.name = "MSI",
	88	.irq_mask = gicv2m_mask_msi_irq,
	89	.irq_unmask = gicv2m_unmask_msi_irq,
	90	.irq_eoi = irq_chip_eoi_parent,
	91	.irq_write_msi_msg = pci_msi_domain_write_msg,
	92	};
	93
	94	static struct msi_domain_info gicv2m_msi_domain_info = {
	95	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	96	MSI_FLAG_PCI_MSIX),
	97	.chip = &gicv2m_msi_irq_chip,
	98	};
	99
853a33ce SS	100	static void gicv2m_compose_msi_msg(struct irq_data data, struct msi_msg msg)
	101	{
	102	struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
	103	phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS;
	104
157add60 PF	105	msg->address_hi = upper_32_bits(addr);
157add60 PF	106	msg->address_lo = lower_32_bits(addr);
853a33ce	107	msg->data = data->hwirq;
ee5f7d64 DD	108
ee5f7d64 DD	109	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
74c967aa	110	msg->data -= v2m->spi_offset;
853a33ce SS	111	}
	112
	113	static struct irq_chip gicv2m_irq_chip = {
	114	.name = "GICv2m",
	115	.irq_mask = irq_chip_mask_parent,
	116	.irq_unmask = irq_chip_unmask_parent,
	117	.irq_eoi = irq_chip_eoi_parent,
0407dace	118	.irq_set_affinity = irq_chip_set_affinity_parent,
853a33ce SS	119	.irq_compose_msi_msg = gicv2m_compose_msi_msg,
	120	};
	121
	122	static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
	123	unsigned int virq,
	124	irq_hw_number_t hwirq)
	125	{
f833f57f	126	struct irq_fwspec fwspec;
853a33ce SS	127	struct irq_data *d;
	128	int err;
	129
f833f57f MZ	130	if (is_of_node(domain->parent->fwnode)) {
	131	fwspec.fwnode = domain->parent->fwnode;
	132	fwspec.param_count = 3;
	133	fwspec.param[0] = 0;
	134	fwspec.param[1] = hwirq - 32;
	135	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0644b3da SS	136	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
	137	fwspec.fwnode = domain->parent->fwnode;
	138	fwspec.param_count = 2;
	139	fwspec.param[0] = hwirq;
	140	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
f833f57f MZ	141	} else {
	142	return -EINVAL;
	143	}
853a33ce	144
f833f57f	145	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
853a33ce SS	146	if (err)
	147	return err;
	148
	149	/* Configure the interrupt line to be edge */
	150	d = irq_domain_get_irq_data(domain->parent, virq);
	151	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
	152	return 0;
	153	}
	154
	155	static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
	156	{
	157	int pos;
	158
	159	pos = hwirq - v2m->spi_start;
	160	if (pos < 0 \|\| pos >= v2m->nr_spis) {
	161	pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
	162	return;
	163	}
	164
a71225e2	165	spin_lock(&v2m_lock);
853a33ce	166	__clear_bit(pos, v2m->bm);
a71225e2	167	spin_unlock(&v2m_lock);
853a33ce SS	168	}
	169
	170	static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	171	unsigned int nr_irqs, void *args)
	172	{
a71225e2	173	struct v2m_data v2m = NULL, tmp;
853a33ce SS	174	int hwirq, offset, err = 0;
853a33ce SS	175
a71225e2 MZ	176	spin_lock(&v2m_lock);
	177	list_for_each_entry(tmp, &v2m_nodes, entry) {
	178	offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
	179	if (offset < tmp->nr_spis) {
	180	__set_bit(offset, tmp->bm);
	181	v2m = tmp;
	182	break;
	183	}
	184	}
	185	spin_unlock(&v2m_lock);
853a33ce	186
a71225e2 MZ	187	if (!v2m)
a71225e2 MZ	188	return -ENOSPC;
853a33ce SS	189
	190	hwirq = v2m->spi_start + offset;
	191
	192	err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
	193	if (err) {
	194	gicv2m_unalloc_msi(v2m, hwirq);
	195	return err;
	196	}
	197
	198	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
	199	&gicv2m_irq_chip, v2m);
	200
	201	return 0;
	202	}
	203
	204	static void gicv2m_irq_domain_free(struct irq_domain *domain,
	205	unsigned int virq, unsigned int nr_irqs)
	206	{
	207	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	208	struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
	209
	210	BUG_ON(nr_irqs != 1);
	211	gicv2m_unalloc_msi(v2m, d->hwirq);
	212	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
	213	}
	214
	215	static const struct irq_domain_ops gicv2m_domain_ops = {
	216	.alloc = gicv2m_irq_domain_alloc,
	217	.free = gicv2m_irq_domain_free,
	218	};
	219
	220	static bool is_msi_spi_valid(u32 base, u32 num)
	221	{
	222	if (base < V2M_MIN_SPI) {
	223	pr_err("Invalid MSI base SPI (base:%u)\n", base);
	224	return false;
	225	}
	226
	227	if ((num == 0) \|\| (base + num > V2M_MAX_SPI)) {
	228	pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
	229	num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
	230	return false;
	231	}
	232
	233	return true;
	234	}
	235
ef50645a MZ	236	static struct irq_chip gicv2m_pmsi_irq_chip = {
	237	.name = "pMSI",
	238	};
	239
	240	static struct msi_domain_ops gicv2m_pmsi_ops = {
	241	};
	242
	243	static struct msi_domain_info gicv2m_pmsi_domain_info = {
	244	.flags = (MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS),
	245	.ops = &gicv2m_pmsi_ops,
	246	.chip = &gicv2m_pmsi_irq_chip,
	247	};
	248
a71225e2 MZ	249	static void gicv2m_teardown(void)
	250	{
	251	struct v2m_data v2m, tmp;
	252
	253	list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
	254	list_del(&v2m->entry);
	255	kfree(v2m->bm);
	256	iounmap(v2m->base);
4266ab1a	257	of_node_put(to_of_node(v2m->fwnode));
0644b3da SS	258	if (is_fwnode_irqchip(v2m->fwnode))
0644b3da SS	259	irq_domain_free_fwnode(v2m->fwnode);
a71225e2 MZ	260	kfree(v2m);
	261	}
	262	}
	263
	264	static int gicv2m_allocate_domains(struct irq_domain *parent)
	265	{
	266	struct irq_domain inner_domain, pci_domain, *plat_domain;
	267	struct v2m_data *v2m;
	268
	269	v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	270	if (!v2m)
	271	return 0;
	272
4266ab1a	273	inner_domain = irq_domain_create_tree(v2m->fwnode,
a71225e2 MZ	274	&gicv2m_domain_ops, v2m);
	275	if (!inner_domain) {
	276	pr_err("Failed to create GICv2m domain\n");
	277	return -ENOMEM;
	278	}
	279
	280	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
	281	inner_domain->parent = parent;
4266ab1a	282	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	283	&gicv2m_msi_domain_info,
a71225e2 MZ	284	inner_domain);
4266ab1a	285	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
a71225e2 MZ	286	&gicv2m_pmsi_domain_info,
	287	inner_domain);
	288	if (!pci_domain \|\| !plat_domain) {
	289	pr_err("Failed to create MSI domains\n");
	290	if (plat_domain)
	291	irq_domain_remove(plat_domain);
	292	if (pci_domain)
	293	irq_domain_remove(pci_domain);
	294	irq_domain_remove(inner_domain);
	295	return -ENOMEM;
	296	}
	297
	298	return 0;
	299	}
	300
4266ab1a SS	301	static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
	302	u32 spi_start, u32 nr_spis,
	303	struct resource *res)
853a33ce SS	304	{
	305	int ret;
	306	struct v2m_data *v2m;
	307
	308	v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
	309	if (!v2m) {
	310	pr_err("Failed to allocate struct v2m_data.\n");
	311	return -ENOMEM;
	312	}
	313
a71225e2	314	INIT_LIST_HEAD(&v2m->entry);
4266ab1a	315	v2m->fwnode = fwnode;
a71225e2	316
4266ab1a	317	memcpy(&v2m->res, res, sizeof(struct resource));
853a33ce SS	318
	319	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
	320	if (!v2m->base) {
	321	pr_err("Failed to map GICv2m resource\n");
	322	ret = -ENOMEM;
	323	goto err_free_v2m;
	324	}
	325
4266ab1a SS	326	if (spi_start && nr_spis) {
	327	v2m->spi_start = spi_start;
	328	v2m->nr_spis = nr_spis;
853a33ce SS	329	} else {
	330	u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
	331
	332	v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
	333	v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
	334	}
	335
	336	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
	337	ret = -EINVAL;
	338	goto err_iounmap;
	339	}
	340
ee5f7d64 DD	341	/*
	342	* APM X-Gene GICv2m implementation has an erratum where
	343	* the MSI data needs to be the offset from the spi_start
	344	* in order to trigger the correct MSI interrupt. This is
	345	* different from the standard GICv2m implementation where
	346	* the MSI data is the absolute value within the range from
	347	* spi_start to (spi_start + num_spis).
74c967aa RJ	348	*
	349	* Broadom NS2 GICv2m implementation has an erratum where the MSI data
	350	* is 'spi_number - 32'
ee5f7d64	351	*/
74c967aa RJ	352	switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
	353	case XGENE_GICV2M_MSI_IIDR:
	354	v2m->flags \|= GICV2M_NEEDS_SPI_OFFSET;
	355	v2m->spi_offset = v2m->spi_start;
	356	break;
	357	case BCM_NS2_GICV2M_MSI_IIDR:
ee5f7d64	358	v2m->flags \|= GICV2M_NEEDS_SPI_OFFSET;
74c967aa RJ	359	v2m->spi_offset = 32;
	360	break;
	361	}
ee5f7d64	362
853a33ce SS	363	v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis),
	364	GFP_KERNEL);
	365	if (!v2m->bm) {
	366	ret = -ENOMEM;
	367	goto err_iounmap;
	368	}
	369
a71225e2	370	list_add_tail(&v2m->entry, &v2m_nodes);
853a33ce	371
5a1ff480 SS	372	pr_info("range%pR, SPI[%d:%d]\n", res,
5a1ff480 SS	373	v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
853a33ce SS	374	return 0;
853a33ce SS	375
853a33ce SS	376	err_iounmap:
	377	iounmap(v2m->base);
	378	err_free_v2m:
	379	kfree(v2m);
	380	return ret;
	381	}
	382
	383	static struct of_device_id gicv2m_device_id[] = {
	384	{ .compatible = "arm,gic-v2m-frame", },
	385	{},
	386	};
	387
0644b3da SS	388	static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
0644b3da SS	389	struct irq_domain *parent)
853a33ce SS	390	{
853a33ce SS	391	int ret = 0;
0644b3da	392	struct device_node *node = to_of_node(parent_handle);
853a33ce SS	393	struct device_node *child;
	394
	395	for (child = of_find_matching_node(node, gicv2m_device_id); child;
	396	child = of_find_matching_node(child, gicv2m_device_id)) {
4266ab1a SS	397	u32 spi_start = 0, nr_spis = 0;
	398	struct resource res;
	399
853a33ce SS	400	if (!of_find_property(child, "msi-controller", NULL))
	401	continue;
	402
4266ab1a SS	403	ret = of_address_to_resource(child, 0, &res);
	404	if (ret) {
	405	pr_err("Failed to allocate v2m resource.\n");
	406	break;
	407	}
	408
	409	if (!of_property_read_u32(child, "arm,msi-base-spi",
	410	&spi_start) &&
	411	!of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
	412	pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	413	spi_start, nr_spis);
	414
	415	ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
853a33ce	416	if (ret) {
86d14c72	417	of_node_put(child);
853a33ce SS	418	break;
	419	}
	420	}
	421
a71225e2 MZ	422	if (!ret)
	423	ret = gicv2m_allocate_domains(parent);
	424	if (ret)
	425	gicv2m_teardown();
853a33ce SS	426	return ret;
853a33ce SS	427	}
0644b3da SS	428
	429	#ifdef CONFIG_ACPI
	430	static int acpi_num_msi;
	431
	432	static struct fwnode_handle gicv2m_get_fwnode(struct device dev)
	433	{
	434	struct v2m_data *data;
	435
	436	if (WARN_ON(acpi_num_msi <= 0))
	437	return NULL;
	438
	439	/* We only return the fwnode of the first MSI frame. */
	440	data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
	441	if (!data)
	442	return NULL;
	443
	444	return data->fwnode;
	445	}
	446
	447	static int __init
	448	acpi_parse_madt_msi(struct acpi_subtable_header *header,
	449	const unsigned long end)
	450	{
	451	int ret;
	452	struct resource res;
	453	u32 spi_start = 0, nr_spis = 0;
	454	struct acpi_madt_generic_msi_frame *m;
	455	struct fwnode_handle *fwnode;
	456
	457	m = (struct acpi_madt_generic_msi_frame *)header;
	458	if (BAD_MADT_ENTRY(m, end))
	459	return -EINVAL;
	460
	461	res.start = m->base_address;
5a1ff480 SS	462	res.end = m->base_address + SZ_4K - 1;
5a1ff480 SS	463	res.flags = IORESOURCE_MEM;
0644b3da SS	464
	465	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
	466	spi_start = m->spi_base;
	467	nr_spis = m->spi_count;
	468
	469	pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
	470	spi_start, nr_spis);
	471	}
	472
	473	fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
	474	if (!fwnode) {
	475	pr_err("Unable to allocate GICv2m domain token\n");
	476	return -EINVAL;
	477	}
	478
	479	ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
	480	if (ret)
	481	irq_domain_free_fwnode(fwnode);
	482
	483	return ret;
	484	}
	485
	486	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	487	{
	488	int ret;
	489
	490	if (acpi_num_msi > 0)
	491	return 0;
	492
	493	acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
	494	acpi_parse_madt_msi, 0);
	495
	496	if (acpi_num_msi <= 0)
	497	goto err_out;
	498
	499	ret = gicv2m_allocate_domains(parent);
	500	if (ret)
	501	goto err_out;
	502
	503	pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
	504
	505	return 0;
	506
	507	err_out:
	508	gicv2m_teardown();
	509	return -EINVAL;
	510	}
	511	#else /* CONFIG_ACPI */
	512	static int __init gicv2m_acpi_init(struct irq_domain *parent)
	513	{
	514	return -EINVAL;
	515	}
	516	#endif /* CONFIG_ACPI */
	517
	518	int __init gicv2m_init(struct fwnode_handle *parent_handle,
	519	struct irq_domain *parent)
	520	{
	521	if (is_of_node(parent_handle))
	522	return gicv2m_of_init(parent_handle, parent);
	523
	524	return gicv2m_acpi_init(parent);
	525	}