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KVM: VMX: Use shadow TPR/cr8 for 64-bits guests
[deliverable/linux.git] / drivers / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20#include "kvm.h"
21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <asm/processor.h>
29#include <asm/msr.h>
30#include <asm/page.h>
31#include <asm/current.h>
32#include <asm/apicdef.h>
33#include <asm/atomic.h>
34#include <asm/div64.h>
35#include "irq.h"
36
37#define PRId64 "d"
38#define PRIx64 "llx"
39#define PRIu64 "u"
40#define PRIo64 "o"
41
42#define APIC_BUS_CYCLE_NS 1
43
44/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45#define apic_debug(fmt, arg...)
46
47#define APIC_LVT_NUM 6
48/* 14 is the version for Xeon and Pentium 8.4.8*/
49#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50#define LAPIC_MMIO_LENGTH (1 << 12)
51/* followed define is not in apicdef.h */
52#define APIC_SHORT_MASK 0xc0000
53#define APIC_DEST_NOSHORT 0x0
54#define APIC_DEST_MASK 0x800
55#define MAX_APIC_VECTOR 256
56
57#define VEC_POS(v) ((v) & (32 - 1))
58#define REG_POS(v) (((v) >> 5) << 4)
59static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
60{
61 return *((u32 *) (apic->regs + reg_off));
62}
63
64static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
65{
66 *((u32 *) (apic->regs + reg_off)) = val;
67}
68
69static inline int apic_test_and_set_vector(int vec, void *bitmap)
70{
71 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
72}
73
74static inline int apic_test_and_clear_vector(int vec, void *bitmap)
75{
76 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
77}
78
79static inline void apic_set_vector(int vec, void *bitmap)
80{
81 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82}
83
84static inline void apic_clear_vector(int vec, void *bitmap)
85{
86 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline int apic_hw_enabled(struct kvm_lapic *apic)
90{
91 return (apic)->vcpu->apic_base & MSR_IA32_APICBASE_ENABLE;
92}
93
94static inline int apic_sw_enabled(struct kvm_lapic *apic)
95{
96 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
97}
98
99static inline int apic_enabled(struct kvm_lapic *apic)
100{
101 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
102}
103
104#define LVT_MASK \
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106
107#define LINT_MASK \
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
110
111static inline int kvm_apic_id(struct kvm_lapic *apic)
112{
113 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
114}
115
116static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
117{
118 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
119}
120
121static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
122{
123 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
124}
125
126static inline int apic_lvtt_period(struct kvm_lapic *apic)
127{
128 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
129}
130
131static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
132 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
133 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
134 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
135 LINT_MASK, LINT_MASK, /* LVT0-1 */
136 LVT_MASK /* LVTERR */
137};
138
139static int find_highest_vector(void *bitmap)
140{
141 u32 *word = bitmap;
142 int word_offset = MAX_APIC_VECTOR >> 5;
143
144 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
145 continue;
146
147 if (likely(!word_offset && !word[0]))
148 return -1;
149 else
150 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
151}
152
153static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
154{
155 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
156}
157
158static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
159{
160 apic_clear_vector(vec, apic->regs + APIC_IRR);
161}
162
163static inline int apic_find_highest_irr(struct kvm_lapic *apic)
164{
165 int result;
166
167 result = find_highest_vector(apic->regs + APIC_IRR);
168 ASSERT(result == -1 || result >= 16);
169
170 return result;
171}
172
6e5d865c
YS		 173int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
174{
175 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
176 int highest_irr;
177
178 if (!apic)
179 return 0;
180 highest_irr = apic_find_highest_irr(apic);
181
182 return highest_irr;
183}
184EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
185
97222cc8
ED		 186int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig)
187{
188 if (!apic_test_and_set_irr(vec, apic)) {
189 /* a new pending irq is set in IRR */
190 if (trig)
191 apic_set_vector(vec, apic->regs + APIC_TMR);
192 else
193 apic_clear_vector(vec, apic->regs + APIC_TMR);
194 kvm_vcpu_kick(apic->vcpu);
195 return 1;
196 }
197 return 0;
198}
199
200static inline int apic_find_highest_isr(struct kvm_lapic *apic)
201{
202 int result;
203
204 result = find_highest_vector(apic->regs + APIC_ISR);
205 ASSERT(result == -1 || result >= 16);
206
207 return result;
208}
209
210static void apic_update_ppr(struct kvm_lapic *apic)
211{
212 u32 tpr, isrv, ppr;
213 int isr;
214
215 tpr = apic_get_reg(apic, APIC_TASKPRI);
216 isr = apic_find_highest_isr(apic);
217 isrv = (isr != -1) ? isr : 0;
218
219 if ((tpr & 0xf0) >= (isrv & 0xf0))
220 ppr = tpr & 0xff;
221 else
222 ppr = isrv & 0xf0;
223
224 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
225 apic, ppr, isr, isrv);
226
227 apic_set_reg(apic, APIC_PROCPRI, ppr);
228}
229
230static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
231{
232 apic_set_reg(apic, APIC_TASKPRI, tpr);
233 apic_update_ppr(apic);
234}
235
236int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
237{
238 return kvm_apic_id(apic) == dest;
239}
240
241int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
242{
243 int result = 0;
244 u8 logical_id;
245
246 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
247
248 switch (apic_get_reg(apic, APIC_DFR)) {
249 case APIC_DFR_FLAT:
250 if (logical_id & mda)
251 result = 1;
252 break;
253 case APIC_DFR_CLUSTER:
254 if (((logical_id >> 4) == (mda >> 0x4))
255 && (logical_id & mda & 0xf))
256 result = 1;
257 break;
258 default:
259 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
260 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
261 break;
262 }
263
264 return result;
265}
266
267static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
268 int short_hand, int dest, int dest_mode)
269{
270 int result = 0;
271 struct kvm_lapic *target = vcpu->apic;
272
273 apic_debug("target %p, source %p, dest 0x%x, "
274 "dest_mode 0x%x, short_hand 0x%x",
275 target, source, dest, dest_mode, short_hand);
276
277 ASSERT(!target);
278 switch (short_hand) {
279 case APIC_DEST_NOSHORT:
280 if (dest_mode == 0) {
281 /* Physical mode. */
282 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
283 result = 1;
284 } else
285 /* Logical mode. */
286 result = kvm_apic_match_logical_addr(target, dest);
287 break;
288 case APIC_DEST_SELF:
289 if (target == source)
290 result = 1;
291 break;
292 case APIC_DEST_ALLINC:
293 result = 1;
294 break;
295 case APIC_DEST_ALLBUT:
296 if (target != source)
297 result = 1;
298 break;
299 default:
300 printk(KERN_WARNING "Bad dest shorthand value %x\n",
301 short_hand);
302 break;
303 }
304
305 return result;
306}
307
308/*
309 * Add a pending IRQ into lapic.
310 * Return 1 if successfully added and 0 if discarded.
311 */
312static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
313 int vector, int level, int trig_mode)
314{
315 int result = 0;
316
317 switch (delivery_mode) {
318 case APIC_DM_FIXED:
319 case APIC_DM_LOWEST:
320 /* FIXME add logic for vcpu on reset */
321 if (unlikely(!apic_enabled(apic)))
322 break;
323
324 if (apic_test_and_set_irr(vector, apic) && trig_mode) {
325 apic_debug("level trig mode repeatedly for vector %d",
326 vector);
327 break;
328 }
329
330 if (trig_mode) {
331 apic_debug("level trig mode for vector %d", vector);
332 apic_set_vector(vector, apic->regs + APIC_TMR);
333 } else
334 apic_clear_vector(vector, apic->regs + APIC_TMR);
335
336 kvm_vcpu_kick(apic->vcpu);
337
338 result = 1;
339 break;
340
341 case APIC_DM_REMRD:
342 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
343 break;
344
345 case APIC_DM_SMI:
346 printk(KERN_DEBUG "Ignoring guest SMI\n");
347 break;
348 case APIC_DM_NMI:
349 printk(KERN_DEBUG "Ignoring guest NMI\n");
350 break;
351
352 case APIC_DM_INIT:
353 printk(KERN_DEBUG "Ignoring guest INIT\n");
354 break;
355
356 case APIC_DM_STARTUP:
357 printk(KERN_DEBUG "Ignoring guest STARTUP\n");
358 break;
359
360 default:
361 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
362 delivery_mode);
363 break;
364 }
365 return result;
366}
367
368struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
369 unsigned long bitmap)
370{
371 int vcpu_id;
372
373 /* TODO for real round robin */
374 vcpu_id = fls(bitmap) - 1;
375 if (vcpu_id < 0)
376 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
377 return kvm->vcpus[vcpu_id]->apic;
378}
379
380static void apic_set_eoi(struct kvm_lapic *apic)
381{
382 int vector = apic_find_highest_isr(apic);
383
384 /*
385 * Not every write EOI will has corresponding ISR,
386 * one example is when Kernel check timer on setup_IO_APIC
387 */
388 if (vector == -1)
389 return;
390
391 apic_clear_vector(vector, apic->regs + APIC_ISR);
392 apic_update_ppr(apic);
393
394 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
395 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
396}
397
398static void apic_send_ipi(struct kvm_lapic *apic)
399{
400 u32 icr_low = apic_get_reg(apic, APIC_ICR);
401 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
402
403 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
404 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
405 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
406 unsigned int level = icr_low & APIC_INT_ASSERT;
407 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
408 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
409 unsigned int vector = icr_low & APIC_VECTOR_MASK;
410
411 struct kvm_lapic *target;
412 struct kvm_vcpu *vcpu;
413 unsigned long lpr_map = 0;
414 int i;
415
416 apic_debug("icr_high 0x%x, icr_low 0x%x, "
417 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
418 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
419 icr_high, icr_low, short_hand, dest,
420 trig_mode, level, dest_mode, delivery_mode, vector);
421
422 for (i = 0; i < KVM_MAX_VCPUS; i++) {
423 vcpu = apic->vcpu->kvm->vcpus[i];
424 if (!vcpu)
425 continue;
426
427 if (vcpu->apic &&
428 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
429 if (delivery_mode == APIC_DM_LOWEST)
430 set_bit(vcpu->vcpu_id, &lpr_map);
431 else
432 __apic_accept_irq(vcpu->apic, delivery_mode,
433 vector, level, trig_mode);
434 }
435 }
436
437 if (delivery_mode == APIC_DM_LOWEST) {
438 target = kvm_apic_round_robin(vcpu->kvm, vector, lpr_map);
439 if (target != NULL)
440 __apic_accept_irq(target, delivery_mode,
441 vector, level, trig_mode);
442 }
443}
444
445static u32 apic_get_tmcct(struct kvm_lapic *apic)
446{
447 u32 counter_passed;
448 ktime_t passed, now = apic->timer.dev.base->get_time();
449 u32 tmcct = apic_get_reg(apic, APIC_TMICT);
450
451 ASSERT(apic != NULL);
452
453 if (unlikely(ktime_to_ns(now) <=
454 ktime_to_ns(apic->timer.last_update))) {
455 /* Wrap around */
456 passed = ktime_add(( {
457 (ktime_t) {
458 .tv64 = KTIME_MAX -
459 (apic->timer.last_update).tv64}; }
460 ), now);
461 apic_debug("time elapsed\n");
462 } else
463 passed = ktime_sub(now, apic->timer.last_update);
464
465 counter_passed = div64_64(ktime_to_ns(passed),
466 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
467 tmcct -= counter_passed;
468
469 if (tmcct <= 0) {
470 if (unlikely(!apic_lvtt_period(apic)))
471 tmcct = 0;
472 else
473 do {
474 tmcct += apic_get_reg(apic, APIC_TMICT);
475 } while (tmcct <= 0);
476 }
477
478 return tmcct;
479}
480
481static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
482{
483 u32 val = 0;
484
485 if (offset >= LAPIC_MMIO_LENGTH)
486 return 0;
487
488 switch (offset) {
489 case APIC_ARBPRI:
490 printk(KERN_WARNING "Access APIC ARBPRI register "
491 "which is for P6\n");
492 break;
493
494 case APIC_TMCCT: /* Timer CCR */
495 val = apic_get_tmcct(apic);
496 break;
497
498 default:
6e5d865c 499 apic_update_ppr(apic);
97222cc8
ED		 500 val = apic_get_reg(apic, offset);
501 break;
502 }
503
504 return val;
505}
506
507static void apic_mmio_read(struct kvm_io_device *this,
508 gpa_t address, int len, void *data)
509{
510 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
511 unsigned int offset = address - apic->base_address;
512 unsigned char alignment = offset & 0xf;
513 u32 result;
514
515 if ((alignment + len) > 4) {
516 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
517 (unsigned long)address, len);
518 return;
519 }
520 result = __apic_read(apic, offset & ~0xf);
521
522 switch (len) {
523 case 1:
524 case 2:
525 case 4:
526 memcpy(data, (char *)&result + alignment, len);
527 break;
528 default:
529 printk(KERN_ERR "Local APIC read with len = %x, "
530 "should be 1,2, or 4 instead\n", len);
531 break;
532 }
533}
534
535static void update_divide_count(struct kvm_lapic *apic)
536{
537 u32 tmp1, tmp2, tdcr;
538
539 tdcr = apic_get_reg(apic, APIC_TDCR);
540 tmp1 = tdcr & 0xf;
541 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
542 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
543
544 apic_debug("timer divide count is 0x%x\n",
545 apic->timer.divide_count);
546}
547
548static void start_apic_timer(struct kvm_lapic *apic)
549{
550 ktime_t now = apic->timer.dev.base->get_time();
551
552 apic->timer.last_update = now;
553
554 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
555 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
556 atomic_set(&apic->timer.pending, 0);
557 hrtimer_start(&apic->timer.dev,
558 ktime_add_ns(now, apic->timer.period),
559 HRTIMER_MODE_ABS);
560
561 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
562 PRIx64 ", "
563 "timer initial count 0x%x, period %lldns, "
564 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
565 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
566 apic_get_reg(apic, APIC_TMICT),
567 apic->timer.period,
568 ktime_to_ns(ktime_add_ns(now,
569 apic->timer.period)));
570}
571
572static void apic_mmio_write(struct kvm_io_device *this,
573 gpa_t address, int len, const void *data)
574{
575 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
576 unsigned int offset = address - apic->base_address;
577 unsigned char alignment = offset & 0xf;
578 u32 val;
579
580 /*
581 * APIC register must be aligned on 128-bits boundary.
582 * 32/64/128 bits registers must be accessed thru 32 bits.
583 * Refer SDM 8.4.1
584 */
585 if (len != 4 || alignment) {
586 if (printk_ratelimit())
587 printk(KERN_ERR "apic write: bad size=%d %lx\n",
588 len, (long)address);
589 return;
590 }
591
592 val = *(u32 *) data;
593
594 /* too common printing */
595 if (offset != APIC_EOI)
596 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
597 "0x%x\n", __FUNCTION__, offset, len, val);
598
599 offset &= 0xff0;
600
601 switch (offset) {
602 case APIC_ID: /* Local APIC ID */
603 apic_set_reg(apic, APIC_ID, val);
604 break;
605
606 case APIC_TASKPRI:
607 apic_set_tpr(apic, val & 0xff);
608 break;
609
610 case APIC_EOI:
611 apic_set_eoi(apic);
612 break;
613
614 case APIC_LDR:
615 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
616 break;
617
618 case APIC_DFR:
619 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
620 break;
621
622 case APIC_SPIV:
623 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
624 if (!(val & APIC_SPIV_APIC_ENABLED)) {
625 int i;
626 u32 lvt_val;
627
628 for (i = 0; i < APIC_LVT_NUM; i++) {
629 lvt_val = apic_get_reg(apic,
630 APIC_LVTT + 0x10 * i);
631 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
632 lvt_val | APIC_LVT_MASKED);
633 }
634 atomic_set(&apic->timer.pending, 0);
635
636 }
637 break;
638
639 case APIC_ICR:
640 /* No delay here, so we always clear the pending bit */
641 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
642 apic_send_ipi(apic);
643 break;
644
645 case APIC_ICR2:
646 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
647 break;
648
649 case APIC_LVTT:
650 case APIC_LVTTHMR:
651 case APIC_LVTPC:
652 case APIC_LVT0:
653 case APIC_LVT1:
654 case APIC_LVTERR:
655 /* TODO: Check vector */
656 if (!apic_sw_enabled(apic))
657 val |= APIC_LVT_MASKED;
658
659 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
660 apic_set_reg(apic, offset, val);
661
662 break;
663
664 case APIC_TMICT:
665 hrtimer_cancel(&apic->timer.dev);
666 apic_set_reg(apic, APIC_TMICT, val);
667 start_apic_timer(apic);
668 return;
669
670 case APIC_TDCR:
671 if (val & 4)
672 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
673 apic_set_reg(apic, APIC_TDCR, val);
674 update_divide_count(apic);
675 break;
676
677 default:
678 apic_debug("Local APIC Write to read-only register %x\n",
679 offset);
680 break;
681 }
682
683}
684
685static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
686{
687 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
688 int ret = 0;
689
690
691 if (apic_hw_enabled(apic) &&
692 (addr >= apic->base_address) &&
693 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
694 ret = 1;
695
696 return ret;
697}
698
699void kvm_free_apic(struct kvm_lapic *apic)
700{
701 if (!apic)
702 return;
703
704 hrtimer_cancel(&apic->timer.dev);
705
706 if (apic->regs_page) {
707 __free_page(apic->regs_page);
708 apic->regs_page = 0;
709 }
710
711 kfree(apic);
712}
713
714/*
715 *----------------------------------------------------------------------
716 * LAPIC interface
717 *----------------------------------------------------------------------
718 */
719
720void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
721{
722 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
723
724 if (!apic)
725 return;
726 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
727}
728
729u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
730{
731 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
732 u64 tpr;
733
734 if (!apic)
735 return 0;
736 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
737
738 return (tpr & 0xf0) >> 4;
739}
6e5d865c 740EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
97222cc8
ED		 741
742void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
743{
744 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
745
746 if (!apic) {
747 value |= MSR_IA32_APICBASE_BSP;
748 vcpu->apic_base = value;
749 return;
750 }
751 if (apic->vcpu->vcpu_id)
752 value &= ~MSR_IA32_APICBASE_BSP;
753
754 vcpu->apic_base = value;
755 apic->base_address = apic->vcpu->apic_base &
756 MSR_IA32_APICBASE_BASE;
757
758 /* with FSB delivery interrupt, we can restart APIC functionality */
759 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
760 "0x%lx.\n", apic->apic_base, apic->base_address);
761
762}
763
764u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
765{
766 return vcpu->apic_base;
767}
768EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
769
770static void lapic_reset(struct kvm_vcpu *vcpu)
771{
772 struct kvm_lapic *apic;
773 int i;
774
775 apic_debug("%s\n", __FUNCTION__);
776
777 ASSERT(vcpu);
778 apic = vcpu->apic;
779 ASSERT(apic != NULL);
780
781 /* Stop the timer in case it's a reset to an active apic */
782 hrtimer_cancel(&apic->timer.dev);
783
784 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
785 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
786
787 for (i = 0; i < APIC_LVT_NUM; i++)
788 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
789
790 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
791 apic_set_reg(apic, APIC_SPIV, 0xff);
792 apic_set_reg(apic, APIC_TASKPRI, 0);
793 apic_set_reg(apic, APIC_LDR, 0);
794 apic_set_reg(apic, APIC_ESR, 0);
795 apic_set_reg(apic, APIC_ICR, 0);
796 apic_set_reg(apic, APIC_ICR2, 0);
797 apic_set_reg(apic, APIC_TDCR, 0);
798 apic_set_reg(apic, APIC_TMICT, 0);
799 for (i = 0; i < 8; i++) {
800 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
801 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
802 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
803 }
804 apic->timer.divide_count = 0;
805 atomic_set(&apic->timer.pending, 0);
806 if (vcpu->vcpu_id == 0)
807 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
808 apic_update_ppr(apic);
809
810 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
811 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
812 vcpu, kvm_apic_id(apic),
813 vcpu->apic_base, apic->base_address);
814}
815
816int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
817{
818 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
819 int ret = 0;
820
821 if (!apic)
822 return 0;
823 ret = apic_enabled(apic);
824
825 return ret;
826}
6e5d865c 827EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
97222cc8
ED		 828
829/*
830 *----------------------------------------------------------------------
831 * timer interface
832 *----------------------------------------------------------------------
833 */
834static int __apic_timer_fn(struct kvm_lapic *apic)
835{
836 u32 vector;
837 int result = 0;
838
839 if (unlikely(!apic_enabled(apic) ||
840 !apic_lvt_enabled(apic, APIC_LVTT))) {
841 apic_debug("%s: time interrupt although apic is down\n",
842 __FUNCTION__);
843 return 0;
844 }
845
846 vector = apic_lvt_vector(apic, APIC_LVTT);
847 apic->timer.last_update = apic->timer.dev.expires;
848 atomic_inc(&apic->timer.pending);
849 __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
850
851 if (apic_lvtt_period(apic)) {
852 u32 offset;
853 u32 tmict = apic_get_reg(apic, APIC_TMICT);
854
855 offset = APIC_BUS_CYCLE_NS * apic->timer.divide_count * tmict;
856
857 result = 1;
858 apic->timer.dev.expires = ktime_add_ns(
859 apic->timer.dev.expires,
860 apic->timer.period);
861 }
862
863 return result;
864}
865
866static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
867{
868 struct kvm_lapic *apic;
869 int restart_timer = 0;
870
871 apic = container_of(data, struct kvm_lapic, timer.dev);
872
873 restart_timer = __apic_timer_fn(apic);
874
875 if (restart_timer)
876 return HRTIMER_RESTART;
877 else
878 return HRTIMER_NORESTART;
879}
880
881int kvm_create_lapic(struct kvm_vcpu *vcpu)
882{
883 struct kvm_lapic *apic;
884
885 ASSERT(vcpu != NULL);
886 apic_debug("apic_init %d\n", vcpu->vcpu_id);
887
888 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
889 if (!apic)
890 goto nomem;
891
892 vcpu->apic = apic;
893
894 apic->regs_page = alloc_page(GFP_KERNEL);
895 if (apic->regs_page == NULL) {
896 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
897 vcpu->vcpu_id);
898 goto nomem;
899 }
900 apic->regs = page_address(apic->regs_page);
901 memset(apic->regs, 0, PAGE_SIZE);
902 apic->vcpu = vcpu;
903
904 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
905 apic->timer.dev.function = apic_timer_fn;
906 apic->base_address = APIC_DEFAULT_PHYS_BASE;
907 vcpu->apic_base = APIC_DEFAULT_PHYS_BASE;
908
909 lapic_reset(vcpu);
910 apic->dev.read = apic_mmio_read;
911 apic->dev.write = apic_mmio_write;
912 apic->dev.in_range = apic_mmio_range;
913 apic->dev.private = apic;
914
915 return 0;
916nomem:
917 kvm_free_apic(apic);
918 return -ENOMEM;
919}
920EXPORT_SYMBOL_GPL(kvm_create_lapic);
921
922int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
923{
924 struct kvm_lapic *apic = vcpu->apic;
925 int highest_irr;
926
927 if (!apic || !apic_enabled(apic))
928 return -1;
929
6e5d865c 930 apic_update_ppr(apic);
97222cc8
ED		 931 highest_irr = apic_find_highest_irr(apic);
932 if ((highest_irr == -1) ||
933 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
934 return -1;
935 return highest_irr;
936}
937
938int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
939{
940 int vector = kvm_apic_has_interrupt(vcpu);
941 struct kvm_lapic *apic = vcpu->apic;
942
943 if (vector == -1)
944 return -1;
945
946 apic_set_vector(vector, apic->regs + APIC_ISR);
947 apic_update_ppr(apic);
948 apic_clear_irr(vector, apic);
949 return vector;
950}
96ad2cc6
ED		 951
952void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
953{
954 struct kvm_lapic *apic = vcpu->apic;
955
956 apic->base_address = vcpu->apic_base &
957 MSR_IA32_APICBASE_BASE;
958 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
959 apic_update_ppr(apic);
960 hrtimer_cancel(&apic->timer.dev);
961 update_divide_count(apic);
962 start_apic_timer(apic);
963}
Linux kernel - Deliverables
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