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[media] adv7511: fix quantization range handling
[deliverable/linux.git] / drivers / media / i2c / adv7842.c
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a89bcd4c
HV		 1/*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
5b64b205
MR		 23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
7de6fab1
MR		 25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
5b64b205
MR		 27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
a89bcd4c
HV		 30 */
31
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/i2c.h>
37#include <linux/delay.h>
38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
40#include <linux/v4l2-dv-timings.h>
09f90c53 41#include <linux/hdmi.h>
25c84fb1 42#include <media/cec.h>
a89bcd4c 43#include <media/v4l2-device.h>
aef5159f 44#include <media/v4l2-event.h>
a89bcd4c
HV		 45#include <media/v4l2-ctrls.h>
46#include <media/v4l2-dv-timings.h>
b5dcee22 47#include <media/i2c/adv7842.h>
a89bcd4c
HV		 48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
54MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
56MODULE_LICENSE("GPL");
57
58/* ADV7842 system clock frequency */
59#define ADV7842_fsc (28636360)
60
f888ae7e
HV		 61#define ADV7842_RGB_OUT (1 << 1)
62
63#define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
64#define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
65#define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
66
67#define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
68#define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
69#define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
70#define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
71#define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
72#define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
73
74#define ADV7842_OP_CH_SEL_GBR (0 << 5)
75#define ADV7842_OP_CH_SEL_GRB (1 << 5)
76#define ADV7842_OP_CH_SEL_BGR (2 << 5)
77#define ADV7842_OP_CH_SEL_RGB (3 << 5)
78#define ADV7842_OP_CH_SEL_BRG (4 << 5)
79#define ADV7842_OP_CH_SEL_RBG (5 << 5)
80
81#define ADV7842_OP_SWAP_CB_CR (1 << 0)
82
25c84fb1
HV		 83#define ADV7842_MAX_ADDRS (3)
84
a89bcd4c
HV		 85/*
86**********************************************************************
87*
88* Arrays with configuration parameters for the ADV7842
89*
90**********************************************************************
91*/
92
f888ae7e
HV		 93struct adv7842_format_info {
94 u32 code;
95 u8 op_ch_sel;
96 bool rgb_out;
97 bool swap_cb_cr;
98 u8 op_format_sel;
99};
100
a89bcd4c 101struct adv7842_state {
7de5be44 102 struct adv7842_platform_data pdata;
a89bcd4c
HV		 103 struct v4l2_subdev sd;
104 struct media_pad pad;
105 struct v4l2_ctrl_handler hdl;
106 enum adv7842_mode mode;
107 struct v4l2_dv_timings timings;
108 enum adv7842_vid_std_select vid_std_select;
f888ae7e
HV		 109
110 const struct adv7842_format_info *format;
111
a89bcd4c
HV		 112 v4l2_std_id norm;
113 struct {
114 u8 edid[256];
115 u32 present;
116 } hdmi_edid;
117 struct {
118 u8 edid[256];
119 u32 present;
120 } vga_edid;
121 struct v4l2_fract aspect_ratio;
122 u32 rgb_quantization_range;
123 bool is_cea_format;
a89bcd4c 124 struct delayed_work delayed_work_enable_hotplug;
6e9071f2 125 bool restart_stdi_once;
a89bcd4c
HV		 126 bool hdmi_port_a;
127
128 /* i2c clients */
129 struct i2c_client *i2c_sdp_io;
130 struct i2c_client *i2c_sdp;
131 struct i2c_client *i2c_cp;
132 struct i2c_client *i2c_vdp;
133 struct i2c_client *i2c_afe;
134 struct i2c_client *i2c_hdmi;
135 struct i2c_client *i2c_repeater;
136 struct i2c_client *i2c_edid;
137 struct i2c_client *i2c_infoframe;
138 struct i2c_client *i2c_cec;
139 struct i2c_client *i2c_avlink;
140
141 /* controls */
142 struct v4l2_ctrl *detect_tx_5v_ctrl;
143 struct v4l2_ctrl *analog_sampling_phase_ctrl;
144 struct v4l2_ctrl *free_run_color_ctrl_manual;
145 struct v4l2_ctrl *free_run_color_ctrl;
146 struct v4l2_ctrl *rgb_quantization_range_ctrl;
25c84fb1
HV		 147
148 struct cec_adapter *cec_adap;
149 u8 cec_addr[ADV7842_MAX_ADDRS];
150 u8 cec_valid_addrs;
151 bool cec_enabled_adap;
a89bcd4c
HV		 152};
153
154/* Unsupported timings. This device cannot support 720p30. */
155static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
156 V4L2_DV_BT_CEA_1280X720P30,
157 { }
158};
159
160static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
161{
162 int i;
163
164 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
85f9e06c 165 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
a89bcd4c
HV		 166 return false;
167 return true;
168}
169
170struct adv7842_video_standards {
171 struct v4l2_dv_timings timings;
172 u8 vid_std;
173 u8 v_freq;
174};
175
176/* sorted by number of lines */
177static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
178 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
180 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
181 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 /* TODO add 1920x1080P60_RB (CVT timing) */
188 { },
189};
190
191/* sorted by number of lines */
192static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
209 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
211 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
212 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
213 /* TODO add 1600X1200P60_RB (not a DMT timing) */
214 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
215 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
216 { },
217};
218
219/* sorted by number of lines */
220static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
221 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
222 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
223 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
224 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
225 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
226 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
227 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
228 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
229 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
230 { },
231};
232
233/* sorted by number of lines */
234static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
250 { },
251};
252
48519838
HV		 253static const struct v4l2_event adv7842_ev_fmt = {
254 .type = V4L2_EVENT_SOURCE_CHANGE,
255 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
256};
257
a89bcd4c
HV		 258/* ----------------------------------------------------------------------- */
259
260static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
261{
262 return container_of(sd, struct adv7842_state, sd);
263}
264
265static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
266{
267 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
268}
269
f888ae7e
HV		 270static inline unsigned hblanking(const struct v4l2_bt_timings *t)
271{
272 return V4L2_DV_BT_BLANKING_WIDTH(t);
273}
274
a89bcd4c
HV		 275static inline unsigned htotal(const struct v4l2_bt_timings *t)
276{
277 return V4L2_DV_BT_FRAME_WIDTH(t);
278}
279
f888ae7e
HV		 280static inline unsigned vblanking(const struct v4l2_bt_timings *t)
281{
282 return V4L2_DV_BT_BLANKING_HEIGHT(t);
283}
284
a89bcd4c
HV		 285static inline unsigned vtotal(const struct v4l2_bt_timings *t)
286{
287 return V4L2_DV_BT_FRAME_HEIGHT(t);
288}
289
290
291/* ----------------------------------------------------------------------- */
292
293static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
294 u8 command, bool check)
295{
296 union i2c_smbus_data data;
297
298 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
299 I2C_SMBUS_READ, command,
300 I2C_SMBUS_BYTE_DATA, &data))
301 return data.byte;
302 if (check)
303 v4l_err(client, "error reading %02x, %02x\n",
304 client->addr, command);
305 return -EIO;
306}
307
308static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
309{
310 int i;
311
312 for (i = 0; i < 3; i++) {
313 int ret = adv_smbus_read_byte_data_check(client, command, true);
314
315 if (ret >= 0) {
316 if (i)
317 v4l_err(client, "read ok after %d retries\n", i);
318 return ret;
319 }
320 }
321 v4l_err(client, "read failed\n");
322 return -EIO;
323}
324
325static s32 adv_smbus_write_byte_data(struct i2c_client *client,
326 u8 command, u8 value)
327{
328 union i2c_smbus_data data;
329 int err;
330 int i;
331
332 data.byte = value;
333 for (i = 0; i < 3; i++) {
334 err = i2c_smbus_xfer(client->adapter, client->addr,
335 client->flags,
336 I2C_SMBUS_WRITE, command,
337 I2C_SMBUS_BYTE_DATA, &data);
338 if (!err)
339 break;
340 }
341 if (err < 0)
342 v4l_err(client, "error writing %02x, %02x, %02x\n",
343 client->addr, command, value);
344 return err;
345}
346
347static void adv_smbus_write_byte_no_check(struct i2c_client *client,
348 u8 command, u8 value)
349{
350 union i2c_smbus_data data;
351 data.byte = value;
352
353 i2c_smbus_xfer(client->adapter, client->addr,
354 client->flags,
355 I2C_SMBUS_WRITE, command,
356 I2C_SMBUS_BYTE_DATA, &data);
357}
358
359static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
360 u8 command, unsigned length, const u8 *values)
361{
362 union i2c_smbus_data data;
363
364 if (length > I2C_SMBUS_BLOCK_MAX)
365 length = I2C_SMBUS_BLOCK_MAX;
366 data.block[0] = length;
367 memcpy(data.block + 1, values, length);
368 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
369 I2C_SMBUS_WRITE, command,
370 I2C_SMBUS_I2C_BLOCK_DATA, &data);
371}
372
373/* ----------------------------------------------------------------------- */
374
375static inline int io_read(struct v4l2_subdev *sd, u8 reg)
376{
377 struct i2c_client *client = v4l2_get_subdevdata(sd);
378
379 return adv_smbus_read_byte_data(client, reg);
380}
381
382static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383{
384 struct i2c_client *client = v4l2_get_subdevdata(sd);
385
386 return adv_smbus_write_byte_data(client, reg, val);
387}
388
389static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
390{
391 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
392}
393
f888ae7e
HV		 394static inline int io_write_clr_set(struct v4l2_subdev *sd,
395 u8 reg, u8 mask, u8 val)
396{
397 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
398}
399
a89bcd4c
HV		 400static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
401{
402 struct adv7842_state *state = to_state(sd);
403
404 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
405}
406
407static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
408{
409 struct adv7842_state *state = to_state(sd);
410
411 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
412}
413
414static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
415{
416 struct adv7842_state *state = to_state(sd);
417
418 return adv_smbus_read_byte_data(state->i2c_cec, reg);
419}
420
421static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
422{
423 struct adv7842_state *state = to_state(sd);
424
425 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
426}
427
25c84fb1 428static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
a89bcd4c 429{
25c84fb1 430 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
a89bcd4c
HV		 431}
432
433static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
434{
435 struct adv7842_state *state = to_state(sd);
436
437 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
438}
439
440static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
441{
442 struct adv7842_state *state = to_state(sd);
443
444 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
445}
446
447static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
448{
449 struct adv7842_state *state = to_state(sd);
450
451 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
452}
453
454static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
455{
456 struct adv7842_state *state = to_state(sd);
457
458 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
459}
460
461static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
462{
463 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
464}
465
466static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
467{
468 struct adv7842_state *state = to_state(sd);
469
470 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
471}
472
473static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474{
475 struct adv7842_state *state = to_state(sd);
476
477 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
478}
479
480static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
481{
482 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
483}
484
485static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
486{
487 struct adv7842_state *state = to_state(sd);
488
489 return adv_smbus_read_byte_data(state->i2c_afe, reg);
490}
491
492static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
493{
494 struct adv7842_state *state = to_state(sd);
495
496 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
497}
498
499static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
500{
501 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
502}
503
504static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
505{
506 struct adv7842_state *state = to_state(sd);
507
508 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
509}
510
511static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
512{
513 struct adv7842_state *state = to_state(sd);
514
515 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
516}
517
518static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
519{
520 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
521}
522
523static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
524{
525 struct adv7842_state *state = to_state(sd);
526
527 return adv_smbus_read_byte_data(state->i2c_edid, reg);
528}
529
530static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
531{
532 struct adv7842_state *state = to_state(sd);
533
534 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
535}
536
537static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
538{
539 struct adv7842_state *state = to_state(sd);
540
541 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
542}
543
544static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
545{
546 struct adv7842_state *state = to_state(sd);
547
548 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
549}
550
5b64b205
MR		 551static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
552{
553 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
554}
555
a89bcd4c
HV		 556static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
557{
558 struct adv7842_state *state = to_state(sd);
559
560 return adv_smbus_read_byte_data(state->i2c_cp, reg);
561}
562
563static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
564{
565 struct adv7842_state *state = to_state(sd);
566
567 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
568}
569
570static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
571{
572 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
573}
574
575static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
576{
577 struct adv7842_state *state = to_state(sd);
578
579 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
580}
581
582static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
583{
584 struct adv7842_state *state = to_state(sd);
585
586 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
587}
588
589static void main_reset(struct v4l2_subdev *sd)
590{
591 struct i2c_client *client = v4l2_get_subdevdata(sd);
592
593 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
594
595 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
596
84aeed53 597 mdelay(5);
a89bcd4c
HV		 598}
599
f888ae7e
HV		 600/* -----------------------------------------------------------------------------
601 * Format helpers
602 */
603
604static const struct adv7842_format_info adv7842_formats[] = {
605 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
606 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
607 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
608 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
609 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
610 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
611 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
612 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
613 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
614 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
615 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
616 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
617 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
618 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
619 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
620 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
621 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
622 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
623 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
624 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
625 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
626 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
627 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
628 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
629 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
630 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
631 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
632 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
633 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
634 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
635 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
636 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
637 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
638 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
639 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
640 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
641 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
642 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
643};
644
645static const struct adv7842_format_info *
646adv7842_format_info(struct adv7842_state *state, u32 code)
647{
648 unsigned int i;
649
650 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
651 if (adv7842_formats[i].code == code)
652 return &adv7842_formats[i];
653 }
654
655 return NULL;
656}
657
a89bcd4c
HV		 658/* ----------------------------------------------------------------------- */
659
933913da
MB		 660static inline bool is_analog_input(struct v4l2_subdev *sd)
661{
662 struct adv7842_state *state = to_state(sd);
663
664 return ((state->mode == ADV7842_MODE_RGB) ||
665 (state->mode == ADV7842_MODE_COMP));
666}
667
a89bcd4c
HV		 668static inline bool is_digital_input(struct v4l2_subdev *sd)
669{
670 struct adv7842_state *state = to_state(sd);
671
672 return state->mode == ADV7842_MODE_HDMI;
673}
674
675static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
676 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 677 /* keep this initialization for compatibility with GCC < 4.4.6 */
678 .reserved = { 0 },
679 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
680 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 681 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 682 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
683 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 684};
685
686static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
687 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 688 /* keep this initialization for compatibility with GCC < 4.4.6 */
689 .reserved = { 0 },
690 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
691 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 692 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 693 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
694 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 695};
696
697static inline const struct v4l2_dv_timings_cap *
698adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
699{
700 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
701 &adv7842_timings_cap_analog;
702}
703
704/* ----------------------------------------------------------------------- */
705
25c84fb1
HV		 706static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
707{
708 u8 reg = io_read(sd, 0x6f);
709 u16 val = 0;
710
711 if (reg & 0x02)
712 val |= 1; /* port A */
713 if (reg & 0x01)
714 val |= 2; /* port B */
715 return val;
716}
717
a89bcd4c
HV		 718static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
719{
720 struct delayed_work *dwork = to_delayed_work(work);
721 struct adv7842_state *state = container_of(dwork,
722 struct adv7842_state, delayed_work_enable_hotplug);
723 struct v4l2_subdev *sd = &state->sd;
724 int present = state->hdmi_edid.present;
725 u8 mask = 0;
726
727 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
728 __func__, present);
729
7de6fab1
MR		 730 if (present & (0x04 << ADV7842_EDID_PORT_A))
731 mask |= 0x20;
732 if (present & (0x04 << ADV7842_EDID_PORT_B))
733 mask |= 0x10;
a89bcd4c
HV		 734 io_write_and_or(sd, 0x20, 0xcf, mask);
735}
736
737static int edid_write_vga_segment(struct v4l2_subdev *sd)
738{
739 struct i2c_client *client = v4l2_get_subdevdata(sd);
740 struct adv7842_state *state = to_state(sd);
741 const u8 *val = state->vga_edid.edid;
742 int err = 0;
743 int i;
744
745 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
746
747 /* HPA disable on port A and B */
748 io_write_and_or(sd, 0x20, 0xcf, 0x00);
749
750 /* Disable I2C access to internal EDID ram from VGA DDC port */
751 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
752
753 /* edid segment pointer '1' for VGA port */
754 rep_write_and_or(sd, 0x77, 0xef, 0x10);
755
756 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
757 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
758 I2C_SMBUS_BLOCK_MAX, val + i);
759 if (err)
760 return err;
761
762 /* Calculates the checksums and enables I2C access
763 * to internal EDID ram from VGA DDC port.
764 */
765 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
766
767 for (i = 0; i < 1000; i++) {
768 if (rep_read(sd, 0x79) & 0x20)
769 break;
770 mdelay(1);
771 }
772 if (i == 1000) {
773 v4l_err(client, "error enabling edid on VGA port\n");
774 return -EIO;
775 }
776
777 /* enable hotplug after 200 ms */
1d3e1543 778 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
a89bcd4c
HV		 779
780 return 0;
781}
782
a89bcd4c
HV		 783static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
784{
785 struct i2c_client *client = v4l2_get_subdevdata(sd);
786 struct adv7842_state *state = to_state(sd);
25c84fb1
HV		 787 const u8 *edid = state->hdmi_edid.edid;
788 int spa_loc;
789 u16 pa;
a89bcd4c
HV		 790 int err = 0;
791 int i;
792
25c84fb1
HV		 793 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
794 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
a89bcd4c
HV		 795
796 /* HPA disable on port A and B */
797 io_write_and_or(sd, 0x20, 0xcf, 0x00);
798
799 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
800 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
801
fc2e991e
MB		 802 if (!state->hdmi_edid.present)
803 return 0;
804
25c84fb1
HV		 805 pa = cec_get_edid_phys_addr(edid, 256, &spa_loc);
806 err = cec_phys_addr_validate(pa, &pa, NULL);
807 if (err)
808 return err;
809
810 /*
811 * Return an error if no location of the source physical address
812 * was found.
813 */
814 if (spa_loc == 0)
815 return -EINVAL;
816
a89bcd4c
HV		 817 /* edid segment pointer '0' for HDMI ports */
818 rep_write_and_or(sd, 0x77, 0xef, 0x00);
819
820 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
821 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
25c84fb1 822 I2C_SMBUS_BLOCK_MAX, edid + i);
a89bcd4c
HV		 823 if (err)
824 return err;
825
7de6fab1 826 if (port == ADV7842_EDID_PORT_A) {
25c84fb1
HV		 827 rep_write(sd, 0x72, edid[spa_loc]);
828 rep_write(sd, 0x73, edid[spa_loc + 1]);
a89bcd4c 829 } else {
25c84fb1
HV		 830 rep_write(sd, 0x74, edid[spa_loc]);
831 rep_write(sd, 0x75, edid[spa_loc + 1]);
a89bcd4c 832 }
7de6fab1
MR		 833 rep_write(sd, 0x76, spa_loc & 0xff);
834 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
a89bcd4c
HV		 835
836 /* Calculates the checksums and enables I2C access to internal
837 * EDID ram from HDMI DDC ports
838 */
7de6fab1 839 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
a89bcd4c
HV		 840
841 for (i = 0; i < 1000; i++) {
7de6fab1 842 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
a89bcd4c
HV		 843 break;
844 mdelay(1);
845 }
846 if (i == 1000) {
7de6fab1
MR		 847 v4l_err(client, "error enabling edid on port %c\n",
848 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
a89bcd4c
HV		 849 return -EIO;
850 }
25c84fb1 851 cec_s_phys_addr(state->cec_adap, pa, false);
a89bcd4c
HV		 852
853 /* enable hotplug after 200 ms */
1d3e1543 854 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
a89bcd4c
HV		 855
856 return 0;
857}
858
859/* ----------------------------------------------------------------------- */
860
861#ifdef CONFIG_VIDEO_ADV_DEBUG
862static void adv7842_inv_register(struct v4l2_subdev *sd)
863{
864 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
865 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
866 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
867 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
868 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
869 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
870 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
871 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
872 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
873 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
874 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
875 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
876}
877
878static int adv7842_g_register(struct v4l2_subdev *sd,
879 struct v4l2_dbg_register *reg)
880{
881 reg->size = 1;
882 switch (reg->reg >> 8) {
883 case 0:
884 reg->val = io_read(sd, reg->reg & 0xff);
885 break;
886 case 1:
887 reg->val = avlink_read(sd, reg->reg & 0xff);
888 break;
889 case 2:
890 reg->val = cec_read(sd, reg->reg & 0xff);
891 break;
892 case 3:
893 reg->val = infoframe_read(sd, reg->reg & 0xff);
894 break;
895 case 4:
896 reg->val = sdp_io_read(sd, reg->reg & 0xff);
897 break;
898 case 5:
899 reg->val = sdp_read(sd, reg->reg & 0xff);
900 break;
901 case 6:
902 reg->val = afe_read(sd, reg->reg & 0xff);
903 break;
904 case 7:
905 reg->val = rep_read(sd, reg->reg & 0xff);
906 break;
907 case 8:
908 reg->val = edid_read(sd, reg->reg & 0xff);
909 break;
910 case 9:
911 reg->val = hdmi_read(sd, reg->reg & 0xff);
912 break;
913 case 0xa:
914 reg->val = cp_read(sd, reg->reg & 0xff);
915 break;
916 case 0xb:
917 reg->val = vdp_read(sd, reg->reg & 0xff);
918 break;
919 default:
920 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
921 adv7842_inv_register(sd);
922 break;
923 }
924 return 0;
925}
926
927static int adv7842_s_register(struct v4l2_subdev *sd,
928 const struct v4l2_dbg_register *reg)
929{
930 u8 val = reg->val & 0xff;
931
932 switch (reg->reg >> 8) {
933 case 0:
934 io_write(sd, reg->reg & 0xff, val);
935 break;
936 case 1:
937 avlink_write(sd, reg->reg & 0xff, val);
938 break;
939 case 2:
940 cec_write(sd, reg->reg & 0xff, val);
941 break;
942 case 3:
943 infoframe_write(sd, reg->reg & 0xff, val);
944 break;
945 case 4:
946 sdp_io_write(sd, reg->reg & 0xff, val);
947 break;
948 case 5:
949 sdp_write(sd, reg->reg & 0xff, val);
950 break;
951 case 6:
952 afe_write(sd, reg->reg & 0xff, val);
953 break;
954 case 7:
955 rep_write(sd, reg->reg & 0xff, val);
956 break;
957 case 8:
958 edid_write(sd, reg->reg & 0xff, val);
959 break;
960 case 9:
961 hdmi_write(sd, reg->reg & 0xff, val);
962 break;
963 case 0xa:
964 cp_write(sd, reg->reg & 0xff, val);
965 break;
966 case 0xb:
967 vdp_write(sd, reg->reg & 0xff, val);
968 break;
969 default:
970 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
971 adv7842_inv_register(sd);
972 break;
973 }
974 return 0;
975}
976#endif
977
978static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
979{
980 struct adv7842_state *state = to_state(sd);
25c84fb1 981 u16 cable_det = adv7842_read_cable_det(sd);
a89bcd4c 982
25c84fb1 983 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
a89bcd4c 984
25c84fb1 985 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
a89bcd4c
HV		 986}
987
988static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
989 u8 prim_mode,
990 const struct adv7842_video_standards *predef_vid_timings,
991 const struct v4l2_dv_timings *timings)
992{
993 int i;
994
995 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
996 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
85f9e06c 997 is_digital_input(sd) ? 250000 : 1000000, false))
a89bcd4c
HV		 998 continue;
999 /* video std */
1000 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1001 /* v_freq and prim mode */
1002 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
1003 return 0;
1004 }
1005
1006 return -1;
1007}
1008
1009static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1010 struct v4l2_dv_timings *timings)
1011{
1012 struct adv7842_state *state = to_state(sd);
1013 int err;
1014
1015 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1016
1017 /* reset to default values */
1018 io_write(sd, 0x16, 0x43);
1019 io_write(sd, 0x17, 0x5a);
1020 /* disable embedded syncs for auto graphics mode */
1021 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1022 cp_write(sd, 0x26, 0x00);
1023 cp_write(sd, 0x27, 0x00);
1024 cp_write(sd, 0x28, 0x00);
1025 cp_write(sd, 0x29, 0x00);
6251e65f 1026 cp_write(sd, 0x8f, 0x40);
a89bcd4c
HV		 1027 cp_write(sd, 0x90, 0x00);
1028 cp_write(sd, 0xa5, 0x00);
1029 cp_write(sd, 0xa6, 0x00);
1030 cp_write(sd, 0xa7, 0x00);
1031 cp_write(sd, 0xab, 0x00);
1032 cp_write(sd, 0xac, 0x00);
1033
1034 switch (state->mode) {
1035 case ADV7842_MODE_COMP:
1036 case ADV7842_MODE_RGB:
1037 err = find_and_set_predefined_video_timings(sd,
1038 0x01, adv7842_prim_mode_comp, timings);
1039 if (err)
1040 err = find_and_set_predefined_video_timings(sd,
1041 0x02, adv7842_prim_mode_gr, timings);
1042 break;
1043 case ADV7842_MODE_HDMI:
1044 err = find_and_set_predefined_video_timings(sd,
1045 0x05, adv7842_prim_mode_hdmi_comp, timings);
1046 if (err)
1047 err = find_and_set_predefined_video_timings(sd,
1048 0x06, adv7842_prim_mode_hdmi_gr, timings);
1049 break;
1050 default:
1051 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1052 __func__, state->mode);
1053 err = -1;
1054 break;
1055 }
1056
1057
1058 return err;
1059}
1060
1061static void configure_custom_video_timings(struct v4l2_subdev *sd,
1062 const struct v4l2_bt_timings *bt)
1063{
1064 struct adv7842_state *state = to_state(sd);
1065 struct i2c_client *client = v4l2_get_subdevdata(sd);
1066 u32 width = htotal(bt);
1067 u32 height = vtotal(bt);
1068 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1069 u16 cp_start_eav = width - bt->hfrontporch;
1070 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1071 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1072 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1073 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1074 const u8 pll[2] = {
1075 0xc0 | ((width >> 8) & 0x1f),
1076 width & 0xff
1077 };
1078
1079 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1080
1081 switch (state->mode) {
1082 case ADV7842_MODE_COMP:
1083 case ADV7842_MODE_RGB:
1084 /* auto graphics */
1085 io_write(sd, 0x00, 0x07); /* video std */
1086 io_write(sd, 0x01, 0x02); /* prim mode */
1087 /* enable embedded syncs for auto graphics mode */
1088 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1089
1090 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1091 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1092 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1093 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1094 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1095 break;
1096 }
1097
1098 /* active video - horizontal timing */
1099 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1100 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1101 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1102 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1103
1104 /* active video - vertical timing */
1105 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1106 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1107 ((cp_end_vbi >> 8) & 0xf));
1108 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1109 break;
1110 case ADV7842_MODE_HDMI:
1111 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1112 according to [REF_03, c. 4.2] */
a89bcd4c
HV		 1113 io_write(sd, 0x00, 0x02); /* video std */
1114 io_write(sd, 0x01, 0x06); /* prim mode */
1115 break;
1116 default:
1117 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1118 __func__, state->mode);
1119 break;
1120 }
1121
1122 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1123 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1124 cp_write(sd, 0xab, (height >> 4) & 0xff);
1125 cp_write(sd, 0xac, (height & 0x0f) << 4);
1126}
1127
933913da
MB		 1128static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1129{
1130 struct adv7842_state *state = to_state(sd);
1131 u8 offset_buf[4];
1132
1133 if (auto_offset) {
1134 offset_a = 0x3ff;
1135 offset_b = 0x3ff;
1136 offset_c = 0x3ff;
1137 }
1138
1139 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1140 __func__, auto_offset ? "Auto" : "Manual",
1141 offset_a, offset_b, offset_c);
1142
1143 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1144 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1145 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1146 offset_buf[3] = offset_c & 0x0ff;
1147
1148 /* Registers must be written in this order with no i2c access in between */
1149 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1150 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1151}
1152
1153static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1154{
1155 struct adv7842_state *state = to_state(sd);
1156 u8 gain_buf[4];
1157 u8 gain_man = 1;
1158 u8 agc_mode_man = 1;
1159
1160 if (auto_gain) {
1161 gain_man = 0;
1162 agc_mode_man = 0;
1163 gain_a = 0x100;
1164 gain_b = 0x100;
1165 gain_c = 0x100;
1166 }
1167
1168 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1169 __func__, auto_gain ? "Auto" : "Manual",
1170 gain_a, gain_b, gain_c);
1171
1172 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1173 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1174 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1175 gain_buf[3] = ((gain_c & 0x0ff));
1176
1177 /* Registers must be written in this order with no i2c access in between */
1178 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1179 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1180}
1181
a89bcd4c
HV		 1182static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1183{
1184 struct adv7842_state *state = to_state(sd);
933913da
MB		 1185 bool rgb_output = io_read(sd, 0x02) & 0x02;
1186 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1187
1188 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1189 __func__, state->rgb_quantization_range,
1190 rgb_output, hdmi_signal);
a89bcd4c 1191
933913da
MB		 1192 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1193 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
69e9ba6f 1194
a89bcd4c
HV		 1195 switch (state->rgb_quantization_range) {
1196 case V4L2_DV_RGB_RANGE_AUTO:
69e9ba6f
HV		 1197 if (state->mode == ADV7842_MODE_RGB) {
1198 /* Receiving analog RGB signal
1199 * Set RGB full range (0-255) */
1200 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1201 break;
1202 }
1203
1204 if (state->mode == ADV7842_MODE_COMP) {
1205 /* Receiving analog YPbPr signal
1206 * Set automode */
1207 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1208 break;
1209 }
1210
933913da 1211 if (hdmi_signal) {
69e9ba6f
HV		 1212 /* Receiving HDMI signal
1213 * Set automode */
a89bcd4c 1214 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
69e9ba6f
HV		 1215 break;
1216 }
1217
1218 /* Receiving DVI-D signal
1219 * ADV7842 selects RGB limited range regardless of
1220 * input format (CE/IT) in automatic mode */
680fee04 1221 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
69e9ba6f
HV		 1222 /* RGB limited range (16-235) */
1223 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1224 } else {
1225 /* RGB full range (0-255) */
1226 io_write_and_or(sd, 0x02, 0x0f, 0x10);
933913da
MB		 1227
1228 if (is_digital_input(sd) && rgb_output) {
1229 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1230 } else {
1231 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1232 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1233 }
a89bcd4c
HV		 1234 }
1235 break;
1236 case V4L2_DV_RGB_RANGE_LIMITED:
69e9ba6f
HV		 1237 if (state->mode == ADV7842_MODE_COMP) {
1238 /* YCrCb limited range (16-235) */
1239 io_write_and_or(sd, 0x02, 0x0f, 0x20);
933913da 1240 break;
69e9ba6f 1241 }
933913da
MB		 1242
1243 /* RGB limited range (16-235) */
1244 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1245
a89bcd4c
HV		 1246 break;
1247 case V4L2_DV_RGB_RANGE_FULL:
69e9ba6f
HV		 1248 if (state->mode == ADV7842_MODE_COMP) {
1249 /* YCrCb full range (0-255) */
1250 io_write_and_or(sd, 0x02, 0x0f, 0x60);
933913da
MB		 1251 break;
1252 }
1253
1254 /* RGB full range (0-255) */
1255 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1256
1257 if (is_analog_input(sd) || hdmi_signal)
1258 break;
1259
1260 /* Adjust gain/offset for DVI-D signals only */
1261 if (rgb_output) {
1262 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
69e9ba6f 1263 } else {
933913da
MB		 1264 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1265 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
69e9ba6f 1266 }
a89bcd4c
HV		 1267 break;
1268 }
1269}
1270
1271static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1272{
1273 struct v4l2_subdev *sd = to_sd(ctrl);
1274 struct adv7842_state *state = to_state(sd);
1275
1276 /* TODO SDP ctrls
1277 contrast/brightness/hue/free run is acting a bit strange,
1278 not sure if sdp csc is correct.
1279 */
1280 switch (ctrl->id) {
1281 /* standard ctrls */
1282 case V4L2_CID_BRIGHTNESS:
1283 cp_write(sd, 0x3c, ctrl->val);
1284 sdp_write(sd, 0x14, ctrl->val);
1285 /* ignore lsb sdp 0x17[3:2] */
1286 return 0;
1287 case V4L2_CID_CONTRAST:
1288 cp_write(sd, 0x3a, ctrl->val);
1289 sdp_write(sd, 0x13, ctrl->val);
1290 /* ignore lsb sdp 0x17[1:0] */
1291 return 0;
1292 case V4L2_CID_SATURATION:
1293 cp_write(sd, 0x3b, ctrl->val);
1294 sdp_write(sd, 0x15, ctrl->val);
1295 /* ignore lsb sdp 0x17[5:4] */
1296 return 0;
1297 case V4L2_CID_HUE:
1298 cp_write(sd, 0x3d, ctrl->val);
1299 sdp_write(sd, 0x16, ctrl->val);
1300 /* ignore lsb sdp 0x17[7:6] */
1301 return 0;
1302 /* custom ctrls */
1303 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1304 afe_write(sd, 0xc8, ctrl->val);
1305 return 0;
1306 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1307 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1308 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1309 return 0;
1310 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1311 u8 R = (ctrl->val & 0xff0000) >> 16;
1312 u8 G = (ctrl->val & 0x00ff00) >> 8;
1313 u8 B = (ctrl->val & 0x0000ff);
1314 /* RGB -> YUV, numerical approximation */
1315 int Y = 66 * R + 129 * G + 25 * B;
1316 int U = -38 * R - 74 * G + 112 * B;
1317 int V = 112 * R - 94 * G - 18 * B;
1318
1319 /* Scale down to 8 bits with rounding */
1320 Y = (Y + 128) >> 8;
1321 U = (U + 128) >> 8;
1322 V = (V + 128) >> 8;
1323 /* make U,V positive */
1324 Y += 16;
1325 U += 128;
1326 V += 128;
1327
1328 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1329 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1330
1331 /* CP */
1332 cp_write(sd, 0xc1, R);
1333 cp_write(sd, 0xc0, G);
1334 cp_write(sd, 0xc2, B);
1335 /* SDP */
1336 sdp_write(sd, 0xde, Y);
1337 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1338 return 0;
1339 }
1340 case V4L2_CID_DV_RX_RGB_RANGE:
1341 state->rgb_quantization_range = ctrl->val;
1342 set_rgb_quantization_range(sd);
1343 return 0;
1344 }
1345 return -EINVAL;
1346}
1347
e8979274
HV		 1348static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1349{
1350 struct v4l2_subdev *sd = to_sd(ctrl);
1351
1352 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1353 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1354 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1355 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1356 return 0;
1357 }
1358 return -EINVAL;
1359}
1360
a89bcd4c
HV		 1361static inline bool no_power(struct v4l2_subdev *sd)
1362{
1363 return io_read(sd, 0x0c) & 0x24;
1364}
1365
1366static inline bool no_cp_signal(struct v4l2_subdev *sd)
1367{
1368 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1369}
1370
1371static inline bool is_hdmi(struct v4l2_subdev *sd)
1372{
1373 return hdmi_read(sd, 0x05) & 0x80;
1374}
1375
1376static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1377{
1378 struct adv7842_state *state = to_state(sd);
1379
1380 *status = 0;
1381
1382 if (io_read(sd, 0x0c) & 0x24)
1383 *status |= V4L2_IN_ST_NO_POWER;
1384
1385 if (state->mode == ADV7842_MODE_SDP) {
1386 /* status from SDP block */
1387 if (!(sdp_read(sd, 0x5A) & 0x01))
1388 *status |= V4L2_IN_ST_NO_SIGNAL;
1389
1390 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1391 __func__, *status);
1392 return 0;
1393 }
1394 /* status from CP block */
1395 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1396 !(cp_read(sd, 0xb1) & 0x80))
1397 /* TODO channel 2 */
1398 *status |= V4L2_IN_ST_NO_SIGNAL;
1399
1400 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1401 *status |= V4L2_IN_ST_NO_SIGNAL;
1402
1403 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1404 __func__, *status);
1405
1406 return 0;
1407}
1408
1409struct stdi_readback {
1410 u16 bl, lcf, lcvs;
1411 u8 hs_pol, vs_pol;
1412 bool interlaced;
1413};
1414
1415static int stdi2dv_timings(struct v4l2_subdev *sd,
1416 struct stdi_readback *stdi,
1417 struct v4l2_dv_timings *timings)
1418{
1419 struct adv7842_state *state = to_state(sd);
1420 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1421 u32 pix_clk;
1422 int i;
1423
1424 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1425 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1426
1427 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1428 adv7842_get_dv_timings_cap(sd),
1429 adv7842_check_dv_timings, NULL))
1430 continue;
1431 if (vtotal(bt) != stdi->lcf + 1)
1432 continue;
1433 if (bt->vsync != stdi->lcvs)
1434 continue;
1435
1436 pix_clk = hfreq * htotal(bt);
1437
1438 if ((pix_clk < bt->pixelclock + 1000000) &&
1439 (pix_clk > bt->pixelclock - 1000000)) {
1440 *timings = v4l2_dv_timings_presets[i];
1441 return 0;
1442 }
1443 }
1444
5fea1bb7 1445 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
a89bcd4c
HV		 1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1448 false, timings))
a89bcd4c
HV		 1449 return 0;
1450 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1451 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1453 false, state->aspect_ratio, timings))
a89bcd4c
HV		 1454 return 0;
1455
1456 v4l2_dbg(2, debug, sd,
1457 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1458 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1459 stdi->hs_pol, stdi->vs_pol);
1460 return -1;
1461}
1462
1463static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1464{
1465 u32 status;
1466
1467 adv7842_g_input_status(sd, &status);
1468 if (status & V4L2_IN_ST_NO_SIGNAL) {
1469 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1470 return -ENOLINK;
1471 }
1472
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1476
1477 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1482 } else {
1483 stdi->hs_pol = 'x';
1484 stdi->vs_pol = 'x';
1485 }
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1487
1488 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1489 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1490 return -ENOLINK;
1491 }
1492
1493 v4l2_dbg(2, debug, sd,
1494 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1495 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1496 stdi->hs_pol, stdi->vs_pol,
1497 stdi->interlaced ? "interlaced" : "progressive");
1498
1499 return 0;
1500}
1501
1502static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1503 struct v4l2_enum_dv_timings *timings)
1504{
c916194c
LP		 1505 if (timings->pad != 0)
1506 return -EINVAL;
1507
a89bcd4c
HV		 1508 return v4l2_enum_dv_timings_cap(timings,
1509 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1510}
1511
1512static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1513 struct v4l2_dv_timings_cap *cap)
1514{
c916194c
LP		 1515 if (cap->pad != 0)
1516 return -EINVAL;
1517
a89bcd4c
HV		 1518 *cap = *adv7842_get_dv_timings_cap(sd);
1519 return 0;
1520}
1521
1522/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
69e9ba6f 1523 if the format is listed in adv7842_timings[] */
a89bcd4c
HV		 1524static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1525 struct v4l2_dv_timings *timings)
1526{
1527 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1528 is_digital_input(sd) ? 250000 : 1000000,
1529 adv7842_check_dv_timings, NULL);
1530}
1531
1532static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1533 struct v4l2_dv_timings *timings)
1534{
1535 struct adv7842_state *state = to_state(sd);
1536 struct v4l2_bt_timings *bt = &timings->bt;
1537 struct stdi_readback stdi = { 0 };
1538
e78d834a
MB		 1539 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1540
f8789e6d
HV		 1541 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1542
a89bcd4c
HV		 1543 /* SDP block */
1544 if (state->mode == ADV7842_MODE_SDP)
1545 return -ENODATA;
1546
1547 /* read STDI */
1548 if (read_stdi(sd, &stdi)) {
6e9071f2 1549 state->restart_stdi_once = true;
a89bcd4c
HV		 1550 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1551 return -ENOLINK;
1552 }
1553 bt->interlaced = stdi.interlaced ?
1554 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
f888ae7e
HV		 1555 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1556 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
a89bcd4c
HV		 1557
1558 if (is_digital_input(sd)) {
28a769f1 1559 u32 freq;
e78d834a
MB		 1560
1561 timings->type = V4L2_DV_BT_656_1120;
6e9071f2 1562
e78d834a
MB		 1563 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1564 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
81ba0a4e
MB		 1565 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1566 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
a89bcd4c
HV		 1567 if (is_hdmi(sd)) {
1568 /* adjust for deep color mode */
81ba0a4e 1569 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
a89bcd4c 1570 }
e78d834a
MB		 1571 bt->pixelclock = freq;
1572 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
a89bcd4c 1573 hdmi_read(sd, 0x21);
e78d834a 1574 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
a89bcd4c 1575 hdmi_read(sd, 0x23);
e78d834a 1576 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
a89bcd4c 1577 hdmi_read(sd, 0x25);
e78d834a
MB		 1578 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1579 hdmi_read(sd, 0x2b)) / 2;
1580 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1581 hdmi_read(sd, 0x2f)) / 2;
1582 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1583 hdmi_read(sd, 0x33)) / 2;
1584 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1585 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1586 if (bt->interlaced == V4L2_DV_INTERLACED) {
1587 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1588 hdmi_read(sd, 0x0c);
1589 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1590 hdmi_read(sd, 0x2d)) / 2;
1591 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1592 hdmi_read(sd, 0x31)) / 2;
f8789e6d 1593 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
e78d834a 1594 hdmi_read(sd, 0x35)) / 2;
f888ae7e
HV		 1595 } else {
1596 bt->il_vfrontporch = 0;
1597 bt->il_vsync = 0;
1598 bt->il_vbackporch = 0;
e78d834a
MB		 1599 }
1600 adv7842_fill_optional_dv_timings_fields(sd, timings);
a89bcd4c 1601 } else {
6e9071f2
MB		 1602 /* find format
1603 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1604 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1605 */
1606 if (!stdi2dv_timings(sd, &stdi, timings))
1607 goto found;
1608 stdi.lcvs += 1;
1609 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1610 if (!stdi2dv_timings(sd, &stdi, timings))
1611 goto found;
1612 stdi.lcvs -= 2;
1613 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
a89bcd4c 1614 if (stdi2dv_timings(sd, &stdi, timings)) {
6e9071f2
MB		 1615 /*
1616 * The STDI block may measure wrong values, especially
1617 * for lcvs and lcf. If the driver can not find any
1618 * valid timing, the STDI block is restarted to measure
1619 * the video timings again. The function will return an
1620 * error, but the restart of STDI will generate a new
1621 * STDI interrupt and the format detection process will
1622 * restart.
1623 */
1624 if (state->restart_stdi_once) {
1625 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1626 /* TODO restart STDI for Sync Channel 2 */
1627 /* enter one-shot mode */
1628 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1629 /* trigger STDI restart */
1630 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1631 /* reset to continuous mode */
1632 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1633 state->restart_stdi_once = false;
1634 return -ENOLINK;
1635 }
a89bcd4c
HV		 1636 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1637 return -ERANGE;
1638 }
6e9071f2 1639 state->restart_stdi_once = true;
a89bcd4c 1640 }
6e9071f2 1641found:
a89bcd4c
HV		 1642
1643 if (debug > 1)
6e9071f2
MB		 1644 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1645 timings, true);
a89bcd4c
HV		 1646 return 0;
1647}
1648
1649static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1650 struct v4l2_dv_timings *timings)
1651{
1652 struct adv7842_state *state = to_state(sd);
1653 struct v4l2_bt_timings *bt;
1654 int err;
1655
e78d834a
MB		 1656 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1657
a89bcd4c
HV		 1658 if (state->mode == ADV7842_MODE_SDP)
1659 return -ENODATA;
1660
85f9e06c 1661 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
834a8be1
MB		 1662 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1663 return 0;
1664 }
1665
a89bcd4c
HV		 1666 bt = &timings->bt;
1667
1668 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1669 adv7842_check_dv_timings, NULL))
1670 return -ERANGE;
1671
1672 adv7842_fill_optional_dv_timings_fields(sd, timings);
1673
1674 state->timings = *timings;
1675
6251e65f 1676 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
a89bcd4c
HV		 1677
1678 /* Use prim_mode and vid_std when available */
1679 err = configure_predefined_video_timings(sd, timings);
1680 if (err) {
1681 /* custom settings when the video format
1682 does not have prim_mode/vid_std */
1683 configure_custom_video_timings(sd, bt);
1684 }
1685
1686 set_rgb_quantization_range(sd);
1687
1688
1689 if (debug > 1)
1690 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1691 timings, true);
1692 return 0;
1693}
1694
1695static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1696 struct v4l2_dv_timings *timings)
1697{
1698 struct adv7842_state *state = to_state(sd);
1699
1700 if (state->mode == ADV7842_MODE_SDP)
1701 return -ENODATA;
1702 *timings = state->timings;
1703 return 0;
1704}
1705
1706static void enable_input(struct v4l2_subdev *sd)
1707{
1708 struct adv7842_state *state = to_state(sd);
69e9ba6f
HV		 1709
1710 set_rgb_quantization_range(sd);
a89bcd4c
HV		 1711 switch (state->mode) {
1712 case ADV7842_MODE_SDP:
1713 case ADV7842_MODE_COMP:
1714 case ADV7842_MODE_RGB:
a89bcd4c
HV		 1715 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1716 break;
1717 case ADV7842_MODE_HDMI:
a89bcd4c
HV		 1718 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1719 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5b64b205 1720 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
a89bcd4c
HV		 1721 break;
1722 default:
1723 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1724 __func__, state->mode);
1725 break;
1726 }
1727}
1728
1729static void disable_input(struct v4l2_subdev *sd)
1730{
5b64b205
MR		 1731 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1732 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
a89bcd4c 1733 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
a89bcd4c
HV		 1734 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1735}
1736
1737static void sdp_csc_coeff(struct v4l2_subdev *sd,
1738 const struct adv7842_sdp_csc_coeff *c)
1739{
1740 /* csc auto/manual */
1741 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1742
1743 if (!c->manual)
1744 return;
1745
1746 /* csc scaling */
1747 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1748
1749 /* A coeff */
1750 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1751 sdp_io_write(sd, 0xe1, c->A1);
1752 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1753 sdp_io_write(sd, 0xe3, c->A2);
1754 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1755 sdp_io_write(sd, 0xe5, c->A3);
1756
1757 /* A scale */
1758 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1759 sdp_io_write(sd, 0xe7, c->A4);
1760
1761 /* B coeff */
1762 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1763 sdp_io_write(sd, 0xe9, c->B1);
1764 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1765 sdp_io_write(sd, 0xeb, c->B2);
1766 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1767 sdp_io_write(sd, 0xed, c->B3);
1768
1769 /* B scale */
1770 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1771 sdp_io_write(sd, 0xef, c->B4);
1772
1773 /* C coeff */
1774 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1775 sdp_io_write(sd, 0xf1, c->C1);
1776 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1777 sdp_io_write(sd, 0xf3, c->C2);
1778 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1779 sdp_io_write(sd, 0xf5, c->C3);
1780
1781 /* C scale */
1782 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1783 sdp_io_write(sd, 0xf7, c->C4);
1784}
1785
1786static void select_input(struct v4l2_subdev *sd,
1787 enum adv7842_vid_std_select vid_std_select)
1788{
1789 struct adv7842_state *state = to_state(sd);
1790
1791 switch (state->mode) {
1792 case ADV7842_MODE_SDP:
1793 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1794 io_write(sd, 0x01, 0); /* prim mode */
1795 /* enable embedded syncs for auto graphics mode */
1796 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1797
1798 afe_write(sd, 0x00, 0x00); /* power up ADC */
1799 afe_write(sd, 0xc8, 0x00); /* phase control */
1800
a89bcd4c
HV		 1801 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1802 /* script says register 0xde, which don't exist in manual */
1803
1804 /* Manual analog input muxing mode, CVBS (6.4)*/
1805 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1806 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1807 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1808 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1809 } else {
1810 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1811 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1812 }
1813 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1814 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1815
1816 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1817 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1818
1819 /* SDP recommended settings */
1820 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1821 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1822
1823 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1824 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1825 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1826 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1827 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1828 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1829 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1830
1831 /* deinterlacer enabled and 3D comb */
1832 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1833
a89bcd4c
HV		 1834 break;
1835
1836 case ADV7842_MODE_COMP:
1837 case ADV7842_MODE_RGB:
1838 /* Automatic analog input muxing mode */
1839 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1840 /* set mode and select free run resolution */
1841 io_write(sd, 0x00, vid_std_select); /* video std */
1842 io_write(sd, 0x01, 0x02); /* prim mode */
1843 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1844 for auto graphics mode */
1845
1846 afe_write(sd, 0x00, 0x00); /* power up ADC */
1847 afe_write(sd, 0xc8, 0x00); /* phase control */
69e9ba6f
HV		 1848 if (state->mode == ADV7842_MODE_COMP) {
1849 /* force to YCrCb */
1850 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1851 } else {
1852 /* force to RGB */
1853 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1854 }
a89bcd4c
HV		 1855
1856 /* set ADI recommended settings for digitizer */
1857 /* "ADV7842 Register Settings Recommendations
1858 * (rev. 1.8, November 2010)" p. 9. */
1859 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1860 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1861
1862 /* set to default gain for RGB */
1863 cp_write(sd, 0x73, 0x10);
1864 cp_write(sd, 0x74, 0x04);
1865 cp_write(sd, 0x75, 0x01);
1866 cp_write(sd, 0x76, 0x00);
1867
1868 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1869 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1870 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1871 break;
1872
1873 case ADV7842_MODE_HDMI:
1874 /* Automatic analog input muxing mode */
1875 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1876 /* set mode and select free run resolution */
1877 if (state->hdmi_port_a)
1878 hdmi_write(sd, 0x00, 0x02); /* select port A */
1879 else
1880 hdmi_write(sd, 0x00, 0x03); /* select port B */
1881 io_write(sd, 0x00, vid_std_select); /* video std */
1882 io_write(sd, 0x01, 5); /* prim mode */
1883 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1884 for auto graphics mode */
1885
1886 /* set ADI recommended settings for HDMI: */
1887 /* "ADV7842 Register Settings Recommendations
1888 * (rev. 1.8, November 2010)" p. 3. */
1889 hdmi_write(sd, 0xc0, 0x00);
1890 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1891 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1892 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1894 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1895 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1896 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1897 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1898 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1899 Improve robustness */
1900 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1901 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1902 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1903 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1904 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1905 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1906 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1907 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1908 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1909 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1910
1911 afe_write(sd, 0x00, 0xff); /* power down ADC */
1912 afe_write(sd, 0xc8, 0x40); /* phase control */
1913
1914 /* set to default gain for HDMI */
1915 cp_write(sd, 0x73, 0x10);
1916 cp_write(sd, 0x74, 0x04);
1917 cp_write(sd, 0x75, 0x01);
1918 cp_write(sd, 0x76, 0x00);
1919
1920 /* reset ADI recommended settings for digitizer */
1921 /* "ADV7842 Register Settings Recommendations
1922 * (rev. 2.5, June 2010)" p. 17. */
1923 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1924 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
933913da
MB		 1925 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1926
a89bcd4c
HV		 1927 /* CP coast control */
1928 cp_write(sd, 0xc3, 0x33); /* Component mode */
1929
1930 /* color space conversion, autodetect color space */
1931 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1932 break;
1933
1934 default:
1935 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1936 __func__, state->mode);
1937 break;
1938 }
1939}
1940
1941static int adv7842_s_routing(struct v4l2_subdev *sd,
1942 u32 input, u32 output, u32 config)
1943{
1944 struct adv7842_state *state = to_state(sd);
1945
1946 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1947
1948 switch (input) {
1949 case ADV7842_SELECT_HDMI_PORT_A:
a89bcd4c
HV		 1950 state->mode = ADV7842_MODE_HDMI;
1951 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1952 state->hdmi_port_a = true;
1953 break;
1954 case ADV7842_SELECT_HDMI_PORT_B:
a89bcd4c
HV		 1955 state->mode = ADV7842_MODE_HDMI;
1956 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1957 state->hdmi_port_a = false;
1958 break;
1959 case ADV7842_SELECT_VGA_COMP:
69e9ba6f
HV		 1960 state->mode = ADV7842_MODE_COMP;
1961 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1962 break;
a89bcd4c
HV		 1963 case ADV7842_SELECT_VGA_RGB:
1964 state->mode = ADV7842_MODE_RGB;
1965 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1966 break;
1967 case ADV7842_SELECT_SDP_CVBS:
1968 state->mode = ADV7842_MODE_SDP;
1969 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1970 break;
1971 case ADV7842_SELECT_SDP_YC:
1972 state->mode = ADV7842_MODE_SDP;
1973 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1974 break;
1975 default:
1976 return -EINVAL;
1977 }
1978
1979 disable_input(sd);
1980 select_input(sd, state->vid_std_select);
1981 enable_input(sd);
1982
2cf4090f 1983 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
a89bcd4c
HV		 1984
1985 return 0;
1986}
1987
ebcff5fc
HV		 1988static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1989 struct v4l2_subdev_pad_config *cfg,
1990 struct v4l2_subdev_mbus_code_enum *code)
a89bcd4c 1991{
f888ae7e 1992 if (code->index >= ARRAY_SIZE(adv7842_formats))
a89bcd4c 1993 return -EINVAL;
f888ae7e 1994 code->code = adv7842_formats[code->index].code;
a89bcd4c
HV		 1995 return 0;
1996}
1997
f888ae7e
HV		 1998static void adv7842_fill_format(struct adv7842_state *state,
1999 struct v4l2_mbus_framefmt *format)
2000{
2001 memset(format, 0, sizeof(*format));
2002
2003 format->width = state->timings.bt.width;
2004 format->height = state->timings.bt.height;
2005 format->field = V4L2_FIELD_NONE;
2006 format->colorspace = V4L2_COLORSPACE_SRGB;
2007
2008 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2009 format->colorspace = (state->timings.bt.height <= 576) ?
2010 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2011}
2012
2013/*
2014 * Compute the op_ch_sel value required to obtain on the bus the component order
2015 * corresponding to the selected format taking into account bus reordering
2016 * applied by the board at the output of the device.
2017 *
2018 * The following table gives the op_ch_value from the format component order
2019 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2020 * adv7842_bus_order value in row).
2021 *
2022 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2023 * ----------+-------------------------------------------------
2024 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2025 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2026 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2027 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2028 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2029 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2030 */
2031static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2032{
2033#define _SEL(a, b, c, d, e, f) { \
2034 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2035 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2036#define _BUS(x) [ADV7842_BUS_ORDER_##x]
2037
2038 static const unsigned int op_ch_sel[6][6] = {
2039 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2040 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2041 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2042 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2043 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2044 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2045 };
2046
2047 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2048}
2049
2050static void adv7842_setup_format(struct adv7842_state *state)
2051{
2052 struct v4l2_subdev *sd = &state->sd;
2053
2054 io_write_clr_set(sd, 0x02, 0x02,
2055 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2056 io_write(sd, 0x03, state->format->op_format_sel |
2057 state->pdata.op_format_mode_sel);
2058 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2059 io_write_clr_set(sd, 0x05, 0x01,
2060 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2061}
2062
2063static int adv7842_get_format(struct v4l2_subdev *sd,
2064 struct v4l2_subdev_pad_config *cfg,
2065 struct v4l2_subdev_format *format)
a89bcd4c
HV		 2066{
2067 struct adv7842_state *state = to_state(sd);
2068
f888ae7e 2069 if (format->pad != ADV7842_PAD_SOURCE)
da298c6d
HV		 2070 return -EINVAL;
2071
a89bcd4c
HV		 2072 if (state->mode == ADV7842_MODE_SDP) {
2073 /* SPD block */
f888ae7e 2074 if (!(sdp_read(sd, 0x5a) & 0x01))
a89bcd4c 2075 return -EINVAL;
f888ae7e
HV		 2076 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2077 format->format.width = 720;
a89bcd4c
HV		 2078 /* valid signal */
2079 if (state->norm & V4L2_STD_525_60)
f888ae7e 2080 format->format.height = 480;
a89bcd4c 2081 else
f888ae7e
HV		 2082 format->format.height = 576;
2083 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
a89bcd4c
HV		 2084 return 0;
2085 }
2086
f888ae7e
HV		 2087 adv7842_fill_format(state, &format->format);
2088
2089 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2090 struct v4l2_mbus_framefmt *fmt;
2091
2092 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2093 format->format.code = fmt->code;
2094 } else {
2095 format->format.code = state->format->code;
a89bcd4c 2096 }
f888ae7e
HV		 2097
2098 return 0;
2099}
2100
2101static int adv7842_set_format(struct v4l2_subdev *sd,
2102 struct v4l2_subdev_pad_config *cfg,
2103 struct v4l2_subdev_format *format)
2104{
2105 struct adv7842_state *state = to_state(sd);
2106 const struct adv7842_format_info *info;
2107
2108 if (format->pad != ADV7842_PAD_SOURCE)
2109 return -EINVAL;
2110
2111 if (state->mode == ADV7842_MODE_SDP)
2112 return adv7842_get_format(sd, cfg, format);
2113
2114 info = adv7842_format_info(state, format->format.code);
2115 if (info == NULL)
2116 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2117
2118 adv7842_fill_format(state, &format->format);
2119 format->format.code = info->code;
2120
2121 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2122 struct v4l2_mbus_framefmt *fmt;
2123
2124 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2125 fmt->code = format->format.code;
2126 } else {
2127 state->format = info;
2128 adv7842_setup_format(state);
2129 }
2130
a89bcd4c
HV		 2131 return 0;
2132}
2133
2134static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2135{
2136 if (enable) {
2137 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2138 io_write(sd, 0x46, 0x9c);
2139 /* ESDP_50HZ_DET interrupt */
2140 io_write(sd, 0x5a, 0x10);
2141 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2142 io_write(sd, 0x73, 0x03);
2143 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2144 io_write(sd, 0x78, 0x03);
2145 /* Enable SDP Standard Detection Change and SDP Video Detected */
2146 io_write(sd, 0xa0, 0x09);
019aa8be
MB		 2147 /* Enable HDMI_MODE interrupt */
2148 io_write(sd, 0x69, 0x08);
a89bcd4c
HV		 2149 } else {
2150 io_write(sd, 0x46, 0x0);
2151 io_write(sd, 0x5a, 0x0);
2152 io_write(sd, 0x73, 0x0);
2153 io_write(sd, 0x78, 0x0);
2154 io_write(sd, 0xa0, 0x0);
019aa8be 2155 io_write(sd, 0x69, 0x0);
a89bcd4c
HV		 2156 }
2157}
2158
25c84fb1
HV		 2159#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2160static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2161{
2162 struct adv7842_state *state = to_state(sd);
2163
2164 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2165 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2166 return;
2167 }
2168
2169 if (tx_raw_status & 0x02) {
2170 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2171 __func__);
2172 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2173 1, 0, 0, 0);
2174 return;
2175 }
2176 if (tx_raw_status & 0x04) {
2177 u8 status;
2178 u8 nack_cnt;
2179 u8 low_drive_cnt;
2180
2181 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2182 /*
2183 * We set this status bit since this hardware performs
2184 * retransmissions.
2185 */
2186 status = CEC_TX_STATUS_MAX_RETRIES;
2187 nack_cnt = cec_read(sd, 0x14) & 0xf;
2188 if (nack_cnt)
2189 status |= CEC_TX_STATUS_NACK;
2190 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2191 if (low_drive_cnt)
2192 status |= CEC_TX_STATUS_LOW_DRIVE;
2193 cec_transmit_done(state->cec_adap, status,
2194 0, nack_cnt, low_drive_cnt, 0);
2195 return;
2196 }
2197 if (tx_raw_status & 0x01) {
2198 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2199 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2200 return;
2201 }
2202}
2203
2204static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2205{
2206 u8 cec_irq;
2207
2208 /* cec controller */
2209 cec_irq = io_read(sd, 0x93) & 0x0f;
2210 if (!cec_irq)
2211 return;
2212
2213 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2214 adv7842_cec_tx_raw_status(sd, cec_irq);
2215 if (cec_irq & 0x08) {
2216 struct adv7842_state *state = to_state(sd);
2217 struct cec_msg msg;
2218
2219 msg.len = cec_read(sd, 0x25) & 0x1f;
2220 if (msg.len > 16)
2221 msg.len = 16;
2222
2223 if (msg.len) {
2224 u8 i;
2225
2226 for (i = 0; i < msg.len; i++)
2227 msg.msg[i] = cec_read(sd, i + 0x15);
2228 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2229 cec_received_msg(state->cec_adap, &msg);
2230 }
2231 }
2232
2233 io_write(sd, 0x94, cec_irq);
2234
2235 if (handled)
2236 *handled = true;
2237}
2238
2239static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2240{
2241 struct adv7842_state *state = adap->priv;
2242 struct v4l2_subdev *sd = &state->sd;
2243
2244 if (!state->cec_enabled_adap && enable) {
2245 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2246 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2247 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2248 /* enabled irqs: */
2249 /* tx: ready */
2250 /* tx: arbitration lost */
2251 /* tx: retry timeout */
2252 /* rx: ready */
2253 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2254 cec_write(sd, 0x26, 0x01); /* enable rx */
2255 } else if (state->cec_enabled_adap && !enable) {
2256 /* disable cec interrupts */
2257 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2258 /* disable address mask 1-3 */
2259 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2260 /* power down cec section */
2261 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2262 state->cec_valid_addrs = 0;
2263 }
2264 state->cec_enabled_adap = enable;
2265 return 0;
2266}
2267
2268static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2269{
2270 struct adv7842_state *state = adap->priv;
2271 struct v4l2_subdev *sd = &state->sd;
2272 unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2273
2274 if (!state->cec_enabled_adap)
2275 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2276
2277 if (addr == CEC_LOG_ADDR_INVALID) {
2278 cec_write_clr_set(sd, 0x27, 0x70, 0);
2279 state->cec_valid_addrs = 0;
2280 return 0;
2281 }
2282
2283 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2284 bool is_valid = state->cec_valid_addrs & (1 << i);
2285
2286 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2287 free_idx = i;
2288 if (is_valid && state->cec_addr[i] == addr)
2289 return 0;
2290 }
2291 if (i == ADV7842_MAX_ADDRS) {
2292 i = free_idx;
2293 if (i == ADV7842_MAX_ADDRS)
2294 return -ENXIO;
2295 }
2296 state->cec_addr[i] = addr;
2297 state->cec_valid_addrs |= 1 << i;
2298
2299 switch (i) {
2300 case 0:
2301 /* enable address mask 0 */
2302 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2303 /* set address for mask 0 */
2304 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2305 break;
2306 case 1:
2307 /* enable address mask 1 */
2308 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2309 /* set address for mask 1 */
2310 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2311 break;
2312 case 2:
2313 /* enable address mask 2 */
2314 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2315 /* set address for mask 1 */
2316 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2317 break;
2318 }
2319 return 0;
2320}
2321
2322static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2323 u32 signal_free_time, struct cec_msg *msg)
2324{
2325 struct adv7842_state *state = adap->priv;
2326 struct v4l2_subdev *sd = &state->sd;
2327 u8 len = msg->len;
2328 unsigned int i;
2329
2330 /*
2331 * The number of retries is the number of attempts - 1, but retry
2332 * at least once. It's not clear if a value of 0 is allowed, so
2333 * let's do at least one retry.
2334 */
2335 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2336
2337 if (len > 16) {
2338 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2339 return -EINVAL;
2340 }
2341
2342 /* write data */
2343 for (i = 0; i < len; i++)
2344 cec_write(sd, i, msg->msg[i]);
2345
2346 /* set length (data + header) */
2347 cec_write(sd, 0x10, len);
2348 /* start transmit, enable tx */
2349 cec_write(sd, 0x11, 0x01);
2350 return 0;
2351}
2352
2353static const struct cec_adap_ops adv7842_cec_adap_ops = {
2354 .adap_enable = adv7842_cec_adap_enable,
2355 .adap_log_addr = adv7842_cec_adap_log_addr,
2356 .adap_transmit = adv7842_cec_adap_transmit,
2357};
2358#endif
2359
a89bcd4c
HV		 2360static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2361{
2362 struct adv7842_state *state = to_state(sd);
2363 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
019aa8be 2364 u8 irq_status[6];
a89bcd4c 2365
c9f1f271 2366 adv7842_irq_enable(sd, false);
a89bcd4c
HV		 2367
2368 /* read status */
2369 irq_status[0] = io_read(sd, 0x43);
2370 irq_status[1] = io_read(sd, 0x57);
2371 irq_status[2] = io_read(sd, 0x70);
2372 irq_status[3] = io_read(sd, 0x75);
2373 irq_status[4] = io_read(sd, 0x9d);
019aa8be 2374 irq_status[5] = io_read(sd, 0x66);
a89bcd4c
HV		 2375
2376 /* and clear */
2377 if (irq_status[0])
2378 io_write(sd, 0x44, irq_status[0]);
2379 if (irq_status[1])
2380 io_write(sd, 0x58, irq_status[1]);
2381 if (irq_status[2])
2382 io_write(sd, 0x71, irq_status[2]);
2383 if (irq_status[3])
2384 io_write(sd, 0x76, irq_status[3]);
2385 if (irq_status[4])
2386 io_write(sd, 0x9e, irq_status[4]);
019aa8be
MB		 2387 if (irq_status[5])
2388 io_write(sd, 0x67, irq_status[5]);
a89bcd4c 2389
c9f1f271
MB		 2390 adv7842_irq_enable(sd, true);
2391
019aa8be 2392 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
a89bcd4c 2393 irq_status[0], irq_status[1], irq_status[2],
019aa8be 2394 irq_status[3], irq_status[4], irq_status[5]);
a89bcd4c
HV		 2395
2396 /* format change CP */
2397 fmt_change_cp = irq_status[0] & 0x9c;
2398
2399 /* format change SDP */
2400 if (state->mode == ADV7842_MODE_SDP)
2401 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2402 else
2403 fmt_change_sdp = 0;
2404
2405 /* digital format CP */
2406 if (is_digital_input(sd))
2407 fmt_change_digital = irq_status[3] & 0x03;
2408 else
2409 fmt_change_digital = 0;
2410
019aa8be 2411 /* format change */
a89bcd4c
HV		 2412 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2413 v4l2_dbg(1, debug, sd,
2414 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2415 __func__, fmt_change_cp, fmt_change_digital,
2416 fmt_change_sdp);
2cf4090f 2417 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
019aa8be
MB		 2418 if (handled)
2419 *handled = true;
a89bcd4c
HV		 2420 }
2421
019aa8be
MB		 2422 /* HDMI/DVI mode */
2423 if (irq_status[5] & 0x08) {
2424 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2425 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
5046f26b 2426 set_rgb_quantization_range(sd);
019aa8be
MB		 2427 if (handled)
2428 *handled = true;
2429 }
a89bcd4c 2430
25c84fb1
HV		 2431#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2432 /* cec */
2433 adv7842_cec_isr(sd, handled);
2434#endif
2435
019aa8be
MB		 2436 /* tx 5v detect */
2437 if (irq_status[2] & 0x3) {
2438 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2439 adv7842_s_detect_tx_5v_ctrl(sd);
2440 if (handled)
2441 *handled = true;
2442 }
a89bcd4c
HV		 2443 return 0;
2444}
2445
b09dfac8 2446static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
245b2b67
MB		 2447{
2448 struct adv7842_state *state = to_state(sd);
2449 u8 *data = NULL;
2450
c909e5ba 2451 memset(edid->reserved, 0, sizeof(edid->reserved));
245b2b67
MB		 2452
2453 switch (edid->pad) {
2454 case ADV7842_EDID_PORT_A:
2455 case ADV7842_EDID_PORT_B:
2456 if (state->hdmi_edid.present & (0x04 << edid->pad))
2457 data = state->hdmi_edid.edid;
2458 break;
2459 case ADV7842_EDID_PORT_VGA:
2460 if (state->vga_edid.present)
2461 data = state->vga_edid.edid;
2462 break;
2463 default:
2464 return -EINVAL;
2465 }
c909e5ba
HV		 2466
2467 if (edid->start_block == 0 && edid->blocks == 0) {
2468 edid->blocks = data ? 2 : 0;
2469 return 0;
2470 }
2471
245b2b67
MB		 2472 if (!data)
2473 return -ENODATA;
2474
c909e5ba
HV		 2475 if (edid->start_block >= 2)
2476 return -EINVAL;
2477
2478 if (edid->start_block + edid->blocks > 2)
2479 edid->blocks = 2 - edid->start_block;
2480
2481 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2482
245b2b67
MB		 2483 return 0;
2484}
2485
b09dfac8 2486static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
a89bcd4c
HV		 2487{
2488 struct adv7842_state *state = to_state(sd);
2489 int err = 0;
2490
c909e5ba
HV		 2491 memset(e->reserved, 0, sizeof(e->reserved));
2492
7de6fab1 2493 if (e->pad > ADV7842_EDID_PORT_VGA)
a89bcd4c
HV		 2494 return -EINVAL;
2495 if (e->start_block != 0)
2496 return -EINVAL;
c909e5ba
HV		 2497 if (e->blocks > 2) {
2498 e->blocks = 2;
a89bcd4c 2499 return -E2BIG;
c909e5ba 2500 }
a89bcd4c
HV		 2501
2502 /* todo, per edid */
2503 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2504 e->edid[0x16]);
2505
7de6fab1
MR		 2506 switch (e->pad) {
2507 case ADV7842_EDID_PORT_VGA:
a89bcd4c
HV		 2508 memset(&state->vga_edid.edid, 0, 256);
2509 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2510 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2511 err = edid_write_vga_segment(sd);
7de6fab1
MR		 2512 break;
2513 case ADV7842_EDID_PORT_A:
2514 case ADV7842_EDID_PORT_B:
a89bcd4c 2515 memset(&state->hdmi_edid.edid, 0, 256);
25c84fb1 2516 if (e->blocks) {
7de6fab1 2517 state->hdmi_edid.present |= 0x04 << e->pad;
25c84fb1 2518 } else {
7de6fab1 2519 state->hdmi_edid.present &= ~(0x04 << e->pad);
25c84fb1
HV		 2520 adv7842_s_detect_tx_5v_ctrl(sd);
2521 }
7de6fab1 2522 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
a89bcd4c 2523 err = edid_write_hdmi_segment(sd, e->pad);
7de6fab1
MR		 2524 break;
2525 default:
2526 return -EINVAL;
a89bcd4c
HV		 2527 }
2528 if (err < 0)
2529 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2530 return err;
2531}
2532
09f90c53
MB		 2533struct adv7842_cfg_read_infoframe {
2534 const char *desc;
2535 u8 present_mask;
2536 u8 head_addr;
2537 u8 payload_addr;
a89bcd4c
HV		 2538};
2539
09f90c53 2540static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
a89bcd4c
HV		 2541{
2542 int i;
28a769f1 2543 u8 buffer[32];
09f90c53
MB		 2544 union hdmi_infoframe frame;
2545 u8 len;
2546 struct i2c_client *client = v4l2_get_subdevdata(sd);
2547 struct device *dev = &client->dev;
a89bcd4c 2548
09f90c53
MB		 2549 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2550 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
a89bcd4c
HV		 2551 return;
2552 }
2553
09f90c53
MB		 2554 for (i = 0; i < 3; i++)
2555 buffer[i] = infoframe_read(sd, cri->head_addr + i);
a89bcd4c 2556
09f90c53 2557 len = buffer[2] + 1;
a89bcd4c 2558
09f90c53
MB		 2559 if (len + 3 > sizeof(buffer)) {
2560 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
a89bcd4c 2561 return;
09f90c53 2562 }
a89bcd4c 2563
09f90c53
MB		 2564 for (i = 0; i < len; i++)
2565 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
a89bcd4c 2566
09f90c53
MB		 2567 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2568 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2569 return;
2570 }
a89bcd4c 2571
09f90c53
MB		 2572 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2573}
a89bcd4c 2574
09f90c53
MB		 2575static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2576{
2577 int i;
2578 struct adv7842_cfg_read_infoframe cri[] = {
2579 { "AVI", 0x01, 0xe0, 0x00 },
2580 { "Audio", 0x02, 0xe3, 0x1c },
2581 { "SDP", 0x04, 0xe6, 0x2a },
2582 { "Vendor", 0x10, 0xec, 0x54 }
2583 };
a89bcd4c 2584
09f90c53
MB		 2585 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2586 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2587 return;
2588 }
2589
2590 for (i = 0; i < ARRAY_SIZE(cri); i++)
2591 log_infoframe(sd, &cri[i]);
a89bcd4c
HV		 2592}
2593
60eb9579
MCC		 2594#if 0
2595/* Let's keep it here for now, as it could be useful for debug */
a89bcd4c
HV		 2596static const char * const prim_mode_txt[] = {
2597 "SDP",
2598 "Component",
2599 "Graphics",
2600 "Reserved",
2601 "CVBS & HDMI AUDIO",
2602 "HDMI-Comp",
2603 "HDMI-GR",
2604 "Reserved",
2605 "Reserved",
2606 "Reserved",
2607 "Reserved",
2608 "Reserved",
2609 "Reserved",
2610 "Reserved",
2611 "Reserved",
2612 "Reserved",
2613};
60eb9579 2614#endif
a89bcd4c
HV		 2615
2616static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2617{
2618 /* SDP (Standard definition processor) block */
28a769f1 2619 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
a89bcd4c
HV		 2620
2621 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2622 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2623 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2624
2625 v4l2_info(sd, "SDP: free run: %s\n",
2626 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2627 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2628 "valid SD/PR signal detected" : "invalid/no signal");
2629 if (sdp_signal_detected) {
2630 static const char * const sdp_std_txt[] = {
2631 "NTSC-M/J",
2632 "1?",
2633 "NTSC-443",
2634 "60HzSECAM",
2635 "PAL-M",
2636 "5?",
2637 "PAL-60",
2638 "7?", "8?", "9?", "a?", "b?",
2639 "PAL-CombN",
2640 "d?",
2641 "PAL-BGHID",
2642 "SECAM"
2643 };
2644 v4l2_info(sd, "SDP: standard %s\n",
2645 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2646 v4l2_info(sd, "SDP: %s\n",
2647 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2648 v4l2_info(sd, "SDP: %s\n",
2649 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2650 v4l2_info(sd, "SDP: deinterlacer %s\n",
2651 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2652 v4l2_info(sd, "SDP: csc %s mode\n",
2653 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2654 }
2655 return 0;
2656}
2657
2658static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2659{
2660 /* CP block */
2661 struct adv7842_state *state = to_state(sd);
2662 struct v4l2_dv_timings timings;
28a769f1
HV		 2663 u8 reg_io_0x02 = io_read(sd, 0x02);
2664 u8 reg_io_0x21 = io_read(sd, 0x21);
2665 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2666 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
a89bcd4c
HV		 2667 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2668 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2669 bool audio_mute = io_read(sd, 0x65) & 0x40;
2670
2671 static const char * const csc_coeff_sel_rb[16] = {
2672 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2673 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2674 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2675 "reserved", "reserved", "reserved", "reserved", "manual"
2676 };
2677 static const char * const input_color_space_txt[16] = {
2678 "RGB limited range (16-235)", "RGB full range (0-255)",
2679 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
69e9ba6f 2680 "xvYCC Bt.601", "xvYCC Bt.709",
a89bcd4c
HV		 2681 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2682 "invalid", "invalid", "invalid", "invalid", "invalid",
2683 "invalid", "invalid", "automatic"
2684 };
2685 static const char * const rgb_quantization_range_txt[] = {
2686 "Automatic",
2687 "RGB limited range (16-235)",
2688 "RGB full range (0-255)",
2689 };
2690 static const char * const deep_color_mode_txt[4] = {
2691 "8-bits per channel",
2692 "10-bits per channel",
2693 "12-bits per channel",
2694 "16-bits per channel (not supported)"
2695 };
2696
2697 v4l2_info(sd, "-----Chip status-----\n");
2698 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
a89bcd4c
HV		 2699 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2700 state->hdmi_port_a ? "A" : "B");
2701 v4l2_info(sd, "EDID A %s, B %s\n",
2702 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2703 "enabled" : "disabled",
2704 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2705 "enabled" : "disabled");
2706 v4l2_info(sd, "HPD A %s, B %s\n",
2707 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2708 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
25c84fb1 2709 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
a89bcd4c 2710 "enabled" : "disabled");
25c84fb1
HV		 2711 if (state->cec_enabled_adap) {
2712 int i;
2713
2714 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2715 bool is_valid = state->cec_valid_addrs & (1 << i);
2716
2717 if (is_valid)
2718 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2719 state->cec_addr[i]);
2720 }
2721 }
a89bcd4c
HV		 2722
2723 v4l2_info(sd, "-----Signal status-----\n");
2724 if (state->hdmi_port_a) {
2725 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2726 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2727 v4l2_info(sd, "TMDS signal detected: %s\n",
2728 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2729 v4l2_info(sd, "TMDS signal locked: %s\n",
2730 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2731 } else {
2732 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2733 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2734 v4l2_info(sd, "TMDS signal detected: %s\n",
2735 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2736 v4l2_info(sd, "TMDS signal locked: %s\n",
2737 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2738 }
2739 v4l2_info(sd, "CP free run: %s\n",
2740 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2741 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2742 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2743 (io_read(sd, 0x01) & 0x70) >> 4);
2744
2745 v4l2_info(sd, "-----Video Timings-----\n");
2746 if (no_cp_signal(sd)) {
2747 v4l2_info(sd, "STDI: not locked\n");
2748 } else {
28a769f1
HV		 2749 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2750 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2751 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2752 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
a89bcd4c
HV		 2753 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2754 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2755 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2756 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2757 v4l2_info(sd,
2758 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2759 lcf, bl, lcvs, fcl,
2760 (cp_read(sd, 0xb1) & 0x40) ?
2761 "interlaced" : "progressive",
2762 hs_pol, vs_pol);
2763 }
2764 if (adv7842_query_dv_timings(sd, &timings))
2765 v4l2_info(sd, "No video detected\n");
2766 else
2767 v4l2_print_dv_timings(sd->name, "Detected format: ",
2768 &timings, true);
2769 v4l2_print_dv_timings(sd->name, "Configured format: ",
2770 &state->timings, true);
2771
2772 if (no_cp_signal(sd))
2773 return 0;
2774
2775 v4l2_info(sd, "-----Color space-----\n");
2776 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2777 rgb_quantization_range_txt[state->rgb_quantization_range]);
2778 v4l2_info(sd, "Input color space: %s\n",
2779 input_color_space_txt[reg_io_0x02 >> 4]);
2780 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2781 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2782 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2783 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2784 "enabled" : "disabled");
2785 v4l2_info(sd, "Color space conversion: %s\n",
2786 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2787
2788 if (!is_digital_input(sd))
2789 return 0;
2790
2791 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2792 v4l2_info(sd, "HDCP encrypted content: %s\n",
2793 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2794 v4l2_info(sd, "HDCP keys read: %s%s\n",
2795 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2796 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2797 if (!is_hdmi(sd))
2798 return 0;
2799
2800 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2801 audio_pll_locked ? "locked" : "not locked",
2802 audio_sample_packet_detect ? "detected" : "not detected",
2803 audio_mute ? "muted" : "enabled");
2804 if (audio_pll_locked && audio_sample_packet_detect) {
2805 v4l2_info(sd, "Audio format: %s\n",
2806 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2807 }
2808 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2809 (hdmi_read(sd, 0x5c) << 8) +
2810 (hdmi_read(sd, 0x5d) & 0xf0));
2811 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2812 (hdmi_read(sd, 0x5e) << 8) +
2813 hdmi_read(sd, 0x5f));
2814 v4l2_info(sd, "AV Mute: %s\n",
2815 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2816 v4l2_info(sd, "Deep color mode: %s\n",
2817 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2818
09f90c53
MB		 2819 adv7842_log_infoframes(sd);
2820
a89bcd4c
HV		 2821 return 0;
2822}
2823
2824static int adv7842_log_status(struct v4l2_subdev *sd)
2825{
2826 struct adv7842_state *state = to_state(sd);
2827
2828 if (state->mode == ADV7842_MODE_SDP)
2829 return adv7842_sdp_log_status(sd);
2830 return adv7842_cp_log_status(sd);
2831}
2832
2833static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2834{
2835 struct adv7842_state *state = to_state(sd);
2836
2837 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2838
2839 if (state->mode != ADV7842_MODE_SDP)
2840 return -ENODATA;
2841
2842 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2843 *std = 0;
2844 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2845 return 0;
2846 }
2847
2848 switch (sdp_read(sd, 0x52) & 0x0f) {
2849 case 0:
2850 /* NTSC-M/J */
2851 *std &= V4L2_STD_NTSC;
2852 break;
2853 case 2:
2854 /* NTSC-443 */
2855 *std &= V4L2_STD_NTSC_443;
2856 break;
2857 case 3:
2858 /* 60HzSECAM */
2859 *std &= V4L2_STD_SECAM;
2860 break;
2861 case 4:
2862 /* PAL-M */
2863 *std &= V4L2_STD_PAL_M;
2864 break;
2865 case 6:
2866 /* PAL-60 */
2867 *std &= V4L2_STD_PAL_60;
2868 break;
2869 case 0xc:
2870 /* PAL-CombN */
2871 *std &= V4L2_STD_PAL_Nc;
2872 break;
2873 case 0xe:
2874 /* PAL-BGHID */
2875 *std &= V4L2_STD_PAL;
2876 break;
2877 case 0xf:
2878 /* SECAM */
2879 *std &= V4L2_STD_SECAM;
2880 break;
2881 default:
2882 *std &= V4L2_STD_ALL;
2883 break;
2884 }
2885 return 0;
2886}
2887
3c4da74f
MB		 2888static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2889{
2890 if (s && s->adjust) {
2891 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2892 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2893 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2894 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2895 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2896 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2897 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2898 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
15058aac
MB		 2899 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2900 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2901 sdp_io_write(sd, 0xaa, s->vs_end_o);
2902 sdp_io_write(sd, 0xab, s->vs_end_e);
3c4da74f
MB		 2903 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2904 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2905 sdp_io_write(sd, 0xae, s->de_v_end_o);
2906 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2907 } else {
2908 /* set to default */
2909 sdp_io_write(sd, 0x94, 0x00);
2910 sdp_io_write(sd, 0x95, 0x00);
2911 sdp_io_write(sd, 0x96, 0x00);
2912 sdp_io_write(sd, 0x97, 0x20);
2913 sdp_io_write(sd, 0x98, 0x00);
2914 sdp_io_write(sd, 0x99, 0x00);
2915 sdp_io_write(sd, 0x9a, 0x00);
2916 sdp_io_write(sd, 0x9b, 0x00);
15058aac
MB		 2917 sdp_io_write(sd, 0xa8, 0x04);
2918 sdp_io_write(sd, 0xa9, 0x04);
2919 sdp_io_write(sd, 0xaa, 0x04);
2920 sdp_io_write(sd, 0xab, 0x04);
3c4da74f
MB		 2921 sdp_io_write(sd, 0xac, 0x04);
2922 sdp_io_write(sd, 0xad, 0x04);
2923 sdp_io_write(sd, 0xae, 0x04);
2924 sdp_io_write(sd, 0xaf, 0x04);
2925 }
2926}
2927
a89bcd4c
HV		 2928static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2929{
2930 struct adv7842_state *state = to_state(sd);
3c4da74f 2931 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2932
2933 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2934
2935 if (state->mode != ADV7842_MODE_SDP)
2936 return -ENODATA;
2937
3c4da74f
MB		 2938 if (norm & V4L2_STD_625_50)
2939 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2940 else if (norm & V4L2_STD_525_60)
2941 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2942 else
2943 adv7842_s_sdp_io(sd, NULL);
2944
a89bcd4c
HV		 2945 if (norm & V4L2_STD_ALL) {
2946 state->norm = norm;
2947 return 0;
2948 }
2949 return -EINVAL;
2950}
2951
2952static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2953{
2954 struct adv7842_state *state = to_state(sd);
2955
2956 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2957
2958 if (state->mode != ADV7842_MODE_SDP)
2959 return -ENODATA;
2960
2961 *norm = state->norm;
2962 return 0;
2963}
2964
2965/* ----------------------------------------------------------------------- */
2966
69e9ba6f 2967static int adv7842_core_init(struct v4l2_subdev *sd)
a89bcd4c 2968{
69e9ba6f
HV		 2969 struct adv7842_state *state = to_state(sd);
2970 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2971 hdmi_write(sd, 0x48,
2972 (pdata->disable_pwrdnb ? 0x80 : 0) |
2973 (pdata->disable_cable_det_rst ? 0x40 : 0));
2974
2975 disable_input(sd);
2976
2ff0f16d
MB		 2977 /*
2978 * Disable I2C access to internal EDID ram from HDMI DDC ports
2979 * Disable auto edid enable when leaving powerdown mode
2980 */
2981 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2982
a89bcd4c
HV		 2983 /* power */
2984 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2985 io_write(sd, 0x15, 0x80); /* Power up pads */
2986
2987 /* video format */
2988 io_write(sd, 0x02,
69e9ba6f 2989 0xf0 |
a89bcd4c
HV		 2990 pdata->alt_gamma << 3 |
2991 pdata->op_656_range << 2 |
a89bcd4c 2992 pdata->alt_data_sat << 0);
a89bcd4c
HV		 2993 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2994 pdata->insert_av_codes << 2 |
f888ae7e
HV		 2995 pdata->replicate_av_codes << 1);
2996 adv7842_setup_format(state);
a89bcd4c 2997
5b64b205
MR		 2998 /* HDMI audio */
2999 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3000
a89bcd4c 3001 /* Drive strength */
7f95c904
HV		 3002 io_write_and_or(sd, 0x14, 0xc0,
3003 pdata->dr_str_data << 4 |
3004 pdata->dr_str_clk << 2 |
3005 pdata->dr_str_sync);
a89bcd4c
HV		 3006
3007 /* HDMI free run */
f0ec1742
MB		 3008 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3009 (pdata->hdmi_free_run_mode << 1));
3010
3011 /* SPD free run */
3012 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3013 (pdata->sdp_free_run_cbar_en << 1) |
3014 (pdata->sdp_free_run_man_col_en << 2) |
57f0547f 3015 (pdata->sdp_free_run_auto << 3));
a89bcd4c
HV		 3016
3017 /* TODO from platform data */
3018 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3019 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3020 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3021 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3022
3023 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3024 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3025
3026 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3027
a89bcd4c
HV		 3028 /* todo, improve settings for sdram */
3029 if (pdata->sd_ram_size >= 128) {
3030 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3031 if (pdata->sd_ram_ddr) {
3032 /* SDP setup for the AD eval board */
3033 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3034 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3035 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3036 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3037 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3038 } else {
3039 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3040 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3041 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3042 depends on memory */
3043 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3044 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3045 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3046 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3047 }
3048 } else {
3049 /*
3050 * Manual UG-214, rev 0 is bit confusing on this bit
3051 * but a '1' disables any signal if the Ram is active.
3052 */
3053 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3054 }
3055
3056 select_input(sd, pdata->vid_std_select);
3057
3058 enable_input(sd);
3059
ce2d2b2d
MB		 3060 if (pdata->hpa_auto) {
3061 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
3062 hdmi_write(sd, 0x69, 0x5c);
3063 } else {
3064 /* HPA manual */
3065 hdmi_write(sd, 0x69, 0xa3);
3066 /* HPA disable on port A and B */
3067 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3068 }
a89bcd4c
HV		 3069
3070 /* LLC */
fe808f3c 3071 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
a89bcd4c
HV		 3072 io_write(sd, 0x33, 0x40);
3073
3074 /* interrupts */
c9f1f271 3075 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
a89bcd4c
HV		 3076
3077 adv7842_irq_enable(sd, true);
3078
3079 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3080}
3081
3082/* ----------------------------------------------------------------------- */
3083
3084static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3085{
3086 /*
3087 * From ADV784x external Memory test.pdf
3088 *
3089 * Reset must just been performed before running test.
3090 * Recommended to reset after test.
3091 */
3092 int i;
3093 int pass = 0;
3094 int fail = 0;
3095 int complete = 0;
3096
3097 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3098 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3099 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
3100 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
3101 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
3102 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
3103 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
3104 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3105 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3106 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3107 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3108 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3109
3110 mdelay(5);
3111
3112 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3113 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3114 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3115 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3116 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3117 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3118 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3119 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3120 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3121 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3122 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3123
3124 mdelay(5);
3125
3126 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3127 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3128
3129 mdelay(20);
3130
3131 for (i = 0; i < 10; i++) {
3132 u8 result = sdp_io_read(sd, 0xdb);
3133 if (result & 0x10) {
3134 complete++;
3135 if (result & 0x20)
3136 fail++;
3137 else
3138 pass++;
3139 }
3140 mdelay(20);
3141 }
3142
3143 v4l2_dbg(1, debug, sd,
3144 "Ram Test: completed %d of %d: pass %d, fail %d\n",
3145 complete, i, pass, fail);
3146
3147 if (!complete || fail)
3148 return -EIO;
3149 return 0;
3150}
3151
3152static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3153 struct adv7842_platform_data *pdata)
3154{
3155 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3156 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3157 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3158 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3159 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3160
3161 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3162 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3163 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3164 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3165
3166 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3167 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3168}
3169
3170static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3171{
3172 struct i2c_client *client = v4l2_get_subdevdata(sd);
3173 struct adv7842_state *state = to_state(sd);
3174 struct adv7842_platform_data *pdata = client->dev.platform_data;
1961b720 3175 struct v4l2_dv_timings timings;
a89bcd4c
HV		 3176 int ret = 0;
3177
3178 if (!pdata)
3179 return -ENODEV;
3180
3181 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3182 v4l2_info(sd, "no sdram or no ddr sdram\n");
3183 return -EINVAL;
3184 }
3185
3186 main_reset(sd);
3187
3188 adv7842_rewrite_i2c_addresses(sd, pdata);
3189
3190 /* run ram test */
3191 ret = adv7842_ddr_ram_test(sd);
3192
3193 main_reset(sd);
3194
3195 adv7842_rewrite_i2c_addresses(sd, pdata);
3196
3197 /* and re-init chip and state */
69e9ba6f 3198 adv7842_core_init(sd);
a89bcd4c
HV		 3199
3200 disable_input(sd);
3201
3202 select_input(sd, state->vid_std_select);
3203
3204 enable_input(sd);
3205
a89bcd4c 3206 edid_write_vga_segment(sd);
fc2e991e
MB		 3207 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3208 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
a89bcd4c 3209
1961b720
MB		 3210 timings = state->timings;
3211
3212 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3213
3214 adv7842_s_dv_timings(sd, &timings);
3215
a89bcd4c
HV		 3216 return ret;
3217}
3218
3219static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3220{
3221 switch (cmd) {
3222 case ADV7842_CMD_RAM_TEST:
3223 return adv7842_command_ram_test(sd);
3224 }
3225 return -ENOTTY;
3226}
3227
2cf4090f
LPC		 3228static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3229 struct v4l2_fh *fh,
3230 struct v4l2_event_subscription *sub)
3231{
3232 switch (sub->type) {
3233 case V4L2_EVENT_SOURCE_CHANGE:
3234 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3235 case V4L2_EVENT_CTRL:
3236 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3237 default:
3238 return -EINVAL;
3239 }
3240}
3241
25c84fb1
HV		 3242static int adv7842_registered(struct v4l2_subdev *sd)
3243{
3244 struct adv7842_state *state = to_state(sd);
3245 int err;
3246
3247 err = cec_register_adapter(state->cec_adap);
3248 if (err)
3249 cec_delete_adapter(state->cec_adap);
3250 return err;
3251}
3252
3253static void adv7842_unregistered(struct v4l2_subdev *sd)
3254{
3255 struct adv7842_state *state = to_state(sd);
3256
3257 cec_unregister_adapter(state->cec_adap);
3258}
3259
a89bcd4c
HV		 3260/* ----------------------------------------------------------------------- */
3261
3262static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3263 .s_ctrl = adv7842_s_ctrl,
e8979274 3264 .g_volatile_ctrl = adv7842_g_volatile_ctrl,
a89bcd4c
HV		 3265};
3266
3267static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3268 .log_status = adv7842_log_status,
a89bcd4c
HV		 3269 .ioctl = adv7842_ioctl,
3270 .interrupt_service_routine = adv7842_isr,
2cf4090f 3271 .subscribe_event = adv7842_subscribe_event,
aef5159f 3272 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
a89bcd4c
HV		 3273#ifdef CONFIG_VIDEO_ADV_DEBUG
3274 .g_register = adv7842_g_register,
3275 .s_register = adv7842_s_register,
3276#endif
3277};
3278
3279static const struct v4l2_subdev_video_ops adv7842_video_ops = {
8774bed9
LP		 3280 .g_std = adv7842_g_std,
3281 .s_std = adv7842_s_std,
a89bcd4c
HV		 3282 .s_routing = adv7842_s_routing,
3283 .querystd = adv7842_querystd,
3284 .g_input_status = adv7842_g_input_status,
3285 .s_dv_timings = adv7842_s_dv_timings,
3286 .g_dv_timings = adv7842_g_dv_timings,
3287 .query_dv_timings = adv7842_query_dv_timings,
a89bcd4c
HV		 3288};
3289
3290static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
f888ae7e
HV		 3291 .enum_mbus_code = adv7842_enum_mbus_code,
3292 .get_fmt = adv7842_get_format,
3293 .set_fmt = adv7842_set_format,
245b2b67 3294 .get_edid = adv7842_get_edid,
a89bcd4c 3295 .set_edid = adv7842_set_edid,
c916194c
LP		 3296 .enum_dv_timings = adv7842_enum_dv_timings,
3297 .dv_timings_cap = adv7842_dv_timings_cap,
a89bcd4c
HV		 3298};
3299
3300static const struct v4l2_subdev_ops adv7842_ops = {
3301 .core = &adv7842_core_ops,
3302 .video = &adv7842_video_ops,
3303 .pad = &adv7842_pad_ops,
3304};
3305
25c84fb1
HV		 3306static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3307 .registered = adv7842_registered,
3308 .unregistered = adv7842_unregistered,
3309};
3310
a89bcd4c
HV		 3311/* -------------------------- custom ctrls ---------------------------------- */
3312
3313static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3314 .ops = &adv7842_ctrl_ops,
3315 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3316 .name = "Analog Sampling Phase",
3317 .type = V4L2_CTRL_TYPE_INTEGER,
3318 .min = 0,
3319 .max = 0x1f,
3320 .step = 1,
3321 .def = 0,
3322};
3323
3324static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3325 .ops = &adv7842_ctrl_ops,
3326 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3327 .name = "Free Running Color, Manual",
3328 .type = V4L2_CTRL_TYPE_BOOLEAN,
3329 .max = 1,
3330 .step = 1,
3331 .def = 1,
3332};
3333
3334static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3335 .ops = &adv7842_ctrl_ops,
3336 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3337 .name = "Free Running Color",
3338 .type = V4L2_CTRL_TYPE_INTEGER,
3339 .max = 0xffffff,
3340 .step = 0x1,
3341};
3342
3343
b82e2793 3344static void adv7842_unregister_clients(struct v4l2_subdev *sd)
a89bcd4c 3345{
b82e2793 3346 struct adv7842_state *state = to_state(sd);
a89bcd4c
HV		 3347 if (state->i2c_avlink)
3348 i2c_unregister_device(state->i2c_avlink);
3349 if (state->i2c_cec)
3350 i2c_unregister_device(state->i2c_cec);
3351 if (state->i2c_infoframe)
3352 i2c_unregister_device(state->i2c_infoframe);
3353 if (state->i2c_sdp_io)
3354 i2c_unregister_device(state->i2c_sdp_io);
3355 if (state->i2c_sdp)
3356 i2c_unregister_device(state->i2c_sdp);
3357 if (state->i2c_afe)
3358 i2c_unregister_device(state->i2c_afe);
3359 if (state->i2c_repeater)
3360 i2c_unregister_device(state->i2c_repeater);
3361 if (state->i2c_edid)
3362 i2c_unregister_device(state->i2c_edid);
3363 if (state->i2c_hdmi)
3364 i2c_unregister_device(state->i2c_hdmi);
3365 if (state->i2c_cp)
3366 i2c_unregister_device(state->i2c_cp);
3367 if (state->i2c_vdp)
3368 i2c_unregister_device(state->i2c_vdp);
b82e2793
MB		 3369
3370 state->i2c_avlink = NULL;
3371 state->i2c_cec = NULL;
3372 state->i2c_infoframe = NULL;
3373 state->i2c_sdp_io = NULL;
3374 state->i2c_sdp = NULL;
3375 state->i2c_afe = NULL;
3376 state->i2c_repeater = NULL;
3377 state->i2c_edid = NULL;
3378 state->i2c_hdmi = NULL;
3379 state->i2c_cp = NULL;
3380 state->i2c_vdp = NULL;
a89bcd4c
HV		 3381}
3382
b82e2793 3383static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
a89bcd4c
HV		 3384 u8 addr, u8 io_reg)
3385{
3386 struct i2c_client *client = v4l2_get_subdevdata(sd);
b82e2793 3387 struct i2c_client *cp;
a89bcd4c
HV		 3388
3389 io_write(sd, io_reg, addr << 1);
b82e2793
MB		 3390
3391 if (addr == 0) {
3392 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3393 return NULL;
3394 }
3395
3396 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3397 if (!cp)
3398 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3399
3400 return cp;
3401}
3402
3403static int adv7842_register_clients(struct v4l2_subdev *sd)
3404{
3405 struct adv7842_state *state = to_state(sd);
3406 struct adv7842_platform_data *pdata = &state->pdata;
3407
3408 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3409 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3410 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3411 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3412 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3413 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3414 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3415 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3416 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3417 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3418 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3419
3420 if (!state->i2c_avlink ||
3421 !state->i2c_cec ||
3422 !state->i2c_infoframe ||
3423 !state->i2c_sdp_io ||
3424 !state->i2c_sdp ||
3425 !state->i2c_afe ||
3426 !state->i2c_repeater ||
3427 !state->i2c_edid ||
3428 !state->i2c_hdmi ||
3429 !state->i2c_cp ||
3430 !state->i2c_vdp)
3431 return -1;
3432
3433 return 0;
a89bcd4c
HV		 3434}
3435
3436static int adv7842_probe(struct i2c_client *client,
3437 const struct i2c_device_id *id)
3438{
3439 struct adv7842_state *state;
0bb4e7ab
HV		 3440 static const struct v4l2_dv_timings cea640x480 =
3441 V4L2_DV_BT_CEA_640X480P59_94;
a89bcd4c
HV		 3442 struct adv7842_platform_data *pdata = client->dev.platform_data;
3443 struct v4l2_ctrl_handler *hdl;
e8979274 3444 struct v4l2_ctrl *ctrl;
a89bcd4c
HV		 3445 struct v4l2_subdev *sd;
3446 u16 rev;
3447 int err;
3448
3449 /* Check if the adapter supports the needed features */
3450 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3451 return -EIO;
3452
3453 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3454 client->addr << 1);
3455
3456 if (!pdata) {
3457 v4l_err(client, "No platform data!\n");
3458 return -ENODEV;
3459 }
3460
3461 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3462 if (!state) {
3463 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3464 return -ENOMEM;
3465 }
3466
7de5be44
MB		 3467 /* platform data */
3468 state->pdata = *pdata;
0bb4e7ab 3469 state->timings = cea640x480;
f888ae7e 3470 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
7de5be44 3471
a89bcd4c
HV		 3472 sd = &state->sd;
3473 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
aef5159f 3474 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
25c84fb1 3475 sd->internal_ops = &adv7842_int_ops;
a89bcd4c
HV		 3476 state->mode = pdata->mode;
3477
8e4e3631 3478 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
6e9071f2 3479 state->restart_stdi_once = true;
a89bcd4c
HV		 3480
3481 /* i2c access to adv7842? */
3482 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3483 adv_smbus_read_byte_data_check(client, 0xeb, false);
3484 if (rev != 0x2012) {
3485 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3486 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3487 adv_smbus_read_byte_data_check(client, 0xeb, false);
3488 }
3489 if (rev != 0x2012) {
3490 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3491 client->addr << 1, rev);
3492 return -ENODEV;
3493 }
3494
3495 if (pdata->chip_reset)
3496 main_reset(sd);
3497
3498 /* control handlers */
3499 hdl = &state->hdl;
3500 v4l2_ctrl_handler_init(hdl, 6);
3501
3502 /* add in ascending ID order */
3503 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3504 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3505 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3506 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3507 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3508 V4L2_CID_SATURATION, 0, 255, 1, 128);
3509 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3510 V4L2_CID_HUE, 0, 128, 1, 0);
e8979274
HV		 3511 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3512 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3513 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3514 if (ctrl)
3515 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
a89bcd4c
HV		 3516
3517 /* custom controls */
3518 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3519 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3520 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3521 &adv7842_ctrl_analog_sampling_phase, NULL);
3522 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3523 &adv7842_ctrl_free_run_color_manual, NULL);
3524 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3525 &adv7842_ctrl_free_run_color, NULL);
3526 state->rgb_quantization_range_ctrl =
3527 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3528 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3529 0, V4L2_DV_RGB_RANGE_AUTO);
3530 sd->ctrl_handler = hdl;
3531 if (hdl->error) {
3532 err = hdl->error;
3533 goto err_hdl;
3534 }
a89bcd4c
HV		 3535 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3536 err = -ENODEV;
3537 goto err_hdl;
3538 }
3539
b82e2793 3540 if (adv7842_register_clients(sd) < 0) {
a89bcd4c
HV		 3541 err = -ENOMEM;
3542 v4l2_err(sd, "failed to create all i2c clients\n");
3543 goto err_i2c;
3544 }
3545
a89bcd4c
HV		 3546
3547 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3548 adv7842_delayed_work_enable_hotplug);
3549
3550 state->pad.flags = MEDIA_PAD_FL_SOURCE;
ab22e77c 3551 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
a89bcd4c
HV		 3552 if (err)
3553 goto err_work_queues;
3554
7de5be44 3555 err = adv7842_core_init(sd);
a89bcd4c
HV		 3556 if (err)
3557 goto err_entity;
3558
25c84fb1
HV		 3559#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3560 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3561 state, dev_name(&client->dev),
3562 CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
3563 CEC_CAP_PASSTHROUGH | CEC_CAP_RC, ADV7842_MAX_ADDRS,
3564 &client->dev);
3565 err = PTR_ERR_OR_ZERO(state->cec_adap);
3566 if (err)
3567 goto err_entity;
3568#endif
3569
a89bcd4c
HV		 3570 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3571 client->addr << 1, client->adapter->name);
3572 return 0;
3573
3574err_entity:
3575 media_entity_cleanup(&sd->entity);
3576err_work_queues:
3577 cancel_delayed_work(&state->delayed_work_enable_hotplug);
a89bcd4c 3578err_i2c:
b82e2793 3579 adv7842_unregister_clients(sd);
a89bcd4c
HV		 3580err_hdl:
3581 v4l2_ctrl_handler_free(hdl);
3582 return err;
3583}
3584
3585/* ----------------------------------------------------------------------- */
3586
3587static int adv7842_remove(struct i2c_client *client)
3588{
3589 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3590 struct adv7842_state *state = to_state(sd);
3591
3592 adv7842_irq_enable(sd, false);
a89bcd4c 3593 cancel_delayed_work(&state->delayed_work_enable_hotplug);
a89bcd4c
HV		 3594 v4l2_device_unregister_subdev(sd);
3595 media_entity_cleanup(&sd->entity);
b82e2793 3596 adv7842_unregister_clients(sd);
a89bcd4c
HV		 3597 v4l2_ctrl_handler_free(sd->ctrl_handler);
3598 return 0;
3599}
3600
3601/* ----------------------------------------------------------------------- */
3602
3603static struct i2c_device_id adv7842_id[] = {
3604 { "adv7842", 0 },
3605 { }
3606};
3607MODULE_DEVICE_TABLE(i2c, adv7842_id);
3608
3609/* ----------------------------------------------------------------------- */
3610
3611static struct i2c_driver adv7842_driver = {
3612 .driver = {
a89bcd4c
HV		 3613 .name = "adv7842",
3614 },
3615 .probe = adv7842_probe,
3616 .remove = adv7842_remove,
3617 .id_table = adv7842_id,
3618};
3619
3620module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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