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[media] adv7842: mute audio before switching inputs to avoid noise/pops
[deliverable/linux.git] / drivers / media / i2c / adv7842.c
CommitLineData
a89bcd4c
HV		 1/*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
5b64b205
MR		 23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
7de6fab1
MR		 25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
5b64b205
MR		 27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
a89bcd4c
HV		 30 */
31
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/i2c.h>
37#include <linux/delay.h>
38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
40#include <linux/v4l2-dv-timings.h>
41#include <media/v4l2-device.h>
42#include <media/v4l2-ctrls.h>
43#include <media/v4l2-dv-timings.h>
44#include <media/adv7842.h>
45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7842 system clock frequency */
56#define ADV7842_fsc (28636360)
57
58/*
59**********************************************************************
60*
61* Arrays with configuration parameters for the ADV7842
62*
63**********************************************************************
64*/
65
66struct adv7842_state {
7de5be44 67 struct adv7842_platform_data pdata;
a89bcd4c
HV		 68 struct v4l2_subdev sd;
69 struct media_pad pad;
70 struct v4l2_ctrl_handler hdl;
71 enum adv7842_mode mode;
72 struct v4l2_dv_timings timings;
73 enum adv7842_vid_std_select vid_std_select;
74 v4l2_std_id norm;
75 struct {
76 u8 edid[256];
77 u32 present;
78 } hdmi_edid;
79 struct {
80 u8 edid[256];
81 u32 present;
82 } vga_edid;
83 struct v4l2_fract aspect_ratio;
84 u32 rgb_quantization_range;
85 bool is_cea_format;
86 struct workqueue_struct *work_queues;
87 struct delayed_work delayed_work_enable_hotplug;
a89bcd4c
HV		 88 bool hdmi_port_a;
89
90 /* i2c clients */
91 struct i2c_client *i2c_sdp_io;
92 struct i2c_client *i2c_sdp;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
95 struct i2c_client *i2c_afe;
96 struct i2c_client *i2c_hdmi;
97 struct i2c_client *i2c_repeater;
98 struct i2c_client *i2c_edid;
99 struct i2c_client *i2c_infoframe;
100 struct i2c_client *i2c_cec;
101 struct i2c_client *i2c_avlink;
102
103 /* controls */
104 struct v4l2_ctrl *detect_tx_5v_ctrl;
105 struct v4l2_ctrl *analog_sampling_phase_ctrl;
106 struct v4l2_ctrl *free_run_color_ctrl_manual;
107 struct v4l2_ctrl *free_run_color_ctrl;
108 struct v4l2_ctrl *rgb_quantization_range_ctrl;
109};
110
111/* Unsupported timings. This device cannot support 720p30. */
112static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
113 V4L2_DV_BT_CEA_1280X720P30,
114 { }
115};
116
117static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
118{
119 int i;
120
121 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
122 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
123 return false;
124 return true;
125}
126
127struct adv7842_video_standards {
128 struct v4l2_dv_timings timings;
129 u8 vid_std;
130 u8 v_freq;
131};
132
133/* sorted by number of lines */
134static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
135 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
136 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
137 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
138 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
139 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
140 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
141 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
142 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
143 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
144 /* TODO add 1920x1080P60_RB (CVT timing) */
145 { },
146};
147
148/* sorted by number of lines */
149static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
150 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
151 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
152 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
153 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
154 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
156 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
157 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
158 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
159 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
160 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
161 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
162 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
163 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
164 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
165 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
166 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
167 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
168 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
169 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
170 /* TODO add 1600X1200P60_RB (not a DMT timing) */
171 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
172 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
173 { },
174};
175
176/* sorted by number of lines */
177static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
178 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
180 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
181 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 { },
188};
189
190/* sorted by number of lines */
191static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
192 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 { },
208};
209
210/* ----------------------------------------------------------------------- */
211
212static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
213{
214 return container_of(sd, struct adv7842_state, sd);
215}
216
217static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
218{
219 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
220}
221
222static inline unsigned hblanking(const struct v4l2_bt_timings *t)
223{
224 return V4L2_DV_BT_BLANKING_WIDTH(t);
225}
226
227static inline unsigned htotal(const struct v4l2_bt_timings *t)
228{
229 return V4L2_DV_BT_FRAME_WIDTH(t);
230}
231
232static inline unsigned vblanking(const struct v4l2_bt_timings *t)
233{
234 return V4L2_DV_BT_BLANKING_HEIGHT(t);
235}
236
237static inline unsigned vtotal(const struct v4l2_bt_timings *t)
238{
239 return V4L2_DV_BT_FRAME_HEIGHT(t);
240}
241
242
243/* ----------------------------------------------------------------------- */
244
245static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
246 u8 command, bool check)
247{
248 union i2c_smbus_data data;
249
250 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
251 I2C_SMBUS_READ, command,
252 I2C_SMBUS_BYTE_DATA, &data))
253 return data.byte;
254 if (check)
255 v4l_err(client, "error reading %02x, %02x\n",
256 client->addr, command);
257 return -EIO;
258}
259
260static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
261{
262 int i;
263
264 for (i = 0; i < 3; i++) {
265 int ret = adv_smbus_read_byte_data_check(client, command, true);
266
267 if (ret >= 0) {
268 if (i)
269 v4l_err(client, "read ok after %d retries\n", i);
270 return ret;
271 }
272 }
273 v4l_err(client, "read failed\n");
274 return -EIO;
275}
276
277static s32 adv_smbus_write_byte_data(struct i2c_client *client,
278 u8 command, u8 value)
279{
280 union i2c_smbus_data data;
281 int err;
282 int i;
283
284 data.byte = value;
285 for (i = 0; i < 3; i++) {
286 err = i2c_smbus_xfer(client->adapter, client->addr,
287 client->flags,
288 I2C_SMBUS_WRITE, command,
289 I2C_SMBUS_BYTE_DATA, &data);
290 if (!err)
291 break;
292 }
293 if (err < 0)
294 v4l_err(client, "error writing %02x, %02x, %02x\n",
295 client->addr, command, value);
296 return err;
297}
298
299static void adv_smbus_write_byte_no_check(struct i2c_client *client,
300 u8 command, u8 value)
301{
302 union i2c_smbus_data data;
303 data.byte = value;
304
305 i2c_smbus_xfer(client->adapter, client->addr,
306 client->flags,
307 I2C_SMBUS_WRITE, command,
308 I2C_SMBUS_BYTE_DATA, &data);
309}
310
311static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
312 u8 command, unsigned length, const u8 *values)
313{
314 union i2c_smbus_data data;
315
316 if (length > I2C_SMBUS_BLOCK_MAX)
317 length = I2C_SMBUS_BLOCK_MAX;
318 data.block[0] = length;
319 memcpy(data.block + 1, values, length);
320 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
321 I2C_SMBUS_WRITE, command,
322 I2C_SMBUS_I2C_BLOCK_DATA, &data);
323}
324
325/* ----------------------------------------------------------------------- */
326
327static inline int io_read(struct v4l2_subdev *sd, u8 reg)
328{
329 struct i2c_client *client = v4l2_get_subdevdata(sd);
330
331 return adv_smbus_read_byte_data(client, reg);
332}
333
334static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
335{
336 struct i2c_client *client = v4l2_get_subdevdata(sd);
337
338 return adv_smbus_write_byte_data(client, reg, val);
339}
340
341static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
342{
343 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
344}
345
346static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
347{
348 struct adv7842_state *state = to_state(sd);
349
350 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
351}
352
353static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
354{
355 struct adv7842_state *state = to_state(sd);
356
357 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
358}
359
360static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
361{
362 struct adv7842_state *state = to_state(sd);
363
364 return adv_smbus_read_byte_data(state->i2c_cec, reg);
365}
366
367static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
368{
369 struct adv7842_state *state = to_state(sd);
370
371 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
372}
373
374static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
375{
376 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
377}
378
379static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
380{
381 struct adv7842_state *state = to_state(sd);
382
383 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
384}
385
386static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
387{
388 struct adv7842_state *state = to_state(sd);
389
390 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
391}
392
393static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
394{
395 struct adv7842_state *state = to_state(sd);
396
397 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
398}
399
400static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
401{
402 struct adv7842_state *state = to_state(sd);
403
404 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
405}
406
407static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
408{
409 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
410}
411
412static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
413{
414 struct adv7842_state *state = to_state(sd);
415
416 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
417}
418
419static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
420{
421 struct adv7842_state *state = to_state(sd);
422
423 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
424}
425
426static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
427{
428 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
429}
430
431static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
432{
433 struct adv7842_state *state = to_state(sd);
434
435 return adv_smbus_read_byte_data(state->i2c_afe, reg);
436}
437
438static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439{
440 struct adv7842_state *state = to_state(sd);
441
442 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
443}
444
445static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
446{
447 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
448}
449
450static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
451{
452 struct adv7842_state *state = to_state(sd);
453
454 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
455}
456
457static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
458{
459 struct adv7842_state *state = to_state(sd);
460
461 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
462}
463
464static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
465{
466 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
467}
468
469static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
470{
471 struct adv7842_state *state = to_state(sd);
472
473 return adv_smbus_read_byte_data(state->i2c_edid, reg);
474}
475
476static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
477{
478 struct adv7842_state *state = to_state(sd);
479
480 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
481}
482
483static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
484{
485 struct adv7842_state *state = to_state(sd);
486
487 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
488}
489
490static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
491{
492 struct adv7842_state *state = to_state(sd);
493
494 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
495}
496
5b64b205
MR		 497static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
498{
499 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
500}
501
a89bcd4c
HV		 502static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
503{
504 struct adv7842_state *state = to_state(sd);
505
506 return adv_smbus_read_byte_data(state->i2c_cp, reg);
507}
508
509static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
510{
511 struct adv7842_state *state = to_state(sd);
512
513 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
514}
515
516static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
517{
518 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
519}
520
521static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
522{
523 struct adv7842_state *state = to_state(sd);
524
525 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
526}
527
528static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
529{
530 struct adv7842_state *state = to_state(sd);
531
532 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
533}
534
535static void main_reset(struct v4l2_subdev *sd)
536{
537 struct i2c_client *client = v4l2_get_subdevdata(sd);
538
539 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
540
541 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
542
84aeed53 543 mdelay(5);
a89bcd4c
HV		 544}
545
546/* ----------------------------------------------------------------------- */
547
548static inline bool is_digital_input(struct v4l2_subdev *sd)
549{
550 struct adv7842_state *state = to_state(sd);
551
552 return state->mode == ADV7842_MODE_HDMI;
553}
554
555static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
556 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 557 /* keep this initialization for compatibility with GCC < 4.4.6 */
558 .reserved = { 0 },
559 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
560 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 561 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 562 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
563 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 564};
565
566static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
567 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 568 /* keep this initialization for compatibility with GCC < 4.4.6 */
569 .reserved = { 0 },
570 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
571 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 572 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 573 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
574 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 575};
576
577static inline const struct v4l2_dv_timings_cap *
578adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
579{
580 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
581 &adv7842_timings_cap_analog;
582}
583
584/* ----------------------------------------------------------------------- */
585
586static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
587{
588 struct delayed_work *dwork = to_delayed_work(work);
589 struct adv7842_state *state = container_of(dwork,
590 struct adv7842_state, delayed_work_enable_hotplug);
591 struct v4l2_subdev *sd = &state->sd;
592 int present = state->hdmi_edid.present;
593 u8 mask = 0;
594
595 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
596 __func__, present);
597
7de6fab1
MR		 598 if (present & (0x04 << ADV7842_EDID_PORT_A))
599 mask |= 0x20;
600 if (present & (0x04 << ADV7842_EDID_PORT_B))
601 mask |= 0x10;
a89bcd4c
HV		 602 io_write_and_or(sd, 0x20, 0xcf, mask);
603}
604
605static int edid_write_vga_segment(struct v4l2_subdev *sd)
606{
607 struct i2c_client *client = v4l2_get_subdevdata(sd);
608 struct adv7842_state *state = to_state(sd);
609 const u8 *val = state->vga_edid.edid;
610 int err = 0;
611 int i;
612
613 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
614
615 /* HPA disable on port A and B */
616 io_write_and_or(sd, 0x20, 0xcf, 0x00);
617
618 /* Disable I2C access to internal EDID ram from VGA DDC port */
619 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
620
621 /* edid segment pointer '1' for VGA port */
622 rep_write_and_or(sd, 0x77, 0xef, 0x10);
623
624 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
625 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
626 I2C_SMBUS_BLOCK_MAX, val + i);
627 if (err)
628 return err;
629
630 /* Calculates the checksums and enables I2C access
631 * to internal EDID ram from VGA DDC port.
632 */
633 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
634
635 for (i = 0; i < 1000; i++) {
636 if (rep_read(sd, 0x79) & 0x20)
637 break;
638 mdelay(1);
639 }
640 if (i == 1000) {
641 v4l_err(client, "error enabling edid on VGA port\n");
642 return -EIO;
643 }
644
645 /* enable hotplug after 200 ms */
646 queue_delayed_work(state->work_queues,
647 &state->delayed_work_enable_hotplug, HZ / 5);
648
649 return 0;
650}
651
652static int edid_spa_location(const u8 *edid)
653{
654 u8 d;
655
656 /*
657 * TODO, improve and update for other CEA extensions
658 * currently only for 1 segment (256 bytes),
659 * i.e. 1 extension block and CEA revision 3.
660 */
661 if ((edid[0x7e] != 1) ||
662 (edid[0x80] != 0x02) ||
663 (edid[0x81] != 0x03)) {
664 return -EINVAL;
665 }
666 /*
667 * search Vendor Specific Data Block (tag 3)
668 */
669 d = edid[0x82] & 0x7f;
670 if (d > 4) {
671 int i = 0x84;
672 int end = 0x80 + d;
673 do {
674 u8 tag = edid[i]>>5;
675 u8 len = edid[i] & 0x1f;
676
677 if ((tag == 3) && (len >= 5))
678 return i + 4;
679 i += len + 1;
680 } while (i < end);
681 }
682 return -EINVAL;
683}
684
685static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
686{
687 struct i2c_client *client = v4l2_get_subdevdata(sd);
688 struct adv7842_state *state = to_state(sd);
689 const u8 *val = state->hdmi_edid.edid;
a89bcd4c
HV		 690 int spa_loc = edid_spa_location(val);
691 int err = 0;
692 int i;
693
7de6fab1
MR		 694 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
695 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
a89bcd4c
HV		 696
697 /* HPA disable on port A and B */
698 io_write_and_or(sd, 0x20, 0xcf, 0x00);
699
700 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
701 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
702
703 /* edid segment pointer '0' for HDMI ports */
704 rep_write_and_or(sd, 0x77, 0xef, 0x00);
705
706 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
707 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
708 I2C_SMBUS_BLOCK_MAX, val + i);
709 if (err)
710 return err;
711
7de6fab1
MR		 712 if (spa_loc < 0)
713 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
714
715 if (port == ADV7842_EDID_PORT_A) {
716 rep_write(sd, 0x72, val[spa_loc]);
717 rep_write(sd, 0x73, val[spa_loc + 1]);
a89bcd4c 718 } else {
7de6fab1
MR		 719 rep_write(sd, 0x74, val[spa_loc]);
720 rep_write(sd, 0x75, val[spa_loc + 1]);
a89bcd4c 721 }
7de6fab1
MR		 722 rep_write(sd, 0x76, spa_loc & 0xff);
723 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
a89bcd4c
HV		 724
725 /* Calculates the checksums and enables I2C access to internal
726 * EDID ram from HDMI DDC ports
727 */
7de6fab1 728 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
a89bcd4c
HV		 729
730 for (i = 0; i < 1000; i++) {
7de6fab1 731 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
a89bcd4c
HV		 732 break;
733 mdelay(1);
734 }
735 if (i == 1000) {
7de6fab1
MR		 736 v4l_err(client, "error enabling edid on port %c\n",
737 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
a89bcd4c
HV		 738 return -EIO;
739 }
740
741 /* enable hotplug after 200 ms */
742 queue_delayed_work(state->work_queues,
743 &state->delayed_work_enable_hotplug, HZ / 5);
744
745 return 0;
746}
747
748/* ----------------------------------------------------------------------- */
749
750#ifdef CONFIG_VIDEO_ADV_DEBUG
751static void adv7842_inv_register(struct v4l2_subdev *sd)
752{
753 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
754 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
755 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
756 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
757 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
758 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
759 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
760 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
761 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
762 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
763 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
764 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
765}
766
767static int adv7842_g_register(struct v4l2_subdev *sd,
768 struct v4l2_dbg_register *reg)
769{
770 reg->size = 1;
771 switch (reg->reg >> 8) {
772 case 0:
773 reg->val = io_read(sd, reg->reg & 0xff);
774 break;
775 case 1:
776 reg->val = avlink_read(sd, reg->reg & 0xff);
777 break;
778 case 2:
779 reg->val = cec_read(sd, reg->reg & 0xff);
780 break;
781 case 3:
782 reg->val = infoframe_read(sd, reg->reg & 0xff);
783 break;
784 case 4:
785 reg->val = sdp_io_read(sd, reg->reg & 0xff);
786 break;
787 case 5:
788 reg->val = sdp_read(sd, reg->reg & 0xff);
789 break;
790 case 6:
791 reg->val = afe_read(sd, reg->reg & 0xff);
792 break;
793 case 7:
794 reg->val = rep_read(sd, reg->reg & 0xff);
795 break;
796 case 8:
797 reg->val = edid_read(sd, reg->reg & 0xff);
798 break;
799 case 9:
800 reg->val = hdmi_read(sd, reg->reg & 0xff);
801 break;
802 case 0xa:
803 reg->val = cp_read(sd, reg->reg & 0xff);
804 break;
805 case 0xb:
806 reg->val = vdp_read(sd, reg->reg & 0xff);
807 break;
808 default:
809 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
810 adv7842_inv_register(sd);
811 break;
812 }
813 return 0;
814}
815
816static int adv7842_s_register(struct v4l2_subdev *sd,
817 const struct v4l2_dbg_register *reg)
818{
819 u8 val = reg->val & 0xff;
820
821 switch (reg->reg >> 8) {
822 case 0:
823 io_write(sd, reg->reg & 0xff, val);
824 break;
825 case 1:
826 avlink_write(sd, reg->reg & 0xff, val);
827 break;
828 case 2:
829 cec_write(sd, reg->reg & 0xff, val);
830 break;
831 case 3:
832 infoframe_write(sd, reg->reg & 0xff, val);
833 break;
834 case 4:
835 sdp_io_write(sd, reg->reg & 0xff, val);
836 break;
837 case 5:
838 sdp_write(sd, reg->reg & 0xff, val);
839 break;
840 case 6:
841 afe_write(sd, reg->reg & 0xff, val);
842 break;
843 case 7:
844 rep_write(sd, reg->reg & 0xff, val);
845 break;
846 case 8:
847 edid_write(sd, reg->reg & 0xff, val);
848 break;
849 case 9:
850 hdmi_write(sd, reg->reg & 0xff, val);
851 break;
852 case 0xa:
853 cp_write(sd, reg->reg & 0xff, val);
854 break;
855 case 0xb:
856 vdp_write(sd, reg->reg & 0xff, val);
857 break;
858 default:
859 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
860 adv7842_inv_register(sd);
861 break;
862 }
863 return 0;
864}
865#endif
866
867static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
868{
869 struct adv7842_state *state = to_state(sd);
870 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
871 u8 reg_io_6f = io_read(sd, 0x6f);
872 int val = 0;
873
874 if (reg_io_6f & 0x02)
875 val |= 1; /* port A */
876 if (reg_io_6f & 0x01)
877 val |= 2; /* port B */
878
879 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
880
881 if (val != prev)
882 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
883 return 0;
884}
885
886static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
887 u8 prim_mode,
888 const struct adv7842_video_standards *predef_vid_timings,
889 const struct v4l2_dv_timings *timings)
890{
891 int i;
892
893 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
894 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
895 is_digital_input(sd) ? 250000 : 1000000))
896 continue;
897 /* video std */
898 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
899 /* v_freq and prim mode */
900 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
901 return 0;
902 }
903
904 return -1;
905}
906
907static int configure_predefined_video_timings(struct v4l2_subdev *sd,
908 struct v4l2_dv_timings *timings)
909{
910 struct adv7842_state *state = to_state(sd);
911 int err;
912
913 v4l2_dbg(1, debug, sd, "%s\n", __func__);
914
915 /* reset to default values */
916 io_write(sd, 0x16, 0x43);
917 io_write(sd, 0x17, 0x5a);
918 /* disable embedded syncs for auto graphics mode */
919 cp_write_and_or(sd, 0x81, 0xef, 0x00);
920 cp_write(sd, 0x26, 0x00);
921 cp_write(sd, 0x27, 0x00);
922 cp_write(sd, 0x28, 0x00);
923 cp_write(sd, 0x29, 0x00);
6251e65f 924 cp_write(sd, 0x8f, 0x40);
a89bcd4c
HV		 925 cp_write(sd, 0x90, 0x00);
926 cp_write(sd, 0xa5, 0x00);
927 cp_write(sd, 0xa6, 0x00);
928 cp_write(sd, 0xa7, 0x00);
929 cp_write(sd, 0xab, 0x00);
930 cp_write(sd, 0xac, 0x00);
931
932 switch (state->mode) {
933 case ADV7842_MODE_COMP:
934 case ADV7842_MODE_RGB:
935 err = find_and_set_predefined_video_timings(sd,
936 0x01, adv7842_prim_mode_comp, timings);
937 if (err)
938 err = find_and_set_predefined_video_timings(sd,
939 0x02, adv7842_prim_mode_gr, timings);
940 break;
941 case ADV7842_MODE_HDMI:
942 err = find_and_set_predefined_video_timings(sd,
943 0x05, adv7842_prim_mode_hdmi_comp, timings);
944 if (err)
945 err = find_and_set_predefined_video_timings(sd,
946 0x06, adv7842_prim_mode_hdmi_gr, timings);
947 break;
948 default:
949 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
950 __func__, state->mode);
951 err = -1;
952 break;
953 }
954
955
956 return err;
957}
958
959static void configure_custom_video_timings(struct v4l2_subdev *sd,
960 const struct v4l2_bt_timings *bt)
961{
962 struct adv7842_state *state = to_state(sd);
963 struct i2c_client *client = v4l2_get_subdevdata(sd);
964 u32 width = htotal(bt);
965 u32 height = vtotal(bt);
966 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
967 u16 cp_start_eav = width - bt->hfrontporch;
968 u16 cp_start_vbi = height - bt->vfrontporch + 1;
969 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
970 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
971 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
972 const u8 pll[2] = {
973 0xc0 | ((width >> 8) & 0x1f),
974 width & 0xff
975 };
976
977 v4l2_dbg(2, debug, sd, "%s\n", __func__);
978
979 switch (state->mode) {
980 case ADV7842_MODE_COMP:
981 case ADV7842_MODE_RGB:
982 /* auto graphics */
983 io_write(sd, 0x00, 0x07); /* video std */
984 io_write(sd, 0x01, 0x02); /* prim mode */
985 /* enable embedded syncs for auto graphics mode */
986 cp_write_and_or(sd, 0x81, 0xef, 0x10);
987
988 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
989 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
990 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
991 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
992 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
993 break;
994 }
995
996 /* active video - horizontal timing */
997 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
998 cp_write(sd, 0x27, (cp_start_sav & 0xff));
999 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1000 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1001
1002 /* active video - vertical timing */
1003 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1004 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1005 ((cp_end_vbi >> 8) & 0xf));
1006 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1007 break;
1008 case ADV7842_MODE_HDMI:
1009 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1010 according to [REF_03, c. 4.2] */
a89bcd4c
HV		 1011 io_write(sd, 0x00, 0x02); /* video std */
1012 io_write(sd, 0x01, 0x06); /* prim mode */
1013 break;
1014 default:
1015 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1016 __func__, state->mode);
1017 break;
1018 }
1019
1020 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1021 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1022 cp_write(sd, 0xab, (height >> 4) & 0xff);
1023 cp_write(sd, 0xac, (height & 0x0f) << 4);
1024}
1025
1026static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1027{
1028 struct adv7842_state *state = to_state(sd);
1029
69e9ba6f
HV		 1030 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
1031 __func__, state->rgb_quantization_range);
1032
a89bcd4c
HV		 1033 switch (state->rgb_quantization_range) {
1034 case V4L2_DV_RGB_RANGE_AUTO:
69e9ba6f
HV		 1035 if (state->mode == ADV7842_MODE_RGB) {
1036 /* Receiving analog RGB signal
1037 * Set RGB full range (0-255) */
1038 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1039 break;
1040 }
1041
1042 if (state->mode == ADV7842_MODE_COMP) {
1043 /* Receiving analog YPbPr signal
1044 * Set automode */
1045 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1046 break;
1047 }
1048
1049 if (hdmi_read(sd, 0x05) & 0x80) {
1050 /* Receiving HDMI signal
1051 * Set automode */
a89bcd4c 1052 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
69e9ba6f
HV		 1053 break;
1054 }
1055
1056 /* Receiving DVI-D signal
1057 * ADV7842 selects RGB limited range regardless of
1058 * input format (CE/IT) in automatic mode */
1059 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1060 /* RGB limited range (16-235) */
1061 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1062 } else {
1063 /* RGB full range (0-255) */
1064 io_write_and_or(sd, 0x02, 0x0f, 0x10);
a89bcd4c
HV		 1065 }
1066 break;
1067 case V4L2_DV_RGB_RANGE_LIMITED:
69e9ba6f
HV		 1068 if (state->mode == ADV7842_MODE_COMP) {
1069 /* YCrCb limited range (16-235) */
1070 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1071 } else {
1072 /* RGB limited range (16-235) */
1073 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1074 }
a89bcd4c
HV		 1075 break;
1076 case V4L2_DV_RGB_RANGE_FULL:
69e9ba6f
HV		 1077 if (state->mode == ADV7842_MODE_COMP) {
1078 /* YCrCb full range (0-255) */
1079 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1080 } else {
1081 /* RGB full range (0-255) */
1082 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1083 }
a89bcd4c
HV		 1084 break;
1085 }
1086}
1087
1088static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1089{
1090 struct v4l2_subdev *sd = to_sd(ctrl);
1091 struct adv7842_state *state = to_state(sd);
1092
1093 /* TODO SDP ctrls
1094 contrast/brightness/hue/free run is acting a bit strange,
1095 not sure if sdp csc is correct.
1096 */
1097 switch (ctrl->id) {
1098 /* standard ctrls */
1099 case V4L2_CID_BRIGHTNESS:
1100 cp_write(sd, 0x3c, ctrl->val);
1101 sdp_write(sd, 0x14, ctrl->val);
1102 /* ignore lsb sdp 0x17[3:2] */
1103 return 0;
1104 case V4L2_CID_CONTRAST:
1105 cp_write(sd, 0x3a, ctrl->val);
1106 sdp_write(sd, 0x13, ctrl->val);
1107 /* ignore lsb sdp 0x17[1:0] */
1108 return 0;
1109 case V4L2_CID_SATURATION:
1110 cp_write(sd, 0x3b, ctrl->val);
1111 sdp_write(sd, 0x15, ctrl->val);
1112 /* ignore lsb sdp 0x17[5:4] */
1113 return 0;
1114 case V4L2_CID_HUE:
1115 cp_write(sd, 0x3d, ctrl->val);
1116 sdp_write(sd, 0x16, ctrl->val);
1117 /* ignore lsb sdp 0x17[7:6] */
1118 return 0;
1119 /* custom ctrls */
1120 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1121 afe_write(sd, 0xc8, ctrl->val);
1122 return 0;
1123 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1124 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1125 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1126 return 0;
1127 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1128 u8 R = (ctrl->val & 0xff0000) >> 16;
1129 u8 G = (ctrl->val & 0x00ff00) >> 8;
1130 u8 B = (ctrl->val & 0x0000ff);
1131 /* RGB -> YUV, numerical approximation */
1132 int Y = 66 * R + 129 * G + 25 * B;
1133 int U = -38 * R - 74 * G + 112 * B;
1134 int V = 112 * R - 94 * G - 18 * B;
1135
1136 /* Scale down to 8 bits with rounding */
1137 Y = (Y + 128) >> 8;
1138 U = (U + 128) >> 8;
1139 V = (V + 128) >> 8;
1140 /* make U,V positive */
1141 Y += 16;
1142 U += 128;
1143 V += 128;
1144
1145 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1146 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1147
1148 /* CP */
1149 cp_write(sd, 0xc1, R);
1150 cp_write(sd, 0xc0, G);
1151 cp_write(sd, 0xc2, B);
1152 /* SDP */
1153 sdp_write(sd, 0xde, Y);
1154 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1155 return 0;
1156 }
1157 case V4L2_CID_DV_RX_RGB_RANGE:
1158 state->rgb_quantization_range = ctrl->val;
1159 set_rgb_quantization_range(sd);
1160 return 0;
1161 }
1162 return -EINVAL;
1163}
1164
1165static inline bool no_power(struct v4l2_subdev *sd)
1166{
1167 return io_read(sd, 0x0c) & 0x24;
1168}
1169
1170static inline bool no_cp_signal(struct v4l2_subdev *sd)
1171{
1172 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1173}
1174
1175static inline bool is_hdmi(struct v4l2_subdev *sd)
1176{
1177 return hdmi_read(sd, 0x05) & 0x80;
1178}
1179
1180static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1181{
1182 struct adv7842_state *state = to_state(sd);
1183
1184 *status = 0;
1185
1186 if (io_read(sd, 0x0c) & 0x24)
1187 *status |= V4L2_IN_ST_NO_POWER;
1188
1189 if (state->mode == ADV7842_MODE_SDP) {
1190 /* status from SDP block */
1191 if (!(sdp_read(sd, 0x5A) & 0x01))
1192 *status |= V4L2_IN_ST_NO_SIGNAL;
1193
1194 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1195 __func__, *status);
1196 return 0;
1197 }
1198 /* status from CP block */
1199 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1200 !(cp_read(sd, 0xb1) & 0x80))
1201 /* TODO channel 2 */
1202 *status |= V4L2_IN_ST_NO_SIGNAL;
1203
1204 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1205 *status |= V4L2_IN_ST_NO_SIGNAL;
1206
1207 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1208 __func__, *status);
1209
1210 return 0;
1211}
1212
1213struct stdi_readback {
1214 u16 bl, lcf, lcvs;
1215 u8 hs_pol, vs_pol;
1216 bool interlaced;
1217};
1218
1219static int stdi2dv_timings(struct v4l2_subdev *sd,
1220 struct stdi_readback *stdi,
1221 struct v4l2_dv_timings *timings)
1222{
1223 struct adv7842_state *state = to_state(sd);
1224 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1225 u32 pix_clk;
1226 int i;
1227
1228 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1229 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1230
1231 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1232 adv7842_get_dv_timings_cap(sd),
1233 adv7842_check_dv_timings, NULL))
1234 continue;
1235 if (vtotal(bt) != stdi->lcf + 1)
1236 continue;
1237 if (bt->vsync != stdi->lcvs)
1238 continue;
1239
1240 pix_clk = hfreq * htotal(bt);
1241
1242 if ((pix_clk < bt->pixelclock + 1000000) &&
1243 (pix_clk > bt->pixelclock - 1000000)) {
1244 *timings = v4l2_dv_timings_presets[i];
1245 return 0;
1246 }
1247 }
1248
1249 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1250 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1251 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1252 timings))
1253 return 0;
1254 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1255 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1256 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1257 state->aspect_ratio, timings))
1258 return 0;
1259
1260 v4l2_dbg(2, debug, sd,
1261 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1262 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1263 stdi->hs_pol, stdi->vs_pol);
1264 return -1;
1265}
1266
1267static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1268{
1269 u32 status;
1270
1271 adv7842_g_input_status(sd, &status);
1272 if (status & V4L2_IN_ST_NO_SIGNAL) {
1273 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1274 return -ENOLINK;
1275 }
1276
1277 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1278 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1279 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1280
1281 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1282 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1283 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1284 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1285 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1286 } else {
1287 stdi->hs_pol = 'x';
1288 stdi->vs_pol = 'x';
1289 }
1290 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1291
1292 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1293 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1294 return -ENOLINK;
1295 }
1296
1297 v4l2_dbg(2, debug, sd,
1298 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1299 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1300 stdi->hs_pol, stdi->vs_pol,
1301 stdi->interlaced ? "interlaced" : "progressive");
1302
1303 return 0;
1304}
1305
1306static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1307 struct v4l2_enum_dv_timings *timings)
1308{
1309 return v4l2_enum_dv_timings_cap(timings,
1310 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1311}
1312
1313static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1314 struct v4l2_dv_timings_cap *cap)
1315{
1316 *cap = *adv7842_get_dv_timings_cap(sd);
1317 return 0;
1318}
1319
1320/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
69e9ba6f 1321 if the format is listed in adv7842_timings[] */
a89bcd4c
HV		 1322static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1323 struct v4l2_dv_timings *timings)
1324{
1325 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1326 is_digital_input(sd) ? 250000 : 1000000,
1327 adv7842_check_dv_timings, NULL);
1328}
1329
1330static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1331 struct v4l2_dv_timings *timings)
1332{
1333 struct adv7842_state *state = to_state(sd);
1334 struct v4l2_bt_timings *bt = &timings->bt;
1335 struct stdi_readback stdi = { 0 };
1336
e78d834a
MB		 1337 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1338
a89bcd4c
HV		 1339 /* SDP block */
1340 if (state->mode == ADV7842_MODE_SDP)
1341 return -ENODATA;
1342
1343 /* read STDI */
1344 if (read_stdi(sd, &stdi)) {
1345 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1346 return -ENOLINK;
1347 }
1348 bt->interlaced = stdi.interlaced ?
1349 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
a89bcd4c
HV		 1350
1351 if (is_digital_input(sd)) {
e78d834a
MB		 1352 uint32_t freq;
1353
1354 timings->type = V4L2_DV_BT_656_1120;
1355 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1356 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1357 freq = (hdmi_read(sd, 0x06) * 1000000) +
1358 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
a89bcd4c
HV		 1359
1360 if (is_hdmi(sd)) {
1361 /* adjust for deep color mode */
e78d834a 1362 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
a89bcd4c 1363 }
e78d834a
MB		 1364 bt->pixelclock = freq;
1365 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
a89bcd4c 1366 hdmi_read(sd, 0x21);
e78d834a 1367 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
a89bcd4c 1368 hdmi_read(sd, 0x23);
e78d834a 1369 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
a89bcd4c 1370 hdmi_read(sd, 0x25);
e78d834a
MB		 1371 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1372 hdmi_read(sd, 0x2b)) / 2;
1373 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1374 hdmi_read(sd, 0x2f)) / 2;
1375 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1376 hdmi_read(sd, 0x33)) / 2;
1377 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1378 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1379 if (bt->interlaced == V4L2_DV_INTERLACED) {
1380 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1381 hdmi_read(sd, 0x0c);
1382 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1383 hdmi_read(sd, 0x2d)) / 2;
1384 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1385 hdmi_read(sd, 0x31)) / 2;
1386 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1387 hdmi_read(sd, 0x35)) / 2;
1388 }
1389 adv7842_fill_optional_dv_timings_fields(sd, timings);
a89bcd4c
HV		 1390 } else {
1391 /* Interlaced? */
1392 if (stdi.interlaced) {
1393 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1394 return -ERANGE;
1395 }
1396
1397 if (stdi2dv_timings(sd, &stdi, timings)) {
1398 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1399 return -ERANGE;
1400 }
1401 }
1402
1403 if (debug > 1)
1404 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1405 timings, true);
1406 return 0;
1407}
1408
1409static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1410 struct v4l2_dv_timings *timings)
1411{
1412 struct adv7842_state *state = to_state(sd);
1413 struct v4l2_bt_timings *bt;
1414 int err;
1415
e78d834a
MB		 1416 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1417
a89bcd4c
HV		 1418 if (state->mode == ADV7842_MODE_SDP)
1419 return -ENODATA;
1420
1421 bt = &timings->bt;
1422
1423 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1424 adv7842_check_dv_timings, NULL))
1425 return -ERANGE;
1426
1427 adv7842_fill_optional_dv_timings_fields(sd, timings);
1428
1429 state->timings = *timings;
1430
6251e65f 1431 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
a89bcd4c
HV		 1432
1433 /* Use prim_mode and vid_std when available */
1434 err = configure_predefined_video_timings(sd, timings);
1435 if (err) {
1436 /* custom settings when the video format
1437 does not have prim_mode/vid_std */
1438 configure_custom_video_timings(sd, bt);
1439 }
1440
1441 set_rgb_quantization_range(sd);
1442
1443
1444 if (debug > 1)
1445 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1446 timings, true);
1447 return 0;
1448}
1449
1450static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1451 struct v4l2_dv_timings *timings)
1452{
1453 struct adv7842_state *state = to_state(sd);
1454
1455 if (state->mode == ADV7842_MODE_SDP)
1456 return -ENODATA;
1457 *timings = state->timings;
1458 return 0;
1459}
1460
1461static void enable_input(struct v4l2_subdev *sd)
1462{
1463 struct adv7842_state *state = to_state(sd);
69e9ba6f
HV		 1464
1465 set_rgb_quantization_range(sd);
a89bcd4c
HV		 1466 switch (state->mode) {
1467 case ADV7842_MODE_SDP:
1468 case ADV7842_MODE_COMP:
1469 case ADV7842_MODE_RGB:
a89bcd4c
HV		 1470 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1471 break;
1472 case ADV7842_MODE_HDMI:
a89bcd4c
HV		 1473 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1474 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5b64b205 1475 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
a89bcd4c
HV		 1476 break;
1477 default:
1478 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1479 __func__, state->mode);
1480 break;
1481 }
1482}
1483
1484static void disable_input(struct v4l2_subdev *sd)
1485{
5b64b205
MR		 1486 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1487 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
a89bcd4c 1488 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
a89bcd4c
HV		 1489 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1490}
1491
1492static void sdp_csc_coeff(struct v4l2_subdev *sd,
1493 const struct adv7842_sdp_csc_coeff *c)
1494{
1495 /* csc auto/manual */
1496 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1497
1498 if (!c->manual)
1499 return;
1500
1501 /* csc scaling */
1502 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1503
1504 /* A coeff */
1505 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1506 sdp_io_write(sd, 0xe1, c->A1);
1507 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1508 sdp_io_write(sd, 0xe3, c->A2);
1509 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1510 sdp_io_write(sd, 0xe5, c->A3);
1511
1512 /* A scale */
1513 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1514 sdp_io_write(sd, 0xe7, c->A4);
1515
1516 /* B coeff */
1517 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1518 sdp_io_write(sd, 0xe9, c->B1);
1519 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1520 sdp_io_write(sd, 0xeb, c->B2);
1521 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1522 sdp_io_write(sd, 0xed, c->B3);
1523
1524 /* B scale */
1525 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1526 sdp_io_write(sd, 0xef, c->B4);
1527
1528 /* C coeff */
1529 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1530 sdp_io_write(sd, 0xf1, c->C1);
1531 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1532 sdp_io_write(sd, 0xf3, c->C2);
1533 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1534 sdp_io_write(sd, 0xf5, c->C3);
1535
1536 /* C scale */
1537 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1538 sdp_io_write(sd, 0xf7, c->C4);
1539}
1540
1541static void select_input(struct v4l2_subdev *sd,
1542 enum adv7842_vid_std_select vid_std_select)
1543{
1544 struct adv7842_state *state = to_state(sd);
1545
1546 switch (state->mode) {
1547 case ADV7842_MODE_SDP:
1548 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1549 io_write(sd, 0x01, 0); /* prim mode */
1550 /* enable embedded syncs for auto graphics mode */
1551 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1552
1553 afe_write(sd, 0x00, 0x00); /* power up ADC */
1554 afe_write(sd, 0xc8, 0x00); /* phase control */
1555
1556 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1557 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1558
1559 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1560 /* script says register 0xde, which don't exist in manual */
1561
1562 /* Manual analog input muxing mode, CVBS (6.4)*/
1563 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1564 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1565 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1566 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1567 } else {
1568 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1569 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1570 }
1571 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1572 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1573
1574 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1575 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1576
1577 /* SDP recommended settings */
1578 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1579 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1580
1581 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1582 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1583 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1584 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1585 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1586 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1587 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1588
1589 /* deinterlacer enabled and 3D comb */
1590 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1591
1592 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1593
1594 break;
1595
1596 case ADV7842_MODE_COMP:
1597 case ADV7842_MODE_RGB:
1598 /* Automatic analog input muxing mode */
1599 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1600 /* set mode and select free run resolution */
1601 io_write(sd, 0x00, vid_std_select); /* video std */
1602 io_write(sd, 0x01, 0x02); /* prim mode */
1603 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1604 for auto graphics mode */
1605
1606 afe_write(sd, 0x00, 0x00); /* power up ADC */
1607 afe_write(sd, 0xc8, 0x00); /* phase control */
69e9ba6f
HV		 1608 if (state->mode == ADV7842_MODE_COMP) {
1609 /* force to YCrCb */
1610 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1611 } else {
1612 /* force to RGB */
1613 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1614 }
a89bcd4c
HV		 1615
1616 /* set ADI recommended settings for digitizer */
1617 /* "ADV7842 Register Settings Recommendations
1618 * (rev. 1.8, November 2010)" p. 9. */
1619 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1620 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1621
1622 /* set to default gain for RGB */
1623 cp_write(sd, 0x73, 0x10);
1624 cp_write(sd, 0x74, 0x04);
1625 cp_write(sd, 0x75, 0x01);
1626 cp_write(sd, 0x76, 0x00);
1627
1628 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1629 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1630 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1631 break;
1632
1633 case ADV7842_MODE_HDMI:
1634 /* Automatic analog input muxing mode */
1635 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1636 /* set mode and select free run resolution */
1637 if (state->hdmi_port_a)
1638 hdmi_write(sd, 0x00, 0x02); /* select port A */
1639 else
1640 hdmi_write(sd, 0x00, 0x03); /* select port B */
1641 io_write(sd, 0x00, vid_std_select); /* video std */
1642 io_write(sd, 0x01, 5); /* prim mode */
1643 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1644 for auto graphics mode */
1645
1646 /* set ADI recommended settings for HDMI: */
1647 /* "ADV7842 Register Settings Recommendations
1648 * (rev. 1.8, November 2010)" p. 3. */
1649 hdmi_write(sd, 0xc0, 0x00);
1650 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1651 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1652 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1653 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1654 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1655 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1656 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1657 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1658 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1659 Improve robustness */
1660 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1661 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1662 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1663 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1664 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1665 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1666 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1667 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1668 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1669 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1670
1671 afe_write(sd, 0x00, 0xff); /* power down ADC */
1672 afe_write(sd, 0xc8, 0x40); /* phase control */
1673
1674 /* set to default gain for HDMI */
1675 cp_write(sd, 0x73, 0x10);
1676 cp_write(sd, 0x74, 0x04);
1677 cp_write(sd, 0x75, 0x01);
1678 cp_write(sd, 0x76, 0x00);
1679
1680 /* reset ADI recommended settings for digitizer */
1681 /* "ADV7842 Register Settings Recommendations
1682 * (rev. 2.5, June 2010)" p. 17. */
1683 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1684 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1685 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1686 enable color control */
1687 /* CP coast control */
1688 cp_write(sd, 0xc3, 0x33); /* Component mode */
1689
1690 /* color space conversion, autodetect color space */
1691 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1692 break;
1693
1694 default:
1695 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1696 __func__, state->mode);
1697 break;
1698 }
1699}
1700
1701static int adv7842_s_routing(struct v4l2_subdev *sd,
1702 u32 input, u32 output, u32 config)
1703{
1704 struct adv7842_state *state = to_state(sd);
1705
1706 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1707
1708 switch (input) {
1709 case ADV7842_SELECT_HDMI_PORT_A:
a89bcd4c
HV		 1710 state->mode = ADV7842_MODE_HDMI;
1711 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1712 state->hdmi_port_a = true;
1713 break;
1714 case ADV7842_SELECT_HDMI_PORT_B:
a89bcd4c
HV		 1715 state->mode = ADV7842_MODE_HDMI;
1716 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1717 state->hdmi_port_a = false;
1718 break;
1719 case ADV7842_SELECT_VGA_COMP:
69e9ba6f
HV		 1720 state->mode = ADV7842_MODE_COMP;
1721 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1722 break;
a89bcd4c
HV		 1723 case ADV7842_SELECT_VGA_RGB:
1724 state->mode = ADV7842_MODE_RGB;
1725 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1726 break;
1727 case ADV7842_SELECT_SDP_CVBS:
1728 state->mode = ADV7842_MODE_SDP;
1729 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1730 break;
1731 case ADV7842_SELECT_SDP_YC:
1732 state->mode = ADV7842_MODE_SDP;
1733 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1734 break;
1735 default:
1736 return -EINVAL;
1737 }
1738
1739 disable_input(sd);
1740 select_input(sd, state->vid_std_select);
1741 enable_input(sd);
1742
1743 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1744
1745 return 0;
1746}
1747
1748static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1749 enum v4l2_mbus_pixelcode *code)
1750{
1751 if (index)
1752 return -EINVAL;
1753 /* Good enough for now */
1754 *code = V4L2_MBUS_FMT_FIXED;
1755 return 0;
1756}
1757
1758static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1759 struct v4l2_mbus_framefmt *fmt)
1760{
1761 struct adv7842_state *state = to_state(sd);
1762
1763 fmt->width = state->timings.bt.width;
1764 fmt->height = state->timings.bt.height;
1765 fmt->code = V4L2_MBUS_FMT_FIXED;
1766 fmt->field = V4L2_FIELD_NONE;
1767
1768 if (state->mode == ADV7842_MODE_SDP) {
1769 /* SPD block */
1770 if (!(sdp_read(sd, 0x5A) & 0x01))
1771 return -EINVAL;
1772 fmt->width = 720;
1773 /* valid signal */
1774 if (state->norm & V4L2_STD_525_60)
1775 fmt->height = 480;
1776 else
1777 fmt->height = 576;
1778 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1779 return 0;
1780 }
1781
1782 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1783 fmt->colorspace = (state->timings.bt.height <= 576) ?
1784 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1785 }
1786 return 0;
1787}
1788
1789static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1790{
1791 if (enable) {
1792 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1793 io_write(sd, 0x46, 0x9c);
1794 /* ESDP_50HZ_DET interrupt */
1795 io_write(sd, 0x5a, 0x10);
1796 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1797 io_write(sd, 0x73, 0x03);
1798 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1799 io_write(sd, 0x78, 0x03);
1800 /* Enable SDP Standard Detection Change and SDP Video Detected */
1801 io_write(sd, 0xa0, 0x09);
1802 } else {
1803 io_write(sd, 0x46, 0x0);
1804 io_write(sd, 0x5a, 0x0);
1805 io_write(sd, 0x73, 0x0);
1806 io_write(sd, 0x78, 0x0);
1807 io_write(sd, 0xa0, 0x0);
1808 }
1809}
1810
1811static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1812{
1813 struct adv7842_state *state = to_state(sd);
1814 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1815 u8 irq_status[5];
a89bcd4c 1816
c9f1f271 1817 adv7842_irq_enable(sd, false);
a89bcd4c
HV		 1818
1819 /* read status */
1820 irq_status[0] = io_read(sd, 0x43);
1821 irq_status[1] = io_read(sd, 0x57);
1822 irq_status[2] = io_read(sd, 0x70);
1823 irq_status[3] = io_read(sd, 0x75);
1824 irq_status[4] = io_read(sd, 0x9d);
1825
1826 /* and clear */
1827 if (irq_status[0])
1828 io_write(sd, 0x44, irq_status[0]);
1829 if (irq_status[1])
1830 io_write(sd, 0x58, irq_status[1]);
1831 if (irq_status[2])
1832 io_write(sd, 0x71, irq_status[2]);
1833 if (irq_status[3])
1834 io_write(sd, 0x76, irq_status[3]);
1835 if (irq_status[4])
1836 io_write(sd, 0x9e, irq_status[4]);
1837
c9f1f271
MB		 1838 adv7842_irq_enable(sd, true);
1839
a89bcd4c
HV		 1840 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1841 irq_status[0], irq_status[1], irq_status[2],
1842 irq_status[3], irq_status[4]);
1843
1844 /* format change CP */
1845 fmt_change_cp = irq_status[0] & 0x9c;
1846
1847 /* format change SDP */
1848 if (state->mode == ADV7842_MODE_SDP)
1849 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1850 else
1851 fmt_change_sdp = 0;
1852
1853 /* digital format CP */
1854 if (is_digital_input(sd))
1855 fmt_change_digital = irq_status[3] & 0x03;
1856 else
1857 fmt_change_digital = 0;
1858
1859 /* notify */
1860 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1861 v4l2_dbg(1, debug, sd,
1862 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1863 __func__, fmt_change_cp, fmt_change_digital,
1864 fmt_change_sdp);
1865 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1866 }
1867
1868 /* 5v cable detect */
1869 if (irq_status[2])
1870 adv7842_s_detect_tx_5v_ctrl(sd);
1871
1872 if (handled)
1873 *handled = true;
1874
a89bcd4c
HV		 1875 return 0;
1876}
1877
1878static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1879{
1880 struct adv7842_state *state = to_state(sd);
1881 int err = 0;
1882
7de6fab1 1883 if (e->pad > ADV7842_EDID_PORT_VGA)
a89bcd4c
HV		 1884 return -EINVAL;
1885 if (e->start_block != 0)
1886 return -EINVAL;
1887 if (e->blocks > 2)
1888 return -E2BIG;
1889 if (!e->edid)
1890 return -EINVAL;
1891
1892 /* todo, per edid */
1893 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1894 e->edid[0x16]);
1895
7de6fab1
MR		 1896 switch (e->pad) {
1897 case ADV7842_EDID_PORT_VGA:
a89bcd4c
HV		 1898 memset(&state->vga_edid.edid, 0, 256);
1899 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1900 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1901 err = edid_write_vga_segment(sd);
7de6fab1
MR		 1902 break;
1903 case ADV7842_EDID_PORT_A:
1904 case ADV7842_EDID_PORT_B:
a89bcd4c
HV		 1905 memset(&state->hdmi_edid.edid, 0, 256);
1906 if (e->blocks)
7de6fab1 1907 state->hdmi_edid.present |= 0x04 << e->pad;
a89bcd4c 1908 else
7de6fab1
MR		 1909 state->hdmi_edid.present &= ~(0x04 << e->pad);
1910 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
a89bcd4c 1911 err = edid_write_hdmi_segment(sd, e->pad);
7de6fab1
MR		 1912 break;
1913 default:
1914 return -EINVAL;
a89bcd4c
HV		 1915 }
1916 if (err < 0)
1917 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1918 return err;
1919}
1920
1921/*********** avi info frame CEA-861-E **************/
1922/* TODO move to common library */
1923
1924struct avi_info_frame {
1925 uint8_t f17;
1926 uint8_t y10;
1927 uint8_t a0;
1928 uint8_t b10;
1929 uint8_t s10;
1930 uint8_t c10;
1931 uint8_t m10;
1932 uint8_t r3210;
1933 uint8_t itc;
1934 uint8_t ec210;
1935 uint8_t q10;
1936 uint8_t sc10;
1937 uint8_t f47;
1938 uint8_t vic;
1939 uint8_t yq10;
1940 uint8_t cn10;
1941 uint8_t pr3210;
1942 uint16_t etb;
1943 uint16_t sbb;
1944 uint16_t elb;
1945 uint16_t srb;
1946};
1947
1948static const char *y10_txt[4] = {
1949 "RGB",
1950 "YCbCr 4:2:2",
1951 "YCbCr 4:4:4",
1952 "Future",
1953};
1954
1955static const char *c10_txt[4] = {
1956 "No Data",
1957 "SMPTE 170M",
1958 "ITU-R 709",
1959 "Extended Colorimetry information valied",
1960};
1961
1962static const char *itc_txt[2] = {
1963 "No Data",
1964 "IT content",
1965};
1966
1967static const char *ec210_txt[8] = {
1968 "xvYCC601",
1969 "xvYCC709",
1970 "sYCC601",
1971 "AdobeYCC601",
1972 "AdobeRGB",
1973 "5 reserved",
1974 "6 reserved",
1975 "7 reserved",
1976};
1977
1978static const char *q10_txt[4] = {
1979 "Default",
1980 "Limited Range",
1981 "Full Range",
1982 "Reserved",
1983};
1984
1985static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
1986 struct avi_info_frame *avi)
1987{
1988 avi->f17 = (buf[1] >> 7) & 0x1;
1989 avi->y10 = (buf[1] >> 5) & 0x3;
1990 avi->a0 = (buf[1] >> 4) & 0x1;
1991 avi->b10 = (buf[1] >> 2) & 0x3;
1992 avi->s10 = buf[1] & 0x3;
1993 avi->c10 = (buf[2] >> 6) & 0x3;
1994 avi->m10 = (buf[2] >> 4) & 0x3;
1995 avi->r3210 = buf[2] & 0xf;
1996 avi->itc = (buf[3] >> 7) & 0x1;
1997 avi->ec210 = (buf[3] >> 4) & 0x7;
1998 avi->q10 = (buf[3] >> 2) & 0x3;
1999 avi->sc10 = buf[3] & 0x3;
2000 avi->f47 = (buf[4] >> 7) & 0x1;
2001 avi->vic = buf[4] & 0x7f;
2002 avi->yq10 = (buf[5] >> 6) & 0x3;
2003 avi->cn10 = (buf[5] >> 4) & 0x3;
2004 avi->pr3210 = buf[5] & 0xf;
2005 avi->etb = buf[6] + 256*buf[7];
2006 avi->sbb = buf[8] + 256*buf[9];
2007 avi->elb = buf[10] + 256*buf[11];
2008 avi->srb = buf[12] + 256*buf[13];
2009}
2010
2011static void print_avi_infoframe(struct v4l2_subdev *sd)
2012{
2013 int i;
2014 uint8_t buf[14];
2015 uint8_t avi_inf_len;
2016 struct avi_info_frame avi;
2017
2018 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2019 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2020 return;
2021 }
2022 if (!(io_read(sd, 0x60) & 0x01)) {
2023 v4l2_info(sd, "AVI infoframe not received\n");
2024 return;
2025 }
2026
2027 if (io_read(sd, 0x88) & 0x10) {
2028 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2029 with a length of 14 or 15. See the ADV7842 Register Settings
2030 Recommendations document for more details. */
2031 v4l2_info(sd, "AVI infoframe checksum error\n");
2032 return;
2033 }
2034
2035 avi_inf_len = infoframe_read(sd, 0xe2);
2036 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2037 infoframe_read(sd, 0xe1), avi_inf_len);
2038
2039 if (infoframe_read(sd, 0xe1) != 0x02)
2040 return;
2041
2042 for (i = 0; i < 14; i++)
2043 buf[i] = infoframe_read(sd, i);
2044
2045 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2046 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2047 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2048
2049 parse_avi_infoframe(sd, buf, &avi);
2050
2051 if (avi.vic)
2052 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2053 if (avi.itc)
2054 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2055
2056 if (avi.y10)
2057 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2058 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2059 else
2060 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2061}
2062
2063static const char * const prim_mode_txt[] = {
2064 "SDP",
2065 "Component",
2066 "Graphics",
2067 "Reserved",
2068 "CVBS & HDMI AUDIO",
2069 "HDMI-Comp",
2070 "HDMI-GR",
2071 "Reserved",
2072 "Reserved",
2073 "Reserved",
2074 "Reserved",
2075 "Reserved",
2076 "Reserved",
2077 "Reserved",
2078 "Reserved",
2079 "Reserved",
2080};
2081
2082static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2083{
2084 /* SDP (Standard definition processor) block */
2085 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2086
2087 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2088 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2089 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2090
2091 v4l2_info(sd, "SDP: free run: %s\n",
2092 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2093 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2094 "valid SD/PR signal detected" : "invalid/no signal");
2095 if (sdp_signal_detected) {
2096 static const char * const sdp_std_txt[] = {
2097 "NTSC-M/J",
2098 "1?",
2099 "NTSC-443",
2100 "60HzSECAM",
2101 "PAL-M",
2102 "5?",
2103 "PAL-60",
2104 "7?", "8?", "9?", "a?", "b?",
2105 "PAL-CombN",
2106 "d?",
2107 "PAL-BGHID",
2108 "SECAM"
2109 };
2110 v4l2_info(sd, "SDP: standard %s\n",
2111 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2112 v4l2_info(sd, "SDP: %s\n",
2113 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2114 v4l2_info(sd, "SDP: %s\n",
2115 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2116 v4l2_info(sd, "SDP: deinterlacer %s\n",
2117 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2118 v4l2_info(sd, "SDP: csc %s mode\n",
2119 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2120 }
2121 return 0;
2122}
2123
2124static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2125{
2126 /* CP block */
2127 struct adv7842_state *state = to_state(sd);
2128 struct v4l2_dv_timings timings;
2129 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2130 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2131 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2132 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2133 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2134 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2135 bool audio_mute = io_read(sd, 0x65) & 0x40;
2136
2137 static const char * const csc_coeff_sel_rb[16] = {
2138 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2139 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2140 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2141 "reserved", "reserved", "reserved", "reserved", "manual"
2142 };
2143 static const char * const input_color_space_txt[16] = {
2144 "RGB limited range (16-235)", "RGB full range (0-255)",
2145 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
69e9ba6f 2146 "xvYCC Bt.601", "xvYCC Bt.709",
a89bcd4c
HV		 2147 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2148 "invalid", "invalid", "invalid", "invalid", "invalid",
2149 "invalid", "invalid", "automatic"
2150 };
2151 static const char * const rgb_quantization_range_txt[] = {
2152 "Automatic",
2153 "RGB limited range (16-235)",
2154 "RGB full range (0-255)",
2155 };
2156 static const char * const deep_color_mode_txt[4] = {
2157 "8-bits per channel",
2158 "10-bits per channel",
2159 "12-bits per channel",
2160 "16-bits per channel (not supported)"
2161 };
2162
2163 v4l2_info(sd, "-----Chip status-----\n");
2164 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
a89bcd4c
HV		 2165 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2166 state->hdmi_port_a ? "A" : "B");
2167 v4l2_info(sd, "EDID A %s, B %s\n",
2168 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2169 "enabled" : "disabled",
2170 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2171 "enabled" : "disabled");
2172 v4l2_info(sd, "HPD A %s, B %s\n",
2173 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2174 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2175 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2176 "enabled" : "disabled");
2177
2178 v4l2_info(sd, "-----Signal status-----\n");
2179 if (state->hdmi_port_a) {
2180 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2181 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2182 v4l2_info(sd, "TMDS signal detected: %s\n",
2183 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2184 v4l2_info(sd, "TMDS signal locked: %s\n",
2185 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2186 } else {
2187 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2188 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2189 v4l2_info(sd, "TMDS signal detected: %s\n",
2190 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2191 v4l2_info(sd, "TMDS signal locked: %s\n",
2192 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2193 }
2194 v4l2_info(sd, "CP free run: %s\n",
2195 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2196 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2197 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2198 (io_read(sd, 0x01) & 0x70) >> 4);
2199
2200 v4l2_info(sd, "-----Video Timings-----\n");
2201 if (no_cp_signal(sd)) {
2202 v4l2_info(sd, "STDI: not locked\n");
2203 } else {
2204 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2205 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2206 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2207 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2208 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2209 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2210 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2211 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2212 v4l2_info(sd,
2213 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2214 lcf, bl, lcvs, fcl,
2215 (cp_read(sd, 0xb1) & 0x40) ?
2216 "interlaced" : "progressive",
2217 hs_pol, vs_pol);
2218 }
2219 if (adv7842_query_dv_timings(sd, &timings))
2220 v4l2_info(sd, "No video detected\n");
2221 else
2222 v4l2_print_dv_timings(sd->name, "Detected format: ",
2223 &timings, true);
2224 v4l2_print_dv_timings(sd->name, "Configured format: ",
2225 &state->timings, true);
2226
2227 if (no_cp_signal(sd))
2228 return 0;
2229
2230 v4l2_info(sd, "-----Color space-----\n");
2231 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2232 rgb_quantization_range_txt[state->rgb_quantization_range]);
2233 v4l2_info(sd, "Input color space: %s\n",
2234 input_color_space_txt[reg_io_0x02 >> 4]);
2235 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2236 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2237 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2238 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2239 "enabled" : "disabled");
2240 v4l2_info(sd, "Color space conversion: %s\n",
2241 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2242
2243 if (!is_digital_input(sd))
2244 return 0;
2245
2246 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2247 v4l2_info(sd, "HDCP encrypted content: %s\n",
2248 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2249 v4l2_info(sd, "HDCP keys read: %s%s\n",
2250 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2251 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2252 if (!is_hdmi(sd))
2253 return 0;
2254
2255 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2256 audio_pll_locked ? "locked" : "not locked",
2257 audio_sample_packet_detect ? "detected" : "not detected",
2258 audio_mute ? "muted" : "enabled");
2259 if (audio_pll_locked && audio_sample_packet_detect) {
2260 v4l2_info(sd, "Audio format: %s\n",
2261 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2262 }
2263 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2264 (hdmi_read(sd, 0x5c) << 8) +
2265 (hdmi_read(sd, 0x5d) & 0xf0));
2266 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2267 (hdmi_read(sd, 0x5e) << 8) +
2268 hdmi_read(sd, 0x5f));
2269 v4l2_info(sd, "AV Mute: %s\n",
2270 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2271 v4l2_info(sd, "Deep color mode: %s\n",
2272 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2273
2274 print_avi_infoframe(sd);
2275 return 0;
2276}
2277
2278static int adv7842_log_status(struct v4l2_subdev *sd)
2279{
2280 struct adv7842_state *state = to_state(sd);
2281
2282 if (state->mode == ADV7842_MODE_SDP)
2283 return adv7842_sdp_log_status(sd);
2284 return adv7842_cp_log_status(sd);
2285}
2286
2287static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2288{
2289 struct adv7842_state *state = to_state(sd);
2290
2291 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2292
2293 if (state->mode != ADV7842_MODE_SDP)
2294 return -ENODATA;
2295
2296 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2297 *std = 0;
2298 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2299 return 0;
2300 }
2301
2302 switch (sdp_read(sd, 0x52) & 0x0f) {
2303 case 0:
2304 /* NTSC-M/J */
2305 *std &= V4L2_STD_NTSC;
2306 break;
2307 case 2:
2308 /* NTSC-443 */
2309 *std &= V4L2_STD_NTSC_443;
2310 break;
2311 case 3:
2312 /* 60HzSECAM */
2313 *std &= V4L2_STD_SECAM;
2314 break;
2315 case 4:
2316 /* PAL-M */
2317 *std &= V4L2_STD_PAL_M;
2318 break;
2319 case 6:
2320 /* PAL-60 */
2321 *std &= V4L2_STD_PAL_60;
2322 break;
2323 case 0xc:
2324 /* PAL-CombN */
2325 *std &= V4L2_STD_PAL_Nc;
2326 break;
2327 case 0xe:
2328 /* PAL-BGHID */
2329 *std &= V4L2_STD_PAL;
2330 break;
2331 case 0xf:
2332 /* SECAM */
2333 *std &= V4L2_STD_SECAM;
2334 break;
2335 default:
2336 *std &= V4L2_STD_ALL;
2337 break;
2338 }
2339 return 0;
2340}
2341
3c4da74f
MB		 2342static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2343{
2344 if (s && s->adjust) {
2345 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2346 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2347 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2348 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2349 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2350 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2351 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2352 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2353 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2354 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2355 sdp_io_write(sd, 0xae, s->de_v_end_o);
2356 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2357 } else {
2358 /* set to default */
2359 sdp_io_write(sd, 0x94, 0x00);
2360 sdp_io_write(sd, 0x95, 0x00);
2361 sdp_io_write(sd, 0x96, 0x00);
2362 sdp_io_write(sd, 0x97, 0x20);
2363 sdp_io_write(sd, 0x98, 0x00);
2364 sdp_io_write(sd, 0x99, 0x00);
2365 sdp_io_write(sd, 0x9a, 0x00);
2366 sdp_io_write(sd, 0x9b, 0x00);
2367 sdp_io_write(sd, 0xac, 0x04);
2368 sdp_io_write(sd, 0xad, 0x04);
2369 sdp_io_write(sd, 0xae, 0x04);
2370 sdp_io_write(sd, 0xaf, 0x04);
2371 }
2372}
2373
a89bcd4c
HV		 2374static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2375{
2376 struct adv7842_state *state = to_state(sd);
3c4da74f 2377 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2378
2379 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2380
2381 if (state->mode != ADV7842_MODE_SDP)
2382 return -ENODATA;
2383
3c4da74f
MB		 2384 if (norm & V4L2_STD_625_50)
2385 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2386 else if (norm & V4L2_STD_525_60)
2387 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2388 else
2389 adv7842_s_sdp_io(sd, NULL);
2390
a89bcd4c
HV		 2391 if (norm & V4L2_STD_ALL) {
2392 state->norm = norm;
2393 return 0;
2394 }
2395 return -EINVAL;
2396}
2397
2398static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2399{
2400 struct adv7842_state *state = to_state(sd);
2401
2402 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2403
2404 if (state->mode != ADV7842_MODE_SDP)
2405 return -ENODATA;
2406
2407 *norm = state->norm;
2408 return 0;
2409}
2410
2411/* ----------------------------------------------------------------------- */
2412
69e9ba6f 2413static int adv7842_core_init(struct v4l2_subdev *sd)
a89bcd4c 2414{
69e9ba6f
HV		 2415 struct adv7842_state *state = to_state(sd);
2416 struct adv7842_platform_data *pdata = &state->pdata;
a89bcd4c
HV		 2417 hdmi_write(sd, 0x48,
2418 (pdata->disable_pwrdnb ? 0x80 : 0) |
2419 (pdata->disable_cable_det_rst ? 0x40 : 0));
2420
2421 disable_input(sd);
2422
2423 /* power */
2424 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2425 io_write(sd, 0x15, 0x80); /* Power up pads */
2426
2427 /* video format */
2428 io_write(sd, 0x02,
69e9ba6f 2429 0xf0 |
a89bcd4c
HV		 2430 pdata->alt_gamma << 3 |
2431 pdata->op_656_range << 2 |
2432 pdata->rgb_out << 1 |
2433 pdata->alt_data_sat << 0);
2434 io_write(sd, 0x03, pdata->op_format_sel);
2435 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2436 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2437 pdata->insert_av_codes << 2 |
2438 pdata->replicate_av_codes << 1 |
2439 pdata->invert_cbcr << 0);
2440
5b64b205
MR		 2441 /* HDMI audio */
2442 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2443
a89bcd4c
HV		 2444 /* Drive strength */
2445 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2446 pdata->drive_strength.clock<<2 |
2447 pdata->drive_strength.sync);
2448
2449 /* HDMI free run */
2450 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2451
2452 /* TODO from platform data */
2453 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2454 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2455 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2456 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2457
2458 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2459 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2460
2461 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2462
a89bcd4c
HV		 2463 /* todo, improve settings for sdram */
2464 if (pdata->sd_ram_size >= 128) {
2465 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2466 if (pdata->sd_ram_ddr) {
2467 /* SDP setup for the AD eval board */
2468 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2469 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2470 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2471 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2472 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2473 } else {
2474 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2475 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2476 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2477 depends on memory */
2478 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2479 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2480 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2481 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2482 }
2483 } else {
2484 /*
2485 * Manual UG-214, rev 0 is bit confusing on this bit
2486 * but a '1' disables any signal if the Ram is active.
2487 */
2488 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2489 }
2490
2491 select_input(sd, pdata->vid_std_select);
2492
2493 enable_input(sd);
2494
2495 /* disable I2C access to internal EDID ram from HDMI DDC ports */
2496 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2497
2498 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2499 /* HPA disable on port A and B */
2500 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2501
2502 /* LLC */
2503 /* Set phase to 16. TODO: get this from platform_data */
2504 io_write(sd, 0x19, 0x90);
2505 io_write(sd, 0x33, 0x40);
2506
2507 /* interrupts */
c9f1f271 2508 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
a89bcd4c
HV		 2509
2510 adv7842_irq_enable(sd, true);
2511
2512 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2513}
2514
2515/* ----------------------------------------------------------------------- */
2516
2517static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2518{
2519 /*
2520 * From ADV784x external Memory test.pdf
2521 *
2522 * Reset must just been performed before running test.
2523 * Recommended to reset after test.
2524 */
2525 int i;
2526 int pass = 0;
2527 int fail = 0;
2528 int complete = 0;
2529
2530 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2531 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2532 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2533 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2534 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2535 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2536 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2537 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2538 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2539 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2540 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2541 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2542
2543 mdelay(5);
2544
2545 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2546 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2547 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2548 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2549 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2550 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2551 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2552 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2553 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2554 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2555 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2556
2557 mdelay(5);
2558
2559 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2560 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2561
2562 mdelay(20);
2563
2564 for (i = 0; i < 10; i++) {
2565 u8 result = sdp_io_read(sd, 0xdb);
2566 if (result & 0x10) {
2567 complete++;
2568 if (result & 0x20)
2569 fail++;
2570 else
2571 pass++;
2572 }
2573 mdelay(20);
2574 }
2575
2576 v4l2_dbg(1, debug, sd,
2577 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2578 complete, i, pass, fail);
2579
2580 if (!complete || fail)
2581 return -EIO;
2582 return 0;
2583}
2584
2585static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2586 struct adv7842_platform_data *pdata)
2587{
2588 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2589 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2590 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2591 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2592 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2593
2594 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2595 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2596 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2597 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2598
2599 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2600 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2601}
2602
2603static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2604{
2605 struct i2c_client *client = v4l2_get_subdevdata(sd);
2606 struct adv7842_state *state = to_state(sd);
2607 struct adv7842_platform_data *pdata = client->dev.platform_data;
2608 int ret = 0;
2609
2610 if (!pdata)
2611 return -ENODEV;
2612
2613 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2614 v4l2_info(sd, "no sdram or no ddr sdram\n");
2615 return -EINVAL;
2616 }
2617
2618 main_reset(sd);
2619
2620 adv7842_rewrite_i2c_addresses(sd, pdata);
2621
2622 /* run ram test */
2623 ret = adv7842_ddr_ram_test(sd);
2624
2625 main_reset(sd);
2626
2627 adv7842_rewrite_i2c_addresses(sd, pdata);
2628
2629 /* and re-init chip and state */
69e9ba6f 2630 adv7842_core_init(sd);
a89bcd4c
HV		 2631
2632 disable_input(sd);
2633
2634 select_input(sd, state->vid_std_select);
2635
2636 enable_input(sd);
2637
2638 adv7842_s_dv_timings(sd, &state->timings);
2639
2640 edid_write_vga_segment(sd);
2641 edid_write_hdmi_segment(sd, 0);
2642 edid_write_hdmi_segment(sd, 1);
2643
2644 return ret;
2645}
2646
2647static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2648{
2649 switch (cmd) {
2650 case ADV7842_CMD_RAM_TEST:
2651 return adv7842_command_ram_test(sd);
2652 }
2653 return -ENOTTY;
2654}
2655
2656/* ----------------------------------------------------------------------- */
2657
2658static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2659 .s_ctrl = adv7842_s_ctrl,
2660};
2661
2662static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2663 .log_status = adv7842_log_status,
2664 .g_std = adv7842_g_std,
2665 .s_std = adv7842_s_std,
2666 .ioctl = adv7842_ioctl,
2667 .interrupt_service_routine = adv7842_isr,
2668#ifdef CONFIG_VIDEO_ADV_DEBUG
2669 .g_register = adv7842_g_register,
2670 .s_register = adv7842_s_register,
2671#endif
2672};
2673
2674static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2675 .s_routing = adv7842_s_routing,
2676 .querystd = adv7842_querystd,
2677 .g_input_status = adv7842_g_input_status,
2678 .s_dv_timings = adv7842_s_dv_timings,
2679 .g_dv_timings = adv7842_g_dv_timings,
2680 .query_dv_timings = adv7842_query_dv_timings,
2681 .enum_dv_timings = adv7842_enum_dv_timings,
2682 .dv_timings_cap = adv7842_dv_timings_cap,
2683 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2684 .g_mbus_fmt = adv7842_g_mbus_fmt,
2685 .try_mbus_fmt = adv7842_g_mbus_fmt,
2686 .s_mbus_fmt = adv7842_g_mbus_fmt,
2687};
2688
2689static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2690 .set_edid = adv7842_set_edid,
2691};
2692
2693static const struct v4l2_subdev_ops adv7842_ops = {
2694 .core = &adv7842_core_ops,
2695 .video = &adv7842_video_ops,
2696 .pad = &adv7842_pad_ops,
2697};
2698
2699/* -------------------------- custom ctrls ---------------------------------- */
2700
2701static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2702 .ops = &adv7842_ctrl_ops,
2703 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2704 .name = "Analog Sampling Phase",
2705 .type = V4L2_CTRL_TYPE_INTEGER,
2706 .min = 0,
2707 .max = 0x1f,
2708 .step = 1,
2709 .def = 0,
2710};
2711
2712static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2713 .ops = &adv7842_ctrl_ops,
2714 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2715 .name = "Free Running Color, Manual",
2716 .type = V4L2_CTRL_TYPE_BOOLEAN,
2717 .max = 1,
2718 .step = 1,
2719 .def = 1,
2720};
2721
2722static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2723 .ops = &adv7842_ctrl_ops,
2724 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2725 .name = "Free Running Color",
2726 .type = V4L2_CTRL_TYPE_INTEGER,
2727 .max = 0xffffff,
2728 .step = 0x1,
2729};
2730
2731
2732static void adv7842_unregister_clients(struct adv7842_state *state)
2733{
2734 if (state->i2c_avlink)
2735 i2c_unregister_device(state->i2c_avlink);
2736 if (state->i2c_cec)
2737 i2c_unregister_device(state->i2c_cec);
2738 if (state->i2c_infoframe)
2739 i2c_unregister_device(state->i2c_infoframe);
2740 if (state->i2c_sdp_io)
2741 i2c_unregister_device(state->i2c_sdp_io);
2742 if (state->i2c_sdp)
2743 i2c_unregister_device(state->i2c_sdp);
2744 if (state->i2c_afe)
2745 i2c_unregister_device(state->i2c_afe);
2746 if (state->i2c_repeater)
2747 i2c_unregister_device(state->i2c_repeater);
2748 if (state->i2c_edid)
2749 i2c_unregister_device(state->i2c_edid);
2750 if (state->i2c_hdmi)
2751 i2c_unregister_device(state->i2c_hdmi);
2752 if (state->i2c_cp)
2753 i2c_unregister_device(state->i2c_cp);
2754 if (state->i2c_vdp)
2755 i2c_unregister_device(state->i2c_vdp);
2756}
2757
2758static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2759 u8 addr, u8 io_reg)
2760{
2761 struct i2c_client *client = v4l2_get_subdevdata(sd);
2762
2763 io_write(sd, io_reg, addr << 1);
2764 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2765}
2766
2767static int adv7842_probe(struct i2c_client *client,
2768 const struct i2c_device_id *id)
2769{
2770 struct adv7842_state *state;
2771 struct adv7842_platform_data *pdata = client->dev.platform_data;
2772 struct v4l2_ctrl_handler *hdl;
2773 struct v4l2_subdev *sd;
2774 u16 rev;
2775 int err;
2776
2777 /* Check if the adapter supports the needed features */
2778 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2779 return -EIO;
2780
2781 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2782 client->addr << 1);
2783
2784 if (!pdata) {
2785 v4l_err(client, "No platform data!\n");
2786 return -ENODEV;
2787 }
2788
2789 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2790 if (!state) {
2791 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2792 return -ENOMEM;
2793 }
2794
7de5be44
MB		 2795 /* platform data */
2796 state->pdata = *pdata;
2797
a89bcd4c
HV		 2798 sd = &state->sd;
2799 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2800 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
a89bcd4c
HV		 2801 state->mode = pdata->mode;
2802
8e4e3631 2803 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
a89bcd4c
HV		 2804
2805 /* i2c access to adv7842? */
2806 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2807 adv_smbus_read_byte_data_check(client, 0xeb, false);
2808 if (rev != 0x2012) {
2809 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2810 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2811 adv_smbus_read_byte_data_check(client, 0xeb, false);
2812 }
2813 if (rev != 0x2012) {
2814 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2815 client->addr << 1, rev);
2816 return -ENODEV;
2817 }
2818
2819 if (pdata->chip_reset)
2820 main_reset(sd);
2821
2822 /* control handlers */
2823 hdl = &state->hdl;
2824 v4l2_ctrl_handler_init(hdl, 6);
2825
2826 /* add in ascending ID order */
2827 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2828 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2829 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2830 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2831 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2832 V4L2_CID_SATURATION, 0, 255, 1, 128);
2833 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2834 V4L2_CID_HUE, 0, 128, 1, 0);
2835
2836 /* custom controls */
2837 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2838 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2839 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2840 &adv7842_ctrl_analog_sampling_phase, NULL);
2841 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2842 &adv7842_ctrl_free_run_color_manual, NULL);
2843 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2844 &adv7842_ctrl_free_run_color, NULL);
2845 state->rgb_quantization_range_ctrl =
2846 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2847 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2848 0, V4L2_DV_RGB_RANGE_AUTO);
2849 sd->ctrl_handler = hdl;
2850 if (hdl->error) {
2851 err = hdl->error;
2852 goto err_hdl;
2853 }
2854 state->detect_tx_5v_ctrl->is_private = true;
2855 state->rgb_quantization_range_ctrl->is_private = true;
2856 state->analog_sampling_phase_ctrl->is_private = true;
2857 state->free_run_color_ctrl_manual->is_private = true;
2858 state->free_run_color_ctrl->is_private = true;
2859
2860 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2861 err = -ENODEV;
2862 goto err_hdl;
2863 }
2864
2865 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2866 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2867 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2868 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2869 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2870 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2871 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2872 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2873 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2874 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2875 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2876 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2877 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2878 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2879 !state->i2c_cp || !state->i2c_vdp) {
2880 err = -ENOMEM;
2881 v4l2_err(sd, "failed to create all i2c clients\n");
2882 goto err_i2c;
2883 }
2884
2885 /* work queues */
2886 state->work_queues = create_singlethread_workqueue(client->name);
2887 if (!state->work_queues) {
2888 v4l2_err(sd, "Could not create work queue\n");
2889 err = -ENOMEM;
2890 goto err_i2c;
2891 }
2892
2893 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2894 adv7842_delayed_work_enable_hotplug);
2895
2896 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2897 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2898 if (err)
2899 goto err_work_queues;
2900
7de5be44 2901 err = adv7842_core_init(sd);
a89bcd4c
HV		 2902 if (err)
2903 goto err_entity;
2904
2905 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2906 client->addr << 1, client->adapter->name);
2907 return 0;
2908
2909err_entity:
2910 media_entity_cleanup(&sd->entity);
2911err_work_queues:
2912 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2913 destroy_workqueue(state->work_queues);
2914err_i2c:
2915 adv7842_unregister_clients(state);
2916err_hdl:
2917 v4l2_ctrl_handler_free(hdl);
2918 return err;
2919}
2920
2921/* ----------------------------------------------------------------------- */
2922
2923static int adv7842_remove(struct i2c_client *client)
2924{
2925 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2926 struct adv7842_state *state = to_state(sd);
2927
2928 adv7842_irq_enable(sd, false);
2929
2930 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2931 destroy_workqueue(state->work_queues);
2932 v4l2_device_unregister_subdev(sd);
2933 media_entity_cleanup(&sd->entity);
2934 adv7842_unregister_clients(to_state(sd));
2935 v4l2_ctrl_handler_free(sd->ctrl_handler);
2936 return 0;
2937}
2938
2939/* ----------------------------------------------------------------------- */
2940
2941static struct i2c_device_id adv7842_id[] = {
2942 { "adv7842", 0 },
2943 { }
2944};
2945MODULE_DEVICE_TABLE(i2c, adv7842_id);
2946
2947/* ----------------------------------------------------------------------- */
2948
2949static struct i2c_driver adv7842_driver = {
2950 .driver = {
2951 .owner = THIS_MODULE,
2952 .name = "adv7842",
2953 },
2954 .probe = adv7842_probe,
2955 .remove = adv7842_remove,
2956 .id_table = adv7842_id,
2957};
2958
2959module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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