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[media] adv7842: Re-worked query_dv_timings()
[deliverable/linux.git] / drivers / media / i2c / adv7842.c
CommitLineData
a89bcd4c
HV		 1/*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 */
28
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/slab.h>
33#include <linux/i2c.h>
34#include <linux/delay.h>
35#include <linux/videodev2.h>
36#include <linux/workqueue.h>
37#include <linux/v4l2-dv-timings.h>
38#include <media/v4l2-device.h>
39#include <media/v4l2-ctrls.h>
40#include <media/v4l2-dv-timings.h>
41#include <media/adv7842.h>
42
43static int debug;
44module_param(debug, int, 0644);
45MODULE_PARM_DESC(debug, "debug level (0-2)");
46
47MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
48MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
49MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
50MODULE_LICENSE("GPL");
51
52/* ADV7842 system clock frequency */
53#define ADV7842_fsc (28636360)
54
55/*
56**********************************************************************
57*
58* Arrays with configuration parameters for the ADV7842
59*
60**********************************************************************
61*/
62
63struct adv7842_state {
64 struct v4l2_subdev sd;
65 struct media_pad pad;
66 struct v4l2_ctrl_handler hdl;
67 enum adv7842_mode mode;
68 struct v4l2_dv_timings timings;
69 enum adv7842_vid_std_select vid_std_select;
70 v4l2_std_id norm;
71 struct {
72 u8 edid[256];
73 u32 present;
74 } hdmi_edid;
75 struct {
76 u8 edid[256];
77 u32 present;
78 } vga_edid;
79 struct v4l2_fract aspect_ratio;
80 u32 rgb_quantization_range;
81 bool is_cea_format;
82 struct workqueue_struct *work_queues;
83 struct delayed_work delayed_work_enable_hotplug;
84 bool connector_hdmi;
85 bool hdmi_port_a;
86
87 /* i2c clients */
88 struct i2c_client *i2c_sdp_io;
89 struct i2c_client *i2c_sdp;
90 struct i2c_client *i2c_cp;
91 struct i2c_client *i2c_vdp;
92 struct i2c_client *i2c_afe;
93 struct i2c_client *i2c_hdmi;
94 struct i2c_client *i2c_repeater;
95 struct i2c_client *i2c_edid;
96 struct i2c_client *i2c_infoframe;
97 struct i2c_client *i2c_cec;
98 struct i2c_client *i2c_avlink;
99
100 /* controls */
101 struct v4l2_ctrl *detect_tx_5v_ctrl;
102 struct v4l2_ctrl *analog_sampling_phase_ctrl;
103 struct v4l2_ctrl *free_run_color_ctrl_manual;
104 struct v4l2_ctrl *free_run_color_ctrl;
105 struct v4l2_ctrl *rgb_quantization_range_ctrl;
106};
107
108/* Unsupported timings. This device cannot support 720p30. */
109static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
110 V4L2_DV_BT_CEA_1280X720P30,
111 { }
112};
113
114static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
115{
116 int i;
117
118 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
119 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
120 return false;
121 return true;
122}
123
124struct adv7842_video_standards {
125 struct v4l2_dv_timings timings;
126 u8 vid_std;
127 u8 v_freq;
128};
129
130/* sorted by number of lines */
131static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
132 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
133 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
134 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
135 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
136 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
137 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
138 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
139 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
140 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
141 /* TODO add 1920x1080P60_RB (CVT timing) */
142 { },
143};
144
145/* sorted by number of lines */
146static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
147 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
148 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
149 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
150 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
151 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
152 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
153 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
154 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
156 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
157 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
158 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
159 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
160 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
161 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
162 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
163 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
164 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
165 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
166 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
167 /* TODO add 1600X1200P60_RB (not a DMT timing) */
168 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
169 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
170 { },
171};
172
173/* sorted by number of lines */
174static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
175 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
184 { },
185};
186
187/* sorted by number of lines */
188static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
204 { },
205};
206
207/* ----------------------------------------------------------------------- */
208
209static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
210{
211 return container_of(sd, struct adv7842_state, sd);
212}
213
214static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
215{
216 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
217}
218
219static inline unsigned hblanking(const struct v4l2_bt_timings *t)
220{
221 return V4L2_DV_BT_BLANKING_WIDTH(t);
222}
223
224static inline unsigned htotal(const struct v4l2_bt_timings *t)
225{
226 return V4L2_DV_BT_FRAME_WIDTH(t);
227}
228
229static inline unsigned vblanking(const struct v4l2_bt_timings *t)
230{
231 return V4L2_DV_BT_BLANKING_HEIGHT(t);
232}
233
234static inline unsigned vtotal(const struct v4l2_bt_timings *t)
235{
236 return V4L2_DV_BT_FRAME_HEIGHT(t);
237}
238
239
240/* ----------------------------------------------------------------------- */
241
242static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
243 u8 command, bool check)
244{
245 union i2c_smbus_data data;
246
247 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
248 I2C_SMBUS_READ, command,
249 I2C_SMBUS_BYTE_DATA, &data))
250 return data.byte;
251 if (check)
252 v4l_err(client, "error reading %02x, %02x\n",
253 client->addr, command);
254 return -EIO;
255}
256
257static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
258{
259 int i;
260
261 for (i = 0; i < 3; i++) {
262 int ret = adv_smbus_read_byte_data_check(client, command, true);
263
264 if (ret >= 0) {
265 if (i)
266 v4l_err(client, "read ok after %d retries\n", i);
267 return ret;
268 }
269 }
270 v4l_err(client, "read failed\n");
271 return -EIO;
272}
273
274static s32 adv_smbus_write_byte_data(struct i2c_client *client,
275 u8 command, u8 value)
276{
277 union i2c_smbus_data data;
278 int err;
279 int i;
280
281 data.byte = value;
282 for (i = 0; i < 3; i++) {
283 err = i2c_smbus_xfer(client->adapter, client->addr,
284 client->flags,
285 I2C_SMBUS_WRITE, command,
286 I2C_SMBUS_BYTE_DATA, &data);
287 if (!err)
288 break;
289 }
290 if (err < 0)
291 v4l_err(client, "error writing %02x, %02x, %02x\n",
292 client->addr, command, value);
293 return err;
294}
295
296static void adv_smbus_write_byte_no_check(struct i2c_client *client,
297 u8 command, u8 value)
298{
299 union i2c_smbus_data data;
300 data.byte = value;
301
302 i2c_smbus_xfer(client->adapter, client->addr,
303 client->flags,
304 I2C_SMBUS_WRITE, command,
305 I2C_SMBUS_BYTE_DATA, &data);
306}
307
308static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
309 u8 command, unsigned length, const u8 *values)
310{
311 union i2c_smbus_data data;
312
313 if (length > I2C_SMBUS_BLOCK_MAX)
314 length = I2C_SMBUS_BLOCK_MAX;
315 data.block[0] = length;
316 memcpy(data.block + 1, values, length);
317 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
318 I2C_SMBUS_WRITE, command,
319 I2C_SMBUS_I2C_BLOCK_DATA, &data);
320}
321
322/* ----------------------------------------------------------------------- */
323
324static inline int io_read(struct v4l2_subdev *sd, u8 reg)
325{
326 struct i2c_client *client = v4l2_get_subdevdata(sd);
327
328 return adv_smbus_read_byte_data(client, reg);
329}
330
331static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
332{
333 struct i2c_client *client = v4l2_get_subdevdata(sd);
334
335 return adv_smbus_write_byte_data(client, reg, val);
336}
337
338static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
339{
340 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
341}
342
343static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
344{
345 struct adv7842_state *state = to_state(sd);
346
347 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
348}
349
350static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
351{
352 struct adv7842_state *state = to_state(sd);
353
354 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
355}
356
357static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
358{
359 struct adv7842_state *state = to_state(sd);
360
361 return adv_smbus_read_byte_data(state->i2c_cec, reg);
362}
363
364static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
365{
366 struct adv7842_state *state = to_state(sd);
367
368 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
369}
370
371static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
372{
373 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
374}
375
376static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
377{
378 struct adv7842_state *state = to_state(sd);
379
380 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
381}
382
383static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
384{
385 struct adv7842_state *state = to_state(sd);
386
387 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
388}
389
390static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
391{
392 struct adv7842_state *state = to_state(sd);
393
394 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
395}
396
397static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
398{
399 struct adv7842_state *state = to_state(sd);
400
401 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
402}
403
404static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
405{
406 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
407}
408
409static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
410{
411 struct adv7842_state *state = to_state(sd);
412
413 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
414}
415
416static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
417{
418 struct adv7842_state *state = to_state(sd);
419
420 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
421}
422
423static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
424{
425 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
426}
427
428static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
429{
430 struct adv7842_state *state = to_state(sd);
431
432 return adv_smbus_read_byte_data(state->i2c_afe, reg);
433}
434
435static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
436{
437 struct adv7842_state *state = to_state(sd);
438
439 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
440}
441
442static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
443{
444 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
445}
446
447static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
448{
449 struct adv7842_state *state = to_state(sd);
450
451 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
452}
453
454static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
455{
456 struct adv7842_state *state = to_state(sd);
457
458 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
459}
460
461static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
462{
463 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
464}
465
466static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
467{
468 struct adv7842_state *state = to_state(sd);
469
470 return adv_smbus_read_byte_data(state->i2c_edid, reg);
471}
472
473static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474{
475 struct adv7842_state *state = to_state(sd);
476
477 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
478}
479
480static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
481{
482 struct adv7842_state *state = to_state(sd);
483
484 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
485}
486
487static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
488{
489 struct adv7842_state *state = to_state(sd);
490
491 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
492}
493
494static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
495{
496 struct adv7842_state *state = to_state(sd);
497
498 return adv_smbus_read_byte_data(state->i2c_cp, reg);
499}
500
501static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
502{
503 struct adv7842_state *state = to_state(sd);
504
505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
506}
507
508static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
509{
510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
511}
512
513static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
514{
515 struct adv7842_state *state = to_state(sd);
516
517 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
518}
519
520static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
521{
522 struct adv7842_state *state = to_state(sd);
523
524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
525}
526
527static void main_reset(struct v4l2_subdev *sd)
528{
529 struct i2c_client *client = v4l2_get_subdevdata(sd);
530
531 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
532
533 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
534
535 mdelay(2);
536}
537
538/* ----------------------------------------------------------------------- */
539
540static inline bool is_digital_input(struct v4l2_subdev *sd)
541{
542 struct adv7842_state *state = to_state(sd);
543
544 return state->mode == ADV7842_MODE_HDMI;
545}
546
547static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
548 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 549 /* keep this initialization for compatibility with GCC < 4.4.6 */
550 .reserved = { 0 },
551 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
552 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 553 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 554 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
555 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 556};
557
558static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
559 .type = V4L2_DV_BT_656_1120,
9b51f175
GG		 560 /* keep this initialization for compatibility with GCC < 4.4.6 */
561 .reserved = { 0 },
562 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
563 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
a89bcd4c 564 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
9b51f175
GG		 565 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
566 V4L2_DV_BT_CAP_CUSTOM)
a89bcd4c
HV		 567};
568
569static inline const struct v4l2_dv_timings_cap *
570adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
571{
572 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
573 &adv7842_timings_cap_analog;
574}
575
576/* ----------------------------------------------------------------------- */
577
578static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
579{
580 struct delayed_work *dwork = to_delayed_work(work);
581 struct adv7842_state *state = container_of(dwork,
582 struct adv7842_state, delayed_work_enable_hotplug);
583 struct v4l2_subdev *sd = &state->sd;
584 int present = state->hdmi_edid.present;
585 u8 mask = 0;
586
587 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
588 __func__, present);
589
590 if (present & 0x1)
591 mask |= 0x20; /* port A */
592 if (present & 0x2)
593 mask |= 0x10; /* port B */
594 io_write_and_or(sd, 0x20, 0xcf, mask);
595}
596
597static int edid_write_vga_segment(struct v4l2_subdev *sd)
598{
599 struct i2c_client *client = v4l2_get_subdevdata(sd);
600 struct adv7842_state *state = to_state(sd);
601 const u8 *val = state->vga_edid.edid;
602 int err = 0;
603 int i;
604
605 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
606
607 /* HPA disable on port A and B */
608 io_write_and_or(sd, 0x20, 0xcf, 0x00);
609
610 /* Disable I2C access to internal EDID ram from VGA DDC port */
611 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
612
613 /* edid segment pointer '1' for VGA port */
614 rep_write_and_or(sd, 0x77, 0xef, 0x10);
615
616 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
617 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
618 I2C_SMBUS_BLOCK_MAX, val + i);
619 if (err)
620 return err;
621
622 /* Calculates the checksums and enables I2C access
623 * to internal EDID ram from VGA DDC port.
624 */
625 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
626
627 for (i = 0; i < 1000; i++) {
628 if (rep_read(sd, 0x79) & 0x20)
629 break;
630 mdelay(1);
631 }
632 if (i == 1000) {
633 v4l_err(client, "error enabling edid on VGA port\n");
634 return -EIO;
635 }
636
637 /* enable hotplug after 200 ms */
638 queue_delayed_work(state->work_queues,
639 &state->delayed_work_enable_hotplug, HZ / 5);
640
641 return 0;
642}
643
644static int edid_spa_location(const u8 *edid)
645{
646 u8 d;
647
648 /*
649 * TODO, improve and update for other CEA extensions
650 * currently only for 1 segment (256 bytes),
651 * i.e. 1 extension block and CEA revision 3.
652 */
653 if ((edid[0x7e] != 1) ||
654 (edid[0x80] != 0x02) ||
655 (edid[0x81] != 0x03)) {
656 return -EINVAL;
657 }
658 /*
659 * search Vendor Specific Data Block (tag 3)
660 */
661 d = edid[0x82] & 0x7f;
662 if (d > 4) {
663 int i = 0x84;
664 int end = 0x80 + d;
665 do {
666 u8 tag = edid[i]>>5;
667 u8 len = edid[i] & 0x1f;
668
669 if ((tag == 3) && (len >= 5))
670 return i + 4;
671 i += len + 1;
672 } while (i < end);
673 }
674 return -EINVAL;
675}
676
677static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
678{
679 struct i2c_client *client = v4l2_get_subdevdata(sd);
680 struct adv7842_state *state = to_state(sd);
681 const u8 *val = state->hdmi_edid.edid;
682 u8 cur_mask = rep_read(sd, 0x77) & 0x0c;
683 u8 mask = port == 0 ? 0x4 : 0x8;
684 int spa_loc = edid_spa_location(val);
685 int err = 0;
686 int i;
687
688 v4l2_dbg(2, debug, sd, "%s: write EDID on port %d (spa at 0x%x)\n",
689 __func__, port, spa_loc);
690
691 /* HPA disable on port A and B */
692 io_write_and_or(sd, 0x20, 0xcf, 0x00);
693
694 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
695 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
696
697 /* edid segment pointer '0' for HDMI ports */
698 rep_write_and_or(sd, 0x77, 0xef, 0x00);
699
700 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
701 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
702 I2C_SMBUS_BLOCK_MAX, val + i);
703 if (err)
704 return err;
705
706 if (spa_loc > 0) {
707 if (port == 0) {
708 /* port A SPA */
709 rep_write(sd, 0x72, val[spa_loc]);
710 rep_write(sd, 0x73, val[spa_loc + 1]);
711 } else {
712 /* port B SPA */
713 rep_write(sd, 0x74, val[spa_loc]);
714 rep_write(sd, 0x75, val[spa_loc + 1]);
715 }
716 rep_write(sd, 0x76, spa_loc);
717 } else {
718 /* default register values for SPA */
719 if (port == 0) {
720 /* port A SPA */
721 rep_write(sd, 0x72, 0);
722 rep_write(sd, 0x73, 0);
723 } else {
724 /* port B SPA */
725 rep_write(sd, 0x74, 0);
726 rep_write(sd, 0x75, 0);
727 }
728 rep_write(sd, 0x76, 0xc0);
729 }
730 rep_write_and_or(sd, 0x77, 0xbf, 0x00);
731
732 /* Calculates the checksums and enables I2C access to internal
733 * EDID ram from HDMI DDC ports
734 */
735 rep_write_and_or(sd, 0x77, 0xf3, mask | cur_mask);
736
737 for (i = 0; i < 1000; i++) {
738 if (rep_read(sd, 0x7d) & mask)
739 break;
740 mdelay(1);
741 }
742 if (i == 1000) {
743 v4l_err(client, "error enabling edid on port %d\n", port);
744 return -EIO;
745 }
746
747 /* enable hotplug after 200 ms */
748 queue_delayed_work(state->work_queues,
749 &state->delayed_work_enable_hotplug, HZ / 5);
750
751 return 0;
752}
753
754/* ----------------------------------------------------------------------- */
755
756#ifdef CONFIG_VIDEO_ADV_DEBUG
757static void adv7842_inv_register(struct v4l2_subdev *sd)
758{
759 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
760 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
761 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
762 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
763 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
764 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
765 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
766 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
767 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
768 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
769 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
770 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
771}
772
773static int adv7842_g_register(struct v4l2_subdev *sd,
774 struct v4l2_dbg_register *reg)
775{
776 reg->size = 1;
777 switch (reg->reg >> 8) {
778 case 0:
779 reg->val = io_read(sd, reg->reg & 0xff);
780 break;
781 case 1:
782 reg->val = avlink_read(sd, reg->reg & 0xff);
783 break;
784 case 2:
785 reg->val = cec_read(sd, reg->reg & 0xff);
786 break;
787 case 3:
788 reg->val = infoframe_read(sd, reg->reg & 0xff);
789 break;
790 case 4:
791 reg->val = sdp_io_read(sd, reg->reg & 0xff);
792 break;
793 case 5:
794 reg->val = sdp_read(sd, reg->reg & 0xff);
795 break;
796 case 6:
797 reg->val = afe_read(sd, reg->reg & 0xff);
798 break;
799 case 7:
800 reg->val = rep_read(sd, reg->reg & 0xff);
801 break;
802 case 8:
803 reg->val = edid_read(sd, reg->reg & 0xff);
804 break;
805 case 9:
806 reg->val = hdmi_read(sd, reg->reg & 0xff);
807 break;
808 case 0xa:
809 reg->val = cp_read(sd, reg->reg & 0xff);
810 break;
811 case 0xb:
812 reg->val = vdp_read(sd, reg->reg & 0xff);
813 break;
814 default:
815 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
816 adv7842_inv_register(sd);
817 break;
818 }
819 return 0;
820}
821
822static int adv7842_s_register(struct v4l2_subdev *sd,
823 const struct v4l2_dbg_register *reg)
824{
825 u8 val = reg->val & 0xff;
826
827 switch (reg->reg >> 8) {
828 case 0:
829 io_write(sd, reg->reg & 0xff, val);
830 break;
831 case 1:
832 avlink_write(sd, reg->reg & 0xff, val);
833 break;
834 case 2:
835 cec_write(sd, reg->reg & 0xff, val);
836 break;
837 case 3:
838 infoframe_write(sd, reg->reg & 0xff, val);
839 break;
840 case 4:
841 sdp_io_write(sd, reg->reg & 0xff, val);
842 break;
843 case 5:
844 sdp_write(sd, reg->reg & 0xff, val);
845 break;
846 case 6:
847 afe_write(sd, reg->reg & 0xff, val);
848 break;
849 case 7:
850 rep_write(sd, reg->reg & 0xff, val);
851 break;
852 case 8:
853 edid_write(sd, reg->reg & 0xff, val);
854 break;
855 case 9:
856 hdmi_write(sd, reg->reg & 0xff, val);
857 break;
858 case 0xa:
859 cp_write(sd, reg->reg & 0xff, val);
860 break;
861 case 0xb:
862 vdp_write(sd, reg->reg & 0xff, val);
863 break;
864 default:
865 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
866 adv7842_inv_register(sd);
867 break;
868 }
869 return 0;
870}
871#endif
872
873static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
874{
875 struct adv7842_state *state = to_state(sd);
876 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
877 u8 reg_io_6f = io_read(sd, 0x6f);
878 int val = 0;
879
880 if (reg_io_6f & 0x02)
881 val |= 1; /* port A */
882 if (reg_io_6f & 0x01)
883 val |= 2; /* port B */
884
885 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
886
887 if (val != prev)
888 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
889 return 0;
890}
891
892static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
893 u8 prim_mode,
894 const struct adv7842_video_standards *predef_vid_timings,
895 const struct v4l2_dv_timings *timings)
896{
897 int i;
898
899 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
900 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
901 is_digital_input(sd) ? 250000 : 1000000))
902 continue;
903 /* video std */
904 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
905 /* v_freq and prim mode */
906 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
907 return 0;
908 }
909
910 return -1;
911}
912
913static int configure_predefined_video_timings(struct v4l2_subdev *sd,
914 struct v4l2_dv_timings *timings)
915{
916 struct adv7842_state *state = to_state(sd);
917 int err;
918
919 v4l2_dbg(1, debug, sd, "%s\n", __func__);
920
921 /* reset to default values */
922 io_write(sd, 0x16, 0x43);
923 io_write(sd, 0x17, 0x5a);
924 /* disable embedded syncs for auto graphics mode */
925 cp_write_and_or(sd, 0x81, 0xef, 0x00);
926 cp_write(sd, 0x26, 0x00);
927 cp_write(sd, 0x27, 0x00);
928 cp_write(sd, 0x28, 0x00);
929 cp_write(sd, 0x29, 0x00);
930 cp_write(sd, 0x8f, 0x00);
931 cp_write(sd, 0x90, 0x00);
932 cp_write(sd, 0xa5, 0x00);
933 cp_write(sd, 0xa6, 0x00);
934 cp_write(sd, 0xa7, 0x00);
935 cp_write(sd, 0xab, 0x00);
936 cp_write(sd, 0xac, 0x00);
937
938 switch (state->mode) {
939 case ADV7842_MODE_COMP:
940 case ADV7842_MODE_RGB:
941 err = find_and_set_predefined_video_timings(sd,
942 0x01, adv7842_prim_mode_comp, timings);
943 if (err)
944 err = find_and_set_predefined_video_timings(sd,
945 0x02, adv7842_prim_mode_gr, timings);
946 break;
947 case ADV7842_MODE_HDMI:
948 err = find_and_set_predefined_video_timings(sd,
949 0x05, adv7842_prim_mode_hdmi_comp, timings);
950 if (err)
951 err = find_and_set_predefined_video_timings(sd,
952 0x06, adv7842_prim_mode_hdmi_gr, timings);
953 break;
954 default:
955 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
956 __func__, state->mode);
957 err = -1;
958 break;
959 }
960
961
962 return err;
963}
964
965static void configure_custom_video_timings(struct v4l2_subdev *sd,
966 const struct v4l2_bt_timings *bt)
967{
968 struct adv7842_state *state = to_state(sd);
969 struct i2c_client *client = v4l2_get_subdevdata(sd);
970 u32 width = htotal(bt);
971 u32 height = vtotal(bt);
972 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
973 u16 cp_start_eav = width - bt->hfrontporch;
974 u16 cp_start_vbi = height - bt->vfrontporch + 1;
975 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
976 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
977 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
978 const u8 pll[2] = {
979 0xc0 | ((width >> 8) & 0x1f),
980 width & 0xff
981 };
982
983 v4l2_dbg(2, debug, sd, "%s\n", __func__);
984
985 switch (state->mode) {
986 case ADV7842_MODE_COMP:
987 case ADV7842_MODE_RGB:
988 /* auto graphics */
989 io_write(sd, 0x00, 0x07); /* video std */
990 io_write(sd, 0x01, 0x02); /* prim mode */
991 /* enable embedded syncs for auto graphics mode */
992 cp_write_and_or(sd, 0x81, 0xef, 0x10);
993
994 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
995 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
996 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
997 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
998 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
999 break;
1000 }
1001
1002 /* active video - horizontal timing */
1003 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1004 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1005 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1006 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1007
1008 /* active video - vertical timing */
1009 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1010 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1011 ((cp_end_vbi >> 8) & 0xf));
1012 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1013 break;
1014 case ADV7842_MODE_HDMI:
1015 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1016 according to [REF_03, c. 4.2] */
a89bcd4c
HV		 1017 io_write(sd, 0x00, 0x02); /* video std */
1018 io_write(sd, 0x01, 0x06); /* prim mode */
1019 break;
1020 default:
1021 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1022 __func__, state->mode);
1023 break;
1024 }
1025
1026 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1027 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1028 cp_write(sd, 0xab, (height >> 4) & 0xff);
1029 cp_write(sd, 0xac, (height & 0x0f) << 4);
1030}
1031
1032static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1033{
1034 struct adv7842_state *state = to_state(sd);
1035
1036 switch (state->rgb_quantization_range) {
1037 case V4L2_DV_RGB_RANGE_AUTO:
1038 /* automatic */
1039 if (is_digital_input(sd) && !(hdmi_read(sd, 0x05) & 0x80)) {
1040 /* receiving DVI-D signal */
1041
1042 /* ADV7842 selects RGB limited range regardless of
1043 input format (CE/IT) in automatic mode */
1044 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1045 /* RGB limited range (16-235) */
1046 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1047
1048 } else {
1049 /* RGB full range (0-255) */
1050 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1051 }
1052 } else {
1053 /* receiving HDMI or analog signal, set automode */
1054 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1055 }
1056 break;
1057 case V4L2_DV_RGB_RANGE_LIMITED:
1058 /* RGB limited range (16-235) */
1059 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1060 break;
1061 case V4L2_DV_RGB_RANGE_FULL:
1062 /* RGB full range (0-255) */
1063 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1064 break;
1065 }
1066}
1067
1068static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1069{
1070 struct v4l2_subdev *sd = to_sd(ctrl);
1071 struct adv7842_state *state = to_state(sd);
1072
1073 /* TODO SDP ctrls
1074 contrast/brightness/hue/free run is acting a bit strange,
1075 not sure if sdp csc is correct.
1076 */
1077 switch (ctrl->id) {
1078 /* standard ctrls */
1079 case V4L2_CID_BRIGHTNESS:
1080 cp_write(sd, 0x3c, ctrl->val);
1081 sdp_write(sd, 0x14, ctrl->val);
1082 /* ignore lsb sdp 0x17[3:2] */
1083 return 0;
1084 case V4L2_CID_CONTRAST:
1085 cp_write(sd, 0x3a, ctrl->val);
1086 sdp_write(sd, 0x13, ctrl->val);
1087 /* ignore lsb sdp 0x17[1:0] */
1088 return 0;
1089 case V4L2_CID_SATURATION:
1090 cp_write(sd, 0x3b, ctrl->val);
1091 sdp_write(sd, 0x15, ctrl->val);
1092 /* ignore lsb sdp 0x17[5:4] */
1093 return 0;
1094 case V4L2_CID_HUE:
1095 cp_write(sd, 0x3d, ctrl->val);
1096 sdp_write(sd, 0x16, ctrl->val);
1097 /* ignore lsb sdp 0x17[7:6] */
1098 return 0;
1099 /* custom ctrls */
1100 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1101 afe_write(sd, 0xc8, ctrl->val);
1102 return 0;
1103 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1104 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1105 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1106 return 0;
1107 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1108 u8 R = (ctrl->val & 0xff0000) >> 16;
1109 u8 G = (ctrl->val & 0x00ff00) >> 8;
1110 u8 B = (ctrl->val & 0x0000ff);
1111 /* RGB -> YUV, numerical approximation */
1112 int Y = 66 * R + 129 * G + 25 * B;
1113 int U = -38 * R - 74 * G + 112 * B;
1114 int V = 112 * R - 94 * G - 18 * B;
1115
1116 /* Scale down to 8 bits with rounding */
1117 Y = (Y + 128) >> 8;
1118 U = (U + 128) >> 8;
1119 V = (V + 128) >> 8;
1120 /* make U,V positive */
1121 Y += 16;
1122 U += 128;
1123 V += 128;
1124
1125 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1126 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1127
1128 /* CP */
1129 cp_write(sd, 0xc1, R);
1130 cp_write(sd, 0xc0, G);
1131 cp_write(sd, 0xc2, B);
1132 /* SDP */
1133 sdp_write(sd, 0xde, Y);
1134 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1135 return 0;
1136 }
1137 case V4L2_CID_DV_RX_RGB_RANGE:
1138 state->rgb_quantization_range = ctrl->val;
1139 set_rgb_quantization_range(sd);
1140 return 0;
1141 }
1142 return -EINVAL;
1143}
1144
1145static inline bool no_power(struct v4l2_subdev *sd)
1146{
1147 return io_read(sd, 0x0c) & 0x24;
1148}
1149
1150static inline bool no_cp_signal(struct v4l2_subdev *sd)
1151{
1152 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1153}
1154
1155static inline bool is_hdmi(struct v4l2_subdev *sd)
1156{
1157 return hdmi_read(sd, 0x05) & 0x80;
1158}
1159
1160static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1161{
1162 struct adv7842_state *state = to_state(sd);
1163
1164 *status = 0;
1165
1166 if (io_read(sd, 0x0c) & 0x24)
1167 *status |= V4L2_IN_ST_NO_POWER;
1168
1169 if (state->mode == ADV7842_MODE_SDP) {
1170 /* status from SDP block */
1171 if (!(sdp_read(sd, 0x5A) & 0x01))
1172 *status |= V4L2_IN_ST_NO_SIGNAL;
1173
1174 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1175 __func__, *status);
1176 return 0;
1177 }
1178 /* status from CP block */
1179 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1180 !(cp_read(sd, 0xb1) & 0x80))
1181 /* TODO channel 2 */
1182 *status |= V4L2_IN_ST_NO_SIGNAL;
1183
1184 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1185 *status |= V4L2_IN_ST_NO_SIGNAL;
1186
1187 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1188 __func__, *status);
1189
1190 return 0;
1191}
1192
1193struct stdi_readback {
1194 u16 bl, lcf, lcvs;
1195 u8 hs_pol, vs_pol;
1196 bool interlaced;
1197};
1198
1199static int stdi2dv_timings(struct v4l2_subdev *sd,
1200 struct stdi_readback *stdi,
1201 struct v4l2_dv_timings *timings)
1202{
1203 struct adv7842_state *state = to_state(sd);
1204 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1205 u32 pix_clk;
1206 int i;
1207
1208 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1209 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1210
1211 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1212 adv7842_get_dv_timings_cap(sd),
1213 adv7842_check_dv_timings, NULL))
1214 continue;
1215 if (vtotal(bt) != stdi->lcf + 1)
1216 continue;
1217 if (bt->vsync != stdi->lcvs)
1218 continue;
1219
1220 pix_clk = hfreq * htotal(bt);
1221
1222 if ((pix_clk < bt->pixelclock + 1000000) &&
1223 (pix_clk > bt->pixelclock - 1000000)) {
1224 *timings = v4l2_dv_timings_presets[i];
1225 return 0;
1226 }
1227 }
1228
1229 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1230 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1231 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1232 timings))
1233 return 0;
1234 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1235 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1236 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1237 state->aspect_ratio, timings))
1238 return 0;
1239
1240 v4l2_dbg(2, debug, sd,
1241 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1242 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1243 stdi->hs_pol, stdi->vs_pol);
1244 return -1;
1245}
1246
1247static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1248{
1249 u32 status;
1250
1251 adv7842_g_input_status(sd, &status);
1252 if (status & V4L2_IN_ST_NO_SIGNAL) {
1253 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1254 return -ENOLINK;
1255 }
1256
1257 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1258 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1259 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1260
1261 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1262 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1263 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1264 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1265 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1266 } else {
1267 stdi->hs_pol = 'x';
1268 stdi->vs_pol = 'x';
1269 }
1270 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1271
1272 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1273 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1274 return -ENOLINK;
1275 }
1276
1277 v4l2_dbg(2, debug, sd,
1278 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1279 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1280 stdi->hs_pol, stdi->vs_pol,
1281 stdi->interlaced ? "interlaced" : "progressive");
1282
1283 return 0;
1284}
1285
1286static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1287 struct v4l2_enum_dv_timings *timings)
1288{
1289 return v4l2_enum_dv_timings_cap(timings,
1290 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1291}
1292
1293static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1294 struct v4l2_dv_timings_cap *cap)
1295{
1296 *cap = *adv7842_get_dv_timings_cap(sd);
1297 return 0;
1298}
1299
1300/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1301 if the format is listed in adv7604_timings[] */
1302static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1303 struct v4l2_dv_timings *timings)
1304{
1305 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1306 is_digital_input(sd) ? 250000 : 1000000,
1307 adv7842_check_dv_timings, NULL);
1308}
1309
1310static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1311 struct v4l2_dv_timings *timings)
1312{
1313 struct adv7842_state *state = to_state(sd);
1314 struct v4l2_bt_timings *bt = &timings->bt;
1315 struct stdi_readback stdi = { 0 };
1316
e78d834a
MB		 1317 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1318
a89bcd4c
HV		 1319 /* SDP block */
1320 if (state->mode == ADV7842_MODE_SDP)
1321 return -ENODATA;
1322
1323 /* read STDI */
1324 if (read_stdi(sd, &stdi)) {
1325 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1326 return -ENOLINK;
1327 }
1328 bt->interlaced = stdi.interlaced ?
1329 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
a89bcd4c
HV		 1330
1331 if (is_digital_input(sd)) {
e78d834a
MB		 1332 uint32_t freq;
1333
1334 timings->type = V4L2_DV_BT_656_1120;
1335 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1336 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1337 freq = (hdmi_read(sd, 0x06) * 1000000) +
1338 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
a89bcd4c
HV		 1339
1340 if (is_hdmi(sd)) {
1341 /* adjust for deep color mode */
e78d834a 1342 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 5) + 8);
a89bcd4c 1343 }
e78d834a
MB		 1344 bt->pixelclock = freq;
1345 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
a89bcd4c 1346 hdmi_read(sd, 0x21);
e78d834a 1347 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
a89bcd4c 1348 hdmi_read(sd, 0x23);
e78d834a 1349 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
a89bcd4c 1350 hdmi_read(sd, 0x25);
e78d834a
MB		 1351 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1352 hdmi_read(sd, 0x2b)) / 2;
1353 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1354 hdmi_read(sd, 0x2f)) / 2;
1355 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1356 hdmi_read(sd, 0x33)) / 2;
1357 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1358 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1359 if (bt->interlaced == V4L2_DV_INTERLACED) {
1360 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1361 hdmi_read(sd, 0x0c);
1362 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1363 hdmi_read(sd, 0x2d)) / 2;
1364 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1365 hdmi_read(sd, 0x31)) / 2;
1366 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1367 hdmi_read(sd, 0x35)) / 2;
1368 }
1369 adv7842_fill_optional_dv_timings_fields(sd, timings);
a89bcd4c
HV		 1370 } else {
1371 /* Interlaced? */
1372 if (stdi.interlaced) {
1373 v4l2_dbg(1, debug, sd, "%s: interlaced video not supported\n", __func__);
1374 return -ERANGE;
1375 }
1376
1377 if (stdi2dv_timings(sd, &stdi, timings)) {
1378 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1379 return -ERANGE;
1380 }
1381 }
1382
1383 if (debug > 1)
1384 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings: ",
1385 timings, true);
1386 return 0;
1387}
1388
1389static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1390 struct v4l2_dv_timings *timings)
1391{
1392 struct adv7842_state *state = to_state(sd);
1393 struct v4l2_bt_timings *bt;
1394 int err;
1395
e78d834a
MB		 1396 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1397
a89bcd4c
HV		 1398 if (state->mode == ADV7842_MODE_SDP)
1399 return -ENODATA;
1400
1401 bt = &timings->bt;
1402
1403 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1404 adv7842_check_dv_timings, NULL))
1405 return -ERANGE;
1406
1407 adv7842_fill_optional_dv_timings_fields(sd, timings);
1408
1409 state->timings = *timings;
1410
1411 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1412
1413 /* Use prim_mode and vid_std when available */
1414 err = configure_predefined_video_timings(sd, timings);
1415 if (err) {
1416 /* custom settings when the video format
1417 does not have prim_mode/vid_std */
1418 configure_custom_video_timings(sd, bt);
1419 }
1420
1421 set_rgb_quantization_range(sd);
1422
1423
1424 if (debug > 1)
1425 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1426 timings, true);
1427 return 0;
1428}
1429
1430static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1431 struct v4l2_dv_timings *timings)
1432{
1433 struct adv7842_state *state = to_state(sd);
1434
1435 if (state->mode == ADV7842_MODE_SDP)
1436 return -ENODATA;
1437 *timings = state->timings;
1438 return 0;
1439}
1440
1441static void enable_input(struct v4l2_subdev *sd)
1442{
1443 struct adv7842_state *state = to_state(sd);
1444 switch (state->mode) {
1445 case ADV7842_MODE_SDP:
1446 case ADV7842_MODE_COMP:
1447 case ADV7842_MODE_RGB:
1448 /* enable */
1449 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1450 break;
1451 case ADV7842_MODE_HDMI:
1452 /* enable */
1453 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1454 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1455 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1456 break;
1457 default:
1458 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1459 __func__, state->mode);
1460 break;
1461 }
1462}
1463
1464static void disable_input(struct v4l2_subdev *sd)
1465{
1466 /* disable */
1467 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1468 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1469 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1470}
1471
1472static void sdp_csc_coeff(struct v4l2_subdev *sd,
1473 const struct adv7842_sdp_csc_coeff *c)
1474{
1475 /* csc auto/manual */
1476 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1477
1478 if (!c->manual)
1479 return;
1480
1481 /* csc scaling */
1482 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1483
1484 /* A coeff */
1485 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1486 sdp_io_write(sd, 0xe1, c->A1);
1487 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1488 sdp_io_write(sd, 0xe3, c->A2);
1489 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1490 sdp_io_write(sd, 0xe5, c->A3);
1491
1492 /* A scale */
1493 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1494 sdp_io_write(sd, 0xe7, c->A4);
1495
1496 /* B coeff */
1497 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1498 sdp_io_write(sd, 0xe9, c->B1);
1499 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1500 sdp_io_write(sd, 0xeb, c->B2);
1501 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1502 sdp_io_write(sd, 0xed, c->B3);
1503
1504 /* B scale */
1505 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1506 sdp_io_write(sd, 0xef, c->B4);
1507
1508 /* C coeff */
1509 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1510 sdp_io_write(sd, 0xf1, c->C1);
1511 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1512 sdp_io_write(sd, 0xf3, c->C2);
1513 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1514 sdp_io_write(sd, 0xf5, c->C3);
1515
1516 /* C scale */
1517 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1518 sdp_io_write(sd, 0xf7, c->C4);
1519}
1520
1521static void select_input(struct v4l2_subdev *sd,
1522 enum adv7842_vid_std_select vid_std_select)
1523{
1524 struct adv7842_state *state = to_state(sd);
1525
1526 switch (state->mode) {
1527 case ADV7842_MODE_SDP:
1528 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1529 io_write(sd, 0x01, 0); /* prim mode */
1530 /* enable embedded syncs for auto graphics mode */
1531 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1532
1533 afe_write(sd, 0x00, 0x00); /* power up ADC */
1534 afe_write(sd, 0xc8, 0x00); /* phase control */
1535
1536 io_write(sd, 0x19, 0x83); /* LLC DLL phase */
1537 io_write(sd, 0x33, 0x40); /* LLC DLL enable */
1538
1539 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1540 /* script says register 0xde, which don't exist in manual */
1541
1542 /* Manual analog input muxing mode, CVBS (6.4)*/
1543 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1544 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1545 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1546 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1547 } else {
1548 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1549 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1550 }
1551 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1552 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1553
1554 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1555 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1556
1557 /* SDP recommended settings */
1558 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1559 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1560
1561 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1562 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1563 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1564 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1565 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1566 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1567 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1568
1569 /* deinterlacer enabled and 3D comb */
1570 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1571
1572 sdp_write(sd, 0xdd, 0x08); /* free run auto */
1573
1574 break;
1575
1576 case ADV7842_MODE_COMP:
1577 case ADV7842_MODE_RGB:
1578 /* Automatic analog input muxing mode */
1579 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1580 /* set mode and select free run resolution */
1581 io_write(sd, 0x00, vid_std_select); /* video std */
1582 io_write(sd, 0x01, 0x02); /* prim mode */
1583 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1584 for auto graphics mode */
1585
1586 afe_write(sd, 0x00, 0x00); /* power up ADC */
1587 afe_write(sd, 0xc8, 0x00); /* phase control */
1588
1589 /* set ADI recommended settings for digitizer */
1590 /* "ADV7842 Register Settings Recommendations
1591 * (rev. 1.8, November 2010)" p. 9. */
1592 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1593 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1594
1595 /* set to default gain for RGB */
1596 cp_write(sd, 0x73, 0x10);
1597 cp_write(sd, 0x74, 0x04);
1598 cp_write(sd, 0x75, 0x01);
1599 cp_write(sd, 0x76, 0x00);
1600
1601 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1602 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1603 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1604 break;
1605
1606 case ADV7842_MODE_HDMI:
1607 /* Automatic analog input muxing mode */
1608 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1609 /* set mode and select free run resolution */
1610 if (state->hdmi_port_a)
1611 hdmi_write(sd, 0x00, 0x02); /* select port A */
1612 else
1613 hdmi_write(sd, 0x00, 0x03); /* select port B */
1614 io_write(sd, 0x00, vid_std_select); /* video std */
1615 io_write(sd, 0x01, 5); /* prim mode */
1616 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1617 for auto graphics mode */
1618
1619 /* set ADI recommended settings for HDMI: */
1620 /* "ADV7842 Register Settings Recommendations
1621 * (rev. 1.8, November 2010)" p. 3. */
1622 hdmi_write(sd, 0xc0, 0x00);
1623 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1624 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1625 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1626 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1627 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1628 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1629 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1630 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1631 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1632 Improve robustness */
1633 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1634 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1635 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1636 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1637 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1638 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1639 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1640 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1641 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1642 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1643
1644 afe_write(sd, 0x00, 0xff); /* power down ADC */
1645 afe_write(sd, 0xc8, 0x40); /* phase control */
1646
1647 /* set to default gain for HDMI */
1648 cp_write(sd, 0x73, 0x10);
1649 cp_write(sd, 0x74, 0x04);
1650 cp_write(sd, 0x75, 0x01);
1651 cp_write(sd, 0x76, 0x00);
1652
1653 /* reset ADI recommended settings for digitizer */
1654 /* "ADV7842 Register Settings Recommendations
1655 * (rev. 2.5, June 2010)" p. 17. */
1656 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1657 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1658 cp_write(sd, 0x3e, 0x80); /* CP core pre-gain control,
1659 enable color control */
1660 /* CP coast control */
1661 cp_write(sd, 0xc3, 0x33); /* Component mode */
1662
1663 /* color space conversion, autodetect color space */
1664 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1665 break;
1666
1667 default:
1668 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1669 __func__, state->mode);
1670 break;
1671 }
1672}
1673
1674static int adv7842_s_routing(struct v4l2_subdev *sd,
1675 u32 input, u32 output, u32 config)
1676{
1677 struct adv7842_state *state = to_state(sd);
1678
1679 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1680
1681 switch (input) {
1682 case ADV7842_SELECT_HDMI_PORT_A:
1683 /* TODO select HDMI_COMP or HDMI_GR */
1684 state->mode = ADV7842_MODE_HDMI;
1685 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1686 state->hdmi_port_a = true;
1687 break;
1688 case ADV7842_SELECT_HDMI_PORT_B:
1689 /* TODO select HDMI_COMP or HDMI_GR */
1690 state->mode = ADV7842_MODE_HDMI;
1691 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1692 state->hdmi_port_a = false;
1693 break;
1694 case ADV7842_SELECT_VGA_COMP:
1695 v4l2_info(sd, "%s: VGA component: todo\n", __func__);
1696 case ADV7842_SELECT_VGA_RGB:
1697 state->mode = ADV7842_MODE_RGB;
1698 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1699 break;
1700 case ADV7842_SELECT_SDP_CVBS:
1701 state->mode = ADV7842_MODE_SDP;
1702 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1703 break;
1704 case ADV7842_SELECT_SDP_YC:
1705 state->mode = ADV7842_MODE_SDP;
1706 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1707 break;
1708 default:
1709 return -EINVAL;
1710 }
1711
1712 disable_input(sd);
1713 select_input(sd, state->vid_std_select);
1714 enable_input(sd);
1715
1716 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1717
1718 return 0;
1719}
1720
1721static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1722 enum v4l2_mbus_pixelcode *code)
1723{
1724 if (index)
1725 return -EINVAL;
1726 /* Good enough for now */
1727 *code = V4L2_MBUS_FMT_FIXED;
1728 return 0;
1729}
1730
1731static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1732 struct v4l2_mbus_framefmt *fmt)
1733{
1734 struct adv7842_state *state = to_state(sd);
1735
1736 fmt->width = state->timings.bt.width;
1737 fmt->height = state->timings.bt.height;
1738 fmt->code = V4L2_MBUS_FMT_FIXED;
1739 fmt->field = V4L2_FIELD_NONE;
1740
1741 if (state->mode == ADV7842_MODE_SDP) {
1742 /* SPD block */
1743 if (!(sdp_read(sd, 0x5A) & 0x01))
1744 return -EINVAL;
1745 fmt->width = 720;
1746 /* valid signal */
1747 if (state->norm & V4L2_STD_525_60)
1748 fmt->height = 480;
1749 else
1750 fmt->height = 576;
1751 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1752 return 0;
1753 }
1754
1755 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1756 fmt->colorspace = (state->timings.bt.height <= 576) ?
1757 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1758 }
1759 return 0;
1760}
1761
1762static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1763{
1764 if (enable) {
1765 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1766 io_write(sd, 0x46, 0x9c);
1767 /* ESDP_50HZ_DET interrupt */
1768 io_write(sd, 0x5a, 0x10);
1769 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1770 io_write(sd, 0x73, 0x03);
1771 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1772 io_write(sd, 0x78, 0x03);
1773 /* Enable SDP Standard Detection Change and SDP Video Detected */
1774 io_write(sd, 0xa0, 0x09);
1775 } else {
1776 io_write(sd, 0x46, 0x0);
1777 io_write(sd, 0x5a, 0x0);
1778 io_write(sd, 0x73, 0x0);
1779 io_write(sd, 0x78, 0x0);
1780 io_write(sd, 0xa0, 0x0);
1781 }
1782}
1783
1784static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1785{
1786 struct adv7842_state *state = to_state(sd);
1787 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1788 u8 irq_status[5];
1789 u8 irq_cfg = io_read(sd, 0x40);
1790
1791 /* disable irq-pin output */
1792 io_write(sd, 0x40, irq_cfg | 0x3);
1793
1794 /* read status */
1795 irq_status[0] = io_read(sd, 0x43);
1796 irq_status[1] = io_read(sd, 0x57);
1797 irq_status[2] = io_read(sd, 0x70);
1798 irq_status[3] = io_read(sd, 0x75);
1799 irq_status[4] = io_read(sd, 0x9d);
1800
1801 /* and clear */
1802 if (irq_status[0])
1803 io_write(sd, 0x44, irq_status[0]);
1804 if (irq_status[1])
1805 io_write(sd, 0x58, irq_status[1]);
1806 if (irq_status[2])
1807 io_write(sd, 0x71, irq_status[2]);
1808 if (irq_status[3])
1809 io_write(sd, 0x76, irq_status[3]);
1810 if (irq_status[4])
1811 io_write(sd, 0x9e, irq_status[4]);
1812
1813 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x\n", __func__,
1814 irq_status[0], irq_status[1], irq_status[2],
1815 irq_status[3], irq_status[4]);
1816
1817 /* format change CP */
1818 fmt_change_cp = irq_status[0] & 0x9c;
1819
1820 /* format change SDP */
1821 if (state->mode == ADV7842_MODE_SDP)
1822 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1823 else
1824 fmt_change_sdp = 0;
1825
1826 /* digital format CP */
1827 if (is_digital_input(sd))
1828 fmt_change_digital = irq_status[3] & 0x03;
1829 else
1830 fmt_change_digital = 0;
1831
1832 /* notify */
1833 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1834 v4l2_dbg(1, debug, sd,
1835 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1836 __func__, fmt_change_cp, fmt_change_digital,
1837 fmt_change_sdp);
1838 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1839 }
1840
1841 /* 5v cable detect */
1842 if (irq_status[2])
1843 adv7842_s_detect_tx_5v_ctrl(sd);
1844
1845 if (handled)
1846 *handled = true;
1847
1848 /* re-enable irq-pin output */
1849 io_write(sd, 0x40, irq_cfg);
1850
1851 return 0;
1852}
1853
1854static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *e)
1855{
1856 struct adv7842_state *state = to_state(sd);
1857 int err = 0;
1858
1859 if (e->pad > 2)
1860 return -EINVAL;
1861 if (e->start_block != 0)
1862 return -EINVAL;
1863 if (e->blocks > 2)
1864 return -E2BIG;
1865 if (!e->edid)
1866 return -EINVAL;
1867
1868 /* todo, per edid */
1869 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
1870 e->edid[0x16]);
1871
1872 if (e->pad == 2) {
1873 memset(&state->vga_edid.edid, 0, 256);
1874 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
1875 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
1876 err = edid_write_vga_segment(sd);
1877 } else {
1878 u32 mask = 0x1<<e->pad;
1879 memset(&state->hdmi_edid.edid, 0, 256);
1880 if (e->blocks)
1881 state->hdmi_edid.present |= mask;
1882 else
1883 state->hdmi_edid.present &= ~mask;
1884 memcpy(&state->hdmi_edid.edid, e->edid, 128*e->blocks);
1885 err = edid_write_hdmi_segment(sd, e->pad);
1886 }
1887 if (err < 0)
1888 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
1889 return err;
1890}
1891
1892/*********** avi info frame CEA-861-E **************/
1893/* TODO move to common library */
1894
1895struct avi_info_frame {
1896 uint8_t f17;
1897 uint8_t y10;
1898 uint8_t a0;
1899 uint8_t b10;
1900 uint8_t s10;
1901 uint8_t c10;
1902 uint8_t m10;
1903 uint8_t r3210;
1904 uint8_t itc;
1905 uint8_t ec210;
1906 uint8_t q10;
1907 uint8_t sc10;
1908 uint8_t f47;
1909 uint8_t vic;
1910 uint8_t yq10;
1911 uint8_t cn10;
1912 uint8_t pr3210;
1913 uint16_t etb;
1914 uint16_t sbb;
1915 uint16_t elb;
1916 uint16_t srb;
1917};
1918
1919static const char *y10_txt[4] = {
1920 "RGB",
1921 "YCbCr 4:2:2",
1922 "YCbCr 4:4:4",
1923 "Future",
1924};
1925
1926static const char *c10_txt[4] = {
1927 "No Data",
1928 "SMPTE 170M",
1929 "ITU-R 709",
1930 "Extended Colorimetry information valied",
1931};
1932
1933static const char *itc_txt[2] = {
1934 "No Data",
1935 "IT content",
1936};
1937
1938static const char *ec210_txt[8] = {
1939 "xvYCC601",
1940 "xvYCC709",
1941 "sYCC601",
1942 "AdobeYCC601",
1943 "AdobeRGB",
1944 "5 reserved",
1945 "6 reserved",
1946 "7 reserved",
1947};
1948
1949static const char *q10_txt[4] = {
1950 "Default",
1951 "Limited Range",
1952 "Full Range",
1953 "Reserved",
1954};
1955
1956static void parse_avi_infoframe(struct v4l2_subdev *sd, uint8_t *buf,
1957 struct avi_info_frame *avi)
1958{
1959 avi->f17 = (buf[1] >> 7) & 0x1;
1960 avi->y10 = (buf[1] >> 5) & 0x3;
1961 avi->a0 = (buf[1] >> 4) & 0x1;
1962 avi->b10 = (buf[1] >> 2) & 0x3;
1963 avi->s10 = buf[1] & 0x3;
1964 avi->c10 = (buf[2] >> 6) & 0x3;
1965 avi->m10 = (buf[2] >> 4) & 0x3;
1966 avi->r3210 = buf[2] & 0xf;
1967 avi->itc = (buf[3] >> 7) & 0x1;
1968 avi->ec210 = (buf[3] >> 4) & 0x7;
1969 avi->q10 = (buf[3] >> 2) & 0x3;
1970 avi->sc10 = buf[3] & 0x3;
1971 avi->f47 = (buf[4] >> 7) & 0x1;
1972 avi->vic = buf[4] & 0x7f;
1973 avi->yq10 = (buf[5] >> 6) & 0x3;
1974 avi->cn10 = (buf[5] >> 4) & 0x3;
1975 avi->pr3210 = buf[5] & 0xf;
1976 avi->etb = buf[6] + 256*buf[7];
1977 avi->sbb = buf[8] + 256*buf[9];
1978 avi->elb = buf[10] + 256*buf[11];
1979 avi->srb = buf[12] + 256*buf[13];
1980}
1981
1982static void print_avi_infoframe(struct v4l2_subdev *sd)
1983{
1984 int i;
1985 uint8_t buf[14];
1986 uint8_t avi_inf_len;
1987 struct avi_info_frame avi;
1988
1989 if (!(hdmi_read(sd, 0x05) & 0x80)) {
1990 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1991 return;
1992 }
1993 if (!(io_read(sd, 0x60) & 0x01)) {
1994 v4l2_info(sd, "AVI infoframe not received\n");
1995 return;
1996 }
1997
1998 if (io_read(sd, 0x88) & 0x10) {
1999 /* Note: the ADV7842 calculated incorrect checksums for InfoFrames
2000 with a length of 14 or 15. See the ADV7842 Register Settings
2001 Recommendations document for more details. */
2002 v4l2_info(sd, "AVI infoframe checksum error\n");
2003 return;
2004 }
2005
2006 avi_inf_len = infoframe_read(sd, 0xe2);
2007 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2008 infoframe_read(sd, 0xe1), avi_inf_len);
2009
2010 if (infoframe_read(sd, 0xe1) != 0x02)
2011 return;
2012
2013 for (i = 0; i < 14; i++)
2014 buf[i] = infoframe_read(sd, i);
2015
2016 v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2017 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2018 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2019
2020 parse_avi_infoframe(sd, buf, &avi);
2021
2022 if (avi.vic)
2023 v4l2_info(sd, "\tVIC: %d\n", avi.vic);
2024 if (avi.itc)
2025 v4l2_info(sd, "\t%s\n", itc_txt[avi.itc]);
2026
2027 if (avi.y10)
2028 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], !avi.c10 ? "" :
2029 (avi.c10 == 0x3 ? ec210_txt[avi.ec210] : c10_txt[avi.c10]));
2030 else
2031 v4l2_info(sd, "\t%s %s\n", y10_txt[avi.y10], q10_txt[avi.q10]);
2032}
2033
2034static const char * const prim_mode_txt[] = {
2035 "SDP",
2036 "Component",
2037 "Graphics",
2038 "Reserved",
2039 "CVBS & HDMI AUDIO",
2040 "HDMI-Comp",
2041 "HDMI-GR",
2042 "Reserved",
2043 "Reserved",
2044 "Reserved",
2045 "Reserved",
2046 "Reserved",
2047 "Reserved",
2048 "Reserved",
2049 "Reserved",
2050 "Reserved",
2051};
2052
2053static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2054{
2055 /* SDP (Standard definition processor) block */
2056 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2057
2058 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2059 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2060 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2061
2062 v4l2_info(sd, "SDP: free run: %s\n",
2063 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2064 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2065 "valid SD/PR signal detected" : "invalid/no signal");
2066 if (sdp_signal_detected) {
2067 static const char * const sdp_std_txt[] = {
2068 "NTSC-M/J",
2069 "1?",
2070 "NTSC-443",
2071 "60HzSECAM",
2072 "PAL-M",
2073 "5?",
2074 "PAL-60",
2075 "7?", "8?", "9?", "a?", "b?",
2076 "PAL-CombN",
2077 "d?",
2078 "PAL-BGHID",
2079 "SECAM"
2080 };
2081 v4l2_info(sd, "SDP: standard %s\n",
2082 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2083 v4l2_info(sd, "SDP: %s\n",
2084 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2085 v4l2_info(sd, "SDP: %s\n",
2086 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2087 v4l2_info(sd, "SDP: deinterlacer %s\n",
2088 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2089 v4l2_info(sd, "SDP: csc %s mode\n",
2090 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2091 }
2092 return 0;
2093}
2094
2095static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2096{
2097 /* CP block */
2098 struct adv7842_state *state = to_state(sd);
2099 struct v4l2_dv_timings timings;
2100 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2101 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2102 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2103 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2104 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2105 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2106 bool audio_mute = io_read(sd, 0x65) & 0x40;
2107
2108 static const char * const csc_coeff_sel_rb[16] = {
2109 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2110 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2111 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2112 "reserved", "reserved", "reserved", "reserved", "manual"
2113 };
2114 static const char * const input_color_space_txt[16] = {
2115 "RGB limited range (16-235)", "RGB full range (0-255)",
2116 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2117 "XvYCC Bt.601", "XvYCC Bt.709",
2118 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2119 "invalid", "invalid", "invalid", "invalid", "invalid",
2120 "invalid", "invalid", "automatic"
2121 };
2122 static const char * const rgb_quantization_range_txt[] = {
2123 "Automatic",
2124 "RGB limited range (16-235)",
2125 "RGB full range (0-255)",
2126 };
2127 static const char * const deep_color_mode_txt[4] = {
2128 "8-bits per channel",
2129 "10-bits per channel",
2130 "12-bits per channel",
2131 "16-bits per channel (not supported)"
2132 };
2133
2134 v4l2_info(sd, "-----Chip status-----\n");
2135 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2136 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
2137 "HDMI" : (is_digital_input(sd) ? "DVI-D" : "DVI-A"));
2138 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2139 state->hdmi_port_a ? "A" : "B");
2140 v4l2_info(sd, "EDID A %s, B %s\n",
2141 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2142 "enabled" : "disabled",
2143 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2144 "enabled" : "disabled");
2145 v4l2_info(sd, "HPD A %s, B %s\n",
2146 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2147 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2148 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2149 "enabled" : "disabled");
2150
2151 v4l2_info(sd, "-----Signal status-----\n");
2152 if (state->hdmi_port_a) {
2153 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2154 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2155 v4l2_info(sd, "TMDS signal detected: %s\n",
2156 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2157 v4l2_info(sd, "TMDS signal locked: %s\n",
2158 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2159 } else {
2160 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2161 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2162 v4l2_info(sd, "TMDS signal detected: %s\n",
2163 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2164 v4l2_info(sd, "TMDS signal locked: %s\n",
2165 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2166 }
2167 v4l2_info(sd, "CP free run: %s\n",
2168 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2169 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2170 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2171 (io_read(sd, 0x01) & 0x70) >> 4);
2172
2173 v4l2_info(sd, "-----Video Timings-----\n");
2174 if (no_cp_signal(sd)) {
2175 v4l2_info(sd, "STDI: not locked\n");
2176 } else {
2177 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2178 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2179 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2180 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2181 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2182 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2183 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2184 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2185 v4l2_info(sd,
2186 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2187 lcf, bl, lcvs, fcl,
2188 (cp_read(sd, 0xb1) & 0x40) ?
2189 "interlaced" : "progressive",
2190 hs_pol, vs_pol);
2191 }
2192 if (adv7842_query_dv_timings(sd, &timings))
2193 v4l2_info(sd, "No video detected\n");
2194 else
2195 v4l2_print_dv_timings(sd->name, "Detected format: ",
2196 &timings, true);
2197 v4l2_print_dv_timings(sd->name, "Configured format: ",
2198 &state->timings, true);
2199
2200 if (no_cp_signal(sd))
2201 return 0;
2202
2203 v4l2_info(sd, "-----Color space-----\n");
2204 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2205 rgb_quantization_range_txt[state->rgb_quantization_range]);
2206 v4l2_info(sd, "Input color space: %s\n",
2207 input_color_space_txt[reg_io_0x02 >> 4]);
2208 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2209 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2210 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2211 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2212 "enabled" : "disabled");
2213 v4l2_info(sd, "Color space conversion: %s\n",
2214 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2215
2216 if (!is_digital_input(sd))
2217 return 0;
2218
2219 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2220 v4l2_info(sd, "HDCP encrypted content: %s\n",
2221 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2222 v4l2_info(sd, "HDCP keys read: %s%s\n",
2223 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2224 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2225 if (!is_hdmi(sd))
2226 return 0;
2227
2228 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2229 audio_pll_locked ? "locked" : "not locked",
2230 audio_sample_packet_detect ? "detected" : "not detected",
2231 audio_mute ? "muted" : "enabled");
2232 if (audio_pll_locked && audio_sample_packet_detect) {
2233 v4l2_info(sd, "Audio format: %s\n",
2234 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2235 }
2236 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2237 (hdmi_read(sd, 0x5c) << 8) +
2238 (hdmi_read(sd, 0x5d) & 0xf0));
2239 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2240 (hdmi_read(sd, 0x5e) << 8) +
2241 hdmi_read(sd, 0x5f));
2242 v4l2_info(sd, "AV Mute: %s\n",
2243 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2244 v4l2_info(sd, "Deep color mode: %s\n",
2245 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2246
2247 print_avi_infoframe(sd);
2248 return 0;
2249}
2250
2251static int adv7842_log_status(struct v4l2_subdev *sd)
2252{
2253 struct adv7842_state *state = to_state(sd);
2254
2255 if (state->mode == ADV7842_MODE_SDP)
2256 return adv7842_sdp_log_status(sd);
2257 return adv7842_cp_log_status(sd);
2258}
2259
2260static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2261{
2262 struct adv7842_state *state = to_state(sd);
2263
2264 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2265
2266 if (state->mode != ADV7842_MODE_SDP)
2267 return -ENODATA;
2268
2269 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2270 *std = 0;
2271 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2272 return 0;
2273 }
2274
2275 switch (sdp_read(sd, 0x52) & 0x0f) {
2276 case 0:
2277 /* NTSC-M/J */
2278 *std &= V4L2_STD_NTSC;
2279 break;
2280 case 2:
2281 /* NTSC-443 */
2282 *std &= V4L2_STD_NTSC_443;
2283 break;
2284 case 3:
2285 /* 60HzSECAM */
2286 *std &= V4L2_STD_SECAM;
2287 break;
2288 case 4:
2289 /* PAL-M */
2290 *std &= V4L2_STD_PAL_M;
2291 break;
2292 case 6:
2293 /* PAL-60 */
2294 *std &= V4L2_STD_PAL_60;
2295 break;
2296 case 0xc:
2297 /* PAL-CombN */
2298 *std &= V4L2_STD_PAL_Nc;
2299 break;
2300 case 0xe:
2301 /* PAL-BGHID */
2302 *std &= V4L2_STD_PAL;
2303 break;
2304 case 0xf:
2305 /* SECAM */
2306 *std &= V4L2_STD_SECAM;
2307 break;
2308 default:
2309 *std &= V4L2_STD_ALL;
2310 break;
2311 }
2312 return 0;
2313}
2314
2315static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2316{
2317 struct adv7842_state *state = to_state(sd);
2318
2319 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2320
2321 if (state->mode != ADV7842_MODE_SDP)
2322 return -ENODATA;
2323
2324 if (norm & V4L2_STD_ALL) {
2325 state->norm = norm;
2326 return 0;
2327 }
2328 return -EINVAL;
2329}
2330
2331static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2332{
2333 struct adv7842_state *state = to_state(sd);
2334
2335 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2336
2337 if (state->mode != ADV7842_MODE_SDP)
2338 return -ENODATA;
2339
2340 *norm = state->norm;
2341 return 0;
2342}
2343
2344/* ----------------------------------------------------------------------- */
2345
2346static int adv7842_core_init(struct v4l2_subdev *sd,
2347 const struct adv7842_platform_data *pdata)
2348{
2349 hdmi_write(sd, 0x48,
2350 (pdata->disable_pwrdnb ? 0x80 : 0) |
2351 (pdata->disable_cable_det_rst ? 0x40 : 0));
2352
2353 disable_input(sd);
2354
2355 /* power */
2356 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2357 io_write(sd, 0x15, 0x80); /* Power up pads */
2358
2359 /* video format */
2360 io_write(sd, 0x02,
2361 pdata->inp_color_space << 4 |
2362 pdata->alt_gamma << 3 |
2363 pdata->op_656_range << 2 |
2364 pdata->rgb_out << 1 |
2365 pdata->alt_data_sat << 0);
2366 io_write(sd, 0x03, pdata->op_format_sel);
2367 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2368 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2369 pdata->insert_av_codes << 2 |
2370 pdata->replicate_av_codes << 1 |
2371 pdata->invert_cbcr << 0);
2372
2373 /* Drive strength */
2374 io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
2375 pdata->drive_strength.clock<<2 |
2376 pdata->drive_strength.sync);
2377
2378 /* HDMI free run */
2379 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2380
2381 /* TODO from platform data */
2382 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2383 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2384 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2385 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2386
2387 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2388 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2389
2390 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2391
2392 if (pdata->sdp_io_sync.adjust) {
2393 const struct adv7842_sdp_io_sync_adjustment *s = &pdata->sdp_io_sync;
2394 sdp_io_write(sd, 0x94, (s->hs_beg>>8) & 0xf);
2395 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2396 sdp_io_write(sd, 0x96, (s->hs_width>>8) & 0xf);
2397 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2398 sdp_io_write(sd, 0x98, (s->de_beg>>8) & 0xf);
2399 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2400 sdp_io_write(sd, 0x9a, (s->de_end>>8) & 0xf);
2401 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2402 }
2403
2404 /* todo, improve settings for sdram */
2405 if (pdata->sd_ram_size >= 128) {
2406 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2407 if (pdata->sd_ram_ddr) {
2408 /* SDP setup for the AD eval board */
2409 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2410 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2411 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2412 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2413 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2414 } else {
2415 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2416 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2417 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2418 depends on memory */
2419 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2420 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2421 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2422 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2423 }
2424 } else {
2425 /*
2426 * Manual UG-214, rev 0 is bit confusing on this bit
2427 * but a '1' disables any signal if the Ram is active.
2428 */
2429 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2430 }
2431
2432 select_input(sd, pdata->vid_std_select);
2433
2434 enable_input(sd);
2435
2436 /* disable I2C access to internal EDID ram from HDMI DDC ports */
2437 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
2438
2439 hdmi_write(sd, 0x69, 0xa3); /* HPA manual */
2440 /* HPA disable on port A and B */
2441 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2442
2443 /* LLC */
2444 /* Set phase to 16. TODO: get this from platform_data */
2445 io_write(sd, 0x19, 0x90);
2446 io_write(sd, 0x33, 0x40);
2447
2448 /* interrupts */
2449 io_write(sd, 0x40, 0xe2); /* Configure INT1 */
2450
2451 adv7842_irq_enable(sd, true);
2452
2453 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2454}
2455
2456/* ----------------------------------------------------------------------- */
2457
2458static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2459{
2460 /*
2461 * From ADV784x external Memory test.pdf
2462 *
2463 * Reset must just been performed before running test.
2464 * Recommended to reset after test.
2465 */
2466 int i;
2467 int pass = 0;
2468 int fail = 0;
2469 int complete = 0;
2470
2471 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2472 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2473 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2474 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2475 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2476 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2477 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2478 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2479 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2480 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2481 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2482 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2483
2484 mdelay(5);
2485
2486 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2487 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2488 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2489 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2490 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2491 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2492 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2493 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2494 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2495 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2496 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2497
2498 mdelay(5);
2499
2500 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2501 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2502
2503 mdelay(20);
2504
2505 for (i = 0; i < 10; i++) {
2506 u8 result = sdp_io_read(sd, 0xdb);
2507 if (result & 0x10) {
2508 complete++;
2509 if (result & 0x20)
2510 fail++;
2511 else
2512 pass++;
2513 }
2514 mdelay(20);
2515 }
2516
2517 v4l2_dbg(1, debug, sd,
2518 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2519 complete, i, pass, fail);
2520
2521 if (!complete || fail)
2522 return -EIO;
2523 return 0;
2524}
2525
2526static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2527 struct adv7842_platform_data *pdata)
2528{
2529 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2530 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2531 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2532 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2533 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2534
2535 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2536 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2537 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2538 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2539
2540 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2541 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2542}
2543
2544static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2545{
2546 struct i2c_client *client = v4l2_get_subdevdata(sd);
2547 struct adv7842_state *state = to_state(sd);
2548 struct adv7842_platform_data *pdata = client->dev.platform_data;
2549 int ret = 0;
2550
2551 if (!pdata)
2552 return -ENODEV;
2553
2554 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2555 v4l2_info(sd, "no sdram or no ddr sdram\n");
2556 return -EINVAL;
2557 }
2558
2559 main_reset(sd);
2560
2561 adv7842_rewrite_i2c_addresses(sd, pdata);
2562
2563 /* run ram test */
2564 ret = adv7842_ddr_ram_test(sd);
2565
2566 main_reset(sd);
2567
2568 adv7842_rewrite_i2c_addresses(sd, pdata);
2569
2570 /* and re-init chip and state */
2571 adv7842_core_init(sd, pdata);
2572
2573 disable_input(sd);
2574
2575 select_input(sd, state->vid_std_select);
2576
2577 enable_input(sd);
2578
2579 adv7842_s_dv_timings(sd, &state->timings);
2580
2581 edid_write_vga_segment(sd);
2582 edid_write_hdmi_segment(sd, 0);
2583 edid_write_hdmi_segment(sd, 1);
2584
2585 return ret;
2586}
2587
2588static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2589{
2590 switch (cmd) {
2591 case ADV7842_CMD_RAM_TEST:
2592 return adv7842_command_ram_test(sd);
2593 }
2594 return -ENOTTY;
2595}
2596
2597/* ----------------------------------------------------------------------- */
2598
2599static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2600 .s_ctrl = adv7842_s_ctrl,
2601};
2602
2603static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2604 .log_status = adv7842_log_status,
2605 .g_std = adv7842_g_std,
2606 .s_std = adv7842_s_std,
2607 .ioctl = adv7842_ioctl,
2608 .interrupt_service_routine = adv7842_isr,
2609#ifdef CONFIG_VIDEO_ADV_DEBUG
2610 .g_register = adv7842_g_register,
2611 .s_register = adv7842_s_register,
2612#endif
2613};
2614
2615static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2616 .s_routing = adv7842_s_routing,
2617 .querystd = adv7842_querystd,
2618 .g_input_status = adv7842_g_input_status,
2619 .s_dv_timings = adv7842_s_dv_timings,
2620 .g_dv_timings = adv7842_g_dv_timings,
2621 .query_dv_timings = adv7842_query_dv_timings,
2622 .enum_dv_timings = adv7842_enum_dv_timings,
2623 .dv_timings_cap = adv7842_dv_timings_cap,
2624 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2625 .g_mbus_fmt = adv7842_g_mbus_fmt,
2626 .try_mbus_fmt = adv7842_g_mbus_fmt,
2627 .s_mbus_fmt = adv7842_g_mbus_fmt,
2628};
2629
2630static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2631 .set_edid = adv7842_set_edid,
2632};
2633
2634static const struct v4l2_subdev_ops adv7842_ops = {
2635 .core = &adv7842_core_ops,
2636 .video = &adv7842_video_ops,
2637 .pad = &adv7842_pad_ops,
2638};
2639
2640/* -------------------------- custom ctrls ---------------------------------- */
2641
2642static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2643 .ops = &adv7842_ctrl_ops,
2644 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2645 .name = "Analog Sampling Phase",
2646 .type = V4L2_CTRL_TYPE_INTEGER,
2647 .min = 0,
2648 .max = 0x1f,
2649 .step = 1,
2650 .def = 0,
2651};
2652
2653static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2654 .ops = &adv7842_ctrl_ops,
2655 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2656 .name = "Free Running Color, Manual",
2657 .type = V4L2_CTRL_TYPE_BOOLEAN,
2658 .max = 1,
2659 .step = 1,
2660 .def = 1,
2661};
2662
2663static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2664 .ops = &adv7842_ctrl_ops,
2665 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2666 .name = "Free Running Color",
2667 .type = V4L2_CTRL_TYPE_INTEGER,
2668 .max = 0xffffff,
2669 .step = 0x1,
2670};
2671
2672
2673static void adv7842_unregister_clients(struct adv7842_state *state)
2674{
2675 if (state->i2c_avlink)
2676 i2c_unregister_device(state->i2c_avlink);
2677 if (state->i2c_cec)
2678 i2c_unregister_device(state->i2c_cec);
2679 if (state->i2c_infoframe)
2680 i2c_unregister_device(state->i2c_infoframe);
2681 if (state->i2c_sdp_io)
2682 i2c_unregister_device(state->i2c_sdp_io);
2683 if (state->i2c_sdp)
2684 i2c_unregister_device(state->i2c_sdp);
2685 if (state->i2c_afe)
2686 i2c_unregister_device(state->i2c_afe);
2687 if (state->i2c_repeater)
2688 i2c_unregister_device(state->i2c_repeater);
2689 if (state->i2c_edid)
2690 i2c_unregister_device(state->i2c_edid);
2691 if (state->i2c_hdmi)
2692 i2c_unregister_device(state->i2c_hdmi);
2693 if (state->i2c_cp)
2694 i2c_unregister_device(state->i2c_cp);
2695 if (state->i2c_vdp)
2696 i2c_unregister_device(state->i2c_vdp);
2697}
2698
2699static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd,
2700 u8 addr, u8 io_reg)
2701{
2702 struct i2c_client *client = v4l2_get_subdevdata(sd);
2703
2704 io_write(sd, io_reg, addr << 1);
2705 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2706}
2707
2708static int adv7842_probe(struct i2c_client *client,
2709 const struct i2c_device_id *id)
2710{
2711 struct adv7842_state *state;
2712 struct adv7842_platform_data *pdata = client->dev.platform_data;
2713 struct v4l2_ctrl_handler *hdl;
2714 struct v4l2_subdev *sd;
2715 u16 rev;
2716 int err;
2717
2718 /* Check if the adapter supports the needed features */
2719 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2720 return -EIO;
2721
2722 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2723 client->addr << 1);
2724
2725 if (!pdata) {
2726 v4l_err(client, "No platform data!\n");
2727 return -ENODEV;
2728 }
2729
2730 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2731 if (!state) {
2732 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2733 return -ENOMEM;
2734 }
2735
2736 sd = &state->sd;
2737 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2738 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2739 state->connector_hdmi = pdata->connector_hdmi;
2740 state->mode = pdata->mode;
2741
2742 state->hdmi_port_a = true;
2743
2744 /* i2c access to adv7842? */
2745 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2746 adv_smbus_read_byte_data_check(client, 0xeb, false);
2747 if (rev != 0x2012) {
2748 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
2749 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2750 adv_smbus_read_byte_data_check(client, 0xeb, false);
2751 }
2752 if (rev != 0x2012) {
2753 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
2754 client->addr << 1, rev);
2755 return -ENODEV;
2756 }
2757
2758 if (pdata->chip_reset)
2759 main_reset(sd);
2760
2761 /* control handlers */
2762 hdl = &state->hdl;
2763 v4l2_ctrl_handler_init(hdl, 6);
2764
2765 /* add in ascending ID order */
2766 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2767 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2768 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2769 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2770 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2771 V4L2_CID_SATURATION, 0, 255, 1, 128);
2772 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
2773 V4L2_CID_HUE, 0, 128, 1, 0);
2774
2775 /* custom controls */
2776 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2777 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
2778 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
2779 &adv7842_ctrl_analog_sampling_phase, NULL);
2780 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
2781 &adv7842_ctrl_free_run_color_manual, NULL);
2782 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
2783 &adv7842_ctrl_free_run_color, NULL);
2784 state->rgb_quantization_range_ctrl =
2785 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
2786 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2787 0, V4L2_DV_RGB_RANGE_AUTO);
2788 sd->ctrl_handler = hdl;
2789 if (hdl->error) {
2790 err = hdl->error;
2791 goto err_hdl;
2792 }
2793 state->detect_tx_5v_ctrl->is_private = true;
2794 state->rgb_quantization_range_ctrl->is_private = true;
2795 state->analog_sampling_phase_ctrl->is_private = true;
2796 state->free_run_color_ctrl_manual->is_private = true;
2797 state->free_run_color_ctrl->is_private = true;
2798
2799 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
2800 err = -ENODEV;
2801 goto err_hdl;
2802 }
2803
2804 state->i2c_avlink = adv7842_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2805 state->i2c_cec = adv7842_dummy_client(sd, pdata->i2c_cec, 0xf4);
2806 state->i2c_infoframe = adv7842_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2807 state->i2c_sdp_io = adv7842_dummy_client(sd, pdata->i2c_sdp_io, 0xf2);
2808 state->i2c_sdp = adv7842_dummy_client(sd, pdata->i2c_sdp, 0xf1);
2809 state->i2c_afe = adv7842_dummy_client(sd, pdata->i2c_afe, 0xf8);
2810 state->i2c_repeater = adv7842_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2811 state->i2c_edid = adv7842_dummy_client(sd, pdata->i2c_edid, 0xfa);
2812 state->i2c_hdmi = adv7842_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2813 state->i2c_cp = adv7842_dummy_client(sd, pdata->i2c_cp, 0xfd);
2814 state->i2c_vdp = adv7842_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2815 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2816 !state->i2c_sdp_io || !state->i2c_sdp || !state->i2c_afe ||
2817 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2818 !state->i2c_cp || !state->i2c_vdp) {
2819 err = -ENOMEM;
2820 v4l2_err(sd, "failed to create all i2c clients\n");
2821 goto err_i2c;
2822 }
2823
2824 /* work queues */
2825 state->work_queues = create_singlethread_workqueue(client->name);
2826 if (!state->work_queues) {
2827 v4l2_err(sd, "Could not create work queue\n");
2828 err = -ENOMEM;
2829 goto err_i2c;
2830 }
2831
2832 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2833 adv7842_delayed_work_enable_hotplug);
2834
2835 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2836 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2837 if (err)
2838 goto err_work_queues;
2839
2840 err = adv7842_core_init(sd, pdata);
2841 if (err)
2842 goto err_entity;
2843
2844 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2845 client->addr << 1, client->adapter->name);
2846 return 0;
2847
2848err_entity:
2849 media_entity_cleanup(&sd->entity);
2850err_work_queues:
2851 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2852 destroy_workqueue(state->work_queues);
2853err_i2c:
2854 adv7842_unregister_clients(state);
2855err_hdl:
2856 v4l2_ctrl_handler_free(hdl);
2857 return err;
2858}
2859
2860/* ----------------------------------------------------------------------- */
2861
2862static int adv7842_remove(struct i2c_client *client)
2863{
2864 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2865 struct adv7842_state *state = to_state(sd);
2866
2867 adv7842_irq_enable(sd, false);
2868
2869 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2870 destroy_workqueue(state->work_queues);
2871 v4l2_device_unregister_subdev(sd);
2872 media_entity_cleanup(&sd->entity);
2873 adv7842_unregister_clients(to_state(sd));
2874 v4l2_ctrl_handler_free(sd->ctrl_handler);
2875 return 0;
2876}
2877
2878/* ----------------------------------------------------------------------- */
2879
2880static struct i2c_device_id adv7842_id[] = {
2881 { "adv7842", 0 },
2882 { }
2883};
2884MODULE_DEVICE_TABLE(i2c, adv7842_id);
2885
2886/* ----------------------------------------------------------------------- */
2887
2888static struct i2c_driver adv7842_driver = {
2889 .driver = {
2890 .owner = THIS_MODULE,
2891 .name = "adv7842",
2892 },
2893 .probe = adv7842_probe,
2894 .remove = adv7842_remove,
2895 .id_table = adv7842_id,
2896};
2897
2898module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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