Commit | Line | Data |
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111f3356 JC |
1 | /* |
2 | * A V4L2 driver for OmniVision OV7670 cameras. | |
3 | * | |
4 | * Copyright 2006 One Laptop Per Child Association, Inc. Written | |
5 | * by Jonathan Corbet with substantial inspiration from Mark | |
6 | * McClelland's ovcamchip code. | |
7 | * | |
77d5140f JC |
8 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
9 | * | |
111f3356 JC |
10 | * This file may be distributed under the terms of the GNU General |
11 | * Public License, version 2. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
14386c2b | 16 | #include <linux/i2c.h> |
111f3356 | 17 | #include <linux/delay.h> |
7e0a16f6 | 18 | #include <linux/videodev2.h> |
14386c2b | 19 | #include <media/v4l2-device.h> |
3434eb7e | 20 | #include <media/v4l2-chip-ident.h> |
ca07561a | 21 | #include <media/v4l2-i2c-drv.h> |
111f3356 JC |
22 | |
23 | ||
5e614475 | 24 | MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); |
111f3356 JC |
25 | MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); |
26 | MODULE_LICENSE("GPL"); | |
27 | ||
14386c2b HV |
28 | static int debug; |
29 | module_param(debug, bool, 0644); | |
30 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
31 | ||
111f3356 JC |
32 | /* |
33 | * Basic window sizes. These probably belong somewhere more globally | |
34 | * useful. | |
35 | */ | |
36 | #define VGA_WIDTH 640 | |
37 | #define VGA_HEIGHT 480 | |
38 | #define QVGA_WIDTH 320 | |
39 | #define QVGA_HEIGHT 240 | |
40 | #define CIF_WIDTH 352 | |
41 | #define CIF_HEIGHT 288 | |
42 | #define QCIF_WIDTH 176 | |
43 | #define QCIF_HEIGHT 144 | |
44 | ||
c8f5b2f5 JC |
45 | /* |
46 | * Our nominal (default) frame rate. | |
47 | */ | |
48 | #define OV7670_FRAME_RATE 30 | |
49 | ||
111f3356 JC |
50 | /* |
51 | * The 7670 sits on i2c with ID 0x42 | |
52 | */ | |
53 | #define OV7670_I2C_ADDR 0x42 | |
54 | ||
55 | /* Registers */ | |
56 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ | |
57 | #define REG_BLUE 0x01 /* blue gain */ | |
58 | #define REG_RED 0x02 /* red gain */ | |
59 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ | |
60 | #define REG_COM1 0x04 /* Control 1 */ | |
61 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ | |
62 | #define REG_BAVE 0x05 /* U/B Average level */ | |
63 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ | |
64 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ | |
65 | #define REG_RAVE 0x08 /* V/R Average level */ | |
66 | #define REG_COM2 0x09 /* Control 2 */ | |
67 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ | |
68 | #define REG_PID 0x0a /* Product ID MSB */ | |
69 | #define REG_VER 0x0b /* Product ID LSB */ | |
70 | #define REG_COM3 0x0c /* Control 3 */ | |
71 | #define COM3_SWAP 0x40 /* Byte swap */ | |
72 | #define COM3_SCALEEN 0x08 /* Enable scaling */ | |
73 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ | |
74 | #define REG_COM4 0x0d /* Control 4 */ | |
75 | #define REG_COM5 0x0e /* All "reserved" */ | |
76 | #define REG_COM6 0x0f /* Control 6 */ | |
77 | #define REG_AECH 0x10 /* More bits of AEC value */ | |
78 | #define REG_CLKRC 0x11 /* Clocl control */ | |
79 | #define CLK_EXT 0x40 /* Use external clock directly */ | |
80 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ | |
81 | #define REG_COM7 0x12 /* Control 7 */ | |
82 | #define COM7_RESET 0x80 /* Register reset */ | |
83 | #define COM7_FMT_MASK 0x38 | |
84 | #define COM7_FMT_VGA 0x00 | |
85 | #define COM7_FMT_CIF 0x20 /* CIF format */ | |
86 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ | |
87 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ | |
88 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ | |
89 | #define COM7_YUV 0x00 /* YUV */ | |
90 | #define COM7_BAYER 0x01 /* Bayer format */ | |
91 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ | |
92 | #define REG_COM8 0x13 /* Control 8 */ | |
93 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ | |
94 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ | |
95 | #define COM8_BFILT 0x20 /* Band filter enable */ | |
96 | #define COM8_AGC 0x04 /* Auto gain enable */ | |
97 | #define COM8_AWB 0x02 /* White balance enable */ | |
98 | #define COM8_AEC 0x01 /* Auto exposure enable */ | |
99 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ | |
100 | #define REG_COM10 0x15 /* Control 10 */ | |
101 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ | |
102 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ | |
103 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ | |
104 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ | |
105 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ | |
106 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ | |
107 | #define REG_HSTART 0x17 /* Horiz start high bits */ | |
108 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ | |
109 | #define REG_VSTART 0x19 /* Vert start high bits */ | |
110 | #define REG_VSTOP 0x1a /* Vert stop high bits */ | |
111 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ | |
112 | #define REG_MIDH 0x1c /* Manuf. ID high */ | |
113 | #define REG_MIDL 0x1d /* Manuf. ID low */ | |
114 | #define REG_MVFP 0x1e /* Mirror / vflip */ | |
115 | #define MVFP_MIRROR 0x20 /* Mirror image */ | |
116 | #define MVFP_FLIP 0x10 /* Vertical flip */ | |
117 | ||
118 | #define REG_AEW 0x24 /* AGC upper limit */ | |
119 | #define REG_AEB 0x25 /* AGC lower limit */ | |
120 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ | |
121 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ | |
122 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ | |
123 | #define REG_HREF 0x32 /* HREF pieces */ | |
124 | #define REG_TSLB 0x3a /* lots of stuff */ | |
125 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ | |
126 | #define REG_COM11 0x3b /* Control 11 */ | |
127 | #define COM11_NIGHT 0x80 /* NIght mode enable */ | |
128 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ | |
129 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ | |
130 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ | |
131 | #define COM11_EXP 0x02 | |
132 | #define REG_COM12 0x3c /* Control 12 */ | |
133 | #define COM12_HREF 0x80 /* HREF always */ | |
134 | #define REG_COM13 0x3d /* Control 13 */ | |
135 | #define COM13_GAMMA 0x80 /* Gamma enable */ | |
136 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ | |
137 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ | |
138 | #define REG_COM14 0x3e /* Control 14 */ | |
139 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ | |
140 | #define REG_EDGE 0x3f /* Edge enhancement factor */ | |
141 | #define REG_COM15 0x40 /* Control 15 */ | |
142 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ | |
143 | #define COM15_R01FE 0x80 /* 01 to FE */ | |
144 | #define COM15_R00FF 0xc0 /* 00 to FF */ | |
145 | #define COM15_RGB565 0x10 /* RGB565 output */ | |
146 | #define COM15_RGB555 0x30 /* RGB555 output */ | |
147 | #define REG_COM16 0x41 /* Control 16 */ | |
148 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ | |
149 | #define REG_COM17 0x42 /* Control 17 */ | |
150 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ | |
151 | #define COM17_CBAR 0x08 /* DSP Color bar */ | |
152 | ||
f9a76156 JC |
153 | /* |
154 | * This matrix defines how the colors are generated, must be | |
155 | * tweaked to adjust hue and saturation. | |
156 | * | |
157 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue | |
158 | * | |
159 | * They are nine-bit signed quantities, with the sign bit | |
160 | * stored in 0x58. Sign for v-red is bit 0, and up from there. | |
161 | */ | |
162 | #define REG_CMATRIX_BASE 0x4f | |
163 | #define CMATRIX_LEN 6 | |
164 | #define REG_CMATRIX_SIGN 0x58 | |
165 | ||
166 | ||
111f3356 JC |
167 | #define REG_BRIGHT 0x55 /* Brightness */ |
168 | #define REG_CONTRAS 0x56 /* Contrast control */ | |
169 | ||
170 | #define REG_GFIX 0x69 /* Fix gain control */ | |
171 | ||
585553ec JC |
172 | #define REG_REG76 0x76 /* OV's name */ |
173 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ | |
174 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ | |
175 | ||
111f3356 JC |
176 | #define REG_RGB444 0x8c /* RGB 444 control */ |
177 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ | |
178 | #define R444_RGBX 0x01 /* Empty nibble at end */ | |
179 | ||
180 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ | |
181 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ | |
182 | ||
183 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ | |
184 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ | |
185 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ | |
186 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ | |
187 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ | |
188 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | |
189 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ | |
190 | ||
191 | ||
f9a76156 JC |
192 | /* |
193 | * Information we maintain about a known sensor. | |
194 | */ | |
195 | struct ov7670_format_struct; /* coming later */ | |
196 | struct ov7670_info { | |
14386c2b | 197 | struct v4l2_subdev sd; |
f9a76156 JC |
198 | struct ov7670_format_struct *fmt; /* Current format */ |
199 | unsigned char sat; /* Saturation value */ | |
200 | int hue; /* Hue value */ | |
d8d20155 | 201 | u8 clkrc; /* Clock divider value */ |
f9a76156 JC |
202 | }; |
203 | ||
14386c2b HV |
204 | static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) |
205 | { | |
206 | return container_of(sd, struct ov7670_info, sd); | |
207 | } | |
f9a76156 JC |
208 | |
209 | ||
210 | ||
111f3356 JC |
211 | /* |
212 | * The default register settings, as obtained from OmniVision. There | |
213 | * is really no making sense of most of these - lots of "reserved" values | |
214 | * and such. | |
215 | * | |
216 | * These settings give VGA YUYV. | |
217 | */ | |
218 | ||
219 | struct regval_list { | |
220 | unsigned char reg_num; | |
221 | unsigned char value; | |
222 | }; | |
223 | ||
224 | static struct regval_list ov7670_default_regs[] = { | |
225 | { REG_COM7, COM7_RESET }, | |
226 | /* | |
227 | * Clock scale: 3 = 15fps | |
228 | * 2 = 20fps | |
229 | * 1 = 30fps | |
230 | */ | |
f9a76156 | 231 | { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ |
111f3356 JC |
232 | { REG_TSLB, 0x04 }, /* OV */ |
233 | { REG_COM7, 0 }, /* VGA */ | |
234 | /* | |
235 | * Set the hardware window. These values from OV don't entirely | |
236 | * make sense - hstop is less than hstart. But they work... | |
237 | */ | |
238 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, | |
239 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, | |
240 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, | |
241 | ||
242 | { REG_COM3, 0 }, { REG_COM14, 0 }, | |
243 | /* Mystery scaling numbers */ | |
244 | { 0x70, 0x3a }, { 0x71, 0x35 }, | |
245 | { 0x72, 0x11 }, { 0x73, 0xf0 }, | |
246 | { 0xa2, 0x02 }, { REG_COM10, 0x0 }, | |
247 | ||
248 | /* Gamma curve values */ | |
249 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, | |
250 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, | |
251 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | |
252 | { 0x80, 0x76 }, { 0x81, 0x80 }, | |
253 | { 0x82, 0x88 }, { 0x83, 0x8f }, | |
254 | { 0x84, 0x96 }, { 0x85, 0xa3 }, | |
255 | { 0x86, 0xaf }, { 0x87, 0xc4 }, | |
256 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, | |
257 | ||
258 | /* AGC and AEC parameters. Note we start by disabling those features, | |
259 | then turn them only after tweaking the values. */ | |
260 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, | |
261 | { REG_GAIN, 0 }, { REG_AECH, 0 }, | |
262 | { REG_COM4, 0x40 }, /* magic reserved bit */ | |
263 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | |
264 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, | |
265 | { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, | |
266 | { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, | |
267 | { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ | |
268 | { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, | |
269 | { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, | |
270 | { REG_HAECC7, 0x94 }, | |
271 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, | |
272 | ||
273 | /* Almost all of these are magic "reserved" values. */ | |
274 | { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, | |
7f7b12f0 | 275 | { 0x16, 0x02 }, { REG_MVFP, 0x07 }, |
111f3356 JC |
276 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
277 | { 0x29, 0x07 }, { 0x33, 0x0b }, | |
278 | { 0x35, 0x0b }, { 0x37, 0x1d }, | |
279 | { 0x38, 0x71 }, { 0x39, 0x2a }, | |
280 | { REG_COM12, 0x78 }, { 0x4d, 0x40 }, | |
281 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, | |
282 | { 0x6b, 0x4a }, { 0x74, 0x10 }, | |
283 | { 0x8d, 0x4f }, { 0x8e, 0 }, | |
284 | { 0x8f, 0 }, { 0x90, 0 }, | |
285 | { 0x91, 0 }, { 0x96, 0 }, | |
286 | { 0x9a, 0 }, { 0xb0, 0x84 }, | |
287 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, | |
288 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, | |
289 | ||
290 | /* More reserved magic, some of which tweaks white balance */ | |
291 | { 0x43, 0x0a }, { 0x44, 0xf0 }, | |
292 | { 0x45, 0x34 }, { 0x46, 0x58 }, | |
293 | { 0x47, 0x28 }, { 0x48, 0x3a }, | |
294 | { 0x59, 0x88 }, { 0x5a, 0x88 }, | |
295 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, | |
296 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, | |
297 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, | |
298 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ | |
299 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, | |
300 | { REG_RED, 0x60 }, | |
301 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, | |
302 | ||
303 | /* Matrix coefficients */ | |
304 | { 0x4f, 0x80 }, { 0x50, 0x80 }, | |
305 | { 0x51, 0 }, { 0x52, 0x22 }, | |
306 | { 0x53, 0x5e }, { 0x54, 0x80 }, | |
307 | { 0x58, 0x9e }, | |
308 | ||
309 | { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, | |
310 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | |
311 | { 0x4c, 0 }, { 0x77, 0x01 }, | |
312 | { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | |
313 | { 0xc9, 0x60 }, { REG_COM16, 0x38 }, | |
314 | { 0x56, 0x40 }, | |
315 | ||
c8f5b2f5 | 316 | { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, |
111f3356 JC |
317 | { 0xa4, 0x88 }, { 0x96, 0 }, |
318 | { 0x97, 0x30 }, { 0x98, 0x20 }, | |
319 | { 0x99, 0x30 }, { 0x9a, 0x84 }, | |
320 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, | |
321 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, | |
322 | { 0x78, 0x04 }, | |
323 | ||
324 | /* Extra-weird stuff. Some sort of multiplexor register */ | |
325 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, | |
326 | { 0x79, 0x0f }, { 0xc8, 0x00 }, | |
327 | { 0x79, 0x10 }, { 0xc8, 0x7e }, | |
328 | { 0x79, 0x0a }, { 0xc8, 0x80 }, | |
329 | { 0x79, 0x0b }, { 0xc8, 0x01 }, | |
330 | { 0x79, 0x0c }, { 0xc8, 0x0f }, | |
331 | { 0x79, 0x0d }, { 0xc8, 0x20 }, | |
332 | { 0x79, 0x09 }, { 0xc8, 0x80 }, | |
333 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, | |
334 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | |
335 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | |
336 | { 0x79, 0x26 }, | |
337 | ||
111f3356 JC |
338 | { 0xff, 0xff }, /* END MARKER */ |
339 | }; | |
340 | ||
341 | ||
342 | /* | |
343 | * Here we'll try to encapsulate the changes for just the output | |
344 | * video format. | |
345 | * | |
346 | * RGB656 and YUV422 come from OV; RGB444 is homebrewed. | |
347 | * | |
348 | * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. | |
349 | */ | |
350 | ||
351 | ||
352 | static struct regval_list ov7670_fmt_yuv422[] = { | |
353 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | |
354 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 355 | { REG_COM1, 0 }, /* CCIR601 */ |
111f3356 JC |
356 | { REG_COM15, COM15_R00FF }, |
357 | { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */ | |
358 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ | |
359 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | |
f9a76156 | 360 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
361 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ |
362 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | |
363 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | |
364 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
365 | { 0xff, 0xff }, | |
366 | }; | |
367 | ||
368 | static struct regval_list ov7670_fmt_rgb565[] = { | |
369 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
370 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 371 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
372 | { REG_COM15, COM15_RGB565 }, |
373 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
374 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
375 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 376 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
377 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
378 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
379 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
380 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
381 | { 0xff, 0xff }, | |
382 | }; | |
383 | ||
384 | static struct regval_list ov7670_fmt_rgb444[] = { | |
385 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
386 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | |
97693f91 | 387 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
388 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
389 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
390 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
391 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 392 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
393 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
394 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
395 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
396 | { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ | |
397 | { 0xff, 0xff }, | |
398 | }; | |
399 | ||
585553ec JC |
400 | static struct regval_list ov7670_fmt_raw[] = { |
401 | { REG_COM7, COM7_BAYER }, | |
402 | { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ | |
403 | { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ | |
404 | { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ | |
405 | { 0xff, 0xff }, | |
406 | }; | |
111f3356 JC |
407 | |
408 | ||
409 | ||
410 | /* | |
411 | * Low-level register I/O. | |
46714209 JC |
412 | * |
413 | * Note that there are two versions of these. On the XO 1, the | |
414 | * i2c controller only does SMBUS, so that's what we use. The | |
415 | * ov7670 is not really an SMBUS device, though, so the communication | |
416 | * is not always entirely reliable. | |
417 | */ | |
418 | #ifdef CONFIG_OLPC_XO_1 | |
419 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, | |
420 | unsigned char *value) | |
421 | { | |
422 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
423 | int ret; | |
424 | ||
425 | ret = i2c_smbus_read_byte_data(client, reg); | |
426 | if (ret >= 0) { | |
427 | *value = (unsigned char)ret; | |
428 | ret = 0; | |
429 | } | |
430 | return ret; | |
431 | } | |
432 | ||
433 | ||
434 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |
435 | unsigned char value) | |
436 | { | |
437 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
438 | int ret = i2c_smbus_write_byte_data(client, reg, value); | |
439 | ||
440 | if (reg == REG_COM7 && (value & COM7_RESET)) | |
441 | msleep(5); /* Wait for reset to run */ | |
442 | return ret; | |
443 | } | |
444 | ||
445 | #else /* ! CONFIG_OLPC_XO_1 */ | |
446 | /* | |
447 | * On most platforms, we'd rather do straight i2c I/O. | |
111f3356 | 448 | */ |
14386c2b | 449 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
450 | unsigned char *value) |
451 | { | |
14386c2b | 452 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
453 | u8 data = reg; |
454 | struct i2c_msg msg; | |
111f3356 JC |
455 | int ret; |
456 | ||
2bf7de48 JC |
457 | /* |
458 | * Send out the register address... | |
459 | */ | |
460 | msg.addr = client->addr; | |
461 | msg.flags = 0; | |
462 | msg.len = 1; | |
463 | msg.buf = &data; | |
464 | ret = i2c_transfer(client->adapter, &msg, 1); | |
465 | if (ret < 0) { | |
466 | printk(KERN_ERR "Error %d on register write\n", ret); | |
467 | return ret; | |
468 | } | |
469 | /* | |
470 | * ...then read back the result. | |
471 | */ | |
472 | msg.flags = I2C_M_RD; | |
473 | ret = i2c_transfer(client->adapter, &msg, 1); | |
bca5c2c5 | 474 | if (ret >= 0) { |
2bf7de48 | 475 | *value = data; |
bca5c2c5 AS |
476 | ret = 0; |
477 | } | |
111f3356 JC |
478 | return ret; |
479 | } | |
480 | ||
481 | ||
14386c2b | 482 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
483 | unsigned char value) |
484 | { | |
14386c2b | 485 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
486 | struct i2c_msg msg; |
487 | unsigned char data[2] = { reg, value }; | |
488 | int ret; | |
14386c2b | 489 | |
2bf7de48 JC |
490 | msg.addr = client->addr; |
491 | msg.flags = 0; | |
492 | msg.len = 2; | |
493 | msg.buf = data; | |
494 | ret = i2c_transfer(client->adapter, &msg, 1); | |
495 | if (ret > 0) | |
496 | ret = 0; | |
6d77444a | 497 | if (reg == REG_COM7 && (value & COM7_RESET)) |
97693f91 | 498 | msleep(5); /* Wait for reset to run */ |
6d77444a | 499 | return ret; |
111f3356 | 500 | } |
46714209 | 501 | #endif /* CONFIG_OLPC_XO_1 */ |
111f3356 JC |
502 | |
503 | ||
504 | /* | |
505 | * Write a list of register settings; ff/ff stops the process. | |
506 | */ | |
14386c2b | 507 | static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) |
111f3356 JC |
508 | { |
509 | while (vals->reg_num != 0xff || vals->value != 0xff) { | |
14386c2b | 510 | int ret = ov7670_write(sd, vals->reg_num, vals->value); |
111f3356 JC |
511 | if (ret < 0) |
512 | return ret; | |
513 | vals++; | |
514 | } | |
515 | return 0; | |
516 | } | |
517 | ||
518 | ||
519 | /* | |
520 | * Stuff that knows about the sensor. | |
521 | */ | |
14386c2b | 522 | static int ov7670_reset(struct v4l2_subdev *sd, u32 val) |
111f3356 | 523 | { |
14386c2b | 524 | ov7670_write(sd, REG_COM7, COM7_RESET); |
111f3356 | 525 | msleep(1); |
14386c2b | 526 | return 0; |
111f3356 JC |
527 | } |
528 | ||
529 | ||
14386c2b | 530 | static int ov7670_init(struct v4l2_subdev *sd, u32 val) |
111f3356 | 531 | { |
14386c2b | 532 | return ov7670_write_array(sd, ov7670_default_regs); |
111f3356 JC |
533 | } |
534 | ||
535 | ||
536 | ||
14386c2b | 537 | static int ov7670_detect(struct v4l2_subdev *sd) |
111f3356 JC |
538 | { |
539 | unsigned char v; | |
540 | int ret; | |
541 | ||
14386c2b | 542 | ret = ov7670_init(sd, 0); |
111f3356 JC |
543 | if (ret < 0) |
544 | return ret; | |
14386c2b | 545 | ret = ov7670_read(sd, REG_MIDH, &v); |
111f3356 JC |
546 | if (ret < 0) |
547 | return ret; | |
548 | if (v != 0x7f) /* OV manuf. id. */ | |
549 | return -ENODEV; | |
14386c2b | 550 | ret = ov7670_read(sd, REG_MIDL, &v); |
111f3356 JC |
551 | if (ret < 0) |
552 | return ret; | |
553 | if (v != 0xa2) | |
554 | return -ENODEV; | |
555 | /* | |
556 | * OK, we know we have an OmniVision chip...but which one? | |
557 | */ | |
14386c2b | 558 | ret = ov7670_read(sd, REG_PID, &v); |
111f3356 JC |
559 | if (ret < 0) |
560 | return ret; | |
561 | if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ | |
562 | return -ENODEV; | |
14386c2b | 563 | ret = ov7670_read(sd, REG_VER, &v); |
111f3356 JC |
564 | if (ret < 0) |
565 | return ret; | |
566 | if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ | |
567 | return -ENODEV; | |
568 | return 0; | |
569 | } | |
570 | ||
571 | ||
f9a76156 JC |
572 | /* |
573 | * Store information about the video data format. The color matrix | |
574 | * is deeply tied into the format, so keep the relevant values here. | |
575 | * The magic matrix nubmers come from OmniVision. | |
576 | */ | |
111f3356 JC |
577 | static struct ov7670_format_struct { |
578 | __u8 *desc; | |
579 | __u32 pixelformat; | |
580 | struct regval_list *regs; | |
f9a76156 | 581 | int cmatrix[CMATRIX_LEN]; |
585553ec | 582 | int bpp; /* Bytes per pixel */ |
111f3356 JC |
583 | } ov7670_formats[] = { |
584 | { | |
585 | .desc = "YUYV 4:2:2", | |
586 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
587 | .regs = ov7670_fmt_yuv422, | |
f9a76156 | 588 | .cmatrix = { 128, -128, 0, -34, -94, 128 }, |
585553ec | 589 | .bpp = 2, |
111f3356 JC |
590 | }, |
591 | { | |
592 | .desc = "RGB 444", | |
593 | .pixelformat = V4L2_PIX_FMT_RGB444, | |
594 | .regs = ov7670_fmt_rgb444, | |
f9a76156 | 595 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec | 596 | .bpp = 2, |
111f3356 JC |
597 | }, |
598 | { | |
599 | .desc = "RGB 565", | |
600 | .pixelformat = V4L2_PIX_FMT_RGB565, | |
601 | .regs = ov7670_fmt_rgb565, | |
f9a76156 | 602 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec JC |
603 | .bpp = 2, |
604 | }, | |
605 | { | |
606 | .desc = "Raw RGB Bayer", | |
607 | .pixelformat = V4L2_PIX_FMT_SBGGR8, | |
608 | .regs = ov7670_fmt_raw, | |
609 | .cmatrix = { 0, 0, 0, 0, 0, 0 }, | |
610 | .bpp = 1 | |
111f3356 | 611 | }, |
111f3356 | 612 | }; |
585553ec | 613 | #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) |
111f3356 | 614 | |
111f3356 JC |
615 | |
616 | /* | |
617 | * Then there is the issue of window sizes. Try to capture the info here. | |
618 | */ | |
f9a76156 JC |
619 | |
620 | /* | |
621 | * QCIF mode is done (by OV) in a very strange way - it actually looks like | |
622 | * VGA with weird scaling options - they do *not* use the canned QCIF mode | |
623 | * which is allegedly provided by the sensor. So here's the weird register | |
624 | * settings. | |
625 | */ | |
626 | static struct regval_list ov7670_qcif_regs[] = { | |
627 | { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, | |
628 | { REG_COM3, COM3_DCWEN }, | |
629 | { REG_COM14, COM14_DCWEN | 0x01}, | |
630 | { 0x73, 0xf1 }, | |
631 | { 0xa2, 0x52 }, | |
632 | { 0x7b, 0x1c }, | |
633 | { 0x7c, 0x28 }, | |
634 | { 0x7d, 0x3c }, | |
635 | { 0x7f, 0x69 }, | |
636 | { REG_COM9, 0x38 }, | |
637 | { 0xa1, 0x0b }, | |
638 | { 0x74, 0x19 }, | |
639 | { 0x9a, 0x80 }, | |
640 | { 0x43, 0x14 }, | |
641 | { REG_COM13, 0xc0 }, | |
642 | { 0xff, 0xff }, | |
643 | }; | |
644 | ||
111f3356 JC |
645 | static struct ov7670_win_size { |
646 | int width; | |
647 | int height; | |
648 | unsigned char com7_bit; | |
649 | int hstart; /* Start/stop values for the camera. Note */ | |
650 | int hstop; /* that they do not always make complete */ | |
651 | int vstart; /* sense to humans, but evidently the sensor */ | |
652 | int vstop; /* will do the right thing... */ | |
f9a76156 | 653 | struct regval_list *regs; /* Regs to tweak */ |
111f3356 JC |
654 | /* h/vref stuff */ |
655 | } ov7670_win_sizes[] = { | |
656 | /* VGA */ | |
657 | { | |
658 | .width = VGA_WIDTH, | |
659 | .height = VGA_HEIGHT, | |
660 | .com7_bit = COM7_FMT_VGA, | |
661 | .hstart = 158, /* These values from */ | |
662 | .hstop = 14, /* Omnivision */ | |
663 | .vstart = 10, | |
664 | .vstop = 490, | |
f9a76156 | 665 | .regs = NULL, |
111f3356 JC |
666 | }, |
667 | /* CIF */ | |
668 | { | |
669 | .width = CIF_WIDTH, | |
670 | .height = CIF_HEIGHT, | |
671 | .com7_bit = COM7_FMT_CIF, | |
672 | .hstart = 170, /* Empirically determined */ | |
673 | .hstop = 90, | |
674 | .vstart = 14, | |
675 | .vstop = 494, | |
f9a76156 | 676 | .regs = NULL, |
111f3356 JC |
677 | }, |
678 | /* QVGA */ | |
679 | { | |
680 | .width = QVGA_WIDTH, | |
681 | .height = QVGA_HEIGHT, | |
682 | .com7_bit = COM7_FMT_QVGA, | |
683 | .hstart = 164, /* Empirically determined */ | |
684 | .hstop = 20, | |
685 | .vstart = 14, | |
686 | .vstop = 494, | |
f9a76156 JC |
687 | .regs = NULL, |
688 | }, | |
689 | /* QCIF */ | |
690 | { | |
691 | .width = QCIF_WIDTH, | |
692 | .height = QCIF_HEIGHT, | |
693 | .com7_bit = COM7_FMT_VGA, /* see comment above */ | |
694 | .hstart = 456, /* Empirically determined */ | |
695 | .hstop = 24, | |
696 | .vstart = 14, | |
697 | .vstop = 494, | |
698 | .regs = ov7670_qcif_regs, | |
111f3356 JC |
699 | }, |
700 | }; | |
701 | ||
0c71bf1c | 702 | #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes)) |
111f3356 JC |
703 | |
704 | ||
705 | /* | |
706 | * Store a set of start/stop values into the camera. | |
707 | */ | |
14386c2b | 708 | static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, |
111f3356 JC |
709 | int vstart, int vstop) |
710 | { | |
711 | int ret; | |
712 | unsigned char v; | |
713 | /* | |
714 | * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of | |
715 | * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is | |
716 | * a mystery "edge offset" value in the top two bits of href. | |
717 | */ | |
14386c2b HV |
718 | ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); |
719 | ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); | |
720 | ret += ov7670_read(sd, REG_HREF, &v); | |
111f3356 JC |
721 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); |
722 | msleep(10); | |
14386c2b | 723 | ret += ov7670_write(sd, REG_HREF, v); |
111f3356 JC |
724 | /* |
725 | * Vertical: similar arrangement, but only 10 bits. | |
726 | */ | |
14386c2b HV |
727 | ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); |
728 | ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); | |
729 | ret += ov7670_read(sd, REG_VREF, &v); | |
111f3356 JC |
730 | v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); |
731 | msleep(10); | |
14386c2b | 732 | ret += ov7670_write(sd, REG_VREF, v); |
111f3356 JC |
733 | return ret; |
734 | } | |
735 | ||
736 | ||
14386c2b | 737 | static int ov7670_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmt) |
111f3356 JC |
738 | { |
739 | struct ov7670_format_struct *ofmt; | |
740 | ||
741 | if (fmt->index >= N_OV7670_FMTS) | |
742 | return -EINVAL; | |
743 | ||
744 | ofmt = ov7670_formats + fmt->index; | |
745 | fmt->flags = 0; | |
746 | strcpy(fmt->description, ofmt->desc); | |
747 | fmt->pixelformat = ofmt->pixelformat; | |
748 | return 0; | |
749 | } | |
750 | ||
751 | ||
14386c2b HV |
752 | static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, |
753 | struct v4l2_format *fmt, | |
111f3356 JC |
754 | struct ov7670_format_struct **ret_fmt, |
755 | struct ov7670_win_size **ret_wsize) | |
756 | { | |
757 | int index; | |
758 | struct ov7670_win_size *wsize; | |
759 | struct v4l2_pix_format *pix = &fmt->fmt.pix; | |
760 | ||
761 | for (index = 0; index < N_OV7670_FMTS; index++) | |
762 | if (ov7670_formats[index].pixelformat == pix->pixelformat) | |
763 | break; | |
cd257a6f DD |
764 | if (index >= N_OV7670_FMTS) { |
765 | /* default to first format */ | |
766 | index = 0; | |
767 | pix->pixelformat = ov7670_formats[0].pixelformat; | |
768 | } | |
111f3356 JC |
769 | if (ret_fmt != NULL) |
770 | *ret_fmt = ov7670_formats + index; | |
771 | /* | |
772 | * Fields: the OV devices claim to be progressive. | |
773 | */ | |
cd257a6f | 774 | pix->field = V4L2_FIELD_NONE; |
111f3356 JC |
775 | /* |
776 | * Round requested image size down to the nearest | |
777 | * we support, but not below the smallest. | |
778 | */ | |
779 | for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES; | |
780 | wsize++) | |
781 | if (pix->width >= wsize->width && pix->height >= wsize->height) | |
782 | break; | |
f9a76156 | 783 | if (wsize >= ov7670_win_sizes + N_WIN_SIZES) |
111f3356 JC |
784 | wsize--; /* Take the smallest one */ |
785 | if (ret_wsize != NULL) | |
786 | *ret_wsize = wsize; | |
787 | /* | |
788 | * Note the size we'll actually handle. | |
789 | */ | |
790 | pix->width = wsize->width; | |
791 | pix->height = wsize->height; | |
585553ec | 792 | pix->bytesperline = pix->width*ov7670_formats[index].bpp; |
111f3356 JC |
793 | pix->sizeimage = pix->height*pix->bytesperline; |
794 | return 0; | |
111f3356 JC |
795 | } |
796 | ||
14386c2b HV |
797 | static int ov7670_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
798 | { | |
799 | return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); | |
800 | } | |
801 | ||
111f3356 JC |
802 | /* |
803 | * Set a format. | |
804 | */ | |
14386c2b | 805 | static int ov7670_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
111f3356 JC |
806 | { |
807 | int ret; | |
808 | struct ov7670_format_struct *ovfmt; | |
809 | struct ov7670_win_size *wsize; | |
14386c2b | 810 | struct ov7670_info *info = to_state(sd); |
d8d20155 | 811 | unsigned char com7; |
111f3356 | 812 | |
14386c2b | 813 | ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); |
111f3356 JC |
814 | if (ret) |
815 | return ret; | |
816 | /* | |
817 | * COM7 is a pain in the ass, it doesn't like to be read then | |
818 | * quickly written afterward. But we have everything we need | |
819 | * to set it absolutely here, as long as the format-specific | |
820 | * register sets list it first. | |
821 | */ | |
822 | com7 = ovfmt->regs[0].value; | |
823 | com7 |= wsize->com7_bit; | |
14386c2b | 824 | ov7670_write(sd, REG_COM7, com7); |
111f3356 JC |
825 | /* |
826 | * Now write the rest of the array. Also store start/stops | |
827 | */ | |
14386c2b HV |
828 | ov7670_write_array(sd, ovfmt->regs + 1); |
829 | ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, | |
111f3356 | 830 | wsize->vstop); |
f9a76156 JC |
831 | ret = 0; |
832 | if (wsize->regs) | |
14386c2b | 833 | ret = ov7670_write_array(sd, wsize->regs); |
f9a76156 | 834 | info->fmt = ovfmt; |
edd75ede | 835 | |
d8d20155 JC |
836 | /* |
837 | * If we're running RGB565, we must rewrite clkrc after setting | |
838 | * the other parameters or the image looks poor. If we're *not* | |
839 | * doing RGB565, we must not rewrite clkrc or the image looks | |
840 | * *really* poor. | |
841 | */ | |
edd75ede | 842 | if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565 && ret == 0) |
d8d20155 | 843 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); |
edd75ede | 844 | return ret; |
111f3356 JC |
845 | } |
846 | ||
c8f5b2f5 JC |
847 | /* |
848 | * Implement G/S_PARM. There is a "high quality" mode we could try | |
849 | * to do someday; for now, we just do the frame rate tweak. | |
850 | */ | |
14386c2b | 851 | static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
852 | { |
853 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
d8d20155 | 854 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
855 | |
856 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
857 | return -EINVAL; | |
d8d20155 | 858 | |
c8f5b2f5 JC |
859 | memset(cp, 0, sizeof(struct v4l2_captureparm)); |
860 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
861 | cp->timeperframe.numerator = 1; | |
862 | cp->timeperframe.denominator = OV7670_FRAME_RATE; | |
d8d20155 JC |
863 | if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) |
864 | cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE); | |
c8f5b2f5 JC |
865 | return 0; |
866 | } | |
867 | ||
14386c2b | 868 | static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
869 | { |
870 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
871 | struct v4l2_fract *tpf = &cp->timeperframe; | |
d8d20155 | 872 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
873 | unsigned char clkrc; |
874 | int ret, div; | |
875 | ||
876 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
877 | return -EINVAL; | |
878 | if (cp->extendedmode != 0) | |
879 | return -EINVAL; | |
d8d20155 | 880 | |
c8f5b2f5 JC |
881 | if (tpf->numerator == 0 || tpf->denominator == 0) |
882 | div = 1; /* Reset to full rate */ | |
883 | else | |
884 | div = (tpf->numerator*OV7670_FRAME_RATE)/tpf->denominator; | |
885 | if (div == 0) | |
886 | div = 1; | |
887 | else if (div > CLK_SCALE) | |
888 | div = CLK_SCALE; | |
d8d20155 | 889 | info->clkrc = (info->clkrc & 0x80) | div; |
c8f5b2f5 JC |
890 | tpf->numerator = 1; |
891 | tpf->denominator = OV7670_FRAME_RATE/div; | |
d8d20155 | 892 | return ov7670_write(sd, REG_CLKRC, info->clkrc); |
c8f5b2f5 JC |
893 | } |
894 | ||
895 | ||
896 | ||
111f3356 JC |
897 | /* |
898 | * Code for dealing with controls. | |
899 | */ | |
900 | ||
f9a76156 JC |
901 | |
902 | ||
903 | ||
904 | ||
14386c2b | 905 | static int ov7670_store_cmatrix(struct v4l2_subdev *sd, |
f9a76156 JC |
906 | int matrix[CMATRIX_LEN]) |
907 | { | |
908 | int i, ret; | |
e3bf20de | 909 | unsigned char signbits = 0; |
f9a76156 JC |
910 | |
911 | /* | |
912 | * Weird crap seems to exist in the upper part of | |
913 | * the sign bits register, so let's preserve it. | |
914 | */ | |
14386c2b | 915 | ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); |
f9a76156 JC |
916 | signbits &= 0xc0; |
917 | ||
918 | for (i = 0; i < CMATRIX_LEN; i++) { | |
919 | unsigned char raw; | |
920 | ||
921 | if (matrix[i] < 0) { | |
922 | signbits |= (1 << i); | |
923 | if (matrix[i] < -255) | |
924 | raw = 0xff; | |
925 | else | |
926 | raw = (-1 * matrix[i]) & 0xff; | |
927 | } | |
928 | else { | |
929 | if (matrix[i] > 255) | |
930 | raw = 0xff; | |
931 | else | |
932 | raw = matrix[i] & 0xff; | |
933 | } | |
14386c2b | 934 | ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); |
f9a76156 | 935 | } |
14386c2b | 936 | ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); |
f9a76156 JC |
937 | return ret; |
938 | } | |
939 | ||
940 | ||
941 | /* | |
942 | * Hue also requires messing with the color matrix. It also requires | |
943 | * trig functions, which tend not to be well supported in the kernel. | |
944 | * So here is a simple table of sine values, 0-90 degrees, in steps | |
945 | * of five degrees. Values are multiplied by 1000. | |
946 | * | |
947 | * The following naive approximate trig functions require an argument | |
948 | * carefully limited to -180 <= theta <= 180. | |
949 | */ | |
950 | #define SIN_STEP 5 | |
951 | static const int ov7670_sin_table[] = { | |
952 | 0, 87, 173, 258, 342, 422, | |
953 | 499, 573, 642, 707, 766, 819, | |
954 | 866, 906, 939, 965, 984, 996, | |
955 | 1000 | |
956 | }; | |
957 | ||
958 | static int ov7670_sine(int theta) | |
959 | { | |
960 | int chs = 1; | |
961 | int sine; | |
962 | ||
963 | if (theta < 0) { | |
964 | theta = -theta; | |
965 | chs = -1; | |
966 | } | |
967 | if (theta <= 90) | |
968 | sine = ov7670_sin_table[theta/SIN_STEP]; | |
969 | else { | |
970 | theta -= 90; | |
971 | sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; | |
972 | } | |
973 | return sine*chs; | |
974 | } | |
975 | ||
976 | static int ov7670_cosine(int theta) | |
977 | { | |
978 | theta = 90 - theta; | |
979 | if (theta > 180) | |
980 | theta -= 360; | |
981 | else if (theta < -180) | |
982 | theta += 360; | |
983 | return ov7670_sine(theta); | |
984 | } | |
985 | ||
986 | ||
987 | ||
988 | ||
989 | static void ov7670_calc_cmatrix(struct ov7670_info *info, | |
990 | int matrix[CMATRIX_LEN]) | |
991 | { | |
992 | int i; | |
993 | /* | |
994 | * Apply the current saturation setting first. | |
995 | */ | |
996 | for (i = 0; i < CMATRIX_LEN; i++) | |
997 | matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7; | |
998 | /* | |
999 | * Then, if need be, rotate the hue value. | |
1000 | */ | |
1001 | if (info->hue != 0) { | |
1002 | int sinth, costh, tmpmatrix[CMATRIX_LEN]; | |
1003 | ||
1004 | memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); | |
1005 | sinth = ov7670_sine(info->hue); | |
1006 | costh = ov7670_cosine(info->hue); | |
1007 | ||
1008 | matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; | |
1009 | matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; | |
1010 | matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; | |
1011 | matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; | |
1012 | matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; | |
1013 | matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | ||
1018 | ||
ca07561a | 1019 | static int ov7670_s_sat(struct v4l2_subdev *sd, int value) |
f9a76156 | 1020 | { |
14386c2b | 1021 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1022 | int matrix[CMATRIX_LEN]; |
1023 | int ret; | |
1024 | ||
1025 | info->sat = value; | |
1026 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1027 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1028 | return ret; |
1029 | } | |
1030 | ||
ca07561a | 1031 | static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1032 | { |
14386c2b | 1033 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1034 | |
1035 | *value = info->sat; | |
1036 | return 0; | |
1037 | } | |
1038 | ||
ca07561a | 1039 | static int ov7670_s_hue(struct v4l2_subdev *sd, int value) |
f9a76156 | 1040 | { |
14386c2b | 1041 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1042 | int matrix[CMATRIX_LEN]; |
1043 | int ret; | |
1044 | ||
1045 | if (value < -180 || value > 180) | |
1046 | return -EINVAL; | |
1047 | info->hue = value; | |
1048 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1049 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1050 | return ret; |
1051 | } | |
1052 | ||
1053 | ||
ca07561a | 1054 | static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1055 | { |
14386c2b | 1056 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1057 | |
1058 | *value = info->hue; | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | ||
111f3356 JC |
1063 | /* |
1064 | * Some weird registers seem to store values in a sign/magnitude format! | |
1065 | */ | |
1066 | static unsigned char ov7670_sm_to_abs(unsigned char v) | |
1067 | { | |
1068 | if ((v & 0x80) == 0) | |
1069 | return v + 128; | |
14386c2b | 1070 | return 128 - (v & 0x7f); |
111f3356 JC |
1071 | } |
1072 | ||
1073 | ||
1074 | static unsigned char ov7670_abs_to_sm(unsigned char v) | |
1075 | { | |
1076 | if (v > 127) | |
1077 | return v & 0x7f; | |
14386c2b | 1078 | return (128 - v) | 0x80; |
111f3356 JC |
1079 | } |
1080 | ||
ca07561a | 1081 | static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) |
111f3356 | 1082 | { |
e3bf20de | 1083 | unsigned char com8 = 0, v; |
111f3356 JC |
1084 | int ret; |
1085 | ||
14386c2b | 1086 | ov7670_read(sd, REG_COM8, &com8); |
111f3356 | 1087 | com8 &= ~COM8_AEC; |
14386c2b | 1088 | ov7670_write(sd, REG_COM8, com8); |
f9a76156 | 1089 | v = ov7670_abs_to_sm(value); |
14386c2b | 1090 | ret = ov7670_write(sd, REG_BRIGHT, v); |
111f3356 JC |
1091 | return ret; |
1092 | } | |
1093 | ||
ca07561a | 1094 | static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1095 | { |
e3bf20de | 1096 | unsigned char v = 0; |
14386c2b | 1097 | int ret = ov7670_read(sd, REG_BRIGHT, &v); |
f9a76156 JC |
1098 | |
1099 | *value = ov7670_sm_to_abs(v); | |
111f3356 JC |
1100 | return ret; |
1101 | } | |
1102 | ||
ca07561a | 1103 | static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) |
111f3356 | 1104 | { |
14386c2b | 1105 | return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); |
111f3356 JC |
1106 | } |
1107 | ||
ca07561a | 1108 | static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1109 | { |
e3bf20de | 1110 | unsigned char v = 0; |
14386c2b | 1111 | int ret = ov7670_read(sd, REG_CONTRAS, &v); |
f9a76156 JC |
1112 | |
1113 | *value = v; | |
1114 | return ret; | |
111f3356 JC |
1115 | } |
1116 | ||
ca07561a | 1117 | static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1118 | { |
1119 | int ret; | |
e3bf20de | 1120 | unsigned char v = 0; |
111f3356 | 1121 | |
14386c2b | 1122 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1123 | *value = (v & MVFP_MIRROR) == MVFP_MIRROR; |
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | ||
ca07561a | 1128 | static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1129 | { |
e3bf20de | 1130 | unsigned char v = 0; |
111f3356 JC |
1131 | int ret; |
1132 | ||
14386c2b | 1133 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1134 | if (value) |
1135 | v |= MVFP_MIRROR; | |
1136 | else | |
1137 | v &= ~MVFP_MIRROR; | |
1138 | msleep(10); /* FIXME */ | |
14386c2b | 1139 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1140 | return ret; |
1141 | } | |
1142 | ||
1143 | ||
1144 | ||
ca07561a | 1145 | static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1146 | { |
1147 | int ret; | |
e3bf20de | 1148 | unsigned char v = 0; |
111f3356 | 1149 | |
14386c2b | 1150 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1151 | *value = (v & MVFP_FLIP) == MVFP_FLIP; |
1152 | return ret; | |
1153 | } | |
1154 | ||
1155 | ||
ca07561a | 1156 | static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1157 | { |
e3bf20de | 1158 | unsigned char v = 0; |
111f3356 JC |
1159 | int ret; |
1160 | ||
14386c2b | 1161 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1162 | if (value) |
1163 | v |= MVFP_FLIP; | |
1164 | else | |
1165 | v &= ~MVFP_FLIP; | |
1166 | msleep(10); /* FIXME */ | |
14386c2b | 1167 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1168 | return ret; |
1169 | } | |
1170 | ||
81898671 JC |
1171 | /* |
1172 | * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes | |
1173 | * the data sheet, the VREF parts should be the most significant, but | |
1174 | * experience shows otherwise. There seems to be little value in | |
1175 | * messing with the VREF bits, so we leave them alone. | |
1176 | */ | |
1177 | static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) | |
1178 | { | |
1179 | int ret; | |
1180 | unsigned char gain; | |
1181 | ||
1182 | ret = ov7670_read(sd, REG_GAIN, &gain); | |
1183 | *value = gain; | |
1184 | return ret; | |
1185 | } | |
1186 | ||
1187 | static int ov7670_s_gain(struct v4l2_subdev *sd, int value) | |
1188 | { | |
1189 | int ret; | |
1190 | unsigned char com8; | |
1191 | ||
1192 | ret = ov7670_write(sd, REG_GAIN, value & 0xff); | |
1193 | /* Have to turn off AGC as well */ | |
1194 | if (ret == 0) { | |
1195 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1196 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); | |
1197 | } | |
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | /* | |
1202 | * Tweak autogain. | |
1203 | */ | |
1204 | static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value) | |
1205 | { | |
1206 | int ret; | |
1207 | unsigned char com8; | |
1208 | ||
1209 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1210 | *value = (com8 & COM8_AGC) != 0; | |
1211 | return ret; | |
1212 | } | |
1213 | ||
1214 | static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) | |
1215 | { | |
1216 | int ret; | |
1217 | unsigned char com8; | |
1218 | ||
1219 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1220 | if (ret == 0) { | |
1221 | if (value) | |
1222 | com8 |= COM8_AGC; | |
1223 | else | |
1224 | com8 &= ~COM8_AGC; | |
1225 | ret = ov7670_write(sd, REG_COM8, com8); | |
1226 | } | |
1227 | return ret; | |
1228 | } | |
1229 | ||
364e9337 JC |
1230 | /* |
1231 | * Exposure is spread all over the place: top 6 bits in AECHH, middle | |
1232 | * 8 in AECH, and two stashed in COM1 just for the hell of it. | |
1233 | */ | |
1234 | static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value) | |
1235 | { | |
1236 | int ret; | |
1237 | unsigned char com1, aech, aechh; | |
1238 | ||
1239 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1240 | ov7670_read(sd, REG_AECH, &aech) + | |
1241 | ov7670_read(sd, REG_AECHH, &aechh); | |
1242 | *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03); | |
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | static int ov7670_s_exp(struct v4l2_subdev *sd, int value) | |
1247 | { | |
1248 | int ret; | |
1249 | unsigned char com1, com8, aech, aechh; | |
1250 | ||
1251 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1252 | ov7670_read(sd, REG_COM8, &com8); | |
1253 | ov7670_read(sd, REG_AECHH, &aechh); | |
1254 | if (ret) | |
1255 | return ret; | |
1256 | ||
1257 | com1 = (com1 & 0xfc) | (value & 0x03); | |
1258 | aech = (value >> 2) & 0xff; | |
1259 | aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); | |
1260 | ret = ov7670_write(sd, REG_COM1, com1) + | |
1261 | ov7670_write(sd, REG_AECH, aech) + | |
1262 | ov7670_write(sd, REG_AECHH, aechh); | |
1263 | /* Have to turn off AEC as well */ | |
1264 | if (ret == 0) | |
1265 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); | |
1266 | return ret; | |
1267 | } | |
1268 | ||
1269 | /* | |
1270 | * Tweak autoexposure. | |
1271 | */ | |
1272 | static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value) | |
1273 | { | |
1274 | int ret; | |
1275 | unsigned char com8; | |
1276 | enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value; | |
1277 | ||
1278 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1279 | if (com8 & COM8_AEC) | |
1280 | *value = V4L2_EXPOSURE_AUTO; | |
1281 | else | |
1282 | *value = V4L2_EXPOSURE_MANUAL; | |
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | static int ov7670_s_autoexp(struct v4l2_subdev *sd, | |
1287 | enum v4l2_exposure_auto_type value) | |
1288 | { | |
1289 | int ret; | |
1290 | unsigned char com8; | |
1291 | ||
1292 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1293 | if (ret == 0) { | |
1294 | if (value == V4L2_EXPOSURE_AUTO) | |
1295 | com8 |= COM8_AEC; | |
1296 | else | |
1297 | com8 &= ~COM8_AEC; | |
1298 | ret = ov7670_write(sd, REG_COM8, com8); | |
1299 | } | |
1300 | return ret; | |
1301 | } | |
1302 | ||
81898671 JC |
1303 | |
1304 | ||
14386c2b | 1305 | static int ov7670_queryctrl(struct v4l2_subdev *sd, |
111f3356 JC |
1306 | struct v4l2_queryctrl *qc) |
1307 | { | |
ca07561a HV |
1308 | /* Fill in min, max, step and default value for these controls. */ |
1309 | switch (qc->id) { | |
1310 | case V4L2_CID_BRIGHTNESS: | |
1311 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1312 | case V4L2_CID_CONTRAST: | |
1313 | return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); | |
1314 | case V4L2_CID_VFLIP: | |
1315 | case V4L2_CID_HFLIP: | |
1316 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
1317 | case V4L2_CID_SATURATION: | |
1318 | return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128); | |
1319 | case V4L2_CID_HUE: | |
1320 | return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); | |
81898671 JC |
1321 | case V4L2_CID_GAIN: |
1322 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1323 | case V4L2_CID_AUTOGAIN: | |
1324 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); | |
364e9337 JC |
1325 | case V4L2_CID_EXPOSURE: |
1326 | return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500); | |
1327 | case V4L2_CID_EXPOSURE_AUTO: | |
1328 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
ca07561a HV |
1329 | } |
1330 | return -EINVAL; | |
111f3356 JC |
1331 | } |
1332 | ||
14386c2b | 1333 | static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1334 | { |
ca07561a HV |
1335 | switch (ctrl->id) { |
1336 | case V4L2_CID_BRIGHTNESS: | |
1337 | return ov7670_g_brightness(sd, &ctrl->value); | |
1338 | case V4L2_CID_CONTRAST: | |
1339 | return ov7670_g_contrast(sd, &ctrl->value); | |
1340 | case V4L2_CID_SATURATION: | |
1341 | return ov7670_g_sat(sd, &ctrl->value); | |
1342 | case V4L2_CID_HUE: | |
1343 | return ov7670_g_hue(sd, &ctrl->value); | |
1344 | case V4L2_CID_VFLIP: | |
1345 | return ov7670_g_vflip(sd, &ctrl->value); | |
1346 | case V4L2_CID_HFLIP: | |
1347 | return ov7670_g_hflip(sd, &ctrl->value); | |
81898671 JC |
1348 | case V4L2_CID_GAIN: |
1349 | return ov7670_g_gain(sd, &ctrl->value); | |
1350 | case V4L2_CID_AUTOGAIN: | |
1351 | return ov7670_g_autogain(sd, &ctrl->value); | |
364e9337 JC |
1352 | case V4L2_CID_EXPOSURE: |
1353 | return ov7670_g_exp(sd, &ctrl->value); | |
1354 | case V4L2_CID_EXPOSURE_AUTO: | |
1355 | return ov7670_g_autoexp(sd, &ctrl->value); | |
ca07561a HV |
1356 | } |
1357 | return -EINVAL; | |
111f3356 JC |
1358 | } |
1359 | ||
14386c2b | 1360 | static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1361 | { |
ca07561a HV |
1362 | switch (ctrl->id) { |
1363 | case V4L2_CID_BRIGHTNESS: | |
1364 | return ov7670_s_brightness(sd, ctrl->value); | |
1365 | case V4L2_CID_CONTRAST: | |
1366 | return ov7670_s_contrast(sd, ctrl->value); | |
1367 | case V4L2_CID_SATURATION: | |
1368 | return ov7670_s_sat(sd, ctrl->value); | |
1369 | case V4L2_CID_HUE: | |
1370 | return ov7670_s_hue(sd, ctrl->value); | |
1371 | case V4L2_CID_VFLIP: | |
1372 | return ov7670_s_vflip(sd, ctrl->value); | |
1373 | case V4L2_CID_HFLIP: | |
1374 | return ov7670_s_hflip(sd, ctrl->value); | |
81898671 JC |
1375 | case V4L2_CID_GAIN: |
1376 | return ov7670_s_gain(sd, ctrl->value); | |
1377 | case V4L2_CID_AUTOGAIN: | |
1378 | return ov7670_s_autogain(sd, ctrl->value); | |
364e9337 JC |
1379 | case V4L2_CID_EXPOSURE: |
1380 | return ov7670_s_exp(sd, ctrl->value); | |
1381 | case V4L2_CID_EXPOSURE_AUTO: | |
1382 | return ov7670_s_autoexp(sd, | |
1383 | (enum v4l2_exposure_auto_type) ctrl->value); | |
ca07561a HV |
1384 | } |
1385 | return -EINVAL; | |
111f3356 JC |
1386 | } |
1387 | ||
14386c2b HV |
1388 | static int ov7670_g_chip_ident(struct v4l2_subdev *sd, |
1389 | struct v4l2_dbg_chip_ident *chip) | |
1390 | { | |
1391 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1392 | ||
1393 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0); | |
1394 | } | |
1395 | ||
b794aabf HV |
1396 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1397 | static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1398 | { | |
1399 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1400 | unsigned char val = 0; | |
1401 | int ret; | |
1402 | ||
1403 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1404 | return -EINVAL; | |
1405 | if (!capable(CAP_SYS_ADMIN)) | |
1406 | return -EPERM; | |
1407 | ret = ov7670_read(sd, reg->reg & 0xff, &val); | |
1408 | reg->val = val; | |
1409 | reg->size = 1; | |
1410 | return ret; | |
1411 | } | |
1412 | ||
1413 | static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1414 | { | |
1415 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1416 | ||
1417 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1418 | return -EINVAL; | |
1419 | if (!capable(CAP_SYS_ADMIN)) | |
1420 | return -EPERM; | |
1421 | ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); | |
1422 | return 0; | |
1423 | } | |
1424 | #endif | |
1425 | ||
14386c2b | 1426 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1427 | |
14386c2b HV |
1428 | static const struct v4l2_subdev_core_ops ov7670_core_ops = { |
1429 | .g_chip_ident = ov7670_g_chip_ident, | |
1430 | .g_ctrl = ov7670_g_ctrl, | |
1431 | .s_ctrl = ov7670_s_ctrl, | |
1432 | .queryctrl = ov7670_queryctrl, | |
1433 | .reset = ov7670_reset, | |
1434 | .init = ov7670_init, | |
b794aabf HV |
1435 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1436 | .g_register = ov7670_g_register, | |
1437 | .s_register = ov7670_s_register, | |
1438 | #endif | |
14386c2b | 1439 | }; |
111f3356 | 1440 | |
14386c2b HV |
1441 | static const struct v4l2_subdev_video_ops ov7670_video_ops = { |
1442 | .enum_fmt = ov7670_enum_fmt, | |
1443 | .try_fmt = ov7670_try_fmt, | |
1444 | .s_fmt = ov7670_s_fmt, | |
1445 | .s_parm = ov7670_s_parm, | |
1446 | .g_parm = ov7670_g_parm, | |
1447 | }; | |
111f3356 | 1448 | |
14386c2b HV |
1449 | static const struct v4l2_subdev_ops ov7670_ops = { |
1450 | .core = &ov7670_core_ops, | |
1451 | .video = &ov7670_video_ops, | |
1452 | }; | |
111f3356 | 1453 | |
14386c2b | 1454 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1455 | |
14386c2b HV |
1456 | static int ov7670_probe(struct i2c_client *client, |
1457 | const struct i2c_device_id *id) | |
111f3356 | 1458 | { |
14386c2b | 1459 | struct v4l2_subdev *sd; |
f9a76156 | 1460 | struct ov7670_info *info; |
14386c2b | 1461 | int ret; |
111f3356 | 1462 | |
14386c2b HV |
1463 | info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL); |
1464 | if (info == NULL) | |
111f3356 | 1465 | return -ENOMEM; |
14386c2b HV |
1466 | sd = &info->sd; |
1467 | v4l2_i2c_subdev_init(sd, client, &ov7670_ops); | |
1468 | ||
1469 | /* Make sure it's an ov7670 */ | |
1470 | ret = ov7670_detect(sd); | |
1471 | if (ret) { | |
1472 | v4l_dbg(1, debug, client, | |
1473 | "chip found @ 0x%x (%s) is not an ov7670 chip.\n", | |
1474 | client->addr << 1, client->adapter->name); | |
1475 | kfree(info); | |
1476 | return ret; | |
f9a76156 | 1477 | } |
14386c2b HV |
1478 | v4l_info(client, "chip found @ 0x%02x (%s)\n", |
1479 | client->addr << 1, client->adapter->name); | |
1480 | ||
f9a76156 JC |
1481 | info->fmt = &ov7670_formats[0]; |
1482 | info->sat = 128; /* Review this */ | |
d8d20155 | 1483 | info->clkrc = 1; /* 30fps */ |
111f3356 | 1484 | |
111f3356 | 1485 | return 0; |
111f3356 JC |
1486 | } |
1487 | ||
1488 | ||
14386c2b | 1489 | static int ov7670_remove(struct i2c_client *client) |
111f3356 | 1490 | { |
14386c2b | 1491 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
111f3356 | 1492 | |
14386c2b HV |
1493 | v4l2_device_unregister_subdev(sd); |
1494 | kfree(to_state(sd)); | |
1495 | return 0; | |
111f3356 JC |
1496 | } |
1497 | ||
14386c2b HV |
1498 | static const struct i2c_device_id ov7670_id[] = { |
1499 | { "ov7670", 0 }, | |
1500 | { } | |
1501 | }; | |
1502 | MODULE_DEVICE_TABLE(i2c, ov7670_id); | |
1503 | ||
1504 | static struct v4l2_i2c_driver_data v4l2_i2c_data = { | |
1505 | .name = "ov7670", | |
14386c2b HV |
1506 | .probe = ov7670_probe, |
1507 | .remove = ov7670_remove, | |
14386c2b | 1508 | .id_table = ov7670_id, |
111f3356 | 1509 | }; |