Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/rtc_from4.c | |
3 | * | |
4 | * Copyright (C) 2004 Red Hat, Inc. | |
61b03bd7 | 5 | * |
1da177e4 LT |
6 | * Derived from drivers/mtd/nand/spia.c |
7 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) | |
8 | * | |
61b03bd7 | 9 | * $Id: rtc_from4.c,v 1.10 2005/11/07 11:14:31 gleixner Exp $ |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * Overview: | |
16 | * This is a device driver for the AG-AND flash device found on the | |
61b03bd7 TG |
17 | * Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4), |
18 | * which utilizes the Renesas HN29V1G91T-30 part. | |
1da177e4 LT |
19 | * This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device. |
20 | */ | |
21 | ||
22 | #include <linux/delay.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/rslib.h> | |
1605cd3d | 27 | #include <linux/bitrev.h> |
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/mtd/compatmac.h> | |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | #include <asm/io.h> | |
34 | ||
35 | /* | |
36 | * MTD structure for Renesas board | |
37 | */ | |
38 | static struct mtd_info *rtc_from4_mtd = NULL; | |
39 | ||
40 | #define RTC_FROM4_MAX_CHIPS 2 | |
41 | ||
42 | /* HS77x9 processor register defines */ | |
43 | #define SH77X9_BCR1 ((volatile unsigned short *)(0xFFFFFF60)) | |
44 | #define SH77X9_BCR2 ((volatile unsigned short *)(0xFFFFFF62)) | |
45 | #define SH77X9_WCR1 ((volatile unsigned short *)(0xFFFFFF64)) | |
46 | #define SH77X9_WCR2 ((volatile unsigned short *)(0xFFFFFF66)) | |
47 | #define SH77X9_MCR ((volatile unsigned short *)(0xFFFFFF68)) | |
48 | #define SH77X9_PCR ((volatile unsigned short *)(0xFFFFFF6C)) | |
49 | #define SH77X9_FRQCR ((volatile unsigned short *)(0xFFFFFF80)) | |
50 | ||
51 | /* | |
52 | * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor) | |
53 | */ | |
54 | /* Address where flash is mapped */ | |
55 | #define RTC_FROM4_FIO_BASE 0x14000000 | |
56 | ||
57 | /* CLE and ALE are tied to address lines 5 & 4, respectively */ | |
58 | #define RTC_FROM4_CLE (1 << 5) | |
59 | #define RTC_FROM4_ALE (1 << 4) | |
60 | ||
61 | /* address lines A24-A22 used for chip selection */ | |
62 | #define RTC_FROM4_NAND_ADDR_SLOT3 (0x00800000) | |
63 | #define RTC_FROM4_NAND_ADDR_SLOT4 (0x00C00000) | |
64 | #define RTC_FROM4_NAND_ADDR_FPGA (0x01000000) | |
65 | /* mask address lines A24-A22 used for chip selection */ | |
66 | #define RTC_FROM4_NAND_ADDR_MASK (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA) | |
67 | ||
68 | /* FPGA status register for checking device ready (bit zero) */ | |
69 | #define RTC_FROM4_FPGA_SR (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002) | |
70 | #define RTC_FROM4_DEVICE_READY 0x0001 | |
71 | ||
72 | /* FPGA Reed-Solomon ECC Control register */ | |
73 | ||
74 | #define RTC_FROM4_RS_ECC_CTL (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050) | |
75 | #define RTC_FROM4_RS_ECC_CTL_CLR (1 << 7) | |
76 | #define RTC_FROM4_RS_ECC_CTL_GEN (1 << 6) | |
77 | #define RTC_FROM4_RS_ECC_CTL_FD_E (1 << 5) | |
78 | ||
79 | /* FPGA Reed-Solomon ECC code base */ | |
80 | #define RTC_FROM4_RS_ECC (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060) | |
81 | #define RTC_FROM4_RS_ECCN (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080) | |
82 | ||
83 | /* FPGA Reed-Solomon ECC check register */ | |
84 | #define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070) | |
85 | #define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7) | |
86 | ||
ed3786a5 DM |
87 | #define ERR_STAT_ECC_AVAILABLE 0x20 |
88 | ||
1da177e4 LT |
89 | /* Undefine for software ECC */ |
90 | #define RTC_FROM4_HWECC 1 | |
91 | ||
ed3786a5 DM |
92 | /* Define as 1 for no virtual erase blocks (in JFFS2) */ |
93 | #define RTC_FROM4_NO_VIRTBLOCKS 0 | |
94 | ||
1da177e4 LT |
95 | /* |
96 | * Module stuff | |
97 | */ | |
97f1a087 | 98 | static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE); |
1da177e4 | 99 | |
3c6bee1d | 100 | static const struct mtd_partition partition_info[] = { |
e0c7d767 DW |
101 | { |
102 | .name = "Renesas flash partition 1", | |
103 | .offset = 0, | |
104 | .size = MTDPART_SIZ_FULL}, | |
1da177e4 | 105 | }; |
e0c7d767 | 106 | |
1da177e4 LT |
107 | #define NUM_PARTITIONS 1 |
108 | ||
61b03bd7 | 109 | /* |
1da177e4 | 110 | * hardware specific flash bbt decriptors |
61b03bd7 | 111 | * Note: this is to allow debugging by disabling |
1da177e4 LT |
112 | * NAND_BBT_CREATE and/or NAND_BBT_WRITE |
113 | * | |
114 | */ | |
e0c7d767 DW |
115 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; |
116 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1da177e4 LT |
117 | |
118 | static struct nand_bbt_descr rtc_from4_bbt_main_descr = { | |
119 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
120 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
121 | .offs = 40, | |
122 | .len = 4, | |
123 | .veroffs = 44, | |
124 | .maxblocks = 4, | |
125 | .pattern = bbt_pattern | |
126 | }; | |
127 | ||
128 | static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = { | |
129 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
130 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
131 | .offs = 40, | |
132 | .len = 4, | |
133 | .veroffs = 44, | |
134 | .maxblocks = 4, | |
135 | .pattern = mirror_pattern | |
136 | }; | |
137 | ||
1da177e4 LT |
138 | #ifdef RTC_FROM4_HWECC |
139 | ||
140 | /* the Reed Solomon control structure */ | |
141 | static struct rs_control *rs_decoder; | |
142 | ||
61b03bd7 | 143 | /* |
1da177e4 LT |
144 | * hardware specific Out Of Band information |
145 | */ | |
5bd34c09 | 146 | static struct nand_ecclayout rtc_from4_nand_oobinfo = { |
1da177e4 LT |
147 | .eccbytes = 32, |
148 | .eccpos = { | |
e0c7d767 DW |
149 | 0, 1, 2, 3, 4, 5, 6, 7, |
150 | 8, 9, 10, 11, 12, 13, 14, 15, | |
151 | 16, 17, 18, 19, 20, 21, 22, 23, | |
152 | 24, 25, 26, 27, 28, 29, 30, 31}, | |
153 | .oobfree = {{32, 32}} | |
1da177e4 LT |
154 | }; |
155 | ||
1da177e4 LT |
156 | #endif |
157 | ||
61b03bd7 | 158 | /* |
1da177e4 LT |
159 | * rtc_from4_hwcontrol - hardware specific access to control-lines |
160 | * @mtd: MTD device structure | |
161 | * @cmd: hardware control command | |
162 | * | |
61b03bd7 | 163 | * Address lines (A5 and A4) are used to control Command and Address Latch |
1da177e4 LT |
164 | * Enable on this board, so set the read/write address appropriately. |
165 | * | |
61b03bd7 | 166 | * Chip Enable is also controlled by the Chip Select (CS5) and |
1da177e4 LT |
167 | * Address lines (A24-A22), so no action is required here. |
168 | * | |
169 | */ | |
7abd3ef9 TG |
170 | static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd, |
171 | unsigned int ctrl) | |
1da177e4 | 172 | { |
7abd3ef9 | 173 | struct nand_chip *chip = (mtd->priv); |
61b03bd7 | 174 | |
7abd3ef9 TG |
175 | if (cmd == NAND_CMD_NONE) |
176 | return; | |
61b03bd7 | 177 | |
7abd3ef9 TG |
178 | if (ctrl & NAND_CLE) |
179 | writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE); | |
180 | else | |
181 | writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE); | |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 LT |
184 | /* |
185 | * rtc_from4_nand_select_chip - hardware specific chip select | |
186 | * @mtd: MTD device structure | |
187 | * @chip: Chip to select (0 == slot 3, 1 == slot 4) | |
188 | * | |
189 | * The chip select is based on address lines A24-A22. | |
190 | * This driver uses flash slots 3 and 4 (A23-A22). | |
191 | * | |
192 | */ | |
193 | static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip) | |
194 | { | |
e0c7d767 | 195 | struct nand_chip *this = mtd->priv; |
1da177e4 LT |
196 | |
197 | this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK); | |
198 | this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK); | |
199 | ||
e0c7d767 | 200 | switch (chip) { |
1da177e4 | 201 | |
e0c7d767 | 202 | case 0: /* select slot 3 chip */ |
1da177e4 LT |
203 | this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3); |
204 | this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3); | |
e0c7d767 DW |
205 | break; |
206 | case 1: /* select slot 4 chip */ | |
1da177e4 LT |
207 | this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4); |
208 | this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4); | |
e0c7d767 | 209 | break; |
1da177e4 | 210 | |
e0c7d767 | 211 | } |
1da177e4 LT |
212 | } |
213 | ||
1da177e4 LT |
214 | /* |
215 | * rtc_from4_nand_device_ready - hardware specific ready/busy check | |
216 | * @mtd: MTD device structure | |
217 | * | |
218 | * This board provides the Ready/Busy state in the status register | |
219 | * of the FPGA. Bit zero indicates the RDY(1)/BSY(0) signal. | |
220 | * | |
221 | */ | |
222 | static int rtc_from4_nand_device_ready(struct mtd_info *mtd) | |
223 | { | |
224 | unsigned short status; | |
225 | ||
226 | status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR)); | |
227 | ||
228 | return (status & RTC_FROM4_DEVICE_READY); | |
229 | ||
230 | } | |
231 | ||
97f1a087 DM |
232 | /* |
233 | * deplete - code to perform device recovery in case there was a power loss | |
234 | * @mtd: MTD device structure | |
235 | * @chip: Chip to select (0 == slot 3, 1 == slot 4) | |
236 | * | |
61b03bd7 | 237 | * If there was a sudden loss of power during an erase operation, a |
97f1a087 DM |
238 | * "device recovery" operation must be performed when power is restored |
239 | * to ensure correct operation. This routine performs the required steps | |
240 | * for the requested chip. | |
241 | * | |
242 | * See page 86 of the data sheet for details. | |
243 | * | |
244 | */ | |
245 | static void deplete(struct mtd_info *mtd, int chip) | |
246 | { | |
e0c7d767 | 247 | struct nand_chip *this = mtd->priv; |
97f1a087 | 248 | |
e0c7d767 DW |
249 | /* wait until device is ready */ |
250 | while (!this->dev_ready(mtd)) ; | |
97f1a087 DM |
251 | |
252 | this->select_chip(mtd, chip); | |
61b03bd7 | 253 | |
97f1a087 | 254 | /* Send the commands for device recovery, phase 1 */ |
e0c7d767 DW |
255 | this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000); |
256 | this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1); | |
97f1a087 DM |
257 | |
258 | /* Send the commands for device recovery, phase 2 */ | |
e0c7d767 DW |
259 | this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004); |
260 | this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1); | |
97f1a087 DM |
261 | |
262 | } | |
263 | ||
1da177e4 LT |
264 | #ifdef RTC_FROM4_HWECC |
265 | /* | |
266 | * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function | |
267 | * @mtd: MTD device structure | |
268 | * @mode: I/O mode; read or write | |
269 | * | |
61b03bd7 | 270 | * enable hardware ECC for data read or write |
1da177e4 LT |
271 | * |
272 | */ | |
273 | static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode) | |
274 | { | |
e0c7d767 | 275 | volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL); |
1da177e4 LT |
276 | unsigned short status; |
277 | ||
278 | switch (mode) { | |
e0c7d767 DW |
279 | case NAND_ECC_READ: |
280 | status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E; | |
1da177e4 LT |
281 | |
282 | *rs_ecc_ctl = status; | |
283 | break; | |
284 | ||
e0c7d767 DW |
285 | case NAND_ECC_READSYN: |
286 | status = 0x00; | |
1da177e4 LT |
287 | |
288 | *rs_ecc_ctl = status; | |
289 | break; | |
290 | ||
e0c7d767 DW |
291 | case NAND_ECC_WRITE: |
292 | status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_GEN | RTC_FROM4_RS_ECC_CTL_FD_E; | |
1da177e4 LT |
293 | |
294 | *rs_ecc_ctl = status; | |
295 | break; | |
296 | ||
e0c7d767 | 297 | default: |
1da177e4 LT |
298 | BUG(); |
299 | break; | |
300 | } | |
301 | ||
302 | } | |
303 | ||
304 | /* | |
305 | * rtc_from4_calculate_ecc - hardware specific code to read ECC code | |
306 | * @mtd: MTD device structure | |
307 | * @dat: buffer containing the data to generate ECC codes | |
308 | * @ecc_code ECC codes calculated | |
309 | * | |
310 | * The ECC code is calculated by the FPGA. All we have to do is read the values | |
311 | * from the FPGA registers. | |
312 | * | |
313 | * Note: We read from the inverted registers, since data is inverted before | |
314 | * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code | |
315 | * | |
316 | */ | |
317 | static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) | |
318 | { | |
e0c7d767 | 319 | volatile unsigned short *rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN); |
1da177e4 LT |
320 | unsigned short value; |
321 | int i; | |
322 | ||
323 | for (i = 0; i < 8; i++) { | |
324 | value = *rs_eccn; | |
325 | ecc_code[i] = (unsigned char)value; | |
326 | rs_eccn++; | |
327 | } | |
328 | ecc_code[7] |= 0x0f; /* set the last four bits (not used) */ | |
329 | } | |
330 | ||
331 | /* | |
332 | * rtc_from4_correct_data - hardware specific code to correct data using ECC code | |
333 | * @mtd: MTD device structure | |
334 | * @buf: buffer containing the data to generate ECC codes | |
335 | * @ecc1 ECC codes read | |
336 | * @ecc2 ECC codes calculated | |
337 | * | |
338 | * The FPGA tells us fast, if there's an error or not. If no, we go back happy | |
339 | * else we read the ecc results from the fpga and call the rs library to decode | |
ed3786a5 | 340 | * and hopefully correct the error. |
1da177e4 | 341 | * |
1da177e4 LT |
342 | */ |
343 | static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2) | |
344 | { | |
345 | int i, j, res; | |
61b03bd7 | 346 | unsigned short status; |
97f1a087 | 347 | uint16_t par[6], syn[6]; |
1da177e4 | 348 | uint8_t ecc[8]; |
e0c7d767 | 349 | volatile unsigned short *rs_ecc; |
1da177e4 LT |
350 | |
351 | status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK)); | |
352 | ||
353 | if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) { | |
354 | return 0; | |
355 | } | |
356 | ||
357 | /* Read the syndrom pattern from the FPGA and correct the bitorder */ | |
358 | rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC); | |
e0c7d767 | 359 | for (i = 0; i < 8; i++) { |
ce106049 | 360 | ecc[i] = bitrev8(*rs_ecc); |
e0c7d767 DW |
361 | rs_ecc++; |
362 | } | |
1da177e4 LT |
363 | |
364 | /* convert into 6 10bit syndrome fields */ | |
e0c7d767 DW |
365 | par[5] = rs_decoder->index_of[(((uint16_t) ecc[0] >> 0) & 0x0ff) | (((uint16_t) ecc[1] << 8) & 0x300)]; |
366 | par[4] = rs_decoder->index_of[(((uint16_t) ecc[1] >> 2) & 0x03f) | (((uint16_t) ecc[2] << 6) & 0x3c0)]; | |
367 | par[3] = rs_decoder->index_of[(((uint16_t) ecc[2] >> 4) & 0x00f) | (((uint16_t) ecc[3] << 4) & 0x3f0)]; | |
368 | par[2] = rs_decoder->index_of[(((uint16_t) ecc[3] >> 6) & 0x003) | (((uint16_t) ecc[4] << 2) & 0x3fc)]; | |
369 | par[1] = rs_decoder->index_of[(((uint16_t) ecc[5] >> 0) & 0x0ff) | (((uint16_t) ecc[6] << 8) & 0x300)]; | |
370 | par[0] = (((uint16_t) ecc[6] >> 2) & 0x03f) | (((uint16_t) ecc[7] << 6) & 0x3c0); | |
1da177e4 LT |
371 | |
372 | /* Convert to computable syndrome */ | |
373 | for (i = 0; i < 6; i++) { | |
374 | syn[i] = par[0]; | |
375 | for (j = 1; j < 6; j++) | |
376 | if (par[j] != rs_decoder->nn) | |
377 | syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)]; | |
378 | ||
379 | /* Convert to index form */ | |
380 | syn[i] = rs_decoder->index_of[syn[i]]; | |
381 | } | |
382 | ||
e0c7d767 DW |
383 | /* Let the library code do its magic. */ |
384 | res = decode_rs8(rs_decoder, (uint8_t *) buf, par, 512, syn, 0, NULL, 0xff, NULL); | |
1da177e4 | 385 | if (res > 0) { |
e0c7d767 | 386 | DEBUG(MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " "ECC corrected %d errors on read\n", res); |
1da177e4 LT |
387 | } |
388 | return res; | |
389 | } | |
ed3786a5 | 390 | |
ed3786a5 DM |
391 | /** |
392 | * rtc_from4_errstat - perform additional error status checks | |
393 | * @mtd: MTD device structure | |
394 | * @this: NAND chip structure | |
395 | * @state: state or the operation | |
396 | * @status: status code returned from read status | |
397 | * @page: startpage inside the chip, must be called with (page & this->pagemask) | |
61b03bd7 TG |
398 | * |
399 | * Perform additional error status checks on erase and write failures | |
400 | * to determine if errors are correctable. For this device, correctable | |
ed3786a5 DM |
401 | * 1-bit errors on erase and write are considered acceptable. |
402 | * | |
403 | * note: see pages 34..37 of data sheet for details. | |
404 | * | |
405 | */ | |
f5bbdacc TG |
406 | static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this, |
407 | int state, int status, int page) | |
ed3786a5 | 408 | { |
e0c7d767 DW |
409 | int er_stat = 0; |
410 | int rtn, retlen; | |
411 | size_t len; | |
ed3786a5 | 412 | uint8_t *buf; |
e0c7d767 | 413 | int i; |
ed3786a5 | 414 | |
e0c7d767 | 415 | this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1); |
ed3786a5 | 416 | |
e0c7d767 | 417 | if (state == FL_ERASING) { |
f5bbdacc | 418 | |
e0c7d767 | 419 | for (i = 0; i < 4; i++) { |
f5bbdacc TG |
420 | if (!(status & 1 << (i + 1))) |
421 | continue; | |
422 | this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1), | |
423 | -1, -1); | |
424 | rtn = this->read_byte(mtd); | |
425 | this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1); | |
426 | ||
427 | /* err_ecc_not_avail */ | |
428 | if (!(rtn & ERR_STAT_ECC_AVAILABLE)) | |
429 | er_stat |= 1 << (i + 1); | |
ed3786a5 | 430 | } |
f5bbdacc | 431 | |
ed3786a5 | 432 | } else if (state == FL_WRITING) { |
f5bbdacc TG |
433 | |
434 | unsigned long corrected = mtd->ecc_stats.corrected; | |
435 | ||
ed3786a5 | 436 | /* single bank write logic */ |
e0c7d767 | 437 | this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1); |
ed3786a5 | 438 | rtn = this->read_byte(mtd); |
e0c7d767 | 439 | this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1); |
f5bbdacc | 440 | |
ed3786a5 | 441 | if (!(rtn & ERR_STAT_ECC_AVAILABLE)) { |
f5bbdacc TG |
442 | /* err_ecc_not_avail */ |
443 | er_stat |= 1 << 1; | |
444 | goto out; | |
ed3786a5 | 445 | } |
f5bbdacc TG |
446 | |
447 | len = mtd->writesize; | |
448 | buf = kmalloc(len, GFP_KERNEL); | |
449 | if (!buf) { | |
450 | printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n"); | |
451 | er_stat = 1; | |
452 | goto out; | |
453 | } | |
454 | ||
455 | /* recovery read */ | |
456 | rtn = nand_do_read(mtd, page, len, &retlen, buf); | |
457 | ||
458 | /* if read failed or > 1-bit error corrected */ | |
459 | if (rtn || (mtd->ecc_stats.corrected - corrected) > 1) { | |
460 | er_stat |= 1 << 1; | |
461 | kfree(buf); | |
ed3786a5 DM |
462 | } |
463 | ||
464 | rtn = status; | |
e0c7d767 | 465 | if (er_stat == 0) { /* if ECC is available */ |
ed3786a5 DM |
466 | rtn = (status & ~NAND_STATUS_FAIL); /* clear the error bit */ |
467 | } | |
468 | ||
469 | return rtn; | |
470 | } | |
1da177e4 LT |
471 | #endif |
472 | ||
473 | /* | |
474 | * Main initialization routine | |
475 | */ | |
cead4dbc | 476 | static int __init rtc_from4_init(void) |
1da177e4 LT |
477 | { |
478 | struct nand_chip *this; | |
479 | unsigned short bcr1, bcr2, wcr2; | |
97f1a087 | 480 | int i; |
1da177e4 LT |
481 | |
482 | /* Allocate memory for MTD device structure and private data */ | |
e0c7d767 | 483 | rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 | 484 | if (!rtc_from4_mtd) { |
e0c7d767 | 485 | printk("Unable to allocate Renesas NAND MTD device structure.\n"); |
1da177e4 LT |
486 | return -ENOMEM; |
487 | } | |
488 | ||
489 | /* Get pointer to private data */ | |
e0c7d767 | 490 | this = (struct nand_chip *)(&rtc_from4_mtd[1]); |
1da177e4 LT |
491 | |
492 | /* Initialize structures */ | |
e0c7d767 DW |
493 | memset(rtc_from4_mtd, 0, sizeof(struct mtd_info)); |
494 | memset(this, 0, sizeof(struct nand_chip)); | |
1da177e4 LT |
495 | |
496 | /* Link the private data with the MTD structure */ | |
497 | rtc_from4_mtd->priv = this; | |
552d9205 | 498 | rtc_from4_mtd->owner = THIS_MODULE; |
1da177e4 LT |
499 | |
500 | /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */ | |
501 | bcr1 = *SH77X9_BCR1 & ~0x0002; | |
502 | bcr1 |= 0x0002; | |
503 | *SH77X9_BCR1 = bcr1; | |
504 | ||
505 | /* set */ | |
506 | bcr2 = *SH77X9_BCR2 & ~0x0c00; | |
507 | bcr2 |= 0x0800; | |
508 | *SH77X9_BCR2 = bcr2; | |
509 | ||
510 | /* set area 5 wait states */ | |
511 | wcr2 = *SH77X9_WCR2 & ~0x1c00; | |
512 | wcr2 |= 0x1c00; | |
513 | *SH77X9_WCR2 = wcr2; | |
514 | ||
515 | /* Set address of NAND IO lines */ | |
516 | this->IO_ADDR_R = rtc_from4_fio_base; | |
517 | this->IO_ADDR_W = rtc_from4_fio_base; | |
518 | /* Set address of hardware control function */ | |
7abd3ef9 | 519 | this->cmd_ctrl = rtc_from4_hwcontrol; |
1da177e4 | 520 | /* Set address of chip select function */ |
e0c7d767 | 521 | this->select_chip = rtc_from4_nand_select_chip; |
1da177e4 LT |
522 | /* command delay time (in us) */ |
523 | this->chip_delay = 100; | |
524 | /* return the status of the Ready/Busy line */ | |
525 | this->dev_ready = rtc_from4_nand_device_ready; | |
526 | ||
527 | #ifdef RTC_FROM4_HWECC | |
528 | printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n"); | |
529 | ||
6dfc6d25 TG |
530 | this->ecc.mode = NAND_ECC_HW_SYNDROME; |
531 | this->ecc.size = 512; | |
532 | this->ecc.bytes = 8; | |
ed3786a5 DM |
533 | /* return the status of extra status and ECC checks */ |
534 | this->errstat = rtc_from4_errstat; | |
1da177e4 | 535 | /* set the nand_oobinfo to support FPGA H/W error detection */ |
5bd34c09 | 536 | this->ecc.layout = &rtc_from4_nand_oobinfo; |
6dfc6d25 TG |
537 | this->ecc.hwctl = rtc_from4_enable_hwecc; |
538 | this->ecc.calculate = rtc_from4_calculate_ecc; | |
539 | this->ecc.correct = rtc_from4_correct_data; | |
1da177e4 LT |
540 | #else |
541 | printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n"); | |
542 | ||
6dfc6d25 | 543 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
544 | #endif |
545 | ||
546 | /* set the bad block tables to support debugging */ | |
547 | this->bbt_td = &rtc_from4_bbt_main_descr; | |
548 | this->bbt_md = &rtc_from4_bbt_mirror_descr; | |
549 | ||
550 | /* Scan to find existence of the device */ | |
551 | if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) { | |
552 | kfree(rtc_from4_mtd); | |
553 | return -ENXIO; | |
554 | } | |
555 | ||
97f1a087 | 556 | /* Perform 'device recovery' for each chip in case there was a power loss. */ |
e0c7d767 | 557 | for (i = 0; i < this->numchips; i++) { |
97f1a087 DM |
558 | deplete(rtc_from4_mtd, i); |
559 | } | |
560 | ||
ed3786a5 DM |
561 | #if RTC_FROM4_NO_VIRTBLOCKS |
562 | /* use a smaller erase block to minimize wasted space when a block is bad */ | |
563 | /* note: this uses eight times as much RAM as using the default and makes */ | |
564 | /* mounts take four times as long. */ | |
565 | rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS; | |
566 | #endif | |
567 | ||
1da177e4 LT |
568 | /* Register the partitions */ |
569 | add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS); | |
570 | ||
571 | #ifdef RTC_FROM4_HWECC | |
572 | /* We could create the decoder on demand, if memory is a concern. | |
61b03bd7 | 573 | * This way we have it handy, if an error happens |
1da177e4 LT |
574 | * |
575 | * Symbolsize is 10 (bits) | |
576 | * Primitve polynomial is x^10+x^3+1 | |
577 | * first consecutive root is 0 | |
578 | * primitve element to generate roots = 1 | |
579 | * generator polinomial degree = 6 | |
580 | */ | |
581 | rs_decoder = init_rs(10, 0x409, 0, 1, 6); | |
582 | if (!rs_decoder) { | |
e0c7d767 | 583 | printk(KERN_ERR "Could not create a RS decoder\n"); |
1da177e4 LT |
584 | nand_release(rtc_from4_mtd); |
585 | kfree(rtc_from4_mtd); | |
586 | return -ENOMEM; | |
587 | } | |
588 | #endif | |
589 | /* Return happy */ | |
590 | return 0; | |
591 | } | |
1da177e4 | 592 | |
e0c7d767 | 593 | module_init(rtc_from4_init); |
1da177e4 LT |
594 | |
595 | /* | |
596 | * Clean up routine | |
597 | */ | |
e0c7d767 | 598 | static void __exit rtc_from4_cleanup(void) |
1da177e4 LT |
599 | { |
600 | /* Release resource, unregister partitions */ | |
601 | nand_release(rtc_from4_mtd); | |
602 | ||
603 | /* Free the MTD device structure */ | |
e0c7d767 | 604 | kfree(rtc_from4_mtd); |
1da177e4 LT |
605 | |
606 | #ifdef RTC_FROM4_HWECC | |
607 | /* Free the reed solomon resources */ | |
608 | if (rs_decoder) { | |
609 | free_rs(rs_decoder); | |
610 | } | |
611 | #endif | |
612 | } | |
e0c7d767 | 613 | |
1da177e4 | 614 | module_exit(rtc_from4_cleanup); |
1da177e4 LT |
615 | |
616 | MODULE_LICENSE("GPL"); | |
617 | MODULE_AUTHOR("d.marlin <dmarlin@redhat.com"); | |
618 | MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4"); |