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a6a53252 JY |
1 | /* |
2 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. | |
3 | * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com> | |
4 | * | |
5 | * Derived from Intel e1000 driver | |
6 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
23 | #ifndef _ATL1E_H_ | |
24 | #define _ATL1E_H_ | |
25 | ||
26 | #include <linux/version.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/types.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/etherdevice.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/sched.h> | |
40 | #include <linux/in.h> | |
41 | #include <linux/ip.h> | |
42 | #include <linux/ipv6.h> | |
43 | #include <linux/udp.h> | |
44 | #include <linux/mii.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/vmalloc.h> | |
47 | #include <linux/pagemap.h> | |
48 | #include <linux/tcp.h> | |
a6a53252 JY |
49 | #include <linux/ethtool.h> |
50 | #include <linux/if_vlan.h> | |
51 | #include <linux/workqueue.h> | |
52 | #include <net/checksum.h> | |
53 | #include <net/ip6_checksum.h> | |
54 | ||
55 | #include "atl1e_hw.h" | |
56 | ||
57 | #define PCI_REG_COMMAND 0x04 /* PCI Command Register */ | |
58 | #define CMD_IO_SPACE 0x0001 | |
59 | #define CMD_MEMORY_SPACE 0x0002 | |
60 | #define CMD_BUS_MASTER 0x0004 | |
61 | ||
62 | #define BAR_0 0 | |
63 | #define BAR_1 1 | |
64 | #define BAR_5 5 | |
65 | ||
66 | /* Wake Up Filter Control */ | |
67 | #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
68 | #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
69 | #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
70 | #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ | |
71 | #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
72 | ||
73 | #define SPEED_0 0xffff | |
74 | #define HALF_DUPLEX 1 | |
75 | #define FULL_DUPLEX 2 | |
76 | ||
77 | /* Error Codes */ | |
78 | #define AT_ERR_EEPROM 1 | |
79 | #define AT_ERR_PHY 2 | |
80 | #define AT_ERR_CONFIG 3 | |
81 | #define AT_ERR_PARAM 4 | |
82 | #define AT_ERR_MAC_TYPE 5 | |
83 | #define AT_ERR_PHY_TYPE 6 | |
84 | #define AT_ERR_PHY_SPEED 7 | |
85 | #define AT_ERR_PHY_RES 8 | |
86 | #define AT_ERR_TIMEOUT 9 | |
87 | ||
88 | #define MAX_JUMBO_FRAME_SIZE 0x2000 | |
89 | ||
90 | #define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd) \ | |
91 | _tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\ | |
92 | (((_vlan) >> 9) & 8)) | |
93 | ||
94 | #define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan) \ | |
95 | _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\ | |
96 | (((_tdp) & 0x88) << 5)) | |
97 | ||
98 | #define AT_MAX_RECEIVE_QUEUE 4 | |
99 | #define AT_PAGE_NUM_PER_QUEUE 2 | |
100 | ||
101 | #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL | |
102 | #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL | |
103 | ||
104 | #define AT_TX_WATCHDOG (5 * HZ) | |
105 | #define AT_MAX_INT_WORK 10 | |
106 | #define AT_TWSI_EEPROM_TIMEOUT 100 | |
107 | #define AT_HW_MAX_IDLE_DELAY 10 | |
108 | #define AT_SUSPEND_LINK_TIMEOUT 28 | |
109 | ||
110 | #define AT_REGS_LEN 75 | |
111 | #define AT_EEPROM_LEN 512 | |
112 | #define AT_ADV_MASK (ADVERTISE_10_HALF |\ | |
113 | ADVERTISE_10_FULL |\ | |
114 | ADVERTISE_100_HALF |\ | |
115 | ADVERTISE_100_FULL |\ | |
116 | ADVERTISE_1000_FULL) | |
117 | ||
118 | /* tpd word 2 */ | |
119 | #define TPD_BUFLEN_MASK 0x3FFF | |
120 | #define TPD_BUFLEN_SHIFT 0 | |
121 | #define TPD_DMAINT_MASK 0x0001 | |
122 | #define TPD_DMAINT_SHIFT 14 | |
123 | #define TPD_PKTNT_MASK 0x0001 | |
124 | #define TPD_PKTINT_SHIFT 15 | |
125 | #define TPD_VLANTAG_MASK 0xFFFF | |
126 | #define TPD_VLAN_SHIFT 16 | |
127 | ||
128 | /* tpd word 3 bits 0:4 */ | |
129 | #define TPD_EOP_MASK 0x0001 | |
130 | #define TPD_EOP_SHIFT 0 | |
131 | #define TPD_IP_VERSION_MASK 0x0001 | |
132 | #define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */ | |
133 | #define TPD_INS_VL_TAG_MASK 0x0001 | |
134 | #define TPD_INS_VL_TAG_SHIFT 2 | |
135 | #define TPD_CC_SEGMENT_EN_MASK 0x0001 | |
136 | #define TPD_CC_SEGMENT_EN_SHIFT 3 | |
137 | #define TPD_SEGMENT_EN_MASK 0x0001 | |
138 | #define TPD_SEGMENT_EN_SHIFT 4 | |
139 | ||
140 | /* tdp word 3 bits 5:7 if ip version is 0 */ | |
141 | #define TPD_IP_CSUM_MASK 0x0001 | |
142 | #define TPD_IP_CSUM_SHIFT 5 | |
143 | #define TPD_TCP_CSUM_MASK 0x0001 | |
144 | #define TPD_TCP_CSUM_SHIFT 6 | |
145 | #define TPD_UDP_CSUM_MASK 0x0001 | |
146 | #define TPD_UDP_CSUM_SHIFT 7 | |
147 | ||
148 | /* tdp word 3 bits 5:7 if ip version is 1 */ | |
149 | #define TPD_V6_IPHLLO_MASK 0x0007 | |
150 | #define TPD_V6_IPHLLO_SHIFT 7 | |
151 | ||
152 | /* tpd word 3 bits 8:9 bit */ | |
153 | #define TPD_VL_TAGGED_MASK 0x0001 | |
154 | #define TPD_VL_TAGGED_SHIFT 8 | |
155 | #define TPD_ETHTYPE_MASK 0x0001 | |
156 | #define TPD_ETHTYPE_SHIFT 9 | |
157 | ||
158 | /* tdp word 3 bits 10:13 if ip version is 0 */ | |
159 | #define TDP_V4_IPHL_MASK 0x000F | |
160 | #define TPD_V4_IPHL_SHIFT 10 | |
161 | ||
162 | /* tdp word 3 bits 10:13 if ip version is 1 */ | |
163 | #define TPD_V6_IPHLHI_MASK 0x000F | |
164 | #define TPD_V6_IPHLHI_SHIFT 10 | |
165 | ||
166 | /* tpd word 3 bit 14:31 if segment enabled */ | |
167 | #define TPD_TCPHDRLEN_MASK 0x000F | |
168 | #define TPD_TCPHDRLEN_SHIFT 14 | |
169 | #define TPD_HDRFLAG_MASK 0x0001 | |
170 | #define TPD_HDRFLAG_SHIFT 18 | |
171 | #define TPD_MSS_MASK 0x1FFF | |
172 | #define TPD_MSS_SHIFT 19 | |
173 | ||
174 | /* tdp word 3 bit 16:31 if custom csum enabled */ | |
175 | #define TPD_PLOADOFFSET_MASK 0x00FF | |
176 | #define TPD_PLOADOFFSET_SHIFT 16 | |
177 | #define TPD_CCSUMOFFSET_MASK 0x00FF | |
178 | #define TPD_CCSUMOFFSET_SHIFT 24 | |
179 | ||
180 | struct atl1e_tpd_desc { | |
181 | __le64 buffer_addr; | |
182 | __le32 word2; | |
183 | __le32 word3; | |
184 | }; | |
185 | ||
186 | /* how about 0x2000 */ | |
187 | #define MAX_TX_BUF_LEN 0x2000 | |
188 | #define MAX_TX_BUF_SHIFT 13 | |
189 | /*#define MAX_TX_BUF_LEN 0x3000 */ | |
190 | ||
191 | /* rrs word 1 bit 0:31 */ | |
192 | #define RRS_RX_CSUM_MASK 0xFFFF | |
193 | #define RRS_RX_CSUM_SHIFT 0 | |
194 | #define RRS_PKT_SIZE_MASK 0x3FFF | |
195 | #define RRS_PKT_SIZE_SHIFT 16 | |
196 | #define RRS_CPU_NUM_MASK 0x0003 | |
197 | #define RRS_CPU_NUM_SHIFT 30 | |
198 | ||
199 | #define RRS_IS_RSS_IPV4 0x0001 | |
200 | #define RRS_IS_RSS_IPV4_TCP 0x0002 | |
201 | #define RRS_IS_RSS_IPV6 0x0004 | |
202 | #define RRS_IS_RSS_IPV6_TCP 0x0008 | |
203 | #define RRS_IS_IPV6 0x0010 | |
204 | #define RRS_IS_IP_FRAG 0x0020 | |
205 | #define RRS_IS_IP_DF 0x0040 | |
206 | #define RRS_IS_802_3 0x0080 | |
207 | #define RRS_IS_VLAN_TAG 0x0100 | |
208 | #define RRS_IS_ERR_FRAME 0x0200 | |
209 | #define RRS_IS_IPV4 0x0400 | |
210 | #define RRS_IS_UDP 0x0800 | |
211 | #define RRS_IS_TCP 0x1000 | |
212 | #define RRS_IS_BCAST 0x2000 | |
213 | #define RRS_IS_MCAST 0x4000 | |
214 | #define RRS_IS_PAUSE 0x8000 | |
215 | ||
216 | #define RRS_ERR_BAD_CRC 0x0001 | |
217 | #define RRS_ERR_CODE 0x0002 | |
218 | #define RRS_ERR_DRIBBLE 0x0004 | |
219 | #define RRS_ERR_RUNT 0x0008 | |
220 | #define RRS_ERR_RX_OVERFLOW 0x0010 | |
221 | #define RRS_ERR_TRUNC 0x0020 | |
222 | #define RRS_ERR_IP_CSUM 0x0040 | |
223 | #define RRS_ERR_L4_CSUM 0x0080 | |
224 | #define RRS_ERR_LENGTH 0x0100 | |
225 | #define RRS_ERR_DES_ADDR 0x0200 | |
226 | ||
227 | struct atl1e_recv_ret_status { | |
228 | u16 seq_num; | |
229 | u16 hash_lo; | |
230 | __le32 word1; | |
231 | u16 pkt_flag; | |
232 | u16 err_flag; | |
233 | u16 hash_hi; | |
234 | u16 vtag; | |
235 | }; | |
236 | ||
237 | enum atl1e_dma_req_block { | |
238 | atl1e_dma_req_128 = 0, | |
239 | atl1e_dma_req_256 = 1, | |
240 | atl1e_dma_req_512 = 2, | |
241 | atl1e_dma_req_1024 = 3, | |
242 | atl1e_dma_req_2048 = 4, | |
243 | atl1e_dma_req_4096 = 5 | |
244 | }; | |
245 | ||
246 | enum atl1e_rrs_type { | |
247 | atl1e_rrs_disable = 0, | |
248 | atl1e_rrs_ipv4 = 1, | |
249 | atl1e_rrs_ipv4_tcp = 2, | |
250 | atl1e_rrs_ipv6 = 4, | |
251 | atl1e_rrs_ipv6_tcp = 8 | |
252 | }; | |
253 | ||
254 | enum atl1e_nic_type { | |
255 | athr_l1e = 0, | |
256 | athr_l2e_revA = 1, | |
257 | athr_l2e_revB = 2 | |
258 | }; | |
259 | ||
260 | struct atl1e_hw_stats { | |
261 | /* rx */ | |
262 | unsigned long rx_ok; /* The number of good packet received. */ | |
263 | unsigned long rx_bcast; /* The number of good broadcast packet received. */ | |
264 | unsigned long rx_mcast; /* The number of good multicast packet received. */ | |
265 | unsigned long rx_pause; /* The number of Pause packet received. */ | |
266 | unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ | |
267 | unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ | |
268 | unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ | |
269 | unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ | |
270 | unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ | |
271 | unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ | |
272 | unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ | |
273 | unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ | |
274 | unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ | |
275 | unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ | |
276 | unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ | |
277 | unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ | |
278 | unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ | |
279 | unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ | |
280 | unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ | |
281 | unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ | |
282 | unsigned long rx_align_err; /* Alignment Error */ | |
283 | unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ | |
284 | unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ | |
285 | unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ | |
286 | ||
287 | /* tx */ | |
288 | unsigned long tx_ok; /* The number of good packet transmitted. */ | |
289 | unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ | |
290 | unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ | |
291 | unsigned long tx_pause; /* The number of Pause packet transmitted. */ | |
292 | unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ | |
293 | unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ | |
294 | unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ | |
295 | unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ | |
296 | unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ | |
297 | unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ | |
298 | unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ | |
299 | unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ | |
300 | unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ | |
301 | unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ | |
302 | unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ | |
303 | unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ | |
304 | unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ | |
305 | unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ | |
306 | unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ | |
307 | unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ | |
308 | unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ | |
309 | unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ | |
310 | unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ | |
311 | unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ | |
312 | unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ | |
313 | }; | |
314 | ||
315 | struct atl1e_hw { | |
316 | u8 __iomem *hw_addr; /* inner register address */ | |
317 | resource_size_t mem_rang; | |
318 | struct atl1e_adapter *adapter; | |
319 | enum atl1e_nic_type nic_type; | |
320 | u16 device_id; | |
321 | u16 vendor_id; | |
322 | u16 subsystem_id; | |
323 | u16 subsystem_vendor_id; | |
324 | u8 revision_id; | |
325 | u16 pci_cmd_word; | |
326 | u8 mac_addr[ETH_ALEN]; | |
327 | u8 perm_mac_addr[ETH_ALEN]; | |
328 | u8 preamble_len; | |
329 | u16 max_frame_size; | |
330 | u16 rx_jumbo_th; | |
331 | u16 tx_jumbo_th; | |
332 | ||
333 | u16 media_type; | |
334 | #define MEDIA_TYPE_AUTO_SENSOR 0 | |
335 | #define MEDIA_TYPE_100M_FULL 1 | |
336 | #define MEDIA_TYPE_100M_HALF 2 | |
337 | #define MEDIA_TYPE_10M_FULL 3 | |
338 | #define MEDIA_TYPE_10M_HALF 4 | |
339 | ||
340 | u16 autoneg_advertised; | |
341 | #define ADVERTISE_10_HALF 0x0001 | |
342 | #define ADVERTISE_10_FULL 0x0002 | |
343 | #define ADVERTISE_100_HALF 0x0004 | |
344 | #define ADVERTISE_100_FULL 0x0008 | |
345 | #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | |
346 | #define ADVERTISE_1000_FULL 0x0020 | |
347 | u16 mii_autoneg_adv_reg; | |
348 | u16 mii_1000t_ctrl_reg; | |
349 | ||
350 | u16 imt; /* Interrupt Moderator timer ( 2us resolution) */ | |
351 | u16 ict; /* Interrupt Clear timer (2us resolution) */ | |
352 | u32 smb_timer; | |
353 | u16 rrd_thresh; /* Threshold of number of RRD produced to trigger | |
354 | interrupt request */ | |
355 | u16 tpd_thresh; | |
356 | u16 rx_count_down; /* 2us resolution */ | |
357 | u16 tx_count_down; | |
358 | ||
359 | u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ | |
360 | enum atl1e_rrs_type rrs_type; | |
361 | u32 base_cpu; | |
362 | u32 indirect_tab; | |
363 | ||
364 | enum atl1e_dma_req_block dmar_block; | |
365 | enum atl1e_dma_req_block dmaw_block; | |
366 | u8 dmaw_dly_cnt; | |
367 | u8 dmar_dly_cnt; | |
368 | ||
369 | bool phy_configured; | |
370 | bool re_autoneg; | |
371 | bool emi_ca; | |
372 | }; | |
373 | ||
374 | /* | |
375 | * wrapper around a pointer to a socket buffer, | |
376 | * so a DMA handle can be stored along with the buffer | |
377 | */ | |
378 | struct atl1e_tx_buffer { | |
379 | struct sk_buff *skb; | |
380 | u16 length; | |
381 | dma_addr_t dma; | |
382 | }; | |
383 | ||
384 | struct atl1e_rx_page { | |
385 | dma_addr_t dma; /* receive rage DMA address */ | |
386 | u8 *addr; /* receive rage virtual address */ | |
387 | dma_addr_t write_offset_dma; /* the DMA address which contain the | |
388 | receive data offset in the page */ | |
389 | u32 *write_offset_addr; /* the virtaul address which contain | |
390 | the receive data offset in the page */ | |
391 | u32 read_offset; /* the offset where we have read */ | |
392 | }; | |
393 | ||
394 | struct atl1e_rx_page_desc { | |
395 | struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE]; | |
396 | u8 rx_using; | |
397 | u16 rx_nxseq; | |
398 | }; | |
399 | ||
400 | /* transmit packet descriptor (tpd) ring */ | |
401 | struct atl1e_tx_ring { | |
402 | struct atl1e_tpd_desc *desc; /* descriptor ring virtual address */ | |
403 | dma_addr_t dma; /* descriptor ring physical address */ | |
404 | u16 count; /* the count of transmit rings */ | |
405 | rwlock_t tx_lock; | |
406 | u16 next_to_use; | |
407 | atomic_t next_to_clean; | |
408 | struct atl1e_tx_buffer *tx_buffer; | |
409 | dma_addr_t cmb_dma; | |
410 | u32 *cmb; | |
411 | }; | |
412 | ||
413 | /* receive packet descriptor ring */ | |
414 | struct atl1e_rx_ring { | |
415 | void *desc; | |
416 | dma_addr_t dma; | |
417 | int size; | |
418 | u32 page_size; /* bytes length of rxf page */ | |
419 | u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */ | |
420 | struct atl1e_rx_page_desc rx_page_desc[AT_MAX_RECEIVE_QUEUE]; | |
421 | }; | |
422 | ||
423 | /* board specific private data structure */ | |
424 | struct atl1e_adapter { | |
425 | struct net_device *netdev; | |
426 | struct pci_dev *pdev; | |
427 | struct vlan_group *vlgrp; | |
428 | struct napi_struct napi; | |
429 | struct mii_if_info mii; /* MII interface info */ | |
430 | struct atl1e_hw hw; | |
431 | struct atl1e_hw_stats hw_stats; | |
432 | struct net_device_stats net_stats; | |
433 | ||
434 | bool have_msi; | |
435 | u32 wol; | |
436 | u16 link_speed; | |
437 | u16 link_duplex; | |
438 | ||
439 | spinlock_t mdio_lock; | |
440 | spinlock_t tx_lock; | |
441 | atomic_t irq_sem; | |
442 | ||
443 | struct work_struct reset_task; | |
444 | struct work_struct link_chg_task; | |
445 | struct timer_list watchdog_timer; | |
446 | struct timer_list phy_config_timer; | |
447 | ||
448 | /* All Descriptor memory */ | |
449 | dma_addr_t ring_dma; | |
450 | void *ring_vir_addr; | |
451 | int ring_size; | |
452 | ||
453 | struct atl1e_tx_ring tx_ring; | |
454 | struct atl1e_rx_ring rx_ring; | |
455 | int num_rx_queues; | |
456 | unsigned long flags; | |
457 | #define __AT_TESTING 0x0001 | |
458 | #define __AT_RESETTING 0x0002 | |
459 | #define __AT_DOWN 0x0003 | |
460 | ||
461 | u32 bd_number; /* board number;*/ | |
462 | u32 pci_state[16]; | |
463 | u32 *config_space; | |
464 | }; | |
465 | ||
466 | #define AT_WRITE_REG(a, reg, value) ( \ | |
467 | writel((value), ((a)->hw_addr + reg))) | |
468 | ||
469 | #define AT_WRITE_FLUSH(a) (\ | |
470 | readl((a)->hw_addr)) | |
471 | ||
472 | #define AT_READ_REG(a, reg) ( \ | |
473 | readl((a)->hw_addr + reg)) | |
474 | ||
475 | #define AT_WRITE_REGB(a, reg, value) (\ | |
476 | writeb((value), ((a)->hw_addr + reg))) | |
477 | ||
478 | #define AT_READ_REGB(a, reg) (\ | |
479 | readb((a)->hw_addr + reg)) | |
480 | ||
481 | #define AT_WRITE_REGW(a, reg, value) (\ | |
482 | writew((value), ((a)->hw_addr + reg))) | |
483 | ||
484 | #define AT_READ_REGW(a, reg) (\ | |
485 | readw((a)->hw_addr + reg)) | |
486 | ||
487 | #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ | |
488 | writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) | |
489 | ||
490 | #define AT_READ_REG_ARRAY(a, reg, offset) ( \ | |
491 | readl(((a)->hw_addr + reg) + ((offset) << 2))) | |
492 | ||
493 | extern char atl1e_driver_name[]; | |
494 | extern char atl1e_driver_version[]; | |
495 | ||
496 | extern void atl1e_check_options(struct atl1e_adapter *adapter); | |
497 | extern int atl1e_up(struct atl1e_adapter *adapter); | |
498 | extern void atl1e_down(struct atl1e_adapter *adapter); | |
499 | extern void atl1e_reinit_locked(struct atl1e_adapter *adapter); | |
500 | extern s32 atl1e_reset_hw(struct atl1e_hw *hw); | |
501 | extern void atl1e_set_ethtool_ops(struct net_device *netdev); | |
502 | #endif /* _ATL1_E_H_ */ |