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a2fbb9ea ET |
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
523224a3 DK |
9 | #ifndef BNX2X_HSI_H |
10 | #define BNX2X_HSI_H | |
11 | ||
12 | #include "bnx2x_fw_defs.h" | |
a2fbb9ea | 13 | |
619c5cb6 | 14 | #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e |
2ba45142 | 15 | |
e2513065 MC |
16 | struct license_key { |
17 | u32 reserved[6]; | |
18 | ||
2ba45142 VZ |
19 | u32 max_iscsi_conn; |
20 | #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF | |
21 | #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 | |
22 | #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 | |
23 | #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 | |
e2513065 | 24 | |
2ba45142 | 25 | u32 reserved_a; |
e2513065 | 26 | |
2ba45142 VZ |
27 | u32 max_fcoe_conn; |
28 | #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF | |
29 | #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 | |
30 | #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 | |
31 | #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 | |
32 | ||
33 | u32 reserved_b[4]; | |
34 | }; | |
a2fbb9ea | 35 | |
619c5cb6 VZ |
36 | |
37 | #define PORT_0 0 | |
38 | #define PORT_1 1 | |
39 | #define PORT_MAX 2 | |
a2fbb9ea ET |
40 | |
41 | /**************************************************************************** | |
619c5cb6 | 42 | * Shared HW configuration * |
a2fbb9ea | 43 | ****************************************************************************/ |
619c5cb6 VZ |
44 | #define PIN_CFG_NA 0x00000000 |
45 | #define PIN_CFG_GPIO0_P0 0x00000001 | |
46 | #define PIN_CFG_GPIO1_P0 0x00000002 | |
47 | #define PIN_CFG_GPIO2_P0 0x00000003 | |
48 | #define PIN_CFG_GPIO3_P0 0x00000004 | |
49 | #define PIN_CFG_GPIO0_P1 0x00000005 | |
50 | #define PIN_CFG_GPIO1_P1 0x00000006 | |
51 | #define PIN_CFG_GPIO2_P1 0x00000007 | |
52 | #define PIN_CFG_GPIO3_P1 0x00000008 | |
53 | #define PIN_CFG_EPIO0 0x00000009 | |
54 | #define PIN_CFG_EPIO1 0x0000000a | |
55 | #define PIN_CFG_EPIO2 0x0000000b | |
56 | #define PIN_CFG_EPIO3 0x0000000c | |
57 | #define PIN_CFG_EPIO4 0x0000000d | |
58 | #define PIN_CFG_EPIO5 0x0000000e | |
59 | #define PIN_CFG_EPIO6 0x0000000f | |
60 | #define PIN_CFG_EPIO7 0x00000010 | |
61 | #define PIN_CFG_EPIO8 0x00000011 | |
62 | #define PIN_CFG_EPIO9 0x00000012 | |
63 | #define PIN_CFG_EPIO10 0x00000013 | |
64 | #define PIN_CFG_EPIO11 0x00000014 | |
65 | #define PIN_CFG_EPIO12 0x00000015 | |
66 | #define PIN_CFG_EPIO13 0x00000016 | |
67 | #define PIN_CFG_EPIO14 0x00000017 | |
68 | #define PIN_CFG_EPIO15 0x00000018 | |
69 | #define PIN_CFG_EPIO16 0x00000019 | |
70 | #define PIN_CFG_EPIO17 0x0000001a | |
71 | #define PIN_CFG_EPIO18 0x0000001b | |
72 | #define PIN_CFG_EPIO19 0x0000001c | |
73 | #define PIN_CFG_EPIO20 0x0000001d | |
74 | #define PIN_CFG_EPIO21 0x0000001e | |
75 | #define PIN_CFG_EPIO22 0x0000001f | |
76 | #define PIN_CFG_EPIO23 0x00000020 | |
77 | #define PIN_CFG_EPIO24 0x00000021 | |
78 | #define PIN_CFG_EPIO25 0x00000022 | |
79 | #define PIN_CFG_EPIO26 0x00000023 | |
80 | #define PIN_CFG_EPIO27 0x00000024 | |
81 | #define PIN_CFG_EPIO28 0x00000025 | |
82 | #define PIN_CFG_EPIO29 0x00000026 | |
83 | #define PIN_CFG_EPIO30 0x00000027 | |
84 | #define PIN_CFG_EPIO31 0x00000028 | |
85 | ||
86 | /* EPIO definition */ | |
87 | #define EPIO_CFG_NA 0x00000000 | |
88 | #define EPIO_CFG_EPIO0 0x00000001 | |
89 | #define EPIO_CFG_EPIO1 0x00000002 | |
90 | #define EPIO_CFG_EPIO2 0x00000003 | |
91 | #define EPIO_CFG_EPIO3 0x00000004 | |
92 | #define EPIO_CFG_EPIO4 0x00000005 | |
93 | #define EPIO_CFG_EPIO5 0x00000006 | |
94 | #define EPIO_CFG_EPIO6 0x00000007 | |
95 | #define EPIO_CFG_EPIO7 0x00000008 | |
96 | #define EPIO_CFG_EPIO8 0x00000009 | |
97 | #define EPIO_CFG_EPIO9 0x0000000a | |
98 | #define EPIO_CFG_EPIO10 0x0000000b | |
99 | #define EPIO_CFG_EPIO11 0x0000000c | |
100 | #define EPIO_CFG_EPIO12 0x0000000d | |
101 | #define EPIO_CFG_EPIO13 0x0000000e | |
102 | #define EPIO_CFG_EPIO14 0x0000000f | |
103 | #define EPIO_CFG_EPIO15 0x00000010 | |
104 | #define EPIO_CFG_EPIO16 0x00000011 | |
105 | #define EPIO_CFG_EPIO17 0x00000012 | |
106 | #define EPIO_CFG_EPIO18 0x00000013 | |
107 | #define EPIO_CFG_EPIO19 0x00000014 | |
108 | #define EPIO_CFG_EPIO20 0x00000015 | |
109 | #define EPIO_CFG_EPIO21 0x00000016 | |
110 | #define EPIO_CFG_EPIO22 0x00000017 | |
111 | #define EPIO_CFG_EPIO23 0x00000018 | |
112 | #define EPIO_CFG_EPIO24 0x00000019 | |
113 | #define EPIO_CFG_EPIO25 0x0000001a | |
114 | #define EPIO_CFG_EPIO26 0x0000001b | |
115 | #define EPIO_CFG_EPIO27 0x0000001c | |
116 | #define EPIO_CFG_EPIO28 0x0000001d | |
117 | #define EPIO_CFG_EPIO29 0x0000001e | |
118 | #define EPIO_CFG_EPIO30 0x0000001f | |
119 | #define EPIO_CFG_EPIO31 0x00000020 | |
120 | ||
121 | ||
122 | struct shared_hw_cfg { /* NVRAM Offset */ | |
a2fbb9ea | 123 | /* Up to 16 bytes of NULL-terminated string */ |
619c5cb6 VZ |
124 | u8 part_num[16]; /* 0x104 */ |
125 | ||
126 | u32 config; /* 0x114 */ | |
127 | #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 | |
128 | #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 | |
129 | #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 | |
130 | #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 | |
131 | #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 | |
a2fbb9ea | 132 | |
619c5cb6 | 133 | #define SHARED_HW_CFG_PORT_SWAP 0x00000004 |
a2fbb9ea | 134 | |
619c5cb6 | 135 | #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 |
a2fbb9ea | 136 | |
619c5cb6 VZ |
137 | #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 |
138 | #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 | |
a2fbb9ea | 139 | |
619c5cb6 VZ |
140 | #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 |
141 | #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 | |
a2fbb9ea ET |
142 | /* Whatever MFW found in NVM |
143 | (if multiple found, priority order is: NC-SI, UMP, IPMI) */ | |
619c5cb6 VZ |
144 | #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 |
145 | #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 | |
146 | #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 | |
147 | #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 | |
a2fbb9ea ET |
148 | /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI |
149 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 150 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 |
a2fbb9ea ET |
151 | /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI |
152 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 | 153 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 |
a2fbb9ea ET |
154 | /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP |
155 | (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ | |
619c5cb6 VZ |
156 | #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 |
157 | ||
158 | #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 | |
159 | #define SHARED_HW_CFG_LED_MODE_SHIFT 16 | |
160 | #define SHARED_HW_CFG_LED_MAC1 0x00000000 | |
161 | #define SHARED_HW_CFG_LED_PHY1 0x00010000 | |
162 | #define SHARED_HW_CFG_LED_PHY2 0x00020000 | |
163 | #define SHARED_HW_CFG_LED_PHY3 0x00030000 | |
164 | #define SHARED_HW_CFG_LED_MAC2 0x00040000 | |
165 | #define SHARED_HW_CFG_LED_PHY4 0x00050000 | |
166 | #define SHARED_HW_CFG_LED_PHY5 0x00060000 | |
167 | #define SHARED_HW_CFG_LED_PHY6 0x00070000 | |
168 | #define SHARED_HW_CFG_LED_MAC3 0x00080000 | |
169 | #define SHARED_HW_CFG_LED_PHY7 0x00090000 | |
170 | #define SHARED_HW_CFG_LED_PHY9 0x000a0000 | |
171 | #define SHARED_HW_CFG_LED_PHY11 0x000b0000 | |
172 | #define SHARED_HW_CFG_LED_MAC4 0x000c0000 | |
173 | #define SHARED_HW_CFG_LED_PHY8 0x000d0000 | |
174 | #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 | |
175 | ||
176 | ||
177 | #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 | |
178 | #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 | |
179 | #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 | |
180 | #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 | |
181 | #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 | |
182 | #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 | |
183 | #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 | |
184 | #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 | |
185 | ||
186 | #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 | |
187 | #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 | |
188 | #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 | |
189 | ||
190 | #define SHARED_HW_CFG_ATC_MASK 0x80000000 | |
191 | #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 | |
192 | #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 | |
193 | ||
194 | u32 config2; /* 0x118 */ | |
a2fbb9ea | 195 | /* one time auto detect grace period (in sec) */ |
619c5cb6 VZ |
196 | #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff |
197 | #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 | |
a2fbb9ea | 198 | |
619c5cb6 VZ |
199 | #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 |
200 | #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 | |
a2fbb9ea ET |
201 | |
202 | /* The default value for the core clock is 250MHz and it is | |
203 | achieved by setting the clock change to 4 */ | |
619c5cb6 VZ |
204 | #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 |
205 | #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 | |
a2fbb9ea | 206 | |
619c5cb6 VZ |
207 | #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 |
208 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | |
209 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | |
a2fbb9ea | 210 | |
619c5cb6 | 211 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
a2fbb9ea | 212 | |
619c5cb6 VZ |
213 | #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 |
214 | #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 | |
215 | #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 | |
216 | ||
217 | /* Output low when PERST is asserted */ | |
218 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 | |
219 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 | |
220 | #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 | |
a2fbb9ea | 221 | |
619c5cb6 VZ |
222 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 |
223 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 | |
224 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 | |
225 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 | |
226 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 | |
227 | #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 | |
228 | ||
229 | /* The fan failure mechanism is usually related to the PHY type | |
230 | since the power consumption of the board is determined by the PHY. | |
231 | Currently, fan is required for most designs with SFX7101, BCM8727 | |
232 | and BCM8481. If a fan is not required for a board which uses one | |
233 | of those PHYs, this field should be set to "Disabled". If a fan is | |
234 | required for a different PHY type, this option should be set to | |
235 | "Enabled". The fan failure indication is expected on SPIO5 */ | |
236 | #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 | |
237 | #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 | |
238 | #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 | |
239 | #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 | |
240 | #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 | |
241 | ||
242 | /* ASPM Power Management support */ | |
243 | #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 | |
244 | #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 | |
245 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 | |
246 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 | |
247 | #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 | |
248 | #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 | |
249 | ||
250 | /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register | |
251 | tl_control_0 (register 0x2800) */ | |
252 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 | |
253 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 | |
254 | #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 | |
255 | ||
256 | #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 | |
257 | #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 | |
258 | #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 | |
259 | ||
260 | #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 | |
261 | #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 | |
262 | #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 | |
263 | ||
264 | /* Set the MDC/MDIO access for the first external phy */ | |
265 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 | |
266 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 | |
267 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 | |
268 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 | |
269 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 | |
270 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 | |
271 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 | |
272 | ||
273 | /* Set the MDC/MDIO access for the second external phy */ | |
274 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 | |
275 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 | |
276 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 | |
277 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 | |
278 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 | |
279 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 | |
280 | #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 | |
281 | ||
282 | ||
283 | u32 power_dissipated; /* 0x11c */ | |
284 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 | |
285 | #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 | |
286 | #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 | |
287 | #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 | |
288 | #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 | |
289 | #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 | |
290 | ||
291 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | |
292 | #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 | |
293 | ||
294 | u32 ump_nc_si_config; /* 0x120 */ | |
295 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 | |
296 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 | |
297 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 | |
298 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 | |
299 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 | |
300 | #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 | |
301 | ||
302 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 | |
303 | #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 | |
304 | ||
305 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 | |
306 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 | |
307 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 | |
308 | #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 | |
309 | ||
310 | u32 board; /* 0x124 */ | |
311 | #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F | |
312 | #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 | |
313 | #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 | |
314 | #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 | |
315 | /* Use the PIN_CFG_XXX defines on top */ | |
316 | #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 | |
317 | #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 | |
318 | ||
319 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 | |
320 | #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 | |
321 | ||
322 | #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 | |
323 | #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 | |
324 | ||
325 | u32 wc_lane_config; /* 0x128 */ | |
326 | #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF | |
327 | #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
328 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b | |
329 | #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 | |
330 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b | |
331 | #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 | |
332 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF | |
333 | #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
334 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 | |
335 | #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
336 | ||
337 | /* TX lane Polarity swap */ | |
338 | #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 | |
339 | #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 | |
340 | #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 | |
341 | #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 | |
342 | /* TX lane Polarity swap */ | |
343 | #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 | |
344 | #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 | |
345 | #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 | |
346 | #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 | |
347 | ||
348 | /* Selects the port layout of the board */ | |
349 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 | |
350 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 | |
351 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 | |
352 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 | |
353 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 | |
354 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 | |
355 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 | |
356 | #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 | |
a2fbb9ea ET |
357 | }; |
358 | ||
f1410647 | 359 | |
a2fbb9ea | 360 | /**************************************************************************** |
619c5cb6 | 361 | * Port HW configuration * |
a2fbb9ea | 362 | ****************************************************************************/ |
619c5cb6 | 363 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
a2fbb9ea | 364 | |
a2fbb9ea | 365 | u32 pci_id; |
619c5cb6 VZ |
366 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 |
367 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
368 | |
369 | u32 pci_sub_id; | |
619c5cb6 VZ |
370 | #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 |
371 | #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff | |
a2fbb9ea ET |
372 | |
373 | u32 power_dissipated; | |
619c5cb6 VZ |
374 | #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff |
375 | #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 | |
376 | #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 | |
377 | #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 | |
378 | #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 | |
379 | #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 | |
380 | #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 | |
381 | #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 | |
a2fbb9ea ET |
382 | |
383 | u32 power_consumed; | |
619c5cb6 VZ |
384 | #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff |
385 | #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 | |
386 | #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 | |
387 | #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 | |
388 | #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 | |
389 | #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 | |
390 | #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 | |
391 | #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 | |
a2fbb9ea ET |
392 | |
393 | u32 mac_upper; | |
619c5cb6 VZ |
394 | #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff |
395 | #define PORT_HW_CFG_UPPERMAC_SHIFT 0 | |
a2fbb9ea ET |
396 | u32 mac_lower; |
397 | ||
398 | u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ | |
399 | u32 iscsi_mac_lower; | |
400 | ||
401 | u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ | |
402 | u32 rdma_mac_lower; | |
403 | ||
404 | u32 serdes_config; | |
619c5cb6 VZ |
405 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff |
406 | #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 | |
407 | ||
408 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 | |
409 | #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 | |
410 | ||
411 | ||
412 | /* Default values: 2P-64, 4P-32 */ | |
413 | u32 pf_config; /* 0x158 */ | |
414 | #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F | |
415 | #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 | |
416 | ||
417 | /* Default values: 17 */ | |
418 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 | |
419 | #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 | |
420 | ||
421 | #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 | |
422 | #define PORT_HW_CFG_FLR_ENABLED 0x00010000 | |
423 | ||
424 | u32 vf_config; /* 0x15C */ | |
425 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F | |
426 | #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 | |
427 | ||
428 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 | |
429 | #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 | |
430 | ||
431 | u32 mf_pci_id; /* 0x160 */ | |
432 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF | |
433 | #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 | |
434 | ||
435 | /* Controls the TX laser of the SFP+ module */ | |
436 | u32 sfp_ctrl; /* 0x164 */ | |
437 | #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF | |
438 | #define PORT_HW_CFG_TX_LASER_SHIFT 0 | |
439 | #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 | |
440 | #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 | |
441 | #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 | |
442 | #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 | |
443 | #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 | |
444 | ||
445 | /* Controls the fault module LED of the SFP+ */ | |
446 | #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 | |
447 | #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 | |
448 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 | |
449 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 | |
450 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 | |
451 | #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 | |
452 | #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 | |
453 | ||
454 | /* The output pin TX_DIS that controls the TX laser of the SFP+ | |
455 | module. Use the PIN_CFG_XXX defines on top */ | |
456 | u32 e3_sfp_ctrl; /* 0x168 */ | |
457 | #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF | |
458 | #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 | |
459 | ||
460 | /* The output pin for SFPP_TYPE which turns on the Fault module LED */ | |
461 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 | |
462 | #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 | |
463 | ||
464 | /* The input pin MOD_ABS that indicates whether SFP+ module is | |
465 | present or not. Use the PIN_CFG_XXX defines on top */ | |
466 | #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 | |
467 | #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 | |
468 | ||
469 | /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ | |
470 | module. Use the PIN_CFG_XXX defines on top */ | |
471 | #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 | |
472 | #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 | |
473 | ||
474 | /* | |
475 | * The input pin which signals module transmit fault. Use the | |
476 | * PIN_CFG_XXX defines on top | |
477 | */ | |
478 | u32 e3_cmn_pin_cfg; /* 0x16C */ | |
479 | #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF | |
480 | #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 | |
481 | ||
482 | /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on | |
483 | top */ | |
484 | #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 | |
485 | #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 | |
486 | ||
487 | /* | |
488 | * The output pin which powers down the PHY. Use the PIN_CFG_XXX | |
489 | * defines on top | |
490 | */ | |
491 | #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 | |
492 | #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 | |
493 | ||
494 | /* The output pin values BSC_SEL which selects the I2C for this port | |
495 | in the I2C Mux */ | |
496 | #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 | |
497 | #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 | |
498 | ||
a8db5b4c YR |
499 | |
500 | /* | |
619c5cb6 VZ |
501 | * The input pin I_FAULT which indicate over-current has occurred. |
502 | * Use the PIN_CFG_XXX defines on top | |
a8db5b4c | 503 | */ |
619c5cb6 VZ |
504 | u32 e3_cmn_pin_cfg1; /* 0x170 */ |
505 | #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF | |
506 | #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 | |
507 | u32 reserved0[7]; /* 0x174 */ | |
508 | ||
509 | u32 aeu_int_mask; /* 0x190 */ | |
510 | ||
511 | u32 media_type; /* 0x194 */ | |
512 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF | |
513 | #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 | |
514 | ||
515 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 | |
516 | #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 | |
517 | ||
518 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 | |
519 | #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 | |
520 | ||
521 | /* 4 times 16 bits for all 4 lanes. In case external PHY is present | |
522 | (not direct mode), those values will not take effect on the 4 XGXS | |
523 | lanes. For some external PHYs (such as 8706 and 8726) the values | |
524 | will be used to configure the external PHY in those cases, not | |
525 | all 4 values are needed. */ | |
526 | u16 xgxs_config_rx[4]; /* 0x198 */ | |
527 | u16 xgxs_config_tx[4]; /* 0x1A0 */ | |
528 | ||
529 | /* For storing FCOE mac on shared memory */ | |
530 | u32 fcoe_fip_mac_upper; | |
531 | #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff | |
532 | #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 | |
533 | u32 fcoe_fip_mac_lower; | |
534 | ||
535 | u32 fcoe_wwn_port_name_upper; | |
536 | u32 fcoe_wwn_port_name_lower; | |
537 | ||
538 | u32 fcoe_wwn_node_name_upper; | |
539 | u32 fcoe_wwn_node_name_lower; | |
540 | ||
541 | u32 Reserved1[50]; /* 0x1C0 */ | |
542 | ||
543 | u32 default_cfg; /* 0x288 */ | |
544 | #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 | |
545 | #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 | |
546 | #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 | |
547 | #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 | |
548 | #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 | |
549 | #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 | |
550 | ||
551 | #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C | |
552 | #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 | |
553 | #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 | |
554 | #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 | |
555 | #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 | |
556 | #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c | |
557 | ||
558 | #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 | |
559 | #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 | |
560 | #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 | |
561 | #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 | |
562 | #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 | |
563 | #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 | |
564 | ||
565 | #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 | |
566 | #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 | |
567 | #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 | |
568 | #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 | |
569 | #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 | |
570 | #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 | |
571 | ||
572 | /* When KR link is required to be set to force which is not | |
573 | KR-compliant, this parameter determine what is the trigger for it. | |
574 | When GPIO is selected, low input will force the speed. Currently | |
575 | default speed is 1G. In the future, it may be widen to select the | |
576 | forced speed in with another parameter. Note when force-1G is | |
577 | enabled, it override option 56: Link Speed option. */ | |
578 | #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 | |
579 | #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 | |
580 | #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 | |
581 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 | |
582 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 | |
583 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 | |
584 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 | |
585 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 | |
586 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 | |
587 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 | |
588 | #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 | |
589 | #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 | |
590 | /* Enable to determine with which GPIO to reset the external phy */ | |
591 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 | |
592 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 | |
593 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 | |
594 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 | |
595 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 | |
596 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 | |
597 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 | |
598 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 | |
599 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 | |
600 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 | |
601 | #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 | |
602 | ||
121839be | 603 | /* Enable BAM on KR */ |
619c5cb6 VZ |
604 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 |
605 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 | |
606 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 | |
607 | #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 | |
121839be | 608 | |
1bef68e3 | 609 | /* Enable Common Mode Sense */ |
619c5cb6 VZ |
610 | #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 |
611 | #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 | |
612 | #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 | |
613 | #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 | |
614 | ||
615 | /* Enable RJ45 magjack pair swapping on 10GBase-T PHY, 84833 only */ | |
616 | #define PORT_HW_CFG_RJ45_PR_SWP_MASK 0x00400000 | |
617 | #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT 22 | |
618 | #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED 0x00000000 | |
619 | #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED 0x00400000 | |
620 | ||
621 | /* Determine the Serdes electrical interface */ | |
622 | #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 | |
623 | #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 | |
624 | #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 | |
625 | #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 | |
626 | #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 | |
627 | #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 | |
628 | #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 | |
629 | #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 | |
630 | ||
1bef68e3 | 631 | |
a22f0788 | 632 | u32 speed_capability_mask2; /* 0x28C */ |
619c5cb6 VZ |
633 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF |
634 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 | |
635 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 | |
636 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 | |
637 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 | |
638 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 | |
639 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 | |
640 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 | |
641 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 | |
642 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 | |
643 | ||
644 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 | |
645 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 | |
646 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 | |
647 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 | |
648 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 | |
649 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 | |
650 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 | |
651 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 | |
652 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 | |
653 | #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 | |
654 | ||
655 | ||
656 | /* In the case where two media types (e.g. copper and fiber) are | |
657 | present and electrically active at the same time, PHY Selection | |
658 | will determine which of the two PHYs will be designated as the | |
659 | Active PHY and used for a connection to the network. */ | |
660 | u32 multi_phy_config; /* 0x290 */ | |
661 | #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 | |
662 | #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 | |
663 | #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 | |
664 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 | |
665 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 | |
666 | #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 | |
667 | #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 | |
668 | ||
669 | /* When enabled, all second phy nvram parameters will be swapped | |
670 | with the first phy parameters */ | |
671 | #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 | |
672 | #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 | |
673 | #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 | |
674 | #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 | |
675 | ||
676 | ||
677 | /* Address of the second external phy */ | |
678 | u32 external_phy_config2; /* 0x294 */ | |
679 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF | |
680 | #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 | |
681 | ||
682 | /* The second XGXS external PHY type */ | |
683 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 | |
684 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 | |
685 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 | |
686 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 | |
687 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 | |
688 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 | |
689 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 | |
690 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 | |
691 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 | |
692 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 | |
693 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 | |
694 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 | |
695 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 | |
696 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 | |
697 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 | |
698 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 | |
699 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00000e00 | |
700 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 | |
701 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 | |
702 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 | |
703 | ||
704 | ||
705 | /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as | |
706 | 8706, 8726 and 8727) not all 4 values are needed. */ | |
707 | u16 xgxs_config2_rx[4]; /* 0x296 */ | |
708 | u16 xgxs_config2_tx[4]; /* 0x2A0 */ | |
a2fbb9ea ET |
709 | |
710 | u32 lane_config; | |
619c5cb6 VZ |
711 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff |
712 | #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 | |
713 | /* AN and forced */ | |
714 | #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b | |
715 | /* forced only */ | |
716 | #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 | |
717 | /* forced only */ | |
718 | #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 | |
719 | /* forced only */ | |
720 | #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 | |
721 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff | |
722 | #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 | |
723 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 | |
724 | #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 | |
725 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 | |
726 | #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 | |
727 | ||
728 | /* Indicate whether to swap the external phy polarity */ | |
729 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 | |
730 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 | |
731 | #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 | |
732 | ||
a2fbb9ea ET |
733 | |
734 | u32 external_phy_config; | |
619c5cb6 VZ |
735 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff |
736 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 | |
737 | ||
738 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 | |
739 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 | |
740 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 | |
741 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 | |
742 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 | |
743 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 | |
744 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 | |
745 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | |
746 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 | |
747 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 | |
748 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 | |
749 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 | |
750 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | |
751 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | |
752 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 | |
753 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 | |
754 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00000e00 | |
755 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 | |
756 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 | |
757 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | |
758 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | |
759 | ||
760 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 | |
761 | #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 | |
762 | ||
763 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 | |
764 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 | |
765 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 | |
766 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 | |
767 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 | |
768 | #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 | |
a2fbb9ea ET |
769 | |
770 | u32 speed_capability_mask; | |
619c5cb6 VZ |
771 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff |
772 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 | |
773 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 | |
774 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 | |
775 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 | |
776 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 | |
777 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 | |
778 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 | |
779 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 | |
780 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 | |
781 | #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 | |
782 | ||
783 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 | |
784 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 | |
785 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 | |
786 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 | |
787 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 | |
788 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 | |
789 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 | |
790 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 | |
791 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 | |
792 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 | |
793 | #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 | |
794 | ||
795 | /* A place to hold the original MAC address as a backup */ | |
796 | u32 backup_mac_upper; /* 0x2B4 */ | |
797 | u32 backup_mac_lower; /* 0x2B8 */ | |
a2fbb9ea ET |
798 | |
799 | }; | |
800 | ||
f1410647 | 801 | |
a2fbb9ea | 802 | /**************************************************************************** |
619c5cb6 | 803 | * Shared Feature configuration * |
a2fbb9ea | 804 | ****************************************************************************/ |
619c5cb6 VZ |
805 | struct shared_feat_cfg { /* NVRAM Offset */ |
806 | ||
807 | u32 config; /* 0x450 */ | |
808 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 | |
809 | ||
810 | /* Use NVRAM values instead of HW default values */ | |
811 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ | |
812 | 0x00000002 | |
813 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ | |
814 | 0x00000000 | |
815 | #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ | |
816 | 0x00000002 | |
817 | ||
818 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 | |
819 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 | |
820 | #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 | |
f1410647 | 821 | |
619c5cb6 VZ |
822 | #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 |
823 | #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 | |
589abe3a | 824 | |
619c5cb6 VZ |
825 | /* Override the OTP back to single function mode. When using GPIO, |
826 | high means only SF, 0 is according to CLP configuration */ | |
827 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 | |
828 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 | |
829 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 | |
830 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 | |
831 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 | |
832 | #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 | |
589abe3a | 833 | |
619c5cb6 VZ |
834 | /* The interval in seconds between sending LLDP packets. Set to zero |
835 | to disable the feature */ | |
836 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 | |
837 | #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 | |
838 | ||
839 | /* The assigned device type ID for LLDP usage */ | |
840 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 | |
841 | #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 | |
a2fbb9ea ET |
842 | |
843 | }; | |
844 | ||
845 | ||
846 | /**************************************************************************** | |
619c5cb6 | 847 | * Port Feature configuration * |
a2fbb9ea | 848 | ****************************************************************************/ |
619c5cb6 | 849 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
f1410647 | 850 | |
a2fbb9ea | 851 | u32 config; |
619c5cb6 VZ |
852 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f |
853 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | |
854 | #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 | |
855 | #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 | |
856 | #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 | |
857 | #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 | |
858 | #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 | |
859 | #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 | |
860 | #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 | |
861 | #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 | |
862 | #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 | |
863 | #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 | |
864 | #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a | |
865 | #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b | |
866 | #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c | |
867 | #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d | |
868 | #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e | |
869 | #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f | |
870 | #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 | |
871 | #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 | |
872 | #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 | |
873 | #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 | |
874 | #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 | |
875 | #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 | |
876 | #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 | |
877 | #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 | |
878 | #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 | |
879 | #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 | |
880 | #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 | |
881 | #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 | |
882 | #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 | |
883 | #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 | |
884 | #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 | |
885 | #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 | |
886 | #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 | |
887 | #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 | |
888 | ||
889 | #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 | |
890 | #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 | |
891 | #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 | |
892 | ||
893 | #define PORT_FEAT_CFG_AUTOGREEN_MASK 0x00000200 | |
894 | #define PORT_FEAT_CFG_AUTOGREEN_SHIFT 9 | |
895 | #define PORT_FEAT_CFG_AUTOGREEN_DISABLED 0x00000000 | |
896 | #define PORT_FEAT_CFG_AUTOGREEN_ENABLED 0x00000200 | |
897 | ||
898 | #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 | |
899 | #define PORT_FEATURE_EN_SIZE_SHIFT 24 | |
900 | #define PORT_FEATURE_WOL_ENABLED 0x01000000 | |
901 | #define PORT_FEATURE_MBA_ENABLED 0x02000000 | |
902 | #define PORT_FEATURE_MFW_ENABLED 0x04000000 | |
903 | ||
904 | /* Advertise expansion ROM even if MBA is disabled */ | |
905 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 | |
906 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 | |
907 | #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 | |
908 | ||
909 | /* Check the optic vendor via i2c against a list of approved modules | |
910 | in a separate nvram image */ | |
911 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 | |
912 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 | |
913 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ | |
914 | 0x00000000 | |
915 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ | |
916 | 0x20000000 | |
917 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 | |
918 | #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 | |
589abe3a | 919 | |
a2fbb9ea ET |
920 | u32 wol_config; |
921 | /* Default is used when driver sets to "auto" mode */ | |
619c5cb6 VZ |
922 | #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 |
923 | #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 | |
924 | #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 | |
925 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 | |
926 | #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 | |
927 | #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 | |
928 | #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 | |
929 | #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 | |
930 | #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 | |
a2fbb9ea ET |
931 | |
932 | u32 mba_config; | |
619c5cb6 VZ |
933 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 |
934 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 | |
935 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 | |
936 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 | |
937 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 | |
938 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 | |
939 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 | |
940 | #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 | |
941 | ||
942 | #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 | |
943 | #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 | |
944 | ||
945 | #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 | |
946 | #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 | |
947 | #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 | |
948 | #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 | |
949 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 | |
950 | #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 | |
951 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 | |
952 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 | |
953 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 | |
954 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 | |
955 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 | |
956 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 | |
957 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 | |
958 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 | |
959 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 | |
960 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 | |
961 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 | |
962 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 | |
963 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 | |
964 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 | |
965 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 | |
966 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 | |
967 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 | |
968 | #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 | |
969 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 | |
970 | #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 | |
971 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 | |
972 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 | |
973 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 | |
974 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 | |
975 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 | |
976 | #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 | |
977 | #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 | |
978 | #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 | |
979 | #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 | |
980 | #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 | |
981 | #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 | |
982 | #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 | |
983 | #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 | |
984 | #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 | |
985 | #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 | |
986 | #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 | |
987 | #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 | |
a2fbb9ea | 988 | u32 bmc_config; |
619c5cb6 VZ |
989 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 |
990 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 | |
991 | #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 | |
a2fbb9ea ET |
992 | |
993 | u32 mba_vlan_cfg; | |
619c5cb6 VZ |
994 | #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff |
995 | #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 | |
996 | #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 | |
a2fbb9ea ET |
997 | |
998 | u32 resource_cfg; | |
619c5cb6 VZ |
999 | #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 |
1000 | #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 | |
1001 | #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 | |
1002 | #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 | |
1003 | #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 | |
a2fbb9ea ET |
1004 | |
1005 | u32 smbus_config; | |
619c5cb6 VZ |
1006 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
1007 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | |
1008 | ||
1009 | u32 vf_config; | |
1010 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f | |
1011 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 | |
1012 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 | |
1013 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 | |
1014 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 | |
1015 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 | |
1016 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 | |
1017 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 | |
1018 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 | |
1019 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 | |
1020 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 | |
1021 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 | |
1022 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a | |
1023 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b | |
1024 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c | |
1025 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d | |
1026 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e | |
1027 | #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f | |
a2fbb9ea ET |
1028 | |
1029 | u32 link_config; /* Used as HW defaults for the driver */ | |
619c5cb6 VZ |
1030 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
1031 | #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 | |
1032 | /* (forced) low speed switch (< 10G) */ | |
1033 | #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 | |
1034 | /* (forced) high speed switch (>= 10G) */ | |
1035 | #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 | |
1036 | #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 | |
1037 | #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 | |
1038 | ||
1039 | #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 | |
1040 | #define PORT_FEATURE_LINK_SPEED_SHIFT 16 | |
1041 | #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 | |
1042 | #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 | |
1043 | #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 | |
1044 | #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 | |
1045 | #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 | |
1046 | #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 | |
1047 | #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 | |
1048 | #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 | |
1049 | #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 | |
1050 | ||
1051 | #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 | |
1052 | #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 | |
1053 | #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 | |
1054 | #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 | |
1055 | #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 | |
1056 | #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 | |
1057 | #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 | |
a2fbb9ea ET |
1058 | |
1059 | /* The default for MCP link configuration, | |
619c5cb6 | 1060 | uses the same defines as link_config */ |
a2fbb9ea | 1061 | u32 mfw_wol_link_cfg; |
619c5cb6 | 1062 | |
a22f0788 | 1063 | /* The default for the driver of the second external phy, |
619c5cb6 VZ |
1064 | uses the same defines as link_config */ |
1065 | u32 link_config2; /* 0x47C */ | |
a2fbb9ea | 1066 | |
a22f0788 | 1067 | /* The default for MCP of the second external phy, |
619c5cb6 VZ |
1068 | uses the same defines as link_config */ |
1069 | u32 mfw_wol_link_cfg2; /* 0x480 */ | |
a22f0788 | 1070 | |
619c5cb6 | 1071 | u32 Reserved2[17]; /* 0x484 */ |
a2fbb9ea ET |
1072 | |
1073 | }; | |
1074 | ||
1075 | ||
34f80b04 | 1076 | /**************************************************************************** |
619c5cb6 | 1077 | * Device Information * |
34f80b04 | 1078 | ****************************************************************************/ |
619c5cb6 | 1079 | struct shm_dev_info { /* size */ |
f1410647 | 1080 | |
34f80b04 | 1081 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ |
f1410647 | 1082 | |
619c5cb6 | 1083 | struct shared_hw_cfg shared_hw_config; /* 40 */ |
f1410647 | 1084 | |
619c5cb6 | 1085 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ |
f1410647 | 1086 | |
619c5cb6 | 1087 | struct shared_feat_cfg shared_feature_config; /* 4 */ |
f1410647 | 1088 | |
619c5cb6 | 1089 | struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ |
f1410647 ET |
1090 | |
1091 | }; | |
1092 | ||
1093 | ||
619c5cb6 VZ |
1094 | #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) |
1095 | #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." | |
1096 | #endif | |
f1410647 | 1097 | |
619c5cb6 VZ |
1098 | #define FUNC_0 0 |
1099 | #define FUNC_1 1 | |
1100 | #define FUNC_2 2 | |
1101 | #define FUNC_3 3 | |
1102 | #define FUNC_4 4 | |
1103 | #define FUNC_5 5 | |
1104 | #define FUNC_6 6 | |
1105 | #define FUNC_7 7 | |
1106 | #define E1_FUNC_MAX 2 | |
1107 | #define E1H_FUNC_MAX 8 | |
1108 | #define E2_FUNC_MAX 4 /* per path */ | |
1109 | ||
1110 | #define VN_0 0 | |
1111 | #define VN_1 1 | |
1112 | #define VN_2 2 | |
1113 | #define VN_3 3 | |
1114 | #define E1VN_MAX 1 | |
1115 | #define E1HVN_MAX 4 | |
1116 | ||
1117 | #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ | |
f1410647 ET |
1118 | /* This value (in milliseconds) determines the frequency of the driver |
1119 | * issuing the PULSE message code. The firmware monitors this periodic | |
1120 | * pulse to determine when to switch to an OS-absent mode. */ | |
619c5cb6 | 1121 | #define DRV_PULSE_PERIOD_MS 250 |
f1410647 ET |
1122 | |
1123 | /* This value (in milliseconds) determines how long the driver should | |
1124 | * wait for an acknowledgement from the firmware before timing out. Once | |
1125 | * the firmware has timed out, the driver will assume there is no firmware | |
1126 | * running and there won't be any firmware-driver synchronization during a | |
1127 | * driver reset. */ | |
619c5cb6 | 1128 | #define FW_ACK_TIME_OUT_MS 5000 |
f1410647 | 1129 | |
619c5cb6 | 1130 | #define FW_ACK_POLL_TIME_MS 1 |
f1410647 | 1131 | |
619c5cb6 | 1132 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) |
f1410647 ET |
1133 | |
1134 | /* LED Blink rate that will achieve ~15.9Hz */ | |
619c5cb6 | 1135 | #define LED_BLINK_RATE_VAL 480 |
f1410647 | 1136 | |
a2fbb9ea | 1137 | /**************************************************************************** |
619c5cb6 | 1138 | * Driver <-> FW Mailbox * |
a2fbb9ea | 1139 | ****************************************************************************/ |
f1410647 | 1140 | struct drv_port_mb { |
a2fbb9ea | 1141 | |
f1410647 ET |
1142 | u32 link_status; |
1143 | /* Driver should update this field on any link change event */ | |
a2fbb9ea | 1144 | |
619c5cb6 VZ |
1145 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 |
1146 | #define LINK_STATUS_LINK_UP 0x00000001 | |
1147 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | |
1148 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | |
1149 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | |
1150 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | |
1151 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | |
1152 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | |
1153 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | |
1154 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | |
1155 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | |
1156 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | |
1157 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | |
1158 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | |
1159 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | |
1160 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | |
1161 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | |
1162 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) | |
1163 | #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) | |
1164 | ||
1165 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 | |
1166 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
1167 | ||
1168 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
1169 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | |
1170 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
1171 | ||
1172 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | |
1173 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
1174 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | |
1175 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | |
1176 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | |
1177 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | |
1178 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | |
1179 | ||
1180 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | |
1181 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | |
1182 | ||
1183 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | |
1184 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | |
1185 | ||
1186 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
1187 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | |
1188 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | |
1189 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | |
1190 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | |
1191 | ||
1192 | #define LINK_STATUS_SERDES_LINK 0x00100000 | |
1193 | ||
1194 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | |
1195 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | |
1196 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | |
1197 | #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 | |
f1410647 | 1198 | |
34f80b04 EG |
1199 | u32 port_stx; |
1200 | ||
de832a55 EG |
1201 | u32 stat_nig_timer; |
1202 | ||
a35da8db EG |
1203 | /* MCP firmware does not use this field */ |
1204 | u32 ext_phy_fw_version; | |
f1410647 ET |
1205 | |
1206 | }; | |
1207 | ||
1208 | ||
1209 | struct drv_func_mb { | |
1210 | ||
1211 | u32 drv_mb_header; | |
619c5cb6 VZ |
1212 | #define DRV_MSG_CODE_MASK 0xffff0000 |
1213 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
1214 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
1215 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | |
1216 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | |
1217 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | |
1218 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
1219 | #define DRV_MSG_CODE_DCC_OK 0x30000000 | |
1220 | #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 | |
1221 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | |
1222 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | |
1223 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | |
1224 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | |
1225 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | |
1226 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | |
1227 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | |
4d295db0 | 1228 | /* |
619c5cb6 VZ |
1229 | * The optic module verification command requires bootcode |
1230 | * v5.0.6 or later, te specific optic module verification command | |
1231 | * requires bootcode v5.2.12 or later | |
4d295db0 | 1232 | */ |
619c5cb6 VZ |
1233 | #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 |
1234 | #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 | |
1235 | #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 | |
1236 | #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 | |
1237 | ||
1238 | #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 | |
1239 | #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 | |
1240 | ||
1241 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | |
f1410647 | 1242 | |
619c5cb6 VZ |
1243 | #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 |
1244 | #define REQ_BC_VER_4_SET_MF_BW 0x00060202 | |
1245 | #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 | |
34f80b04 | 1246 | |
619c5cb6 VZ |
1247 | #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 |
1248 | ||
1249 | #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 | |
1250 | #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1251 | #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1252 | #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1253 | ||
1254 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1255 | |
1256 | u32 drv_mb_param; | |
619c5cb6 VZ |
1257 | #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 |
1258 | #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 | |
f1410647 ET |
1259 | |
1260 | u32 fw_mb_header; | |
619c5cb6 VZ |
1261 | #define FW_MSG_CODE_MASK 0xffff0000 |
1262 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | |
1263 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
1264 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
1265 | /* Load common chip is supported from bc 6.0.0 */ | |
1266 | #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 | |
1267 | #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 | |
1268 | ||
1269 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | |
1270 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
1271 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | |
1272 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | |
1273 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | |
1274 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
1275 | #define FW_MSG_CODE_DCC_DONE 0x30100000 | |
1276 | #define FW_MSG_CODE_LLDP_DONE 0x40100000 | |
1277 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 | |
1278 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | |
1279 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | |
1280 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | |
1281 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | |
1282 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | |
1283 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | |
1284 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | |
1285 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | |
1286 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | |
1287 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | |
1288 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | |
1289 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | |
1290 | #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 | |
1291 | #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 | |
1292 | #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 | |
1293 | #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 | |
1294 | ||
1295 | #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 | |
1296 | #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 | |
1297 | ||
1298 | #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 | |
1299 | ||
1300 | #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 | |
1301 | #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 | |
1302 | #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 | |
1303 | #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 | |
1304 | ||
1305 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
f1410647 ET |
1306 | |
1307 | u32 fw_mb_param; | |
1308 | ||
1309 | u32 drv_pulse_mb; | |
619c5cb6 VZ |
1310 | #define DRV_PULSE_SEQ_MASK 0x00007fff |
1311 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
1312 | /* | |
1313 | * The system time is in the format of | |
1314 | * (year-2001)*12*32 + month*32 + day. | |
1315 | */ | |
1316 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
1317 | /* | |
1318 | * Indicate to the firmware not to go into the | |
f1410647 | 1319 | * OS-absent when it is not getting driver pulse. |
619c5cb6 VZ |
1320 | * This is used for debugging as well for PXE(MBA). |
1321 | */ | |
f1410647 ET |
1322 | |
1323 | u32 mcp_pulse_mb; | |
619c5cb6 VZ |
1324 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
1325 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
f1410647 ET |
1326 | /* Indicates to the driver not to assert due to lack |
1327 | * of MCP response */ | |
619c5cb6 VZ |
1328 | #define MCP_EVENT_MASK 0xffff0000 |
1329 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
f1410647 ET |
1330 | |
1331 | u32 iscsi_boot_signature; | |
1332 | u32 iscsi_boot_block_offset; | |
1333 | ||
34f80b04 | 1334 | u32 drv_status; |
619c5cb6 VZ |
1335 | #define DRV_STATUS_PMF 0x00000001 |
1336 | #define DRV_STATUS_VF_DISABLED 0x00000002 | |
1337 | #define DRV_STATUS_SET_MF_BW 0x00000004 | |
1338 | #define DRV_STATUS_LINK_EVENT 0x00000008 | |
1339 | ||
1340 | #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 | |
1341 | #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 | |
1342 | #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 | |
1343 | #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 | |
1344 | #define DRV_STATUS_DCC_RESERVED1 0x00000800 | |
1345 | #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 | |
1346 | #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 | |
1347 | ||
1348 | #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 | |
1349 | #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 | |
2691d51d | 1350 | |
34f80b04 | 1351 | u32 virt_mac_upper; |
619c5cb6 VZ |
1352 | #define VIRT_MAC_SIGN_MASK 0xffff0000 |
1353 | #define VIRT_MAC_SIGNATURE 0x564d0000 | |
34f80b04 | 1354 | u32 virt_mac_lower; |
a2fbb9ea ET |
1355 | |
1356 | }; | |
1357 | ||
1358 | ||
1359 | /**************************************************************************** | |
619c5cb6 | 1360 | * Management firmware state * |
a2fbb9ea | 1361 | ****************************************************************************/ |
f1410647 | 1362 | /* Allocate 440 bytes for management firmware */ |
619c5cb6 | 1363 | #define MGMTFW_STATE_WORD_SIZE 110 |
a2fbb9ea ET |
1364 | |
1365 | struct mgmtfw_state { | |
1366 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | |
1367 | }; | |
1368 | ||
1369 | ||
34f80b04 | 1370 | /**************************************************************************** |
619c5cb6 | 1371 | * Multi-Function configuration * |
34f80b04 EG |
1372 | ****************************************************************************/ |
1373 | struct shared_mf_cfg { | |
1374 | ||
1375 | u32 clp_mb; | |
619c5cb6 | 1376 | #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 |
34f80b04 | 1377 | /* set by CLP */ |
619c5cb6 | 1378 | #define SHARED_MF_CLP_EXIT 0x00000001 |
34f80b04 | 1379 | /* set by MCP */ |
619c5cb6 | 1380 | #define SHARED_MF_CLP_EXIT_DONE 0x00010000 |
34f80b04 EG |
1381 | |
1382 | }; | |
1383 | ||
1384 | struct port_mf_cfg { | |
1385 | ||
619c5cb6 VZ |
1386 | u32 dynamic_cfg; /* device control channel */ |
1387 | #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff | |
1388 | #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1389 | #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 EG |
1390 | |
1391 | u32 reserved[3]; | |
1392 | ||
1393 | }; | |
1394 | ||
1395 | struct func_mf_cfg { | |
1396 | ||
1397 | u32 config; | |
1398 | /* E/R/I/D */ | |
1399 | /* function 0 of each port cannot be hidden */ | |
619c5cb6 | 1400 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 |
34f80b04 | 1401 | |
619c5cb6 VZ |
1402 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 |
1403 | #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 | |
1404 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 | |
1405 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 | |
1406 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 | |
1407 | #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ | |
1408 | FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA | |
34f80b04 | 1409 | |
619c5cb6 VZ |
1410 | #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 |
1411 | #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 | |
34f80b04 EG |
1412 | |
1413 | /* PRI */ | |
1414 | /* 0 - low priority, 3 - high priority */ | |
619c5cb6 VZ |
1415 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 |
1416 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 | |
1417 | #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 | |
34f80b04 EG |
1418 | |
1419 | /* MINBW, MAXBW */ | |
1420 | /* value range - 0..100, increments in 100Mbps */ | |
619c5cb6 VZ |
1421 | #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 |
1422 | #define FUNC_MF_CFG_MIN_BW_SHIFT 16 | |
1423 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
1424 | #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 | |
1425 | #define FUNC_MF_CFG_MAX_BW_SHIFT 24 | |
1426 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 | |
1427 | ||
1428 | u32 mac_upper; /* MAC */ | |
1429 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
1430 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
1431 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
34f80b04 | 1432 | u32 mac_lower; |
619c5cb6 | 1433 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff |
34f80b04 EG |
1434 | |
1435 | u32 e1hov_tag; /* VNI */ | |
619c5cb6 VZ |
1436 | #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff |
1437 | #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 | |
1438 | #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK | |
34f80b04 EG |
1439 | |
1440 | u32 reserved[2]; | |
34f80b04 EG |
1441 | }; |
1442 | ||
0793f83f DK |
1443 | /* This structure is not applicable and should not be accessed on 57711 */ |
1444 | struct func_ext_cfg { | |
1445 | u32 func_cfg; | |
619c5cb6 VZ |
1446 | #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF |
1447 | #define MACP_FUNC_CFG_FLAGS_SHIFT 0 | |
1448 | #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 | |
1449 | #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 | |
1450 | #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 | |
1451 | #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 | |
0793f83f DK |
1452 | |
1453 | u32 iscsi_mac_addr_upper; | |
1454 | u32 iscsi_mac_addr_lower; | |
1455 | ||
1456 | u32 fcoe_mac_addr_upper; | |
1457 | u32 fcoe_mac_addr_lower; | |
1458 | ||
1459 | u32 fcoe_wwn_port_name_upper; | |
1460 | u32 fcoe_wwn_port_name_lower; | |
1461 | ||
1462 | u32 fcoe_wwn_node_name_upper; | |
1463 | u32 fcoe_wwn_node_name_lower; | |
1464 | ||
1465 | u32 preserve_data; | |
619c5cb6 VZ |
1466 | #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) |
1467 | #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) | |
1468 | #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) | |
1469 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) | |
1470 | #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) | |
1471 | #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) | |
0793f83f DK |
1472 | }; |
1473 | ||
34f80b04 EG |
1474 | struct mf_cfg { |
1475 | ||
619c5cb6 VZ |
1476 | struct shared_mf_cfg shared_mf_config; /* 0x4 */ |
1477 | struct port_mf_cfg port_mf_config[PORT_MAX]; /* 0x10 * 2 = 0x20 */ | |
1478 | /* for all chips, there are 8 mf functions */ | |
1479 | struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ | |
1480 | /* | |
1481 | * Extended configuration per function - this array does not exist and | |
1482 | * should not be accessed on 57711 | |
1483 | */ | |
1484 | struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ | |
1485 | }; /* 0x224 */ | |
34f80b04 | 1486 | |
a2fbb9ea | 1487 | /**************************************************************************** |
619c5cb6 | 1488 | * Shared Memory Region * |
a2fbb9ea | 1489 | ****************************************************************************/ |
619c5cb6 | 1490 | struct shmem_region { /* SharedMem Offset (size) */ |
f1410647 | 1491 | |
619c5cb6 VZ |
1492 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ |
1493 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 | |
1494 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) | |
f1410647 | 1495 | /* validity bits */ |
619c5cb6 VZ |
1496 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 |
1497 | #define SHR_MEM_VALIDITY_MB 0x00200000 | |
1498 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | |
1499 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | |
a2fbb9ea | 1500 | /* One licensing bit should be set */ |
619c5cb6 VZ |
1501 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
1502 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | |
1503 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | |
1504 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | |
f1410647 | 1505 | /* Active MFW */ |
619c5cb6 VZ |
1506 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 |
1507 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | |
1508 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | |
1509 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | |
1510 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | |
1511 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | |
a2fbb9ea | 1512 | |
619c5cb6 | 1513 | struct shm_dev_info dev_info; /* 0x8 (0x438) */ |
a2fbb9ea | 1514 | |
619c5cb6 | 1515 | struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ |
a2fbb9ea ET |
1516 | |
1517 | /* FW information (for internal FW use) */ | |
619c5cb6 VZ |
1518 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
1519 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ | |
f1410647 | 1520 | |
619c5cb6 VZ |
1521 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ |
1522 | ||
1523 | #ifdef BMAPI | |
1524 | /* This is a variable length array */ | |
1525 | /* the number of function depends on the chip type */ | |
1526 | struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1527 | #else | |
1528 | /* the number of function depends on the chip type */ | |
1529 | struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ | |
1530 | #endif /* BMAPI */ | |
523224a3 DK |
1531 | |
1532 | }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ | |
34f80b04 | 1533 | |
619c5cb6 VZ |
1534 | /**************************************************************************** |
1535 | * Shared Memory 2 Region * | |
1536 | ****************************************************************************/ | |
1537 | /* The fw_flr_ack is actually built in the following way: */ | |
1538 | /* 8 bit: PF ack */ | |
1539 | /* 64 bit: VF ack */ | |
1540 | /* 8 bit: ios_dis_ack */ | |
1541 | /* In order to maintain endianity in the mailbox hsi, we want to keep using */ | |
1542 | /* u32. The fw must have the VF right after the PF since this is how it */ | |
1543 | /* access arrays(it expects always the VF to reside after the PF, and that */ | |
1544 | /* makes the calculation much easier for it. ) */ | |
1545 | /* In order to answer both limitations, and keep the struct small, the code */ | |
1546 | /* will abuse the structure defined here to achieve the actual partition */ | |
1547 | /* above */ | |
1548 | /****************************************************************************/ | |
f2e0899f | 1549 | struct fw_flr_ack { |
619c5cb6 VZ |
1550 | u32 pf_ack; |
1551 | u32 vf_ack[1]; | |
1552 | u32 iov_dis_ack; | |
f2e0899f | 1553 | }; |
a2fbb9ea | 1554 | |
f2e0899f | 1555 | struct fw_flr_mb { |
619c5cb6 VZ |
1556 | u32 aggint; |
1557 | u32 opgen_addr; | |
1558 | struct fw_flr_ack ack; | |
f2e0899f | 1559 | }; |
a2fbb9ea | 1560 | |
e4901dde VZ |
1561 | /**** SUPPORT FOR SHMEM ARRRAYS *** |
1562 | * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to | |
1563 | * define arrays with storage types smaller then unsigned dwords. | |
1564 | * The macros below add generic support for SHMEM arrays with numeric elements | |
1565 | * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword | |
1566 | * array with individual bit-filed elements accessed using shifts and masks. | |
1567 | * | |
1568 | */ | |
1569 | ||
1570 | /* eb is the bitwidth of a single element */ | |
1571 | #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) | |
1572 | #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) | |
1573 | ||
1574 | /* the bit-position macro allows the used to flip the order of the arrays | |
1575 | * elements on a per byte or word boundary. | |
1576 | * | |
1577 | * example: an array with 8 entries each 4 bit wide. This array will fit into | |
1578 | * a single dword. The diagrmas below show the array order of the nibbles. | |
1579 | * | |
1580 | * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: | |
1581 | * | |
619c5cb6 VZ |
1582 | * | | | | |
1583 | * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | | |
1584 | * | | | | | |
e4901dde VZ |
1585 | * |
1586 | * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: | |
1587 | * | |
619c5cb6 VZ |
1588 | * | | | | |
1589 | * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | | |
1590 | * | | | | | |
e4901dde VZ |
1591 | * |
1592 | * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: | |
1593 | * | |
619c5cb6 VZ |
1594 | * | | | | |
1595 | * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | | |
1596 | * | | | | | |
e4901dde VZ |
1597 | */ |
1598 | #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ | |
1599 | ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ | |
1600 | (((i)%((fb)/(eb))) * (eb))) | |
1601 | ||
619c5cb6 | 1602 | #define SHMEM_ARRAY_GET(a, i, eb, fb) \ |
e4901dde VZ |
1603 | ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ |
1604 | SHMEM_ARRAY_MASK(eb)) | |
1605 | ||
619c5cb6 | 1606 | #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ |
e4901dde VZ |
1607 | do { \ |
1608 | a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ | |
619c5cb6 | 1609 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde | 1610 | a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ |
619c5cb6 | 1611 | SHMEM_ARRAY_BITPOS(i, eb, fb)); \ |
e4901dde VZ |
1612 | } while (0) |
1613 | ||
1614 | ||
1615 | /****START OF DCBX STRUCTURES DECLARATIONS****/ | |
1616 | #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 | |
1617 | #define DCBX_PRI_PG_BITWIDTH 4 | |
1618 | #define DCBX_PRI_PG_FBITS 8 | |
1619 | #define DCBX_PRI_PG_GET(a, i) \ | |
1620 | SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) | |
1621 | #define DCBX_PRI_PG_SET(a, i, val) \ | |
1622 | SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) | |
1623 | #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 | |
1624 | #define DCBX_BW_PG_BITWIDTH 8 | |
1625 | #define DCBX_PG_BW_GET(a, i) \ | |
1626 | SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) | |
1627 | #define DCBX_PG_BW_SET(a, i, val) \ | |
1628 | SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) | |
1629 | #define DCBX_STRICT_PRI_PG 15 | |
1630 | #define DCBX_MAX_APP_PROTOCOL 16 | |
1631 | #define FCOE_APP_IDX 0 | |
1632 | #define ISCSI_APP_IDX 1 | |
1633 | #define PREDEFINED_APP_IDX_MAX 2 | |
1634 | ||
619c5cb6 VZ |
1635 | |
1636 | /* Big/Little endian have the same representation. */ | |
e4901dde | 1637 | struct dcbx_ets_feature { |
619c5cb6 VZ |
1638 | /* |
1639 | * For Admin MIB - is this feature supported by the | |
1640 | * driver | For Local MIB - should this feature be enabled. | |
1641 | */ | |
e4901dde VZ |
1642 | u32 enabled; |
1643 | u32 pg_bw_tbl[2]; | |
1644 | u32 pri_pg_tbl[1]; | |
1645 | }; | |
1646 | ||
619c5cb6 | 1647 | /* Driver structure in LE */ |
e4901dde VZ |
1648 | struct dcbx_pfc_feature { |
1649 | #ifdef __BIG_ENDIAN | |
1650 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1651 | #define DCBX_PFC_PRI_0 0x01 |
1652 | #define DCBX_PFC_PRI_1 0x02 | |
1653 | #define DCBX_PFC_PRI_2 0x04 | |
1654 | #define DCBX_PFC_PRI_3 0x08 | |
1655 | #define DCBX_PFC_PRI_4 0x10 | |
1656 | #define DCBX_PFC_PRI_5 0x20 | |
1657 | #define DCBX_PFC_PRI_6 0x40 | |
1658 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1659 | u8 pfc_caps; |
1660 | u8 reserved; | |
1661 | u8 enabled; | |
1662 | #elif defined(__LITTLE_ENDIAN) | |
1663 | u8 enabled; | |
1664 | u8 reserved; | |
1665 | u8 pfc_caps; | |
1666 | u8 pri_en_bitmap; | |
619c5cb6 VZ |
1667 | #define DCBX_PFC_PRI_0 0x01 |
1668 | #define DCBX_PFC_PRI_1 0x02 | |
1669 | #define DCBX_PFC_PRI_2 0x04 | |
1670 | #define DCBX_PFC_PRI_3 0x08 | |
1671 | #define DCBX_PFC_PRI_4 0x10 | |
1672 | #define DCBX_PFC_PRI_5 0x20 | |
1673 | #define DCBX_PFC_PRI_6 0x40 | |
1674 | #define DCBX_PFC_PRI_7 0x80 | |
e4901dde VZ |
1675 | #endif |
1676 | }; | |
1677 | ||
1678 | struct dcbx_app_priority_entry { | |
1679 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1680 | u16 app_id; |
1681 | u8 pri_bitmap; | |
1682 | u8 appBitfield; | |
1683 | #define DCBX_APP_ENTRY_VALID 0x01 | |
1684 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1685 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1686 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1687 | #define DCBX_APP_SF_PORT 0x20 | |
e4901dde VZ |
1688 | #elif defined(__LITTLE_ENDIAN) |
1689 | u8 appBitfield; | |
619c5cb6 VZ |
1690 | #define DCBX_APP_ENTRY_VALID 0x01 |
1691 | #define DCBX_APP_ENTRY_SF_MASK 0x30 | |
1692 | #define DCBX_APP_ENTRY_SF_SHIFT 4 | |
1693 | #define DCBX_APP_SF_ETH_TYPE 0x10 | |
1694 | #define DCBX_APP_SF_PORT 0x20 | |
1695 | u8 pri_bitmap; | |
1696 | u16 app_id; | |
e4901dde VZ |
1697 | #endif |
1698 | }; | |
1699 | ||
619c5cb6 VZ |
1700 | |
1701 | /* FW structure in BE */ | |
e4901dde VZ |
1702 | struct dcbx_app_priority_feature { |
1703 | #ifdef __BIG_ENDIAN | |
1704 | u8 reserved; | |
1705 | u8 default_pri; | |
1706 | u8 tc_supported; | |
1707 | u8 enabled; | |
1708 | #elif defined(__LITTLE_ENDIAN) | |
1709 | u8 enabled; | |
1710 | u8 tc_supported; | |
1711 | u8 default_pri; | |
1712 | u8 reserved; | |
1713 | #endif | |
1714 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; | |
1715 | }; | |
1716 | ||
619c5cb6 | 1717 | /* FW structure in BE */ |
e4901dde | 1718 | struct dcbx_features { |
619c5cb6 | 1719 | /* PG feature */ |
e4901dde | 1720 | struct dcbx_ets_feature ets; |
619c5cb6 | 1721 | /* PFC feature */ |
e4901dde | 1722 | struct dcbx_pfc_feature pfc; |
619c5cb6 | 1723 | /* APP feature */ |
e4901dde VZ |
1724 | struct dcbx_app_priority_feature app; |
1725 | }; | |
1726 | ||
619c5cb6 VZ |
1727 | /* LLDP protocol parameters */ |
1728 | /* FW structure in BE */ | |
e4901dde VZ |
1729 | struct lldp_params { |
1730 | #ifdef __BIG_ENDIAN | |
619c5cb6 VZ |
1731 | u8 msg_fast_tx_interval; |
1732 | u8 msg_tx_hold; | |
1733 | u8 msg_tx_interval; | |
1734 | u8 admin_status; | |
1735 | #define LLDP_TX_ONLY 0x01 | |
1736 | #define LLDP_RX_ONLY 0x02 | |
1737 | #define LLDP_TX_RX 0x03 | |
1738 | #define LLDP_DISABLED 0x04 | |
1739 | u8 reserved1; | |
1740 | u8 tx_fast; | |
1741 | u8 tx_crd_max; | |
1742 | u8 tx_crd; | |
e4901dde | 1743 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
1744 | u8 admin_status; |
1745 | #define LLDP_TX_ONLY 0x01 | |
1746 | #define LLDP_RX_ONLY 0x02 | |
1747 | #define LLDP_TX_RX 0x03 | |
1748 | #define LLDP_DISABLED 0x04 | |
1749 | u8 msg_tx_interval; | |
1750 | u8 msg_tx_hold; | |
1751 | u8 msg_fast_tx_interval; | |
1752 | u8 tx_crd; | |
1753 | u8 tx_crd_max; | |
1754 | u8 tx_fast; | |
1755 | u8 reserved1; | |
e4901dde | 1756 | #endif |
619c5cb6 VZ |
1757 | #define REM_CHASSIS_ID_STAT_LEN 4 |
1758 | #define REM_PORT_ID_STAT_LEN 4 | |
1759 | /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ | |
e4901dde | 1760 | u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1761 | /* Holds remote Port ID TLV header, subtype and 9B of payload. */ |
e4901dde VZ |
1762 | u32 peer_port_id[REM_PORT_ID_STAT_LEN]; |
1763 | }; | |
1764 | ||
1765 | struct lldp_dcbx_stat { | |
619c5cb6 VZ |
1766 | #define LOCAL_CHASSIS_ID_STAT_LEN 2 |
1767 | #define LOCAL_PORT_ID_STAT_LEN 2 | |
1768 | /* Holds local Chassis ID 8B payload of constant subtype 4. */ | |
e4901dde | 1769 | u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; |
619c5cb6 | 1770 | /* Holds local Port ID 8B payload of constant subtype 3. */ |
e4901dde | 1771 | u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; |
619c5cb6 | 1772 | /* Number of DCBX frames transmitted. */ |
e4901dde | 1773 | u32 num_tx_dcbx_pkts; |
619c5cb6 | 1774 | /* Number of DCBX frames received. */ |
e4901dde VZ |
1775 | u32 num_rx_dcbx_pkts; |
1776 | }; | |
1777 | ||
619c5cb6 | 1778 | /* ADMIN MIB - DCBX local machine default configuration. */ |
e4901dde | 1779 | struct lldp_admin_mib { |
619c5cb6 VZ |
1780 | u32 ver_cfg_flags; |
1781 | #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 | |
1782 | #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 | |
1783 | #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 | |
1784 | #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 | |
1785 | #define DCBX_ETS_RECO_VALID 0x00000010 | |
1786 | #define DCBX_ETS_WILLING 0x00000020 | |
1787 | #define DCBX_PFC_WILLING 0x00000040 | |
1788 | #define DCBX_APP_WILLING 0x00000080 | |
1789 | #define DCBX_VERSION_CEE 0x00000100 | |
1790 | #define DCBX_VERSION_IEEE 0x00000200 | |
1791 | #define DCBX_DCBX_ENABLED 0x00000400 | |
1792 | #define DCBX_CEE_VERSION_MASK 0x0000f000 | |
1793 | #define DCBX_CEE_VERSION_SHIFT 12 | |
1794 | #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 | |
1795 | #define DCBX_CEE_MAX_VERSION_SHIFT 16 | |
1796 | struct dcbx_features features; | |
1797 | }; | |
1798 | ||
1799 | /* REMOTE MIB - remote machine DCBX configuration. */ | |
e4901dde VZ |
1800 | struct lldp_remote_mib { |
1801 | u32 prefix_seq_num; | |
1802 | u32 flags; | |
619c5cb6 VZ |
1803 | #define DCBX_ETS_TLV_RX 0x00000001 |
1804 | #define DCBX_PFC_TLV_RX 0x00000002 | |
1805 | #define DCBX_APP_TLV_RX 0x00000004 | |
1806 | #define DCBX_ETS_RX_ERROR 0x00000010 | |
1807 | #define DCBX_PFC_RX_ERROR 0x00000020 | |
1808 | #define DCBX_APP_RX_ERROR 0x00000040 | |
1809 | #define DCBX_ETS_REM_WILLING 0x00000100 | |
1810 | #define DCBX_PFC_REM_WILLING 0x00000200 | |
1811 | #define DCBX_APP_REM_WILLING 0x00000400 | |
1812 | #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 | |
1813 | #define DCBX_REMOTE_MIB_VALID 0x00002000 | |
e4901dde VZ |
1814 | struct dcbx_features features; |
1815 | u32 suffix_seq_num; | |
1816 | }; | |
1817 | ||
619c5cb6 | 1818 | /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ |
e4901dde VZ |
1819 | struct lldp_local_mib { |
1820 | u32 prefix_seq_num; | |
619c5cb6 | 1821 | /* Indicates if there is mismatch with negotiation results. */ |
e4901dde | 1822 | u32 error; |
619c5cb6 VZ |
1823 | #define DCBX_LOCAL_ETS_ERROR 0x00000001 |
1824 | #define DCBX_LOCAL_PFC_ERROR 0x00000002 | |
1825 | #define DCBX_LOCAL_APP_ERROR 0x00000004 | |
1826 | #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 | |
1827 | #define DCBX_LOCAL_APP_MISMATCH 0x00000020 | |
e4901dde VZ |
1828 | struct dcbx_features features; |
1829 | u32 suffix_seq_num; | |
1830 | }; | |
1831 | /***END OF DCBX STRUCTURES DECLARATIONS***/ | |
a2fbb9ea | 1832 | |
619c5cb6 VZ |
1833 | struct ncsi_oem_fcoe_features { |
1834 | u32 fcoe_features1; | |
1835 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF | |
1836 | #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 | |
1837 | ||
1838 | #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 | |
1839 | #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 | |
1840 | ||
1841 | u32 fcoe_features2; | |
1842 | #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF | |
1843 | #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 | |
1844 | ||
1845 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 | |
1846 | #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 | |
1847 | ||
1848 | u32 fcoe_features3; | |
1849 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF | |
1850 | #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 | |
1851 | ||
1852 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 | |
1853 | #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 | |
1854 | ||
1855 | u32 fcoe_features4; | |
1856 | #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F | |
1857 | #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 | |
1858 | }; | |
1859 | ||
1860 | struct ncsi_oem_data { | |
1861 | u32 driver_version[4]; | |
1862 | struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; | |
1863 | }; | |
1864 | ||
2691d51d EG |
1865 | struct shmem2_region { |
1866 | ||
619c5cb6 VZ |
1867 | u32 size; /* 0x0000 */ |
1868 | ||
1869 | u32 dcc_support; /* 0x0004 */ | |
1870 | #define SHMEM_DCC_SUPPORT_NONE 0x00000000 | |
1871 | #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 | |
1872 | #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 | |
1873 | #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 | |
1874 | #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 | |
1875 | #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 | |
1876 | ||
1877 | u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ | |
a22f0788 YR |
1878 | /* |
1879 | * For backwards compatibility, if the mf_cfg_addr does not exist | |
1880 | * (the size filed is smaller than 0xc) the mf_cfg resides at the | |
1881 | * end of struct shmem_region | |
619c5cb6 VZ |
1882 | */ |
1883 | u32 mf_cfg_addr; /* 0x0010 */ | |
1884 | #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 | |
1885 | ||
1886 | struct fw_flr_mb flr_mb; /* 0x0014 */ | |
1887 | u32 dcbx_lldp_params_offset; /* 0x0028 */ | |
1888 | #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 | |
1889 | u32 dcbx_neg_res_offset; /* 0x002c */ | |
1890 | #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 | |
1891 | u32 dcbx_remote_mib_offset; /* 0x0030 */ | |
1892 | #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 | |
f2e0899f DK |
1893 | /* |
1894 | * The other shmemX_base_addr holds the other path's shmem address | |
1895 | * required for example in case of common phy init, or for path1 to know | |
1896 | * the address of mcp debug trace which is located in offset from shmem | |
1897 | * of path0 | |
a22f0788 | 1898 | */ |
619c5cb6 VZ |
1899 | u32 other_shmem_base_addr; /* 0x0034 */ |
1900 | u32 other_shmem2_base_addr; /* 0x0038 */ | |
1901 | /* | |
1902 | * mcp_vf_disabled is set by the MCP to indicate the driver about VFs | |
1903 | * which were disabled/flred | |
1904 | */ | |
1905 | u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ | |
1906 | ||
1907 | /* | |
1908 | * drv_ack_vf_disabled is set by the PF driver to ack handled disabled | |
1909 | * VFs | |
1910 | */ | |
1911 | u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ | |
1912 | ||
1913 | u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ | |
1914 | #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 | |
1915 | ||
1916 | /* | |
1917 | * edebug_driver_if field is used to transfer messages between edebug | |
1918 | * app to the driver through shmem2. | |
1919 | * | |
1920 | * message format: | |
1921 | * bits 0-2 - function number / instance of driver to perform request | |
1922 | * bits 3-5 - op code / is_ack? | |
1923 | * bits 6-63 - data | |
1924 | */ | |
1925 | u32 edebug_driver_if[2]; /* 0x0068 */ | |
1926 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 | |
1927 | #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 | |
1928 | #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 | |
1929 | ||
1930 | u32 nvm_retain_bitmap_addr; /* 0x0070 */ | |
1931 | ||
1932 | u32 reserved1; /* 0x0074 */ | |
1933 | ||
1934 | u32 reserved2[E2_FUNC_MAX]; | |
1935 | ||
1936 | u32 reserved3[E2_FUNC_MAX];/* 0x0088 */ | |
1937 | u32 reserved4[E2_FUNC_MAX];/* 0x0098 */ | |
1938 | ||
1939 | u32 swim_base_addr; /* 0x0108 */ | |
1940 | u32 swim_funcs; | |
1941 | u32 swim_main_cb; | |
1942 | ||
1943 | u32 reserved5[2]; | |
1944 | ||
1945 | /* generic flags controlled by the driver */ | |
1946 | u32 drv_flags; | |
1947 | #define DRV_FLAGS_DCB_CONFIGURED 0x1 | |
1948 | ||
1949 | /* pointer to extended dev_info shared data copied from nvm image */ | |
1950 | u32 extended_dev_info_shared_addr; | |
1951 | u32 ncsi_oem_data_addr; | |
1952 | ||
1953 | u32 ocsd_host_addr; | |
1954 | u32 ocbb_host_addr; | |
1955 | u32 ocsd_req_update_interval; | |
2691d51d EG |
1956 | }; |
1957 | ||
1958 | ||
bb2a0f7a | 1959 | struct emac_stats { |
619c5cb6 VZ |
1960 | u32 rx_stat_ifhcinoctets; |
1961 | u32 rx_stat_ifhcinbadoctets; | |
1962 | u32 rx_stat_etherstatsfragments; | |
1963 | u32 rx_stat_ifhcinucastpkts; | |
1964 | u32 rx_stat_ifhcinmulticastpkts; | |
1965 | u32 rx_stat_ifhcinbroadcastpkts; | |
1966 | u32 rx_stat_dot3statsfcserrors; | |
1967 | u32 rx_stat_dot3statsalignmenterrors; | |
1968 | u32 rx_stat_dot3statscarriersenseerrors; | |
1969 | u32 rx_stat_xonpauseframesreceived; | |
1970 | u32 rx_stat_xoffpauseframesreceived; | |
1971 | u32 rx_stat_maccontrolframesreceived; | |
1972 | u32 rx_stat_xoffstateentered; | |
1973 | u32 rx_stat_dot3statsframestoolong; | |
1974 | u32 rx_stat_etherstatsjabbers; | |
1975 | u32 rx_stat_etherstatsundersizepkts; | |
1976 | u32 rx_stat_etherstatspkts64octets; | |
1977 | u32 rx_stat_etherstatspkts65octetsto127octets; | |
1978 | u32 rx_stat_etherstatspkts128octetsto255octets; | |
1979 | u32 rx_stat_etherstatspkts256octetsto511octets; | |
1980 | u32 rx_stat_etherstatspkts512octetsto1023octets; | |
1981 | u32 rx_stat_etherstatspkts1024octetsto1522octets; | |
1982 | u32 rx_stat_etherstatspktsover1522octets; | |
1983 | ||
1984 | u32 rx_stat_falsecarriererrors; | |
1985 | ||
1986 | u32 tx_stat_ifhcoutoctets; | |
1987 | u32 tx_stat_ifhcoutbadoctets; | |
1988 | u32 tx_stat_etherstatscollisions; | |
1989 | u32 tx_stat_outxonsent; | |
1990 | u32 tx_stat_outxoffsent; | |
1991 | u32 tx_stat_flowcontroldone; | |
1992 | u32 tx_stat_dot3statssinglecollisionframes; | |
1993 | u32 tx_stat_dot3statsmultiplecollisionframes; | |
1994 | u32 tx_stat_dot3statsdeferredtransmissions; | |
1995 | u32 tx_stat_dot3statsexcessivecollisions; | |
1996 | u32 tx_stat_dot3statslatecollisions; | |
1997 | u32 tx_stat_ifhcoutucastpkts; | |
1998 | u32 tx_stat_ifhcoutmulticastpkts; | |
1999 | u32 tx_stat_ifhcoutbroadcastpkts; | |
2000 | u32 tx_stat_etherstatspkts64octets; | |
2001 | u32 tx_stat_etherstatspkts65octetsto127octets; | |
2002 | u32 tx_stat_etherstatspkts128octetsto255octets; | |
2003 | u32 tx_stat_etherstatspkts256octetsto511octets; | |
2004 | u32 tx_stat_etherstatspkts512octetsto1023octets; | |
2005 | u32 tx_stat_etherstatspkts1024octetsto1522octets; | |
2006 | u32 tx_stat_etherstatspktsover1522octets; | |
2007 | u32 tx_stat_dot3statsinternalmactransmiterrors; | |
bb2a0f7a YG |
2008 | }; |
2009 | ||
2010 | ||
523224a3 | 2011 | struct bmac1_stats { |
619c5cb6 VZ |
2012 | u32 tx_stat_gtpkt_lo; |
2013 | u32 tx_stat_gtpkt_hi; | |
2014 | u32 tx_stat_gtxpf_lo; | |
2015 | u32 tx_stat_gtxpf_hi; | |
2016 | u32 tx_stat_gtfcs_lo; | |
2017 | u32 tx_stat_gtfcs_hi; | |
2018 | u32 tx_stat_gtmca_lo; | |
2019 | u32 tx_stat_gtmca_hi; | |
2020 | u32 tx_stat_gtbca_lo; | |
2021 | u32 tx_stat_gtbca_hi; | |
2022 | u32 tx_stat_gtfrg_lo; | |
2023 | u32 tx_stat_gtfrg_hi; | |
2024 | u32 tx_stat_gtovr_lo; | |
2025 | u32 tx_stat_gtovr_hi; | |
2026 | u32 tx_stat_gt64_lo; | |
2027 | u32 tx_stat_gt64_hi; | |
2028 | u32 tx_stat_gt127_lo; | |
2029 | u32 tx_stat_gt127_hi; | |
2030 | u32 tx_stat_gt255_lo; | |
2031 | u32 tx_stat_gt255_hi; | |
2032 | u32 tx_stat_gt511_lo; | |
2033 | u32 tx_stat_gt511_hi; | |
2034 | u32 tx_stat_gt1023_lo; | |
2035 | u32 tx_stat_gt1023_hi; | |
2036 | u32 tx_stat_gt1518_lo; | |
2037 | u32 tx_stat_gt1518_hi; | |
2038 | u32 tx_stat_gt2047_lo; | |
2039 | u32 tx_stat_gt2047_hi; | |
2040 | u32 tx_stat_gt4095_lo; | |
2041 | u32 tx_stat_gt4095_hi; | |
2042 | u32 tx_stat_gt9216_lo; | |
2043 | u32 tx_stat_gt9216_hi; | |
2044 | u32 tx_stat_gt16383_lo; | |
2045 | u32 tx_stat_gt16383_hi; | |
2046 | u32 tx_stat_gtmax_lo; | |
2047 | u32 tx_stat_gtmax_hi; | |
2048 | u32 tx_stat_gtufl_lo; | |
2049 | u32 tx_stat_gtufl_hi; | |
2050 | u32 tx_stat_gterr_lo; | |
2051 | u32 tx_stat_gterr_hi; | |
2052 | u32 tx_stat_gtbyt_lo; | |
2053 | u32 tx_stat_gtbyt_hi; | |
2054 | ||
2055 | u32 rx_stat_gr64_lo; | |
2056 | u32 rx_stat_gr64_hi; | |
2057 | u32 rx_stat_gr127_lo; | |
2058 | u32 rx_stat_gr127_hi; | |
2059 | u32 rx_stat_gr255_lo; | |
2060 | u32 rx_stat_gr255_hi; | |
2061 | u32 rx_stat_gr511_lo; | |
2062 | u32 rx_stat_gr511_hi; | |
2063 | u32 rx_stat_gr1023_lo; | |
2064 | u32 rx_stat_gr1023_hi; | |
2065 | u32 rx_stat_gr1518_lo; | |
2066 | u32 rx_stat_gr1518_hi; | |
2067 | u32 rx_stat_gr2047_lo; | |
2068 | u32 rx_stat_gr2047_hi; | |
2069 | u32 rx_stat_gr4095_lo; | |
2070 | u32 rx_stat_gr4095_hi; | |
2071 | u32 rx_stat_gr9216_lo; | |
2072 | u32 rx_stat_gr9216_hi; | |
2073 | u32 rx_stat_gr16383_lo; | |
2074 | u32 rx_stat_gr16383_hi; | |
2075 | u32 rx_stat_grmax_lo; | |
2076 | u32 rx_stat_grmax_hi; | |
2077 | u32 rx_stat_grpkt_lo; | |
2078 | u32 rx_stat_grpkt_hi; | |
2079 | u32 rx_stat_grfcs_lo; | |
2080 | u32 rx_stat_grfcs_hi; | |
2081 | u32 rx_stat_grmca_lo; | |
2082 | u32 rx_stat_grmca_hi; | |
2083 | u32 rx_stat_grbca_lo; | |
2084 | u32 rx_stat_grbca_hi; | |
2085 | u32 rx_stat_grxcf_lo; | |
2086 | u32 rx_stat_grxcf_hi; | |
2087 | u32 rx_stat_grxpf_lo; | |
2088 | u32 rx_stat_grxpf_hi; | |
2089 | u32 rx_stat_grxuo_lo; | |
2090 | u32 rx_stat_grxuo_hi; | |
2091 | u32 rx_stat_grjbr_lo; | |
2092 | u32 rx_stat_grjbr_hi; | |
2093 | u32 rx_stat_grovr_lo; | |
2094 | u32 rx_stat_grovr_hi; | |
2095 | u32 rx_stat_grflr_lo; | |
2096 | u32 rx_stat_grflr_hi; | |
2097 | u32 rx_stat_grmeg_lo; | |
2098 | u32 rx_stat_grmeg_hi; | |
2099 | u32 rx_stat_grmeb_lo; | |
2100 | u32 rx_stat_grmeb_hi; | |
2101 | u32 rx_stat_grbyt_lo; | |
2102 | u32 rx_stat_grbyt_hi; | |
2103 | u32 rx_stat_grund_lo; | |
2104 | u32 rx_stat_grund_hi; | |
2105 | u32 rx_stat_grfrg_lo; | |
2106 | u32 rx_stat_grfrg_hi; | |
2107 | u32 rx_stat_grerb_lo; | |
2108 | u32 rx_stat_grerb_hi; | |
2109 | u32 rx_stat_grfre_lo; | |
2110 | u32 rx_stat_grfre_hi; | |
2111 | u32 rx_stat_gripj_lo; | |
2112 | u32 rx_stat_gripj_hi; | |
bb2a0f7a YG |
2113 | }; |
2114 | ||
f2e0899f DK |
2115 | struct bmac2_stats { |
2116 | u32 tx_stat_gtpk_lo; /* gtpok */ | |
2117 | u32 tx_stat_gtpk_hi; /* gtpok */ | |
2118 | u32 tx_stat_gtxpf_lo; /* gtpf */ | |
2119 | u32 tx_stat_gtxpf_hi; /* gtpf */ | |
2120 | u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ | |
2121 | u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ | |
2122 | u32 tx_stat_gtfcs_lo; | |
2123 | u32 tx_stat_gtfcs_hi; | |
2124 | u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ | |
2125 | u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ | |
2126 | u32 tx_stat_gtmca_lo; | |
2127 | u32 tx_stat_gtmca_hi; | |
2128 | u32 tx_stat_gtbca_lo; | |
2129 | u32 tx_stat_gtbca_hi; | |
2130 | u32 tx_stat_gtovr_lo; | |
2131 | u32 tx_stat_gtovr_hi; | |
2132 | u32 tx_stat_gtfrg_lo; | |
2133 | u32 tx_stat_gtfrg_hi; | |
2134 | u32 tx_stat_gtpkt1_lo; /* gtpkt */ | |
2135 | u32 tx_stat_gtpkt1_hi; /* gtpkt */ | |
2136 | u32 tx_stat_gt64_lo; | |
2137 | u32 tx_stat_gt64_hi; | |
2138 | u32 tx_stat_gt127_lo; | |
2139 | u32 tx_stat_gt127_hi; | |
2140 | u32 tx_stat_gt255_lo; | |
2141 | u32 tx_stat_gt255_hi; | |
2142 | u32 tx_stat_gt511_lo; | |
2143 | u32 tx_stat_gt511_hi; | |
2144 | u32 tx_stat_gt1023_lo; | |
2145 | u32 tx_stat_gt1023_hi; | |
2146 | u32 tx_stat_gt1518_lo; | |
2147 | u32 tx_stat_gt1518_hi; | |
2148 | u32 tx_stat_gt2047_lo; | |
2149 | u32 tx_stat_gt2047_hi; | |
2150 | u32 tx_stat_gt4095_lo; | |
2151 | u32 tx_stat_gt4095_hi; | |
2152 | u32 tx_stat_gt9216_lo; | |
2153 | u32 tx_stat_gt9216_hi; | |
2154 | u32 tx_stat_gt16383_lo; | |
2155 | u32 tx_stat_gt16383_hi; | |
2156 | u32 tx_stat_gtmax_lo; | |
2157 | u32 tx_stat_gtmax_hi; | |
2158 | u32 tx_stat_gtufl_lo; | |
2159 | u32 tx_stat_gtufl_hi; | |
2160 | u32 tx_stat_gterr_lo; | |
2161 | u32 tx_stat_gterr_hi; | |
2162 | u32 tx_stat_gtbyt_lo; | |
2163 | u32 tx_stat_gtbyt_hi; | |
2164 | ||
2165 | u32 rx_stat_gr64_lo; | |
2166 | u32 rx_stat_gr64_hi; | |
2167 | u32 rx_stat_gr127_lo; | |
2168 | u32 rx_stat_gr127_hi; | |
2169 | u32 rx_stat_gr255_lo; | |
2170 | u32 rx_stat_gr255_hi; | |
2171 | u32 rx_stat_gr511_lo; | |
2172 | u32 rx_stat_gr511_hi; | |
2173 | u32 rx_stat_gr1023_lo; | |
2174 | u32 rx_stat_gr1023_hi; | |
2175 | u32 rx_stat_gr1518_lo; | |
2176 | u32 rx_stat_gr1518_hi; | |
2177 | u32 rx_stat_gr2047_lo; | |
2178 | u32 rx_stat_gr2047_hi; | |
2179 | u32 rx_stat_gr4095_lo; | |
2180 | u32 rx_stat_gr4095_hi; | |
2181 | u32 rx_stat_gr9216_lo; | |
2182 | u32 rx_stat_gr9216_hi; | |
2183 | u32 rx_stat_gr16383_lo; | |
2184 | u32 rx_stat_gr16383_hi; | |
2185 | u32 rx_stat_grmax_lo; | |
2186 | u32 rx_stat_grmax_hi; | |
2187 | u32 rx_stat_grpkt_lo; | |
2188 | u32 rx_stat_grpkt_hi; | |
2189 | u32 rx_stat_grfcs_lo; | |
2190 | u32 rx_stat_grfcs_hi; | |
2191 | u32 rx_stat_gruca_lo; | |
2192 | u32 rx_stat_gruca_hi; | |
2193 | u32 rx_stat_grmca_lo; | |
2194 | u32 rx_stat_grmca_hi; | |
2195 | u32 rx_stat_grbca_lo; | |
2196 | u32 rx_stat_grbca_hi; | |
2197 | u32 rx_stat_grxpf_lo; /* grpf */ | |
2198 | u32 rx_stat_grxpf_hi; /* grpf */ | |
2199 | u32 rx_stat_grpp_lo; | |
2200 | u32 rx_stat_grpp_hi; | |
2201 | u32 rx_stat_grxuo_lo; /* gruo */ | |
2202 | u32 rx_stat_grxuo_hi; /* gruo */ | |
2203 | u32 rx_stat_grjbr_lo; | |
2204 | u32 rx_stat_grjbr_hi; | |
2205 | u32 rx_stat_grovr_lo; | |
2206 | u32 rx_stat_grovr_hi; | |
2207 | u32 rx_stat_grxcf_lo; /* grcf */ | |
2208 | u32 rx_stat_grxcf_hi; /* grcf */ | |
2209 | u32 rx_stat_grflr_lo; | |
2210 | u32 rx_stat_grflr_hi; | |
2211 | u32 rx_stat_grpok_lo; | |
2212 | u32 rx_stat_grpok_hi; | |
2213 | u32 rx_stat_grmeg_lo; | |
2214 | u32 rx_stat_grmeg_hi; | |
2215 | u32 rx_stat_grmeb_lo; | |
2216 | u32 rx_stat_grmeb_hi; | |
2217 | u32 rx_stat_grbyt_lo; | |
2218 | u32 rx_stat_grbyt_hi; | |
2219 | u32 rx_stat_grund_lo; | |
2220 | u32 rx_stat_grund_hi; | |
2221 | u32 rx_stat_grfrg_lo; | |
2222 | u32 rx_stat_grfrg_hi; | |
2223 | u32 rx_stat_grerb_lo; /* grerrbyt */ | |
2224 | u32 rx_stat_grerb_hi; /* grerrbyt */ | |
2225 | u32 rx_stat_grfre_lo; /* grfrerr */ | |
2226 | u32 rx_stat_grfre_hi; /* grfrerr */ | |
2227 | u32 rx_stat_gripj_lo; | |
2228 | u32 rx_stat_gripj_hi; | |
2229 | }; | |
bb2a0f7a | 2230 | |
619c5cb6 VZ |
2231 | struct mstat_stats { |
2232 | struct { | |
2233 | /* OTE MSTAT on E3 has a bug where this register's contents are | |
2234 | * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp | |
2235 | */ | |
2236 | u32 tx_gtxpok_lo; | |
2237 | u32 tx_gtxpok_hi; | |
2238 | u32 tx_gtxpf_lo; | |
2239 | u32 tx_gtxpf_hi; | |
2240 | u32 tx_gtxpp_lo; | |
2241 | u32 tx_gtxpp_hi; | |
2242 | u32 tx_gtfcs_lo; | |
2243 | u32 tx_gtfcs_hi; | |
2244 | u32 tx_gtuca_lo; | |
2245 | u32 tx_gtuca_hi; | |
2246 | u32 tx_gtmca_lo; | |
2247 | u32 tx_gtmca_hi; | |
2248 | u32 tx_gtgca_lo; | |
2249 | u32 tx_gtgca_hi; | |
2250 | u32 tx_gtpkt_lo; | |
2251 | u32 tx_gtpkt_hi; | |
2252 | u32 tx_gt64_lo; | |
2253 | u32 tx_gt64_hi; | |
2254 | u32 tx_gt127_lo; | |
2255 | u32 tx_gt127_hi; | |
2256 | u32 tx_gt255_lo; | |
2257 | u32 tx_gt255_hi; | |
2258 | u32 tx_gt511_lo; | |
2259 | u32 tx_gt511_hi; | |
2260 | u32 tx_gt1023_lo; | |
2261 | u32 tx_gt1023_hi; | |
2262 | u32 tx_gt1518_lo; | |
2263 | u32 tx_gt1518_hi; | |
2264 | u32 tx_gt2047_lo; | |
2265 | u32 tx_gt2047_hi; | |
2266 | u32 tx_gt4095_lo; | |
2267 | u32 tx_gt4095_hi; | |
2268 | u32 tx_gt9216_lo; | |
2269 | u32 tx_gt9216_hi; | |
2270 | u32 tx_gt16383_lo; | |
2271 | u32 tx_gt16383_hi; | |
2272 | u32 tx_gtufl_lo; | |
2273 | u32 tx_gtufl_hi; | |
2274 | u32 tx_gterr_lo; | |
2275 | u32 tx_gterr_hi; | |
2276 | u32 tx_gtbyt_lo; | |
2277 | u32 tx_gtbyt_hi; | |
2278 | u32 tx_collisions_lo; | |
2279 | u32 tx_collisions_hi; | |
2280 | u32 tx_singlecollision_lo; | |
2281 | u32 tx_singlecollision_hi; | |
2282 | u32 tx_multiplecollisions_lo; | |
2283 | u32 tx_multiplecollisions_hi; | |
2284 | u32 tx_deferred_lo; | |
2285 | u32 tx_deferred_hi; | |
2286 | u32 tx_excessivecollisions_lo; | |
2287 | u32 tx_excessivecollisions_hi; | |
2288 | u32 tx_latecollisions_lo; | |
2289 | u32 tx_latecollisions_hi; | |
2290 | } stats_tx; | |
2291 | ||
2292 | struct { | |
2293 | u32 rx_gr64_lo; | |
2294 | u32 rx_gr64_hi; | |
2295 | u32 rx_gr127_lo; | |
2296 | u32 rx_gr127_hi; | |
2297 | u32 rx_gr255_lo; | |
2298 | u32 rx_gr255_hi; | |
2299 | u32 rx_gr511_lo; | |
2300 | u32 rx_gr511_hi; | |
2301 | u32 rx_gr1023_lo; | |
2302 | u32 rx_gr1023_hi; | |
2303 | u32 rx_gr1518_lo; | |
2304 | u32 rx_gr1518_hi; | |
2305 | u32 rx_gr2047_lo; | |
2306 | u32 rx_gr2047_hi; | |
2307 | u32 rx_gr4095_lo; | |
2308 | u32 rx_gr4095_hi; | |
2309 | u32 rx_gr9216_lo; | |
2310 | u32 rx_gr9216_hi; | |
2311 | u32 rx_gr16383_lo; | |
2312 | u32 rx_gr16383_hi; | |
2313 | u32 rx_grpkt_lo; | |
2314 | u32 rx_grpkt_hi; | |
2315 | u32 rx_grfcs_lo; | |
2316 | u32 rx_grfcs_hi; | |
2317 | u32 rx_gruca_lo; | |
2318 | u32 rx_gruca_hi; | |
2319 | u32 rx_grmca_lo; | |
2320 | u32 rx_grmca_hi; | |
2321 | u32 rx_grbca_lo; | |
2322 | u32 rx_grbca_hi; | |
2323 | u32 rx_grxpf_lo; | |
2324 | u32 rx_grxpf_hi; | |
2325 | u32 rx_grxpp_lo; | |
2326 | u32 rx_grxpp_hi; | |
2327 | u32 rx_grxuo_lo; | |
2328 | u32 rx_grxuo_hi; | |
2329 | u32 rx_grovr_lo; | |
2330 | u32 rx_grovr_hi; | |
2331 | u32 rx_grxcf_lo; | |
2332 | u32 rx_grxcf_hi; | |
2333 | u32 rx_grflr_lo; | |
2334 | u32 rx_grflr_hi; | |
2335 | u32 rx_grpok_lo; | |
2336 | u32 rx_grpok_hi; | |
2337 | u32 rx_grbyt_lo; | |
2338 | u32 rx_grbyt_hi; | |
2339 | u32 rx_grund_lo; | |
2340 | u32 rx_grund_hi; | |
2341 | u32 rx_grfrg_lo; | |
2342 | u32 rx_grfrg_hi; | |
2343 | u32 rx_grerb_lo; | |
2344 | u32 rx_grerb_hi; | |
2345 | u32 rx_grfre_lo; | |
2346 | u32 rx_grfre_hi; | |
2347 | ||
2348 | u32 rx_alignmenterrors_lo; | |
2349 | u32 rx_alignmenterrors_hi; | |
2350 | u32 rx_falsecarrier_lo; | |
2351 | u32 rx_falsecarrier_hi; | |
2352 | u32 rx_llfcmsgcnt_lo; | |
2353 | u32 rx_llfcmsgcnt_hi; | |
2354 | } stats_rx; | |
2355 | }; | |
2356 | ||
bb2a0f7a | 2357 | union mac_stats { |
619c5cb6 VZ |
2358 | struct emac_stats emac_stats; |
2359 | struct bmac1_stats bmac1_stats; | |
2360 | struct bmac2_stats bmac2_stats; | |
2361 | struct mstat_stats mstat_stats; | |
bb2a0f7a YG |
2362 | }; |
2363 | ||
2364 | ||
2365 | struct mac_stx { | |
619c5cb6 VZ |
2366 | /* in_bad_octets */ |
2367 | u32 rx_stat_ifhcinbadoctets_hi; | |
2368 | u32 rx_stat_ifhcinbadoctets_lo; | |
2369 | ||
2370 | /* out_bad_octets */ | |
2371 | u32 tx_stat_ifhcoutbadoctets_hi; | |
2372 | u32 tx_stat_ifhcoutbadoctets_lo; | |
2373 | ||
2374 | /* crc_receive_errors */ | |
2375 | u32 rx_stat_dot3statsfcserrors_hi; | |
2376 | u32 rx_stat_dot3statsfcserrors_lo; | |
2377 | /* alignment_errors */ | |
2378 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
2379 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
2380 | /* carrier_sense_errors */ | |
2381 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
2382 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
2383 | /* false_carrier_detections */ | |
2384 | u32 rx_stat_falsecarriererrors_hi; | |
2385 | u32 rx_stat_falsecarriererrors_lo; | |
2386 | ||
2387 | /* runt_packets_received */ | |
2388 | u32 rx_stat_etherstatsundersizepkts_hi; | |
2389 | u32 rx_stat_etherstatsundersizepkts_lo; | |
2390 | /* jabber_packets_received */ | |
2391 | u32 rx_stat_dot3statsframestoolong_hi; | |
2392 | u32 rx_stat_dot3statsframestoolong_lo; | |
2393 | ||
2394 | /* error_runt_packets_received */ | |
2395 | u32 rx_stat_etherstatsfragments_hi; | |
2396 | u32 rx_stat_etherstatsfragments_lo; | |
2397 | /* error_jabber_packets_received */ | |
2398 | u32 rx_stat_etherstatsjabbers_hi; | |
2399 | u32 rx_stat_etherstatsjabbers_lo; | |
2400 | ||
2401 | /* control_frames_received */ | |
2402 | u32 rx_stat_maccontrolframesreceived_hi; | |
2403 | u32 rx_stat_maccontrolframesreceived_lo; | |
2404 | u32 rx_stat_mac_xpf_hi; | |
2405 | u32 rx_stat_mac_xpf_lo; | |
2406 | u32 rx_stat_mac_xcf_hi; | |
2407 | u32 rx_stat_mac_xcf_lo; | |
2408 | ||
2409 | /* xoff_state_entered */ | |
2410 | u32 rx_stat_xoffstateentered_hi; | |
2411 | u32 rx_stat_xoffstateentered_lo; | |
2412 | /* pause_xon_frames_received */ | |
2413 | u32 rx_stat_xonpauseframesreceived_hi; | |
2414 | u32 rx_stat_xonpauseframesreceived_lo; | |
2415 | /* pause_xoff_frames_received */ | |
2416 | u32 rx_stat_xoffpauseframesreceived_hi; | |
2417 | u32 rx_stat_xoffpauseframesreceived_lo; | |
2418 | /* pause_xon_frames_transmitted */ | |
2419 | u32 tx_stat_outxonsent_hi; | |
2420 | u32 tx_stat_outxonsent_lo; | |
2421 | /* pause_xoff_frames_transmitted */ | |
2422 | u32 tx_stat_outxoffsent_hi; | |
2423 | u32 tx_stat_outxoffsent_lo; | |
2424 | /* flow_control_done */ | |
2425 | u32 tx_stat_flowcontroldone_hi; | |
2426 | u32 tx_stat_flowcontroldone_lo; | |
2427 | ||
2428 | /* ether_stats_collisions */ | |
2429 | u32 tx_stat_etherstatscollisions_hi; | |
2430 | u32 tx_stat_etherstatscollisions_lo; | |
2431 | /* single_collision_transmit_frames */ | |
2432 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
2433 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
2434 | /* multiple_collision_transmit_frames */ | |
2435 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
2436 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
2437 | /* deferred_transmissions */ | |
2438 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
2439 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
2440 | /* excessive_collision_frames */ | |
2441 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
2442 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
2443 | /* late_collision_frames */ | |
2444 | u32 tx_stat_dot3statslatecollisions_hi; | |
2445 | u32 tx_stat_dot3statslatecollisions_lo; | |
2446 | ||
2447 | /* frames_transmitted_64_bytes */ | |
2448 | u32 tx_stat_etherstatspkts64octets_hi; | |
2449 | u32 tx_stat_etherstatspkts64octets_lo; | |
2450 | /* frames_transmitted_65_127_bytes */ | |
2451 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
2452 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
2453 | /* frames_transmitted_128_255_bytes */ | |
2454 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
2455 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
2456 | /* frames_transmitted_256_511_bytes */ | |
2457 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
2458 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
2459 | /* frames_transmitted_512_1023_bytes */ | |
2460 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
2461 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
2462 | /* frames_transmitted_1024_1522_bytes */ | |
2463 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
2464 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
2465 | /* frames_transmitted_1523_9022_bytes */ | |
2466 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
2467 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
2468 | u32 tx_stat_mac_2047_hi; | |
2469 | u32 tx_stat_mac_2047_lo; | |
2470 | u32 tx_stat_mac_4095_hi; | |
2471 | u32 tx_stat_mac_4095_lo; | |
2472 | u32 tx_stat_mac_9216_hi; | |
2473 | u32 tx_stat_mac_9216_lo; | |
2474 | u32 tx_stat_mac_16383_hi; | |
2475 | u32 tx_stat_mac_16383_lo; | |
2476 | ||
2477 | /* internal_mac_transmit_errors */ | |
2478 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
2479 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
2480 | ||
2481 | /* if_out_discards */ | |
2482 | u32 tx_stat_mac_ufl_hi; | |
2483 | u32 tx_stat_mac_ufl_lo; | |
2484 | }; | |
2485 | ||
2486 | ||
2487 | #define MAC_STX_IDX_MAX 2 | |
bb2a0f7a YG |
2488 | |
2489 | struct host_port_stats { | |
619c5cb6 | 2490 | u32 host_port_stats_start; |
bb2a0f7a | 2491 | |
619c5cb6 | 2492 | struct mac_stx mac_stx[MAC_STX_IDX_MAX]; |
bb2a0f7a | 2493 | |
619c5cb6 VZ |
2494 | u32 brb_drop_hi; |
2495 | u32 brb_drop_lo; | |
bb2a0f7a | 2496 | |
619c5cb6 | 2497 | u32 host_port_stats_end; |
bb2a0f7a YG |
2498 | }; |
2499 | ||
2500 | ||
2501 | struct host_func_stats { | |
619c5cb6 | 2502 | u32 host_func_stats_start; |
bb2a0f7a | 2503 | |
619c5cb6 VZ |
2504 | u32 total_bytes_received_hi; |
2505 | u32 total_bytes_received_lo; | |
bb2a0f7a | 2506 | |
619c5cb6 VZ |
2507 | u32 total_bytes_transmitted_hi; |
2508 | u32 total_bytes_transmitted_lo; | |
bb2a0f7a | 2509 | |
619c5cb6 VZ |
2510 | u32 total_unicast_packets_received_hi; |
2511 | u32 total_unicast_packets_received_lo; | |
bb2a0f7a | 2512 | |
619c5cb6 VZ |
2513 | u32 total_multicast_packets_received_hi; |
2514 | u32 total_multicast_packets_received_lo; | |
bb2a0f7a | 2515 | |
619c5cb6 VZ |
2516 | u32 total_broadcast_packets_received_hi; |
2517 | u32 total_broadcast_packets_received_lo; | |
bb2a0f7a | 2518 | |
619c5cb6 VZ |
2519 | u32 total_unicast_packets_transmitted_hi; |
2520 | u32 total_unicast_packets_transmitted_lo; | |
bb2a0f7a | 2521 | |
619c5cb6 VZ |
2522 | u32 total_multicast_packets_transmitted_hi; |
2523 | u32 total_multicast_packets_transmitted_lo; | |
bb2a0f7a | 2524 | |
619c5cb6 VZ |
2525 | u32 total_broadcast_packets_transmitted_hi; |
2526 | u32 total_broadcast_packets_transmitted_lo; | |
bb2a0f7a | 2527 | |
619c5cb6 VZ |
2528 | u32 valid_bytes_received_hi; |
2529 | u32 valid_bytes_received_lo; | |
bb2a0f7a | 2530 | |
619c5cb6 | 2531 | u32 host_func_stats_end; |
bb2a0f7a | 2532 | }; |
34f80b04 | 2533 | |
619c5cb6 VZ |
2534 | /* VIC definitions */ |
2535 | #define VICSTATST_UIF_INDEX 2 | |
34f80b04 | 2536 | |
619c5cb6 VZ |
2537 | #define BCM_5710_FW_MAJOR_VERSION 7 |
2538 | #define BCM_5710_FW_MINOR_VERSION 0 | |
2539 | #define BCM_5710_FW_REVISION_VERSION 20 | |
2540 | #define BCM_5710_FW_ENGINEERING_VERSION 0 | |
a2fbb9ea ET |
2541 | #define BCM_5710_FW_COMPILE_FLAGS 1 |
2542 | ||
2543 | ||
2544 | /* | |
2545 | * attention bits | |
2546 | */ | |
523224a3 | 2547 | struct atten_sp_status_block { |
4781bfad EG |
2548 | __le32 attn_bits; |
2549 | __le32 attn_bits_ack; | |
a2fbb9ea ET |
2550 | u8 status_block_id; |
2551 | u8 reserved0; | |
4781bfad EG |
2552 | __le16 attn_bits_index; |
2553 | __le32 reserved1; | |
a2fbb9ea ET |
2554 | }; |
2555 | ||
2556 | ||
2557 | /* | |
619c5cb6 | 2558 | * The eth aggregative context of Cstorm |
a2fbb9ea | 2559 | */ |
619c5cb6 VZ |
2560 | struct cstorm_eth_ag_context { |
2561 | u32 __reserved0[10]; | |
a2fbb9ea ET |
2562 | }; |
2563 | ||
619c5cb6 | 2564 | |
a2fbb9ea | 2565 | /* |
619c5cb6 | 2566 | * dmae command structure |
a2fbb9ea | 2567 | */ |
619c5cb6 VZ |
2568 | struct dmae_command { |
2569 | u32 opcode; | |
2570 | #define DMAE_COMMAND_SRC (0x1<<0) | |
2571 | #define DMAE_COMMAND_SRC_SHIFT 0 | |
2572 | #define DMAE_COMMAND_DST (0x3<<1) | |
2573 | #define DMAE_COMMAND_DST_SHIFT 1 | |
2574 | #define DMAE_COMMAND_C_DST (0x1<<3) | |
2575 | #define DMAE_COMMAND_C_DST_SHIFT 3 | |
2576 | #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) | |
2577 | #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 | |
2578 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) | |
2579 | #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 | |
2580 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) | |
2581 | #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 | |
2582 | #define DMAE_COMMAND_ENDIANITY (0x3<<9) | |
2583 | #define DMAE_COMMAND_ENDIANITY_SHIFT 9 | |
2584 | #define DMAE_COMMAND_PORT (0x1<<11) | |
2585 | #define DMAE_COMMAND_PORT_SHIFT 11 | |
2586 | #define DMAE_COMMAND_CRC_RESET (0x1<<12) | |
2587 | #define DMAE_COMMAND_CRC_RESET_SHIFT 12 | |
2588 | #define DMAE_COMMAND_SRC_RESET (0x1<<13) | |
2589 | #define DMAE_COMMAND_SRC_RESET_SHIFT 13 | |
2590 | #define DMAE_COMMAND_DST_RESET (0x1<<14) | |
2591 | #define DMAE_COMMAND_DST_RESET_SHIFT 14 | |
2592 | #define DMAE_COMMAND_E1HVN (0x3<<15) | |
2593 | #define DMAE_COMMAND_E1HVN_SHIFT 15 | |
2594 | #define DMAE_COMMAND_DST_VN (0x3<<17) | |
2595 | #define DMAE_COMMAND_DST_VN_SHIFT 17 | |
2596 | #define DMAE_COMMAND_C_FUNC (0x1<<19) | |
2597 | #define DMAE_COMMAND_C_FUNC_SHIFT 19 | |
2598 | #define DMAE_COMMAND_ERR_POLICY (0x3<<20) | |
2599 | #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 | |
2600 | #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) | |
2601 | #define DMAE_COMMAND_RESERVED0_SHIFT 22 | |
2602 | u32 src_addr_lo; | |
2603 | u32 src_addr_hi; | |
2604 | u32 dst_addr_lo; | |
2605 | u32 dst_addr_hi; | |
a2fbb9ea | 2606 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
2607 | u16 opcode_iov; |
2608 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2609 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2610 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2611 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2612 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2613 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2614 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2615 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2616 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2617 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2618 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2619 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
2620 | u16 len; | |
a2fbb9ea | 2621 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
2622 | u16 len; |
2623 | u16 opcode_iov; | |
2624 | #define DMAE_COMMAND_SRC_VFID (0x3F<<0) | |
2625 | #define DMAE_COMMAND_SRC_VFID_SHIFT 0 | |
2626 | #define DMAE_COMMAND_SRC_VFPF (0x1<<6) | |
2627 | #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 | |
2628 | #define DMAE_COMMAND_RESERVED1 (0x1<<7) | |
2629 | #define DMAE_COMMAND_RESERVED1_SHIFT 7 | |
2630 | #define DMAE_COMMAND_DST_VFID (0x3F<<8) | |
2631 | #define DMAE_COMMAND_DST_VFID_SHIFT 8 | |
2632 | #define DMAE_COMMAND_DST_VFPF (0x1<<14) | |
2633 | #define DMAE_COMMAND_DST_VFPF_SHIFT 14 | |
2634 | #define DMAE_COMMAND_RESERVED2 (0x1<<15) | |
2635 | #define DMAE_COMMAND_RESERVED2_SHIFT 15 | |
a2fbb9ea | 2636 | #endif |
619c5cb6 VZ |
2637 | u32 comp_addr_lo; |
2638 | u32 comp_addr_hi; | |
2639 | u32 comp_val; | |
2640 | u32 crc32; | |
2641 | u32 crc32_c; | |
2642 | #if defined(__BIG_ENDIAN) | |
2643 | u16 crc16_c; | |
2644 | u16 crc16; | |
2645 | #elif defined(__LITTLE_ENDIAN) | |
2646 | u16 crc16; | |
2647 | u16 crc16_c; | |
2648 | #endif | |
2649 | #if defined(__BIG_ENDIAN) | |
2650 | u16 reserved3; | |
2651 | u16 crc_t10; | |
2652 | #elif defined(__LITTLE_ENDIAN) | |
2653 | u16 crc_t10; | |
2654 | u16 reserved3; | |
2655 | #endif | |
2656 | #if defined(__BIG_ENDIAN) | |
2657 | u16 xsum8; | |
2658 | u16 xsum16; | |
2659 | #elif defined(__LITTLE_ENDIAN) | |
2660 | u16 xsum16; | |
2661 | u16 xsum8; | |
2662 | #endif | |
2663 | }; | |
2664 | ||
2665 | ||
ca00392c | 2666 | /* |
619c5cb6 | 2667 | * common data for all protocols |
ca00392c | 2668 | */ |
619c5cb6 VZ |
2669 | struct doorbell_hdr { |
2670 | u8 header; | |
2671 | #define DOORBELL_HDR_RX (0x1<<0) | |
2672 | #define DOORBELL_HDR_RX_SHIFT 0 | |
2673 | #define DOORBELL_HDR_DB_TYPE (0x1<<1) | |
2674 | #define DOORBELL_HDR_DB_TYPE_SHIFT 1 | |
2675 | #define DOORBELL_HDR_DPM_SIZE (0x3<<2) | |
2676 | #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 | |
2677 | #define DOORBELL_HDR_CONN_TYPE (0xF<<4) | |
2678 | #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 | |
2679 | }; | |
2680 | ||
2681 | /* | |
2682 | * Ethernet doorbell | |
2683 | */ | |
2684 | struct eth_tx_doorbell { | |
ca00392c | 2685 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
2686 | u16 npackets; |
2687 | u8 params; | |
2688 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
2689 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
2690 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
2691 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
2692 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
2693 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
2694 | struct doorbell_hdr hdr; | |
ca00392c | 2695 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
2696 | struct doorbell_hdr hdr; |
2697 | u8 params; | |
2698 | #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) | |
2699 | #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 | |
2700 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) | |
2701 | #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 | |
2702 | #define ETH_TX_DOORBELL_SPARE (0x1<<7) | |
2703 | #define ETH_TX_DOORBELL_SPARE_SHIFT 7 | |
2704 | u16 npackets; | |
ca00392c EG |
2705 | #endif |
2706 | }; | |
2707 | ||
2708 | ||
a2fbb9ea | 2709 | /* |
523224a3 DK |
2710 | * 3 lines. status block |
2711 | */ | |
2712 | struct hc_status_block_e1x { | |
2713 | __le16 index_values[HC_SB_MAX_INDICES_E1X]; | |
2714 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 2715 | __le32 rsrv[11]; |
523224a3 DK |
2716 | }; |
2717 | ||
2718 | /* | |
2719 | * host status block | |
2720 | */ | |
2721 | struct host_hc_status_block_e1x { | |
2722 | struct hc_status_block_e1x sb; | |
2723 | }; | |
2724 | ||
2725 | ||
2726 | /* | |
2727 | * 3 lines. status block | |
2728 | */ | |
2729 | struct hc_status_block_e2 { | |
2730 | __le16 index_values[HC_SB_MAX_INDICES_E2]; | |
2731 | __le16 running_index[HC_SB_MAX_SM]; | |
619c5cb6 | 2732 | __le32 reserved[11]; |
523224a3 DK |
2733 | }; |
2734 | ||
2735 | /* | |
2736 | * host status block | |
2737 | */ | |
2738 | struct host_hc_status_block_e2 { | |
2739 | struct hc_status_block_e2 sb; | |
2740 | }; | |
2741 | ||
2742 | ||
2743 | /* | |
2744 | * 5 lines. slow-path status block | |
2745 | */ | |
2746 | struct hc_sp_status_block { | |
2747 | __le16 index_values[HC_SP_SB_MAX_INDICES]; | |
2748 | __le16 running_index; | |
2749 | __le16 rsrv; | |
2750 | u32 rsrv1; | |
2751 | }; | |
2752 | ||
2753 | /* | |
2754 | * host status block | |
2755 | */ | |
2756 | struct host_sp_status_block { | |
2757 | struct atten_sp_status_block atten_status_block; | |
2758 | struct hc_sp_status_block sp_sb; | |
2759 | }; | |
2760 | ||
2761 | ||
2762 | /* | |
2763 | * IGU driver acknowledgment register | |
a2fbb9ea ET |
2764 | */ |
2765 | struct igu_ack_register { | |
2766 | #if defined(__BIG_ENDIAN) | |
2767 | u16 sb_id_and_flags; | |
2768 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
2769 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
2770 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
2771 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
2772 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
2773 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
2774 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
2775 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
2776 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
2777 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
2778 | u16 status_block_index; | |
2779 | #elif defined(__LITTLE_ENDIAN) | |
2780 | u16 status_block_index; | |
2781 | u16 sb_id_and_flags; | |
2782 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) | |
2783 | #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 | |
2784 | #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) | |
2785 | #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 | |
2786 | #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) | |
2787 | #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 | |
2788 | #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) | |
2789 | #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 | |
2790 | #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) | |
2791 | #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 | |
2792 | #endif | |
2793 | }; | |
2794 | ||
2795 | ||
ca00392c EG |
2796 | /* |
2797 | * IGU driver acknowledgement register | |
2798 | */ | |
2799 | struct igu_backward_compatible { | |
2800 | u32 sb_id_and_flags; | |
2801 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) | |
2802 | #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 | |
2803 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) | |
2804 | #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 | |
2805 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) | |
2806 | #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 | |
2807 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) | |
2808 | #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 | |
2809 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) | |
2810 | #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 | |
2811 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) | |
2812 | #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 | |
2813 | u32 reserved_2; | |
2814 | }; | |
2815 | ||
2816 | ||
2817 | /* | |
2818 | * IGU driver acknowledgement register | |
2819 | */ | |
2820 | struct igu_regular { | |
2821 | u32 sb_id_and_flags; | |
2822 | #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) | |
2823 | #define IGU_REGULAR_SB_INDEX_SHIFT 0 | |
2824 | #define IGU_REGULAR_RESERVED0 (0x1<<20) | |
2825 | #define IGU_REGULAR_RESERVED0_SHIFT 20 | |
2826 | #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) | |
2827 | #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 | |
2828 | #define IGU_REGULAR_BUPDATE (0x1<<24) | |
2829 | #define IGU_REGULAR_BUPDATE_SHIFT 24 | |
2830 | #define IGU_REGULAR_ENABLE_INT (0x3<<25) | |
2831 | #define IGU_REGULAR_ENABLE_INT_SHIFT 25 | |
2832 | #define IGU_REGULAR_RESERVED_1 (0x1<<27) | |
2833 | #define IGU_REGULAR_RESERVED_1_SHIFT 27 | |
2834 | #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) | |
2835 | #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 | |
2836 | #define IGU_REGULAR_CLEANUP_SET (0x1<<30) | |
2837 | #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 | |
2838 | #define IGU_REGULAR_BCLEANUP (0x1<<31) | |
2839 | #define IGU_REGULAR_BCLEANUP_SHIFT 31 | |
2840 | u32 reserved_2; | |
2841 | }; | |
2842 | ||
2843 | /* | |
2844 | * IGU driver acknowledgement register | |
2845 | */ | |
2846 | union igu_consprod_reg { | |
2847 | struct igu_regular regular; | |
2848 | struct igu_backward_compatible backward_compatible; | |
2849 | }; | |
2850 | ||
2851 | ||
619c5cb6 VZ |
2852 | /* |
2853 | * Igu control commands | |
2854 | */ | |
2855 | enum igu_ctrl_cmd { | |
2856 | IGU_CTRL_CMD_TYPE_RD, | |
2857 | IGU_CTRL_CMD_TYPE_WR, | |
2858 | MAX_IGU_CTRL_CMD | |
2859 | }; | |
2860 | ||
2861 | ||
f2e0899f DK |
2862 | /* |
2863 | * Control register for the IGU command register | |
2864 | */ | |
2865 | struct igu_ctrl_reg { | |
2866 | u32 ctrl_data; | |
2867 | #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) | |
2868 | #define IGU_CTRL_REG_ADDRESS_SHIFT 0 | |
2869 | #define IGU_CTRL_REG_FID (0x7F<<12) | |
2870 | #define IGU_CTRL_REG_FID_SHIFT 12 | |
2871 | #define IGU_CTRL_REG_RESERVED (0x1<<19) | |
2872 | #define IGU_CTRL_REG_RESERVED_SHIFT 19 | |
2873 | #define IGU_CTRL_REG_TYPE (0x1<<20) | |
2874 | #define IGU_CTRL_REG_TYPE_SHIFT 20 | |
2875 | #define IGU_CTRL_REG_UNUSED (0x7FF<<21) | |
2876 | #define IGU_CTRL_REG_UNUSED_SHIFT 21 | |
2877 | }; | |
2878 | ||
2879 | ||
619c5cb6 VZ |
2880 | /* |
2881 | * Igu interrupt command | |
2882 | */ | |
2883 | enum igu_int_cmd { | |
2884 | IGU_INT_ENABLE, | |
2885 | IGU_INT_DISABLE, | |
2886 | IGU_INT_NOP, | |
2887 | IGU_INT_NOP2, | |
2888 | MAX_IGU_INT_CMD | |
2889 | }; | |
2890 | ||
2891 | ||
2892 | /* | |
2893 | * Igu segments | |
2894 | */ | |
2895 | enum igu_seg_access { | |
2896 | IGU_SEG_ACCESS_NORM, | |
2897 | IGU_SEG_ACCESS_DEF, | |
2898 | IGU_SEG_ACCESS_ATTN, | |
2899 | MAX_IGU_SEG_ACCESS | |
2900 | }; | |
2901 | ||
2902 | ||
a2fbb9ea ET |
2903 | /* |
2904 | * Parser parsing flags field | |
2905 | */ | |
2906 | struct parsing_flags { | |
4781bfad | 2907 | __le16 flags; |
a2fbb9ea ET |
2908 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) |
2909 | #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 | |
34f80b04 EG |
2910 | #define PARSING_FLAGS_VLAN (0x1<<1) |
2911 | #define PARSING_FLAGS_VLAN_SHIFT 1 | |
2912 | #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) | |
2913 | #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 | |
a2fbb9ea ET |
2914 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) |
2915 | #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 | |
2916 | #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) | |
2917 | #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 | |
2918 | #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) | |
2919 | #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 | |
2920 | #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) | |
2921 | #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 | |
2922 | #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) | |
2923 | #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 | |
2924 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) | |
2925 | #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 | |
2926 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) | |
2927 | #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 | |
2928 | #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) | |
2929 | #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 | |
2930 | #define PARSING_FLAGS_LLC_SNAP (0x1<<13) | |
2931 | #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 | |
2932 | #define PARSING_FLAGS_RESERVED0 (0x3<<14) | |
2933 | #define PARSING_FLAGS_RESERVED0_SHIFT 14 | |
2934 | }; | |
2935 | ||
2936 | ||
619c5cb6 VZ |
2937 | /* |
2938 | * Parsing flags for TCP ACK type | |
2939 | */ | |
2940 | enum prs_flags_ack_type { | |
2941 | PRS_FLAG_PUREACK_PIGGY, | |
2942 | PRS_FLAG_PUREACK_PURE, | |
2943 | MAX_PRS_FLAGS_ACK_TYPE | |
34f80b04 EG |
2944 | }; |
2945 | ||
2946 | ||
a2fbb9ea | 2947 | /* |
619c5cb6 | 2948 | * Parsing flags for Ethernet address type |
a2fbb9ea | 2949 | */ |
619c5cb6 VZ |
2950 | enum prs_flags_eth_addr_type { |
2951 | PRS_FLAG_ETHTYPE_NON_UNICAST, | |
2952 | PRS_FLAG_ETHTYPE_UNICAST, | |
2953 | MAX_PRS_FLAGS_ETH_ADDR_TYPE | |
a2fbb9ea ET |
2954 | }; |
2955 | ||
2956 | ||
619c5cb6 VZ |
2957 | /* |
2958 | * Parsing flags for over-ethernet protocol | |
2959 | */ | |
2960 | enum prs_flags_over_eth { | |
2961 | PRS_FLAG_OVERETH_UNKNOWN, | |
2962 | PRS_FLAG_OVERETH_IPV4, | |
2963 | PRS_FLAG_OVERETH_IPV6, | |
2964 | PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, | |
2965 | MAX_PRS_FLAGS_OVER_ETH | |
2966 | }; | |
2967 | ||
2968 | ||
2969 | /* | |
2970 | * Parsing flags for over-IP protocol | |
2971 | */ | |
2972 | enum prs_flags_over_ip { | |
2973 | PRS_FLAG_OVERIP_UNKNOWN, | |
2974 | PRS_FLAG_OVERIP_TCP, | |
2975 | PRS_FLAG_OVERIP_UDP, | |
2976 | MAX_PRS_FLAGS_OVER_IP | |
a2fbb9ea ET |
2977 | }; |
2978 | ||
2979 | ||
2980 | /* | |
523224a3 | 2981 | * SDM operation gen command (generate aggregative interrupt) |
a2fbb9ea | 2982 | */ |
523224a3 DK |
2983 | struct sdm_op_gen { |
2984 | __le32 command; | |
2985 | #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) | |
2986 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
2987 | #define SDM_OP_GEN_COMP_TYPE (0x7<<5) | |
2988 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 | |
2989 | #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) | |
2990 | #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 | |
2991 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) | |
2992 | #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 | |
2993 | #define SDM_OP_GEN_RESERVED (0x7FFF<<17) | |
2994 | #define SDM_OP_GEN_RESERVED_SHIFT 17 | |
34f80b04 EG |
2995 | }; |
2996 | ||
34f80b04 EG |
2997 | |
2998 | /* | |
619c5cb6 | 2999 | * Timers connection context |
34f80b04 | 3000 | */ |
619c5cb6 VZ |
3001 | struct timers_block_context { |
3002 | u32 __reserved_0; | |
3003 | u32 __reserved_1; | |
3004 | u32 __reserved_2; | |
3005 | u32 flags; | |
3006 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) | |
3007 | #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 | |
3008 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) | |
3009 | #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 | |
3010 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) | |
3011 | #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 | |
34f80b04 EG |
3012 | }; |
3013 | ||
523224a3 | 3014 | |
34f80b04 | 3015 | /* |
619c5cb6 | 3016 | * The eth aggregative context of Tstorm |
34f80b04 | 3017 | */ |
619c5cb6 VZ |
3018 | struct tstorm_eth_ag_context { |
3019 | u32 __reserved0[14]; | |
a2fbb9ea ET |
3020 | }; |
3021 | ||
619c5cb6 | 3022 | |
a2fbb9ea | 3023 | /* |
619c5cb6 | 3024 | * The eth aggregative context of Ustorm |
a2fbb9ea | 3025 | */ |
619c5cb6 VZ |
3026 | struct ustorm_eth_ag_context { |
3027 | u32 __reserved0; | |
3028 | #if defined(__BIG_ENDIAN) | |
3029 | u8 cdu_usage; | |
3030 | u8 __reserved2; | |
3031 | u16 __reserved1; | |
3032 | #elif defined(__LITTLE_ENDIAN) | |
3033 | u16 __reserved1; | |
3034 | u8 __reserved2; | |
3035 | u8 cdu_usage; | |
3036 | #endif | |
3037 | u32 __reserved3[6]; | |
a2fbb9ea ET |
3038 | }; |
3039 | ||
619c5cb6 | 3040 | |
a2fbb9ea ET |
3041 | /* |
3042 | * The eth aggregative context of Xstorm | |
3043 | */ | |
3044 | struct xstorm_eth_ag_context { | |
523224a3 | 3045 | u32 reserved0; |
a2fbb9ea ET |
3046 | #if defined(__BIG_ENDIAN) |
3047 | u8 cdu_reserved; | |
523224a3 DK |
3048 | u8 reserved2; |
3049 | u16 reserved1; | |
a2fbb9ea | 3050 | #elif defined(__LITTLE_ENDIAN) |
523224a3 DK |
3051 | u16 reserved1; |
3052 | u8 reserved2; | |
a2fbb9ea ET |
3053 | u8 cdu_reserved; |
3054 | #endif | |
523224a3 | 3055 | u32 reserved3[30]; |
a2fbb9ea ET |
3056 | }; |
3057 | ||
523224a3 | 3058 | |
a2fbb9ea | 3059 | /* |
619c5cb6 | 3060 | * doorbell message sent to the chip |
a2fbb9ea | 3061 | */ |
619c5cb6 VZ |
3062 | struct doorbell { |
3063 | #if defined(__BIG_ENDIAN) | |
3064 | u16 zero_fill2; | |
3065 | u8 zero_fill1; | |
3066 | struct doorbell_hdr header; | |
3067 | #elif defined(__LITTLE_ENDIAN) | |
3068 | struct doorbell_hdr header; | |
3069 | u8 zero_fill1; | |
3070 | u16 zero_fill2; | |
3071 | #endif | |
a2fbb9ea ET |
3072 | }; |
3073 | ||
523224a3 | 3074 | |
a2fbb9ea | 3075 | /* |
619c5cb6 | 3076 | * doorbell message sent to the chip |
a2fbb9ea | 3077 | */ |
619c5cb6 | 3078 | struct doorbell_set_prod { |
a2fbb9ea | 3079 | #if defined(__BIG_ENDIAN) |
619c5cb6 VZ |
3080 | u16 prod; |
3081 | u8 zero_fill1; | |
3082 | struct doorbell_hdr header; | |
a2fbb9ea | 3083 | #elif defined(__LITTLE_ENDIAN) |
619c5cb6 VZ |
3084 | struct doorbell_hdr header; |
3085 | u8 zero_fill1; | |
3086 | u16 prod; | |
a2fbb9ea | 3087 | #endif |
a2fbb9ea ET |
3088 | }; |
3089 | ||
619c5cb6 VZ |
3090 | |
3091 | struct regpair { | |
3092 | __le32 lo; | |
3093 | __le32 hi; | |
3094 | }; | |
3095 | ||
3096 | ||
a2fbb9ea | 3097 | /* |
619c5cb6 | 3098 | * Classify rule opcodes in E2/E3 |
a2fbb9ea | 3099 | */ |
619c5cb6 VZ |
3100 | enum classify_rule { |
3101 | CLASSIFY_RULE_OPCODE_MAC, | |
3102 | CLASSIFY_RULE_OPCODE_VLAN, | |
3103 | CLASSIFY_RULE_OPCODE_PAIR, | |
3104 | MAX_CLASSIFY_RULE | |
a2fbb9ea ET |
3105 | }; |
3106 | ||
619c5cb6 | 3107 | |
a2fbb9ea | 3108 | /* |
619c5cb6 | 3109 | * Classify rule types in E2/E3 |
a2fbb9ea | 3110 | */ |
619c5cb6 VZ |
3111 | enum classify_rule_action_type { |
3112 | CLASSIFY_RULE_REMOVE, | |
3113 | CLASSIFY_RULE_ADD, | |
3114 | MAX_CLASSIFY_RULE_ACTION_TYPE | |
a2fbb9ea ET |
3115 | }; |
3116 | ||
619c5cb6 | 3117 | |
a2fbb9ea | 3118 | /* |
619c5cb6 | 3119 | * client init ramrod data |
a2fbb9ea | 3120 | */ |
619c5cb6 VZ |
3121 | struct client_init_general_data { |
3122 | u8 client_id; | |
3123 | u8 statistics_counter_id; | |
3124 | u8 statistics_en_flg; | |
3125 | u8 is_fcoe_flg; | |
3126 | u8 activate_flg; | |
3127 | u8 sp_client_id; | |
3128 | __le16 mtu; | |
3129 | u8 statistics_zero_flg; | |
3130 | u8 func_id; | |
3131 | u8 cos; | |
3132 | u8 traffic_type; | |
3133 | u32 reserved0; | |
ca00392c EG |
3134 | }; |
3135 | ||
619c5cb6 | 3136 | |
ca00392c | 3137 | /* |
619c5cb6 | 3138 | * client init rx data |
ca00392c | 3139 | */ |
619c5cb6 VZ |
3140 | struct client_init_rx_data { |
3141 | u8 tpa_en; | |
3142 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) | |
3143 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 | |
3144 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) | |
3145 | #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 | |
3146 | #define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2) | |
3147 | #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2 | |
3148 | u8 vmqueue_mode_en_flg; | |
3149 | u8 extra_data_over_sgl_en_flg; | |
3150 | u8 cache_line_alignment_log_size; | |
3151 | u8 enable_dynamic_hc; | |
3152 | u8 max_sges_for_packet; | |
3153 | u8 client_qzone_id; | |
3154 | u8 drop_ip_cs_err_flg; | |
3155 | u8 drop_tcp_cs_err_flg; | |
3156 | u8 drop_ttl0_flg; | |
3157 | u8 drop_udp_cs_err_flg; | |
3158 | u8 inner_vlan_removal_enable_flg; | |
3159 | u8 outer_vlan_removal_enable_flg; | |
3160 | u8 status_block_id; | |
3161 | u8 rx_sb_index_number; | |
3162 | u8 reserved0; | |
3163 | u8 max_tpa_queues; | |
3164 | u8 silent_vlan_removal_flg; | |
3165 | __le16 max_bytes_on_bd; | |
3166 | __le16 sge_buff_size; | |
3167 | u8 approx_mcast_engine_id; | |
3168 | u8 rss_engine_id; | |
3169 | struct regpair bd_page_base; | |
3170 | struct regpair sge_page_base; | |
3171 | struct regpair cqe_page_base; | |
3172 | u8 is_leading_rss; | |
3173 | u8 is_approx_mcast; | |
3174 | __le16 max_agg_size; | |
3175 | __le16 state; | |
3176 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) | |
3177 | #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 | |
3178 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) | |
3179 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 | |
3180 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3181 | #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3182 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) | |
3183 | #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 | |
3184 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) | |
3185 | #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 | |
3186 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) | |
3187 | #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 | |
3188 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) | |
3189 | #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 | |
3190 | #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) | |
3191 | #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 | |
3192 | __le16 cqe_pause_thr_low; | |
3193 | __le16 cqe_pause_thr_high; | |
3194 | __le16 bd_pause_thr_low; | |
3195 | __le16 bd_pause_thr_high; | |
3196 | __le16 sge_pause_thr_low; | |
3197 | __le16 sge_pause_thr_high; | |
3198 | __le16 rx_cos_mask; | |
3199 | __le16 silent_vlan_value; | |
3200 | __le16 silent_vlan_mask; | |
3201 | __le32 reserved6[2]; | |
a2fbb9ea ET |
3202 | }; |
3203 | ||
3204 | /* | |
619c5cb6 | 3205 | * client init tx data |
a2fbb9ea | 3206 | */ |
619c5cb6 VZ |
3207 | struct client_init_tx_data { |
3208 | u8 enforce_security_flg; | |
3209 | u8 tx_status_block_id; | |
3210 | u8 tx_sb_index_number; | |
3211 | u8 tss_leading_client_id; | |
3212 | u8 tx_switching_flg; | |
3213 | u8 anti_spoofing_flg; | |
3214 | __le16 default_vlan; | |
3215 | struct regpair tx_bd_page_base; | |
3216 | __le16 state; | |
3217 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) | |
3218 | #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 | |
3219 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) | |
3220 | #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 | |
3221 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) | |
3222 | #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 | |
3223 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) | |
3224 | #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 | |
3225 | #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) | |
3226 | #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 | |
3227 | u8 default_vlan_flg; | |
3228 | u8 reserved2; | |
3229 | __le32 reserved3; | |
a2fbb9ea ET |
3230 | }; |
3231 | ||
f2e0899f | 3232 | /* |
619c5cb6 | 3233 | * client init ramrod data |
f2e0899f | 3234 | */ |
619c5cb6 VZ |
3235 | struct client_init_ramrod_data { |
3236 | struct client_init_general_data general; | |
3237 | struct client_init_rx_data rx; | |
3238 | struct client_init_tx_data tx; | |
f2e0899f DK |
3239 | }; |
3240 | ||
619c5cb6 | 3241 | |
a2fbb9ea | 3242 | /* |
619c5cb6 | 3243 | * client update ramrod data |
a2fbb9ea | 3244 | */ |
619c5cb6 VZ |
3245 | struct client_update_ramrod_data { |
3246 | u8 client_id; | |
3247 | u8 func_id; | |
3248 | u8 inner_vlan_removal_enable_flg; | |
3249 | u8 inner_vlan_removal_change_flg; | |
3250 | u8 outer_vlan_removal_enable_flg; | |
3251 | u8 outer_vlan_removal_change_flg; | |
3252 | u8 anti_spoofing_enable_flg; | |
3253 | u8 anti_spoofing_change_flg; | |
3254 | u8 activate_flg; | |
3255 | u8 activate_change_flg; | |
3256 | __le16 default_vlan; | |
3257 | u8 default_vlan_enable_flg; | |
3258 | u8 default_vlan_change_flg; | |
3259 | __le16 silent_vlan_value; | |
3260 | __le16 silent_vlan_mask; | |
3261 | u8 silent_vlan_removal_flg; | |
3262 | u8 silent_vlan_change_flg; | |
3263 | __le32 echo; | |
a2fbb9ea ET |
3264 | }; |
3265 | ||
619c5cb6 | 3266 | |
a2fbb9ea | 3267 | /* |
619c5cb6 | 3268 | * The eth storm context of Cstorm |
a2fbb9ea | 3269 | */ |
619c5cb6 VZ |
3270 | struct cstorm_eth_st_context { |
3271 | u32 __reserved0[4]; | |
3272 | }; | |
3273 | ||
3274 | ||
3275 | struct double_regpair { | |
3276 | u32 regpair0_lo; | |
3277 | u32 regpair0_hi; | |
3278 | u32 regpair1_lo; | |
3279 | u32 regpair1_hi; | |
a2fbb9ea ET |
3280 | }; |
3281 | ||
523224a3 | 3282 | |
a2fbb9ea | 3283 | /* |
619c5cb6 | 3284 | * Ethernet address typesm used in ethernet tx BDs |
a2fbb9ea | 3285 | */ |
619c5cb6 VZ |
3286 | enum eth_addr_type { |
3287 | UNKNOWN_ADDRESS, | |
3288 | UNICAST_ADDRESS, | |
3289 | MULTICAST_ADDRESS, | |
3290 | BROADCAST_ADDRESS, | |
3291 | MAX_ETH_ADDR_TYPE | |
a2fbb9ea ET |
3292 | }; |
3293 | ||
619c5cb6 | 3294 | |
a2fbb9ea | 3295 | /* |
619c5cb6 | 3296 | * |
a2fbb9ea | 3297 | */ |
619c5cb6 VZ |
3298 | struct eth_classify_cmd_header { |
3299 | u8 cmd_general_data; | |
3300 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) | |
3301 | #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 | |
3302 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) | |
3303 | #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 | |
3304 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) | |
3305 | #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 | |
3306 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) | |
3307 | #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 | |
3308 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) | |
3309 | #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 | |
3310 | u8 func_id; | |
3311 | u8 client_id; | |
3312 | u8 reserved1; | |
a2fbb9ea ET |
3313 | }; |
3314 | ||
619c5cb6 | 3315 | |
a2fbb9ea | 3316 | /* |
619c5cb6 | 3317 | * header for eth classification config ramrod |
a2fbb9ea | 3318 | */ |
619c5cb6 VZ |
3319 | struct eth_classify_header { |
3320 | u8 rule_cnt; | |
3321 | u8 reserved0; | |
3322 | __le16 reserved1; | |
3323 | __le32 echo; | |
a2fbb9ea ET |
3324 | }; |
3325 | ||
3326 | ||
3327 | /* | |
619c5cb6 | 3328 | * Command for adding/removing a MAC classification rule |
a2fbb9ea | 3329 | */ |
619c5cb6 VZ |
3330 | struct eth_classify_mac_cmd { |
3331 | struct eth_classify_cmd_header header; | |
3332 | __le32 reserved0; | |
3333 | __le16 mac_lsb; | |
3334 | __le16 mac_mid; | |
3335 | __le16 mac_msb; | |
3336 | __le16 reserved1; | |
3337 | }; | |
3338 | ||
3339 | ||
3340 | /* | |
3341 | * Command for adding/removing a MAC-VLAN pair classification rule | |
3342 | */ | |
3343 | struct eth_classify_pair_cmd { | |
3344 | struct eth_classify_cmd_header header; | |
3345 | __le32 reserved0; | |
3346 | __le16 mac_lsb; | |
3347 | __le16 mac_mid; | |
3348 | __le16 mac_msb; | |
3349 | __le16 vlan; | |
3350 | }; | |
3351 | ||
3352 | ||
3353 | /* | |
3354 | * Command for adding/removing a VLAN classification rule | |
3355 | */ | |
3356 | struct eth_classify_vlan_cmd { | |
3357 | struct eth_classify_cmd_header header; | |
3358 | __le32 reserved0; | |
3359 | __le32 reserved1; | |
3360 | __le16 reserved2; | |
3361 | __le16 vlan; | |
a2fbb9ea ET |
3362 | }; |
3363 | ||
619c5cb6 VZ |
3364 | /* |
3365 | * union for eth classification rule | |
3366 | */ | |
3367 | union eth_classify_rule_cmd { | |
3368 | struct eth_classify_mac_cmd mac; | |
3369 | struct eth_classify_vlan_cmd vlan; | |
3370 | struct eth_classify_pair_cmd pair; | |
3371 | }; | |
a2fbb9ea ET |
3372 | |
3373 | /* | |
619c5cb6 | 3374 | * parameters for eth classification configuration ramrod |
a2fbb9ea | 3375 | */ |
619c5cb6 VZ |
3376 | struct eth_classify_rules_ramrod_data { |
3377 | struct eth_classify_header header; | |
3378 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3379 | }; |
3380 | ||
a2fbb9ea ET |
3381 | |
3382 | /* | |
619c5cb6 | 3383 | * The data contain client ID need to the ramrod |
a2fbb9ea | 3384 | */ |
619c5cb6 VZ |
3385 | struct eth_common_ramrod_data { |
3386 | __le32 client_id; | |
3387 | __le32 reserved1; | |
a2fbb9ea ET |
3388 | }; |
3389 | ||
3390 | ||
3391 | /* | |
619c5cb6 | 3392 | * The eth storm context of Ustorm |
a2fbb9ea | 3393 | */ |
619c5cb6 VZ |
3394 | struct ustorm_eth_st_context { |
3395 | u32 reserved0[52]; | |
523224a3 DK |
3396 | }; |
3397 | ||
3398 | /* | |
619c5cb6 | 3399 | * The eth storm context of Tstorm |
523224a3 | 3400 | */ |
619c5cb6 VZ |
3401 | struct tstorm_eth_st_context { |
3402 | u32 __reserved0[28]; | |
a2fbb9ea ET |
3403 | }; |
3404 | ||
3405 | /* | |
619c5cb6 | 3406 | * The eth storm context of Xstorm |
a2fbb9ea | 3407 | */ |
619c5cb6 VZ |
3408 | struct xstorm_eth_st_context { |
3409 | u32 reserved0[60]; | |
a2fbb9ea ET |
3410 | }; |
3411 | ||
3412 | /* | |
619c5cb6 | 3413 | * Ethernet connection context |
a2fbb9ea | 3414 | */ |
619c5cb6 VZ |
3415 | struct eth_context { |
3416 | struct ustorm_eth_st_context ustorm_st_context; | |
3417 | struct tstorm_eth_st_context tstorm_st_context; | |
3418 | struct xstorm_eth_ag_context xstorm_ag_context; | |
3419 | struct tstorm_eth_ag_context tstorm_ag_context; | |
3420 | struct cstorm_eth_ag_context cstorm_ag_context; | |
3421 | struct ustorm_eth_ag_context ustorm_ag_context; | |
3422 | struct timers_block_context timers_context; | |
3423 | struct xstorm_eth_st_context xstorm_st_context; | |
3424 | struct cstorm_eth_st_context cstorm_st_context; | |
a2fbb9ea ET |
3425 | }; |
3426 | ||
3427 | ||
3428 | /* | |
523224a3 | 3429 | * union for sgl and raw data. |
a2fbb9ea | 3430 | */ |
523224a3 DK |
3431 | union eth_sgl_or_raw_data { |
3432 | __le16 sgl[8]; | |
3433 | u32 raw_data[4]; | |
a2fbb9ea ET |
3434 | }; |
3435 | ||
619c5cb6 VZ |
3436 | /* |
3437 | * eth FP end aggregation CQE parameters struct | |
3438 | */ | |
3439 | struct eth_end_agg_rx_cqe { | |
3440 | u8 type_error_flags; | |
3441 | #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) | |
3442 | #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 | |
3443 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) | |
3444 | #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3445 | #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) | |
3446 | #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 | |
3447 | u8 reserved1; | |
3448 | u8 queue_index; | |
3449 | u8 reserved2; | |
3450 | __le32 timestamp_delta; | |
3451 | __le16 num_of_coalesced_segs; | |
3452 | __le16 pkt_len; | |
3453 | u8 pure_ack_count; | |
3454 | u8 reserved3; | |
3455 | __le16 reserved4; | |
3456 | union eth_sgl_or_raw_data sgl_or_raw_data; | |
3457 | __le32 reserved5[8]; | |
3458 | }; | |
3459 | ||
3460 | ||
a2fbb9ea ET |
3461 | /* |
3462 | * regular eth FP CQE parameters struct | |
3463 | */ | |
3464 | struct eth_fast_path_rx_cqe { | |
34f80b04 | 3465 | u8 type_error_flags; |
619c5cb6 | 3466 | #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 3467 | #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
3468 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) |
3469 | #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 | |
3470 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) | |
3471 | #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 | |
3472 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) | |
3473 | #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 | |
3474 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) | |
3475 | #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 | |
3476 | #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) | |
3477 | #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 | |
a2fbb9ea ET |
3478 | u8 status_flags; |
3479 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) | |
3480 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 | |
3481 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) | |
3482 | #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 | |
3483 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) | |
3484 | #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 | |
3485 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) | |
3486 | #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 | |
3487 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) | |
3488 | #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 | |
3489 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) | |
3490 | #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 | |
34f80b04 | 3491 | u8 queue_index; |
619c5cb6 | 3492 | u8 placement_offset; |
4781bfad EG |
3493 | __le32 rss_hash_result; |
3494 | __le16 vlan_tag; | |
3495 | __le16 pkt_len; | |
3496 | __le16 len_on_bd; | |
a2fbb9ea | 3497 | struct parsing_flags pars_flags; |
523224a3 | 3498 | union eth_sgl_or_raw_data sgl_or_raw_data; |
619c5cb6 VZ |
3499 | __le32 reserved1[8]; |
3500 | }; | |
3501 | ||
3502 | ||
3503 | /* | |
3504 | * Command for setting classification flags for a client | |
3505 | */ | |
3506 | struct eth_filter_rules_cmd { | |
3507 | u8 cmd_general_data; | |
3508 | #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) | |
3509 | #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 | |
3510 | #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) | |
3511 | #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 | |
3512 | #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) | |
3513 | #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 | |
3514 | u8 func_id; | |
3515 | u8 client_id; | |
3516 | u8 reserved1; | |
3517 | __le16 state; | |
3518 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) | |
3519 | #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 | |
3520 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) | |
3521 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 | |
3522 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) | |
3523 | #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
3524 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) | |
3525 | #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 | |
3526 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) | |
3527 | #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 | |
3528 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) | |
3529 | #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 | |
3530 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) | |
3531 | #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 | |
3532 | #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) | |
3533 | #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 | |
3534 | __le16 reserved3; | |
3535 | struct regpair reserved4; | |
3536 | }; | |
3537 | ||
3538 | ||
3539 | /* | |
3540 | * parameters for eth classification filters ramrod | |
3541 | */ | |
3542 | struct eth_filter_rules_ramrod_data { | |
3543 | struct eth_classify_header header; | |
3544 | struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; | |
3545 | }; | |
3546 | ||
3547 | ||
3548 | /* | |
3549 | * parameters for eth classification configuration ramrod | |
3550 | */ | |
3551 | struct eth_general_rules_ramrod_data { | |
3552 | struct eth_classify_header header; | |
3553 | union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; | |
a2fbb9ea ET |
3554 | }; |
3555 | ||
3556 | ||
3557 | /* | |
619c5cb6 | 3558 | * The data for Halt ramrod |
a2fbb9ea ET |
3559 | */ |
3560 | struct eth_halt_ramrod_data { | |
619c5cb6 VZ |
3561 | __le32 client_id; |
3562 | __le32 reserved0; | |
a2fbb9ea ET |
3563 | }; |
3564 | ||
619c5cb6 | 3565 | |
34f80b04 | 3566 | /* |
619c5cb6 | 3567 | * Command for setting multicast classification for a client |
34f80b04 | 3568 | */ |
619c5cb6 VZ |
3569 | struct eth_multicast_rules_cmd { |
3570 | u8 cmd_general_data; | |
3571 | #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) | |
3572 | #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 | |
3573 | #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) | |
3574 | #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 | |
3575 | #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) | |
3576 | #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 | |
3577 | #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) | |
3578 | #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 | |
3579 | u8 func_id; | |
3580 | u8 bin_id; | |
3581 | u8 engine_id; | |
3582 | __le32 reserved2; | |
3583 | struct regpair reserved3; | |
3584 | }; | |
3585 | ||
3586 | ||
3587 | /* | |
3588 | * parameters for multicast classification ramrod | |
3589 | */ | |
3590 | struct eth_multicast_rules_ramrod_data { | |
3591 | struct eth_classify_header header; | |
3592 | struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; | |
34f80b04 EG |
3593 | }; |
3594 | ||
3595 | ||
a2fbb9ea ET |
3596 | /* |
3597 | * Place holder for ramrods protocol specific data | |
3598 | */ | |
3599 | struct ramrod_data { | |
4781bfad EG |
3600 | __le32 data_lo; |
3601 | __le32 data_hi; | |
a2fbb9ea ET |
3602 | }; |
3603 | ||
3604 | /* | |
33471629 | 3605 | * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) |
a2fbb9ea ET |
3606 | */ |
3607 | union eth_ramrod_data { | |
3608 | struct ramrod_data general; | |
3609 | }; | |
3610 | ||
3611 | ||
619c5cb6 VZ |
3612 | /* |
3613 | * RSS toeplitz hash type, as reported in CQE | |
3614 | */ | |
3615 | enum eth_rss_hash_type { | |
3616 | DEFAULT_HASH_TYPE, | |
3617 | IPV4_HASH_TYPE, | |
3618 | TCP_IPV4_HASH_TYPE, | |
3619 | IPV6_HASH_TYPE, | |
3620 | TCP_IPV6_HASH_TYPE, | |
3621 | VLAN_PRI_HASH_TYPE, | |
3622 | E1HOV_PRI_HASH_TYPE, | |
3623 | DSCP_HASH_TYPE, | |
3624 | MAX_ETH_RSS_HASH_TYPE | |
3625 | }; | |
3626 | ||
3627 | ||
3628 | /* | |
3629 | * Ethernet RSS mode | |
3630 | */ | |
3631 | enum eth_rss_mode { | |
3632 | ETH_RSS_MODE_DISABLED, | |
3633 | ETH_RSS_MODE_REGULAR, | |
3634 | ETH_RSS_MODE_VLAN_PRI, | |
3635 | ETH_RSS_MODE_E1HOV_PRI, | |
3636 | ETH_RSS_MODE_IP_DSCP, | |
3637 | MAX_ETH_RSS_MODE | |
3638 | }; | |
3639 | ||
3640 | ||
3641 | /* | |
3642 | * parameters for RSS update ramrod (E2) | |
3643 | */ | |
3644 | struct eth_rss_update_ramrod_data { | |
3645 | u8 rss_engine_id; | |
3646 | u8 capabilities; | |
3647 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) | |
3648 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 | |
3649 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) | |
3650 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 | |
3651 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) | |
3652 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 | |
3653 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) | |
3654 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 | |
3655 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) | |
3656 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 | |
3657 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) | |
3658 | #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 | |
3659 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) | |
3660 | #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 | |
3661 | #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7) | |
3662 | #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7 | |
3663 | u8 rss_result_mask; | |
3664 | u8 rss_mode; | |
3665 | __le32 __reserved2; | |
3666 | u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; | |
3667 | __le32 rss_key[T_ETH_RSS_KEY]; | |
3668 | __le32 echo; | |
3669 | __le32 reserved3; | |
3670 | }; | |
3671 | ||
3672 | ||
3673 | /* | |
3674 | * The eth Rx Buffer Descriptor | |
3675 | */ | |
3676 | struct eth_rx_bd { | |
3677 | __le32 addr_lo; | |
3678 | __le32 addr_hi; | |
3679 | }; | |
3680 | ||
3681 | ||
a2fbb9ea ET |
3682 | /* |
3683 | * Eth Rx Cqe structure- general structure for ramrods | |
3684 | */ | |
3685 | struct common_ramrod_eth_rx_cqe { | |
34f80b04 | 3686 | u8 ramrod_type; |
619c5cb6 | 3687 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) |
34f80b04 | 3688 | #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 |
619c5cb6 VZ |
3689 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) |
3690 | #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 | |
3691 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) | |
3692 | #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 | |
8d9c5f34 | 3693 | u8 conn_type; |
4781bfad EG |
3694 | __le16 reserved1; |
3695 | __le32 conn_and_cmd_data; | |
a2fbb9ea ET |
3696 | #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) |
3697 | #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 | |
3698 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) | |
3699 | #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 | |
3700 | struct ramrod_data protocol_data; | |
619c5cb6 VZ |
3701 | __le32 echo; |
3702 | __le32 reserved2[11]; | |
3703 | }; | |
3704 | ||
3705 | /* | |
3706 | * Rx Last CQE in page (in ETH) | |
3707 | */ | |
3708 | struct eth_rx_cqe_next_page { | |
3709 | __le32 addr_lo; | |
3710 | __le32 addr_hi; | |
3711 | __le32 reserved[14]; | |
3712 | }; | |
3713 | ||
3714 | /* | |
3715 | * union for all eth rx cqe types (fix their sizes) | |
3716 | */ | |
3717 | union eth_rx_cqe { | |
3718 | struct eth_fast_path_rx_cqe fast_path_cqe; | |
3719 | struct common_ramrod_eth_rx_cqe ramrod_cqe; | |
3720 | struct eth_rx_cqe_next_page next_page_cqe; | |
3721 | struct eth_end_agg_rx_cqe end_agg_cqe; | |
3722 | }; | |
3723 | ||
3724 | ||
3725 | /* | |
3726 | * Values for RX ETH CQE type field | |
3727 | */ | |
3728 | enum eth_rx_cqe_type { | |
3729 | RX_ETH_CQE_TYPE_ETH_FASTPATH, | |
3730 | RX_ETH_CQE_TYPE_ETH_RAMROD, | |
3731 | RX_ETH_CQE_TYPE_ETH_START_AGG, | |
3732 | RX_ETH_CQE_TYPE_ETH_STOP_AGG, | |
3733 | MAX_ETH_RX_CQE_TYPE | |
3734 | }; | |
3735 | ||
3736 | ||
3737 | /* | |
3738 | * Type of SGL/Raw field in ETH RX fast path CQE | |
3739 | */ | |
3740 | enum eth_rx_fp_sel { | |
3741 | ETH_FP_CQE_REGULAR, | |
3742 | ETH_FP_CQE_RAW, | |
3743 | MAX_ETH_RX_FP_SEL | |
3744 | }; | |
3745 | ||
3746 | ||
3747 | /* | |
3748 | * The eth Rx SGE Descriptor | |
3749 | */ | |
3750 | struct eth_rx_sge { | |
3751 | __le32 addr_lo; | |
3752 | __le32 addr_hi; | |
3753 | }; | |
3754 | ||
3755 | ||
3756 | /* | |
3757 | * common data for all protocols | |
3758 | */ | |
3759 | struct spe_hdr { | |
3760 | __le32 conn_and_cmd_data; | |
3761 | #define SPE_HDR_CID (0xFFFFFF<<0) | |
3762 | #define SPE_HDR_CID_SHIFT 0 | |
3763 | #define SPE_HDR_CMD_ID (0xFF<<24) | |
3764 | #define SPE_HDR_CMD_ID_SHIFT 24 | |
3765 | __le16 type; | |
3766 | #define SPE_HDR_CONN_TYPE (0xFF<<0) | |
3767 | #define SPE_HDR_CONN_TYPE_SHIFT 0 | |
3768 | #define SPE_HDR_FUNCTION_ID (0xFF<<8) | |
3769 | #define SPE_HDR_FUNCTION_ID_SHIFT 8 | |
3770 | __le16 reserved1; | |
3771 | }; | |
3772 | ||
3773 | /* | |
3774 | * specific data for ethernet slow path element | |
3775 | */ | |
3776 | union eth_specific_data { | |
3777 | u8 protocol_data[8]; | |
3778 | struct regpair client_update_ramrod_data; | |
3779 | struct regpair client_init_ramrod_init_data; | |
3780 | struct eth_halt_ramrod_data halt_ramrod_data; | |
3781 | struct regpair update_data_addr; | |
3782 | struct eth_common_ramrod_data common_ramrod_data; | |
3783 | struct regpair classify_cfg_addr; | |
3784 | struct regpair filter_cfg_addr; | |
3785 | struct regpair mcast_cfg_addr; | |
3786 | }; | |
3787 | ||
3788 | /* | |
3789 | * Ethernet slow path element | |
3790 | */ | |
3791 | struct eth_spe { | |
3792 | struct spe_hdr hdr; | |
3793 | union eth_specific_data data; | |
3794 | }; | |
3795 | ||
3796 | ||
3797 | /* | |
3798 | * Ethernet command ID for slow path elements | |
3799 | */ | |
3800 | enum eth_spqe_cmd_id { | |
3801 | RAMROD_CMD_ID_ETH_UNUSED, | |
3802 | RAMROD_CMD_ID_ETH_CLIENT_SETUP, | |
3803 | RAMROD_CMD_ID_ETH_HALT, | |
3804 | RAMROD_CMD_ID_ETH_FORWARD_SETUP, | |
3805 | RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, | |
3806 | RAMROD_CMD_ID_ETH_CLIENT_UPDATE, | |
3807 | RAMROD_CMD_ID_ETH_EMPTY, | |
3808 | RAMROD_CMD_ID_ETH_TERMINATE, | |
3809 | RAMROD_CMD_ID_ETH_TPA_UPDATE, | |
3810 | RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, | |
3811 | RAMROD_CMD_ID_ETH_FILTER_RULES, | |
3812 | RAMROD_CMD_ID_ETH_MULTICAST_RULES, | |
3813 | RAMROD_CMD_ID_ETH_RSS_UPDATE, | |
3814 | RAMROD_CMD_ID_ETH_SET_MAC, | |
3815 | MAX_ETH_SPQE_CMD_ID | |
3816 | }; | |
3817 | ||
3818 | ||
3819 | /* | |
3820 | * eth tpa update command | |
3821 | */ | |
3822 | enum eth_tpa_update_command { | |
3823 | TPA_UPDATE_NONE_COMMAND, | |
3824 | TPA_UPDATE_ENABLE_COMMAND, | |
3825 | TPA_UPDATE_DISABLE_COMMAND, | |
3826 | MAX_ETH_TPA_UPDATE_COMMAND | |
3827 | }; | |
3828 | ||
3829 | ||
3830 | /* | |
3831 | * Tx regular BD structure | |
3832 | */ | |
3833 | struct eth_tx_bd { | |
3834 | __le32 addr_lo; | |
3835 | __le32 addr_hi; | |
3836 | __le16 total_pkt_bytes; | |
3837 | __le16 nbytes; | |
3838 | u8 reserved[4]; | |
3839 | }; | |
3840 | ||
3841 | ||
3842 | /* | |
3843 | * structure for easy accessibility to assembler | |
3844 | */ | |
3845 | struct eth_tx_bd_flags { | |
3846 | u8 as_bitfield; | |
3847 | #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) | |
3848 | #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 | |
3849 | #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) | |
3850 | #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 | |
3851 | #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) | |
3852 | #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 | |
3853 | #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) | |
3854 | #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 | |
3855 | #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) | |
3856 | #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 | |
3857 | #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) | |
3858 | #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 | |
3859 | #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) | |
3860 | #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 | |
a2fbb9ea ET |
3861 | }; |
3862 | ||
3863 | /* | |
619c5cb6 | 3864 | * The eth Tx Buffer Descriptor |
a2fbb9ea | 3865 | */ |
619c5cb6 | 3866 | struct eth_tx_start_bd { |
4781bfad EG |
3867 | __le32 addr_lo; |
3868 | __le32 addr_hi; | |
619c5cb6 VZ |
3869 | __le16 nbd; |
3870 | __le16 nbytes; | |
3871 | __le16 vlan_or_ethertype; | |
3872 | struct eth_tx_bd_flags bd_flags; | |
3873 | u8 general_data; | |
3874 | #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) | |
3875 | #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 | |
3876 | #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) | |
3877 | #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 | |
3878 | #define ETH_TX_START_BD_RESREVED (0x1<<5) | |
3879 | #define ETH_TX_START_BD_RESREVED_SHIFT 5 | |
3880 | #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) | |
3881 | #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 | |
a2fbb9ea ET |
3882 | }; |
3883 | ||
3884 | /* | |
619c5cb6 | 3885 | * Tx parsing BD structure for ETH E1/E1h |
a2fbb9ea | 3886 | */ |
619c5cb6 VZ |
3887 | struct eth_tx_parse_bd_e1x { |
3888 | u8 global_data; | |
3889 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) | |
3890 | #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 | |
3891 | #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) | |
3892 | #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 | |
3893 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) | |
3894 | #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 | |
3895 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) | |
3896 | #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 | |
3897 | #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) | |
3898 | #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 | |
3899 | u8 tcp_flags; | |
3900 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) | |
3901 | #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 | |
3902 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) | |
3903 | #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 | |
3904 | #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) | |
3905 | #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 | |
3906 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) | |
3907 | #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 | |
3908 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) | |
3909 | #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 | |
3910 | #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) | |
3911 | #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 | |
3912 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) | |
3913 | #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 | |
3914 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) | |
3915 | #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 | |
3916 | u8 ip_hlen_w; | |
3917 | s8 reserved; | |
3918 | __le16 total_hlen_w; | |
3919 | __le16 tcp_pseudo_csum; | |
3920 | __le16 lso_mss; | |
3921 | __le16 ip_id; | |
3922 | __le32 tcp_send_seq; | |
a2fbb9ea ET |
3923 | }; |
3924 | ||
a2fbb9ea | 3925 | /* |
619c5cb6 | 3926 | * Tx parsing BD structure for ETH E2 |
a2fbb9ea | 3927 | */ |
619c5cb6 VZ |
3928 | struct eth_tx_parse_bd_e2 { |
3929 | __le16 dst_mac_addr_lo; | |
3930 | __le16 dst_mac_addr_mid; | |
3931 | __le16 dst_mac_addr_hi; | |
3932 | __le16 src_mac_addr_lo; | |
3933 | __le16 src_mac_addr_mid; | |
3934 | __le16 src_mac_addr_hi; | |
3935 | __le32 parsing_data; | |
3936 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) | |
3937 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 | |
3938 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) | |
3939 | #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 | |
3940 | #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) | |
3941 | #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 | |
3942 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) | |
3943 | #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 | |
a2fbb9ea ET |
3944 | }; |
3945 | ||
a2fbb9ea | 3946 | /* |
619c5cb6 | 3947 | * The last BD in the BD memory will hold a pointer to the next BD memory |
a2fbb9ea | 3948 | */ |
619c5cb6 VZ |
3949 | struct eth_tx_next_bd { |
3950 | __le32 addr_lo; | |
3951 | __le32 addr_hi; | |
3952 | u8 reserved[8]; | |
a2fbb9ea ET |
3953 | }; |
3954 | ||
3955 | /* | |
619c5cb6 | 3956 | * union for 4 Bd types |
a2fbb9ea | 3957 | */ |
619c5cb6 VZ |
3958 | union eth_tx_bd_types { |
3959 | struct eth_tx_start_bd start_bd; | |
3960 | struct eth_tx_bd reg_bd; | |
3961 | struct eth_tx_parse_bd_e1x parse_bd_e1x; | |
3962 | struct eth_tx_parse_bd_e2 parse_bd_e2; | |
3963 | struct eth_tx_next_bd next_bd; | |
a2fbb9ea ET |
3964 | }; |
3965 | ||
a2fbb9ea | 3966 | /* |
ca00392c | 3967 | * array of 13 bds as appears in the eth xstorm context |
a2fbb9ea | 3968 | */ |
ca00392c EG |
3969 | struct eth_tx_bds_array { |
3970 | union eth_tx_bd_types bds[13]; | |
a2fbb9ea ET |
3971 | }; |
3972 | ||
3973 | ||
3974 | /* | |
619c5cb6 | 3975 | * VLAN mode on TX BDs |
a2fbb9ea | 3976 | */ |
619c5cb6 VZ |
3977 | enum eth_tx_vlan_type { |
3978 | X_ETH_NO_VLAN, | |
3979 | X_ETH_OUTBAND_VLAN, | |
3980 | X_ETH_INBAND_VLAN, | |
3981 | X_ETH_FW_ADDED_VLAN, | |
3982 | MAX_ETH_TX_VLAN_TYPE | |
a2fbb9ea ET |
3983 | }; |
3984 | ||
ca00392c | 3985 | |
a2fbb9ea | 3986 | /* |
619c5cb6 | 3987 | * Ethernet VLAN filtering mode in E1x |
a2fbb9ea | 3988 | */ |
619c5cb6 VZ |
3989 | enum eth_vlan_filter_mode { |
3990 | ETH_VLAN_FILTER_ANY_VLAN, | |
3991 | ETH_VLAN_FILTER_SPECIFIC_VLAN, | |
3992 | ETH_VLAN_FILTER_CLASSIFY, | |
3993 | MAX_ETH_VLAN_FILTER_MODE | |
a2fbb9ea ET |
3994 | }; |
3995 | ||
3996 | ||
3997 | /* | |
3998 | * MAC filtering configuration command header | |
3999 | */ | |
4000 | struct mac_configuration_hdr { | |
8d9c5f34 | 4001 | u8 length; |
a2fbb9ea | 4002 | u8 offset; |
619c5cb6 VZ |
4003 | __le16 client_id; |
4004 | __le32 echo; | |
a2fbb9ea ET |
4005 | }; |
4006 | ||
4007 | /* | |
4008 | * MAC address in list for ramrod | |
4009 | */ | |
523224a3 | 4010 | struct mac_configuration_entry { |
4781bfad EG |
4011 | __le16 lsb_mac_addr; |
4012 | __le16 middle_mac_addr; | |
4013 | __le16 msb_mac_addr; | |
523224a3 DK |
4014 | __le16 vlan_id; |
4015 | u8 pf_id; | |
a2fbb9ea | 4016 | u8 flags; |
523224a3 DK |
4017 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) |
4018 | #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 | |
4019 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) | |
4020 | #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 | |
4021 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) | |
4022 | #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 | |
4023 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) | |
4024 | #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 | |
4025 | #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) | |
4026 | #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 | |
4027 | #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) | |
4028 | #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 | |
619c5cb6 VZ |
4029 | __le16 reserved0; |
4030 | __le32 clients_bit_vector; | |
a2fbb9ea ET |
4031 | }; |
4032 | ||
4033 | /* | |
523224a3 | 4034 | * MAC filtering configuration command |
a2fbb9ea ET |
4035 | */ |
4036 | struct mac_configuration_cmd { | |
4037 | struct mac_configuration_hdr hdr; | |
4038 | struct mac_configuration_entry config_table[64]; | |
4039 | }; | |
4040 | ||
4041 | ||
619c5cb6 VZ |
4042 | /* |
4043 | * Set-MAC command type (in E1x) | |
4044 | */ | |
4045 | enum set_mac_action_type { | |
4046 | T_ETH_MAC_COMMAND_INVALIDATE, | |
4047 | T_ETH_MAC_COMMAND_SET, | |
4048 | MAX_SET_MAC_ACTION_TYPE | |
4049 | }; | |
4050 | ||
4051 | ||
4052 | /* | |
4053 | * tpa update ramrod data | |
4054 | */ | |
4055 | struct tpa_update_ramrod_data { | |
4056 | u8 update_ipv4; | |
4057 | u8 update_ipv6; | |
4058 | u8 client_id; | |
4059 | u8 max_tpa_queues; | |
4060 | u8 max_sges_for_packet; | |
4061 | u8 complete_on_both_clients; | |
4062 | __le16 reserved1; | |
4063 | __le16 sge_buff_size; | |
4064 | __le16 max_agg_size; | |
4065 | __le32 sge_page_base_lo; | |
4066 | __le32 sge_page_base_hi; | |
4067 | __le16 sge_pause_thr_low; | |
4068 | __le16 sge_pause_thr_high; | |
4069 | }; | |
4070 | ||
4071 | ||
34f80b04 EG |
4072 | /* |
4073 | * approximate-match multicast filtering for E1H per function in Tstorm | |
4074 | */ | |
4075 | struct tstorm_eth_approximate_match_multicast_filtering { | |
4076 | u32 mcast_add_hash_bit_array[8]; | |
4077 | }; | |
4078 | ||
4079 | ||
619c5cb6 VZ |
4080 | /* |
4081 | * Common configuration parameters per function in Tstorm | |
4082 | */ | |
4083 | struct tstorm_eth_function_common_config { | |
4084 | __le16 config_flags; | |
4085 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) | |
4086 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 | |
4087 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) | |
4088 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 | |
4089 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) | |
4090 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 | |
4091 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) | |
4092 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 | |
4093 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) | |
4094 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 | |
4095 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) | |
4096 | #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 | |
4097 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) | |
4098 | #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 | |
4099 | u8 rss_result_mask; | |
4100 | u8 reserved1; | |
4101 | __le16 vlan_id[2]; | |
4102 | }; | |
4103 | ||
4104 | ||
a2fbb9ea ET |
4105 | /* |
4106 | * MAC filtering configuration parameters per port in Tstorm | |
4107 | */ | |
4108 | struct tstorm_eth_mac_filter_config { | |
619c5cb6 VZ |
4109 | __le32 ucast_drop_all; |
4110 | __le32 ucast_accept_all; | |
4111 | __le32 mcast_drop_all; | |
4112 | __le32 mcast_accept_all; | |
4113 | __le32 bcast_accept_all; | |
4114 | __le32 vlan_filter[2]; | |
4115 | __le32 unmatched_unicast; | |
a2fbb9ea ET |
4116 | }; |
4117 | ||
4118 | ||
8d9c5f34 | 4119 | /* |
619c5cb6 | 4120 | * tx only queue init ramrod data |
8d9c5f34 | 4121 | */ |
619c5cb6 VZ |
4122 | struct tx_queue_init_ramrod_data { |
4123 | struct client_init_general_data general; | |
4124 | struct client_init_tx_data tx; | |
8d9c5f34 EG |
4125 | }; |
4126 | ||
4127 | ||
34f80b04 EG |
4128 | /* |
4129 | * Three RX producers for ETH | |
4130 | */ | |
8d9c5f34 | 4131 | struct ustorm_eth_rx_producers { |
a2fbb9ea | 4132 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4133 | u16 bd_prod; |
4134 | u16 cqe_prod; | |
a2fbb9ea | 4135 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4136 | u16 cqe_prod; |
4137 | u16 bd_prod; | |
a2fbb9ea | 4138 | #endif |
a2fbb9ea | 4139 | #if defined(__BIG_ENDIAN) |
34f80b04 EG |
4140 | u16 reserved; |
4141 | u16 sge_prod; | |
a2fbb9ea | 4142 | #elif defined(__LITTLE_ENDIAN) |
34f80b04 EG |
4143 | u16 sge_prod; |
4144 | u16 reserved; | |
a2fbb9ea | 4145 | #endif |
a2fbb9ea ET |
4146 | }; |
4147 | ||
a2fbb9ea | 4148 | |
523224a3 DK |
4149 | /* |
4150 | * cfc delete event data | |
4151 | */ | |
4152 | struct cfc_del_event_data { | |
4153 | u32 cid; | |
619c5cb6 VZ |
4154 | u32 reserved0; |
4155 | u32 reserved1; | |
523224a3 DK |
4156 | }; |
4157 | ||
4158 | ||
34f80b04 EG |
4159 | /* |
4160 | * per-port SAFC demo variables | |
4161 | */ | |
4162 | struct cmng_flags_per_port { | |
8a1c38d1 EG |
4163 | u32 cmng_enables; |
4164 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) | |
4165 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 | |
4166 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) | |
4167 | #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 | |
619c5cb6 VZ |
4168 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) |
4169 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 | |
4170 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) | |
4171 | #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 | |
4172 | #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) | |
4173 | #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 | |
4174 | u32 __reserved1; | |
a2fbb9ea ET |
4175 | }; |
4176 | ||
34f80b04 EG |
4177 | |
4178 | /* | |
4179 | * per-port rate shaping variables | |
4180 | */ | |
4181 | struct rate_shaping_vars_per_port { | |
4182 | u32 rs_periodic_timeout; | |
4183 | u32 rs_threshold; | |
4184 | }; | |
4185 | ||
34f80b04 EG |
4186 | /* |
4187 | * per-port fairness variables | |
4188 | */ | |
4189 | struct fairness_vars_per_port { | |
4190 | u32 upper_bound; | |
4191 | u32 fair_threshold; | |
4192 | u32 fairness_timeout; | |
619c5cb6 | 4193 | u32 reserved0; |
34f80b04 EG |
4194 | }; |
4195 | ||
34f80b04 EG |
4196 | /* |
4197 | * per-port SAFC variables | |
4198 | */ | |
4199 | struct safc_struct_per_port { | |
4200 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
4201 | u16 __reserved1; |
4202 | u8 __reserved0; | |
34f80b04 EG |
4203 | u8 safc_timeout_usec; |
4204 | #elif defined(__LITTLE_ENDIAN) | |
4205 | u8 safc_timeout_usec; | |
8d9c5f34 EG |
4206 | u8 __reserved0; |
4207 | u16 __reserved1; | |
34f80b04 | 4208 | #endif |
523224a3 | 4209 | u8 cos_to_traffic_types[MAX_COS_NUMBER]; |
8d9c5f34 | 4210 | u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; |
a2fbb9ea ET |
4211 | }; |
4212 | ||
34f80b04 EG |
4213 | /* |
4214 | * Per-port congestion management variables | |
4215 | */ | |
4216 | struct cmng_struct_per_port { | |
4217 | struct rate_shaping_vars_per_port rs_vars; | |
4218 | struct fairness_vars_per_port fair_vars; | |
4219 | struct safc_struct_per_port safc_vars; | |
4220 | struct cmng_flags_per_port flags; | |
a2fbb9ea ET |
4221 | }; |
4222 | ||
4223 | ||
619c5cb6 VZ |
4224 | /* |
4225 | * Protocol-common command ID for slow path elements | |
4226 | */ | |
4227 | enum common_spqe_cmd_id { | |
4228 | RAMROD_CMD_ID_COMMON_UNUSED, | |
4229 | RAMROD_CMD_ID_COMMON_FUNCTION_START, | |
4230 | RAMROD_CMD_ID_COMMON_FUNCTION_STOP, | |
4231 | RAMROD_CMD_ID_COMMON_CFC_DEL, | |
4232 | RAMROD_CMD_ID_COMMON_CFC_DEL_WB, | |
4233 | RAMROD_CMD_ID_COMMON_STAT_QUERY, | |
4234 | RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, | |
4235 | RAMROD_CMD_ID_COMMON_START_TRAFFIC, | |
4236 | RAMROD_CMD_ID_COMMON_RESERVED1, | |
4237 | RAMROD_CMD_ID_COMMON_RESERVED2, | |
4238 | MAX_COMMON_SPQE_CMD_ID | |
4239 | }; | |
4240 | ||
4241 | ||
4242 | /* | |
4243 | * Per-protocol connection types | |
4244 | */ | |
4245 | enum connection_type { | |
4246 | ETH_CONNECTION_TYPE, | |
4247 | TOE_CONNECTION_TYPE, | |
4248 | RDMA_CONNECTION_TYPE, | |
4249 | ISCSI_CONNECTION_TYPE, | |
4250 | FCOE_CONNECTION_TYPE, | |
4251 | RESERVED_CONNECTION_TYPE_0, | |
4252 | RESERVED_CONNECTION_TYPE_1, | |
4253 | RESERVED_CONNECTION_TYPE_2, | |
4254 | NONE_CONNECTION_TYPE, | |
4255 | MAX_CONNECTION_TYPE | |
4256 | }; | |
4257 | ||
4258 | ||
4259 | /* | |
4260 | * Cos modes | |
4261 | */ | |
4262 | enum cos_mode { | |
4263 | OVERRIDE_COS, | |
4264 | STATIC_COS, | |
4265 | FW_WRR, | |
4266 | MAX_COS_MODE | |
4267 | }; | |
4268 | ||
523224a3 DK |
4269 | |
4270 | /* | |
4271 | * Dynamic HC counters set by the driver | |
4272 | */ | |
4273 | struct hc_dynamic_drv_counter { | |
4274 | u32 val[HC_SB_MAX_DYNAMIC_INDICES]; | |
4275 | }; | |
4276 | ||
4277 | /* | |
4278 | * zone A per-queue data | |
4279 | */ | |
4280 | struct cstorm_queue_zone_data { | |
4281 | struct hc_dynamic_drv_counter hc_dyn_drv_cnt; | |
4282 | struct regpair reserved[2]; | |
4283 | }; | |
4284 | ||
619c5cb6 | 4285 | |
ca00392c | 4286 | /* |
619c5cb6 | 4287 | * Vf-PF channel data in cstorm ram (non-triggered zone) |
ca00392c | 4288 | */ |
619c5cb6 VZ |
4289 | struct vf_pf_channel_zone_data { |
4290 | u32 msg_addr_lo; | |
4291 | u32 msg_addr_hi; | |
ca00392c EG |
4292 | }; |
4293 | ||
a2fbb9ea | 4294 | /* |
619c5cb6 | 4295 | * zone for VF non-triggered data |
a2fbb9ea | 4296 | */ |
619c5cb6 VZ |
4297 | struct non_trigger_vf_zone { |
4298 | struct vf_pf_channel_zone_data vf_pf_channel; | |
a2fbb9ea ET |
4299 | }; |
4300 | ||
bb2a0f7a | 4301 | /* |
619c5cb6 | 4302 | * Vf-PF channel trigger zone in cstorm ram |
bb2a0f7a | 4303 | */ |
619c5cb6 VZ |
4304 | struct vf_pf_channel_zone_trigger { |
4305 | u8 addr_valid; | |
bb2a0f7a YG |
4306 | }; |
4307 | ||
bb2a0f7a | 4308 | /* |
619c5cb6 | 4309 | * zone that triggers the in-bound interrupt |
bb2a0f7a | 4310 | */ |
619c5cb6 VZ |
4311 | struct trigger_vf_zone { |
4312 | #if defined(__BIG_ENDIAN) | |
4313 | u16 reserved1; | |
4314 | u8 reserved0; | |
4315 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4316 | #elif defined(__LITTLE_ENDIAN) | |
4317 | struct vf_pf_channel_zone_trigger vf_pf_channel; | |
4318 | u8 reserved0; | |
4319 | u16 reserved1; | |
4320 | #endif | |
4321 | u32 reserved2; | |
bb2a0f7a YG |
4322 | }; |
4323 | ||
a2fbb9ea | 4324 | /* |
619c5cb6 | 4325 | * zone B per-VF data |
a2fbb9ea | 4326 | */ |
619c5cb6 VZ |
4327 | struct cstorm_vf_zone_data { |
4328 | struct non_trigger_vf_zone non_trigger; | |
4329 | struct trigger_vf_zone trigger; | |
a2fbb9ea ET |
4330 | }; |
4331 | ||
619c5cb6 | 4332 | |
a2fbb9ea | 4333 | /* |
619c5cb6 | 4334 | * Dynamic host coalescing init parameters, per state machine |
a2fbb9ea | 4335 | */ |
619c5cb6 VZ |
4336 | struct dynamic_hc_sm_config { |
4337 | u32 threshold[3]; | |
4338 | u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; | |
4339 | u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; | |
4340 | u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; | |
4341 | u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; | |
4342 | u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; | |
a2fbb9ea ET |
4343 | }; |
4344 | ||
de832a55 | 4345 | /* |
619c5cb6 | 4346 | * Dynamic host coalescing init parameters |
de832a55 | 4347 | */ |
619c5cb6 VZ |
4348 | struct dynamic_hc_config { |
4349 | struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; | |
4350 | }; | |
4351 | ||
4352 | ||
4353 | struct e2_integ_data { | |
4354 | #if defined(__BIG_ENDIAN) | |
4355 | u8 flags; | |
4356 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4357 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4358 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4359 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4360 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4361 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4362 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
4363 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
4364 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
4365 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
4366 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
4367 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
4368 | u8 cos; | |
4369 | u8 voq; | |
4370 | u8 pbf_queue; | |
4371 | #elif defined(__LITTLE_ENDIAN) | |
4372 | u8 pbf_queue; | |
4373 | u8 voq; | |
4374 | u8 cos; | |
4375 | u8 flags; | |
4376 | #define E2_INTEG_DATA_TESTING_EN (0x1<<0) | |
4377 | #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 | |
4378 | #define E2_INTEG_DATA_LB_TX (0x1<<1) | |
4379 | #define E2_INTEG_DATA_LB_TX_SHIFT 1 | |
4380 | #define E2_INTEG_DATA_COS_TX (0x1<<2) | |
4381 | #define E2_INTEG_DATA_COS_TX_SHIFT 2 | |
4382 | #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) | |
4383 | #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 | |
4384 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) | |
4385 | #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 | |
4386 | #define E2_INTEG_DATA_RESERVED (0x7<<5) | |
4387 | #define E2_INTEG_DATA_RESERVED_SHIFT 5 | |
4388 | #endif | |
4389 | #if defined(__BIG_ENDIAN) | |
4390 | u16 reserved3; | |
4391 | u8 reserved2; | |
4392 | u8 ramEn; | |
4393 | #elif defined(__LITTLE_ENDIAN) | |
4394 | u8 ramEn; | |
4395 | u8 reserved2; | |
4396 | u16 reserved3; | |
4397 | #endif | |
de832a55 EG |
4398 | }; |
4399 | ||
619c5cb6 | 4400 | |
de832a55 | 4401 | /* |
619c5cb6 | 4402 | * set mac event data |
de832a55 | 4403 | */ |
619c5cb6 VZ |
4404 | struct eth_event_data { |
4405 | u32 echo; | |
4406 | u32 reserved0; | |
4407 | u32 reserved1; | |
de832a55 EG |
4408 | }; |
4409 | ||
619c5cb6 | 4410 | |
a2fbb9ea | 4411 | /* |
619c5cb6 | 4412 | * pf-vf event data |
a2fbb9ea | 4413 | */ |
619c5cb6 VZ |
4414 | struct vf_pf_event_data { |
4415 | u8 vf_id; | |
4416 | u8 reserved0; | |
4417 | u16 reserved1; | |
4418 | u32 msg_addr_lo; | |
4419 | u32 msg_addr_hi; | |
a2fbb9ea ET |
4420 | }; |
4421 | ||
619c5cb6 VZ |
4422 | /* |
4423 | * VF FLR event data | |
4424 | */ | |
4425 | struct vf_flr_event_data { | |
4426 | u8 vf_id; | |
4427 | u8 reserved0; | |
4428 | u16 reserved1; | |
4429 | u32 reserved2; | |
4430 | u32 reserved3; | |
4431 | }; | |
a2fbb9ea | 4432 | |
523224a3 | 4433 | /* |
619c5cb6 | 4434 | * malicious VF event data |
523224a3 | 4435 | */ |
619c5cb6 VZ |
4436 | struct malicious_vf_event_data { |
4437 | u8 vf_id; | |
4438 | u8 reserved0; | |
4439 | u16 reserved1; | |
523224a3 | 4440 | u32 reserved2; |
619c5cb6 | 4441 | u32 reserved3; |
523224a3 DK |
4442 | }; |
4443 | ||
4444 | /* | |
4445 | * union for all event ring message types | |
4446 | */ | |
4447 | union event_data { | |
619c5cb6 VZ |
4448 | struct vf_pf_event_data vf_pf_event; |
4449 | struct eth_event_data eth_event; | |
523224a3 | 4450 | struct cfc_del_event_data cfc_del_event; |
619c5cb6 VZ |
4451 | struct vf_flr_event_data vf_flr_event; |
4452 | struct malicious_vf_event_data malicious_vf_event; | |
523224a3 DK |
4453 | }; |
4454 | ||
4455 | ||
4456 | /* | |
4457 | * per PF event ring data | |
4458 | */ | |
4459 | struct event_ring_data { | |
4460 | struct regpair base_addr; | |
4461 | #if defined(__BIG_ENDIAN) | |
4462 | u8 index_id; | |
4463 | u8 sb_id; | |
4464 | u16 producer; | |
4465 | #elif defined(__LITTLE_ENDIAN) | |
4466 | u16 producer; | |
4467 | u8 sb_id; | |
4468 | u8 index_id; | |
4469 | #endif | |
4470 | u32 reserved0; | |
4471 | }; | |
4472 | ||
4473 | ||
4474 | /* | |
4475 | * event ring message element (each element is 128 bits) | |
4476 | */ | |
4477 | struct event_ring_msg { | |
4478 | u8 opcode; | |
619c5cb6 | 4479 | u8 error; |
523224a3 DK |
4480 | u16 reserved1; |
4481 | union event_data data; | |
4482 | }; | |
4483 | ||
4484 | /* | |
4485 | * event ring next page element (128 bits) | |
4486 | */ | |
4487 | struct event_ring_next { | |
4488 | struct regpair addr; | |
4489 | u32 reserved[2]; | |
4490 | }; | |
4491 | ||
4492 | /* | |
4493 | * union for event ring element types (each element is 128 bits) | |
4494 | */ | |
4495 | union event_ring_elem { | |
4496 | struct event_ring_msg message; | |
4497 | struct event_ring_next next_page; | |
4498 | }; | |
4499 | ||
4500 | ||
619c5cb6 VZ |
4501 | /* |
4502 | * Common event ring opcodes | |
4503 | */ | |
4504 | enum event_ring_opcode { | |
4505 | EVENT_RING_OPCODE_VF_PF_CHANNEL, | |
4506 | EVENT_RING_OPCODE_FUNCTION_START, | |
4507 | EVENT_RING_OPCODE_FUNCTION_STOP, | |
4508 | EVENT_RING_OPCODE_CFC_DEL, | |
4509 | EVENT_RING_OPCODE_CFC_DEL_WB, | |
4510 | EVENT_RING_OPCODE_STAT_QUERY, | |
4511 | EVENT_RING_OPCODE_STOP_TRAFFIC, | |
4512 | EVENT_RING_OPCODE_START_TRAFFIC, | |
4513 | EVENT_RING_OPCODE_VF_FLR, | |
4514 | EVENT_RING_OPCODE_MALICIOUS_VF, | |
4515 | EVENT_RING_OPCODE_FORWARD_SETUP, | |
4516 | EVENT_RING_OPCODE_RSS_UPDATE_RULES, | |
4517 | EVENT_RING_OPCODE_RESERVED1, | |
4518 | EVENT_RING_OPCODE_RESERVED2, | |
4519 | EVENT_RING_OPCODE_SET_MAC, | |
4520 | EVENT_RING_OPCODE_CLASSIFICATION_RULES, | |
4521 | EVENT_RING_OPCODE_FILTERS_RULES, | |
4522 | EVENT_RING_OPCODE_MULTICAST_RULES, | |
4523 | MAX_EVENT_RING_OPCODE | |
4524 | }; | |
4525 | ||
4526 | ||
4527 | /* | |
4528 | * Modes for fairness algorithm | |
4529 | */ | |
4530 | enum fairness_mode { | |
4531 | FAIRNESS_COS_WRR_MODE, | |
4532 | FAIRNESS_COS_ETS_MODE, | |
4533 | MAX_FAIRNESS_MODE | |
4534 | }; | |
4535 | ||
4536 | ||
34f80b04 EG |
4537 | /* |
4538 | * per-vnic fairness variables | |
4539 | */ | |
4540 | struct fairness_vars_per_vn { | |
8a1c38d1 | 4541 | u32 cos_credit_delta[MAX_COS_NUMBER]; |
34f80b04 EG |
4542 | u32 vn_credit_delta; |
4543 | u32 __reserved0; | |
4544 | }; | |
4545 | ||
4546 | ||
619c5cb6 VZ |
4547 | /* |
4548 | * Priority and cos | |
4549 | */ | |
4550 | struct priority_cos { | |
4551 | u8 priority; | |
4552 | u8 cos; | |
4553 | __le16 reserved1; | |
4554 | }; | |
4555 | ||
e4901dde VZ |
4556 | /* |
4557 | * The data for flow control configuration | |
4558 | */ | |
4559 | struct flow_control_configuration { | |
619c5cb6 | 4560 | struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; |
e4901dde VZ |
4561 | u8 dcb_enabled; |
4562 | u8 dcb_version; | |
619c5cb6 VZ |
4563 | u8 dont_add_pri_0_en; |
4564 | u8 reserved1; | |
4565 | __le32 reserved2; | |
4566 | }; | |
4567 | ||
4568 | ||
4569 | /* | |
4570 | * | |
4571 | */ | |
4572 | struct function_start_data { | |
4573 | __le16 function_mode; | |
4574 | __le16 sd_vlan_tag; | |
4575 | u16 reserved; | |
4576 | u8 path_id; | |
4577 | u8 network_cos_mode; | |
e4901dde VZ |
4578 | }; |
4579 | ||
4580 | ||
a2fbb9ea ET |
4581 | /* |
4582 | * FW version stored in the Xstorm RAM | |
4583 | */ | |
4584 | struct fw_version { | |
4585 | #if defined(__BIG_ENDIAN) | |
8d9c5f34 EG |
4586 | u8 engineering; |
4587 | u8 revision; | |
4588 | u8 minor; | |
4589 | u8 major; | |
a2fbb9ea | 4590 | #elif defined(__LITTLE_ENDIAN) |
8d9c5f34 EG |
4591 | u8 major; |
4592 | u8 minor; | |
4593 | u8 revision; | |
4594 | u8 engineering; | |
a2fbb9ea ET |
4595 | #endif |
4596 | u32 flags; | |
4597 | #define FW_VERSION_OPTIMIZED (0x1<<0) | |
4598 | #define FW_VERSION_OPTIMIZED_SHIFT 0 | |
4599 | #define FW_VERSION_BIG_ENDIEN (0x1<<1) | |
4600 | #define FW_VERSION_BIG_ENDIEN_SHIFT 1 | |
34f80b04 EG |
4601 | #define FW_VERSION_CHIP_VERSION (0x3<<2) |
4602 | #define FW_VERSION_CHIP_VERSION_SHIFT 2 | |
4603 | #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) | |
4604 | #define __FW_VERSION_RESERVED_SHIFT 4 | |
a2fbb9ea ET |
4605 | }; |
4606 | ||
4607 | ||
523224a3 DK |
4608 | /* |
4609 | * Dynamic Host-Coalescing - Driver(host) counters | |
4610 | */ | |
4611 | struct hc_dynamic_sb_drv_counters { | |
4612 | u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; | |
4613 | }; | |
4614 | ||
4615 | ||
4616 | /* | |
4617 | * 2 bytes. configuration/state parameters for a single protocol index | |
4618 | */ | |
4619 | struct hc_index_data { | |
4620 | #if defined(__BIG_ENDIAN) | |
4621 | u8 flags; | |
4622 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
4623 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
4624 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
4625 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
4626 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
4627 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
4628 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
4629 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
4630 | u8 timeout; | |
4631 | #elif defined(__LITTLE_ENDIAN) | |
4632 | u8 timeout; | |
4633 | u8 flags; | |
4634 | #define HC_INDEX_DATA_SM_ID (0x1<<0) | |
4635 | #define HC_INDEX_DATA_SM_ID_SHIFT 0 | |
4636 | #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) | |
4637 | #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 | |
4638 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) | |
4639 | #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 | |
4640 | #define HC_INDEX_DATA_RESERVE (0x1F<<3) | |
4641 | #define HC_INDEX_DATA_RESERVE_SHIFT 3 | |
4642 | #endif | |
4643 | }; | |
4644 | ||
4645 | ||
4646 | /* | |
4647 | * HC state-machine | |
4648 | */ | |
4649 | struct hc_status_block_sm { | |
4650 | #if defined(__BIG_ENDIAN) | |
4651 | u8 igu_seg_id; | |
4652 | u8 igu_sb_id; | |
4653 | u8 timer_value; | |
4654 | u8 __flags; | |
4655 | #elif defined(__LITTLE_ENDIAN) | |
4656 | u8 __flags; | |
4657 | u8 timer_value; | |
4658 | u8 igu_sb_id; | |
4659 | u8 igu_seg_id; | |
4660 | #endif | |
4661 | u32 time_to_expire; | |
4662 | }; | |
4663 | ||
4664 | /* | |
4665 | * hold PCI identification variables- used in various places in firmware | |
4666 | */ | |
4667 | struct pci_entity { | |
4668 | #if defined(__BIG_ENDIAN) | |
4669 | u8 vf_valid; | |
4670 | u8 vf_id; | |
4671 | u8 vnic_id; | |
4672 | u8 pf_id; | |
4673 | #elif defined(__LITTLE_ENDIAN) | |
4674 | u8 pf_id; | |
4675 | u8 vnic_id; | |
4676 | u8 vf_id; | |
4677 | u8 vf_valid; | |
4678 | #endif | |
4679 | }; | |
4680 | ||
4681 | /* | |
4682 | * The fast-path status block meta-data, common to all chips | |
4683 | */ | |
4684 | struct hc_sb_data { | |
4685 | struct regpair host_sb_addr; | |
4686 | struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; | |
4687 | struct pci_entity p_func; | |
4688 | #if defined(__BIG_ENDIAN) | |
4689 | u8 rsrv0; | |
619c5cb6 | 4690 | u8 state; |
523224a3 | 4691 | u8 dhc_qzone_id; |
523224a3 DK |
4692 | u8 same_igu_sb_1b; |
4693 | #elif defined(__LITTLE_ENDIAN) | |
4694 | u8 same_igu_sb_1b; | |
523224a3 | 4695 | u8 dhc_qzone_id; |
619c5cb6 | 4696 | u8 state; |
523224a3 DK |
4697 | u8 rsrv0; |
4698 | #endif | |
4699 | struct regpair rsrv1[2]; | |
4700 | }; | |
4701 | ||
4702 | ||
619c5cb6 VZ |
4703 | /* |
4704 | * Segment types for host coaslescing | |
4705 | */ | |
4706 | enum hc_segment { | |
4707 | HC_REGULAR_SEGMENT, | |
4708 | HC_DEFAULT_SEGMENT, | |
4709 | MAX_HC_SEGMENT | |
4710 | }; | |
4711 | ||
4712 | ||
523224a3 DK |
4713 | /* |
4714 | * The fast-path status block meta-data | |
4715 | */ | |
4716 | struct hc_sp_status_block_data { | |
4717 | struct regpair host_sb_addr; | |
4718 | #if defined(__BIG_ENDIAN) | |
619c5cb6 VZ |
4719 | u8 rsrv1; |
4720 | u8 state; | |
523224a3 DK |
4721 | u8 igu_seg_id; |
4722 | u8 igu_sb_id; | |
4723 | #elif defined(__LITTLE_ENDIAN) | |
4724 | u8 igu_sb_id; | |
4725 | u8 igu_seg_id; | |
619c5cb6 VZ |
4726 | u8 state; |
4727 | u8 rsrv1; | |
523224a3 DK |
4728 | #endif |
4729 | struct pci_entity p_func; | |
4730 | }; | |
4731 | ||
4732 | ||
4733 | /* | |
4734 | * The fast-path status block meta-data | |
4735 | */ | |
4736 | struct hc_status_block_data_e1x { | |
4737 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; | |
4738 | struct hc_sb_data common; | |
4739 | }; | |
4740 | ||
4741 | ||
4742 | /* | |
4743 | * The fast-path status block meta-data | |
4744 | */ | |
4745 | struct hc_status_block_data_e2 { | |
4746 | struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; | |
4747 | struct hc_sb_data common; | |
4748 | }; | |
4749 | ||
4750 | ||
619c5cb6 VZ |
4751 | /* |
4752 | * IGU block operartion modes (in Everest2) | |
4753 | */ | |
4754 | enum igu_mode { | |
4755 | HC_IGU_BC_MODE, | |
4756 | HC_IGU_NBC_MODE, | |
4757 | MAX_IGU_MODE | |
4758 | }; | |
4759 | ||
4760 | ||
4761 | /* | |
4762 | * IP versions | |
4763 | */ | |
4764 | enum ip_ver { | |
4765 | IP_V4, | |
4766 | IP_V6, | |
4767 | MAX_IP_VER | |
4768 | }; | |
4769 | ||
4770 | ||
4771 | /* | |
4772 | * Multi-function modes | |
4773 | */ | |
4774 | enum mf_mode { | |
4775 | SINGLE_FUNCTION, | |
4776 | MULTI_FUNCTION_SD, | |
4777 | MULTI_FUNCTION_SI, | |
4778 | MULTI_FUNCTION_RESERVED, | |
4779 | MAX_MF_MODE | |
4780 | }; | |
4781 | ||
4782 | /* | |
4783 | * Protocol-common statistics collected by the Tstorm (per pf) | |
4784 | */ | |
4785 | struct tstorm_per_pf_stats { | |
4786 | struct regpair rcv_error_bytes; | |
4787 | }; | |
4788 | ||
4789 | /* | |
4790 | * | |
4791 | */ | |
4792 | struct per_pf_stats { | |
4793 | struct tstorm_per_pf_stats tstorm_pf_statistics; | |
4794 | }; | |
4795 | ||
4796 | ||
4797 | /* | |
4798 | * Protocol-common statistics collected by the Tstorm (per port) | |
4799 | */ | |
4800 | struct tstorm_per_port_stats { | |
4801 | __le32 mac_discard; | |
4802 | __le32 mac_filter_discard; | |
4803 | __le32 brb_truncate_discard; | |
4804 | __le32 mf_tag_discard; | |
4805 | __le32 packet_drop; | |
4806 | __le32 reserved; | |
4807 | }; | |
4808 | ||
4809 | /* | |
4810 | * | |
4811 | */ | |
4812 | struct per_port_stats { | |
4813 | struct tstorm_per_port_stats tstorm_port_statistics; | |
4814 | }; | |
4815 | ||
4816 | ||
4817 | /* | |
4818 | * Protocol-common statistics collected by the Tstorm (per client) | |
4819 | */ | |
4820 | struct tstorm_per_queue_stats { | |
4821 | struct regpair rcv_ucast_bytes; | |
4822 | __le32 rcv_ucast_pkts; | |
4823 | __le32 checksum_discard; | |
4824 | struct regpair rcv_bcast_bytes; | |
4825 | __le32 rcv_bcast_pkts; | |
4826 | __le32 pkts_too_big_discard; | |
4827 | struct regpair rcv_mcast_bytes; | |
4828 | __le32 rcv_mcast_pkts; | |
4829 | __le32 ttl0_discard; | |
4830 | __le16 no_buff_discard; | |
4831 | __le16 reserved0; | |
4832 | __le32 reserved1; | |
4833 | }; | |
4834 | ||
4835 | /* | |
4836 | * Protocol-common statistics collected by the Ustorm (per client) | |
4837 | */ | |
4838 | struct ustorm_per_queue_stats { | |
4839 | struct regpair ucast_no_buff_bytes; | |
4840 | struct regpair mcast_no_buff_bytes; | |
4841 | struct regpair bcast_no_buff_bytes; | |
4842 | __le32 ucast_no_buff_pkts; | |
4843 | __le32 mcast_no_buff_pkts; | |
4844 | __le32 bcast_no_buff_pkts; | |
4845 | __le32 coalesced_pkts; | |
4846 | struct regpair coalesced_bytes; | |
4847 | __le32 coalesced_events; | |
4848 | __le32 coalesced_aborts; | |
4849 | }; | |
4850 | ||
4851 | /* | |
4852 | * Protocol-common statistics collected by the Xstorm (per client) | |
4853 | */ | |
4854 | struct xstorm_per_queue_stats { | |
4855 | struct regpair ucast_bytes_sent; | |
4856 | struct regpair mcast_bytes_sent; | |
4857 | struct regpair bcast_bytes_sent; | |
4858 | __le32 ucast_pkts_sent; | |
4859 | __le32 mcast_pkts_sent; | |
4860 | __le32 bcast_pkts_sent; | |
4861 | __le32 error_drop_pkts; | |
4862 | }; | |
4863 | ||
4864 | /* | |
4865 | * | |
4866 | */ | |
4867 | struct per_queue_stats { | |
4868 | struct tstorm_per_queue_stats tstorm_queue_statistics; | |
4869 | struct ustorm_per_queue_stats ustorm_queue_statistics; | |
4870 | struct xstorm_per_queue_stats xstorm_queue_statistics; | |
4871 | }; | |
4872 | ||
4873 | ||
a2fbb9ea ET |
4874 | /* |
4875 | * FW version stored in first line of pram | |
4876 | */ | |
4877 | struct pram_fw_version { | |
8d9c5f34 EG |
4878 | u8 major; |
4879 | u8 minor; | |
4880 | u8 revision; | |
4881 | u8 engineering; | |
a2fbb9ea ET |
4882 | u8 flags; |
4883 | #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) | |
4884 | #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 | |
4885 | #define PRAM_FW_VERSION_STORM_ID (0x3<<1) | |
4886 | #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 | |
4887 | #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) | |
4888 | #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 | |
34f80b04 EG |
4889 | #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) |
4890 | #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 | |
4891 | #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) | |
4892 | #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 | |
4893 | }; | |
4894 | ||
4895 | ||
523224a3 DK |
4896 | /* |
4897 | * Ethernet slow path element | |
4898 | */ | |
4899 | union protocol_common_specific_data { | |
4900 | u8 protocol_data[8]; | |
4901 | struct regpair phy_address; | |
4902 | struct regpair mac_config_addr; | |
523224a3 DK |
4903 | }; |
4904 | ||
ca00392c EG |
4905 | /* |
4906 | * The send queue element | |
4907 | */ | |
4908 | struct protocol_common_spe { | |
4909 | struct spe_hdr hdr; | |
523224a3 | 4910 | union protocol_common_specific_data data; |
ca00392c EG |
4911 | }; |
4912 | ||
4913 | ||
34f80b04 EG |
4914 | /* |
4915 | * a single rate shaping counter. can be used as protocol or vnic counter | |
4916 | */ | |
4917 | struct rate_shaping_counter { | |
4918 | u32 quota; | |
4919 | #if defined(__BIG_ENDIAN) | |
4920 | u16 __reserved0; | |
4921 | u16 rate; | |
4922 | #elif defined(__LITTLE_ENDIAN) | |
4923 | u16 rate; | |
4924 | u16 __reserved0; | |
4925 | #endif | |
4926 | }; | |
4927 | ||
4928 | ||
4929 | /* | |
4930 | * per-vnic rate shaping variables | |
4931 | */ | |
4932 | struct rate_shaping_vars_per_vn { | |
34f80b04 | 4933 | struct rate_shaping_counter vn_counter; |
a2fbb9ea ET |
4934 | }; |
4935 | ||
4936 | ||
4937 | /* | |
4938 | * The send queue element | |
4939 | */ | |
4940 | struct slow_path_element { | |
4941 | struct spe_hdr hdr; | |
523224a3 | 4942 | struct regpair protocol_data; |
a2fbb9ea ET |
4943 | }; |
4944 | ||
4945 | ||
4946 | /* | |
619c5cb6 | 4947 | * Protocol-common statistics counter |
a2fbb9ea | 4948 | */ |
619c5cb6 VZ |
4949 | struct stats_counter { |
4950 | __le16 xstats_counter; | |
4951 | __le16 reserved0; | |
4952 | __le32 reserved1; | |
4953 | __le16 tstats_counter; | |
4954 | __le16 reserved2; | |
4955 | __le32 reserved3; | |
4956 | __le16 ustats_counter; | |
4957 | __le16 reserved4; | |
4958 | __le32 reserved5; | |
4959 | __le16 cstats_counter; | |
4960 | __le16 reserved6; | |
4961 | __le32 reserved7; | |
a2fbb9ea ET |
4962 | }; |
4963 | ||
4964 | ||
523224a3 | 4965 | /* |
619c5cb6 | 4966 | * |
523224a3 | 4967 | */ |
619c5cb6 VZ |
4968 | struct stats_query_entry { |
4969 | u8 kind; | |
4970 | u8 index; | |
4971 | __le16 funcID; | |
4972 | __le32 reserved; | |
4973 | struct regpair address; | |
523224a3 DK |
4974 | }; |
4975 | ||
4976 | /* | |
619c5cb6 | 4977 | * statistic command |
523224a3 | 4978 | */ |
619c5cb6 VZ |
4979 | struct stats_query_cmd_group { |
4980 | struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; | |
4981 | }; | |
4982 | ||
4983 | ||
4984 | /* | |
4985 | * statistic command header | |
4986 | */ | |
4987 | struct stats_query_header { | |
4988 | u8 cmd_num; | |
4989 | u8 reserved0; | |
4990 | __le16 drv_stats_counter; | |
4991 | __le32 reserved1; | |
4992 | struct regpair stats_counters_addrs; | |
4993 | }; | |
4994 | ||
4995 | ||
4996 | /* | |
4997 | * Types of statistcis query entry | |
4998 | */ | |
4999 | enum stats_query_type { | |
5000 | STATS_TYPE_QUEUE, | |
5001 | STATS_TYPE_PORT, | |
5002 | STATS_TYPE_PF, | |
5003 | STATS_TYPE_TOE, | |
5004 | STATS_TYPE_FCOE, | |
5005 | MAX_STATS_QUERY_TYPE | |
5006 | }; | |
5007 | ||
5008 | ||
5009 | /* | |
5010 | * Indicate of the function status block state | |
5011 | */ | |
5012 | enum status_block_state { | |
5013 | SB_DISABLED, | |
5014 | SB_ENABLED, | |
5015 | SB_CLEANED, | |
5016 | MAX_STATUS_BLOCK_STATE | |
5017 | }; | |
5018 | ||
5019 | ||
5020 | /* | |
5021 | * Storm IDs (including attentions for IGU related enums) | |
5022 | */ | |
5023 | enum storm_id { | |
5024 | USTORM_ID, | |
5025 | CSTORM_ID, | |
5026 | XSTORM_ID, | |
5027 | TSTORM_ID, | |
5028 | ATTENTION_ID, | |
5029 | MAX_STORM_ID | |
5030 | }; | |
5031 | ||
5032 | ||
5033 | /* | |
5034 | * Taffic types used in ETS and flow control algorithms | |
5035 | */ | |
5036 | enum traffic_type { | |
5037 | LLFC_TRAFFIC_TYPE_NW, | |
5038 | LLFC_TRAFFIC_TYPE_FCOE, | |
5039 | LLFC_TRAFFIC_TYPE_ISCSI, | |
5040 | MAX_TRAFFIC_TYPE | |
523224a3 DK |
5041 | }; |
5042 | ||
5043 | ||
5044 | /* | |
5045 | * zone A per-queue data | |
5046 | */ | |
5047 | struct tstorm_queue_zone_data { | |
5048 | struct regpair reserved[4]; | |
5049 | }; | |
5050 | ||
5051 | ||
5052 | /* | |
5053 | * zone B per-VF data | |
5054 | */ | |
5055 | struct tstorm_vf_zone_data { | |
5056 | struct regpair reserved; | |
5057 | }; | |
5058 | ||
5059 | ||
5060 | /* | |
5061 | * zone A per-queue data | |
5062 | */ | |
5063 | struct ustorm_queue_zone_data { | |
5064 | struct ustorm_eth_rx_producers eth_rx_producers; | |
5065 | struct regpair reserved[3]; | |
5066 | }; | |
5067 | ||
5068 | ||
5069 | /* | |
5070 | * zone B per-VF data | |
5071 | */ | |
5072 | struct ustorm_vf_zone_data { | |
5073 | struct regpair reserved; | |
5074 | }; | |
5075 | ||
5076 | ||
5077 | /* | |
5078 | * data per VF-PF channel | |
5079 | */ | |
5080 | struct vf_pf_channel_data { | |
5081 | #if defined(__BIG_ENDIAN) | |
5082 | u16 reserved0; | |
5083 | u8 valid; | |
5084 | u8 state; | |
5085 | #elif defined(__LITTLE_ENDIAN) | |
5086 | u8 state; | |
5087 | u8 valid; | |
5088 | u16 reserved0; | |
5089 | #endif | |
5090 | u32 reserved1; | |
5091 | }; | |
5092 | ||
5093 | ||
619c5cb6 VZ |
5094 | /* |
5095 | * State of VF-PF channel | |
5096 | */ | |
5097 | enum vf_pf_channel_state { | |
5098 | VF_PF_CHANNEL_STATE_READY, | |
5099 | VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, | |
5100 | MAX_VF_PF_CHANNEL_STATE | |
5101 | }; | |
5102 | ||
5103 | ||
523224a3 DK |
5104 | /* |
5105 | * zone A per-queue data | |
5106 | */ | |
5107 | struct xstorm_queue_zone_data { | |
5108 | struct regpair reserved[4]; | |
5109 | }; | |
5110 | ||
5111 | ||
5112 | /* | |
5113 | * zone B per-VF data | |
5114 | */ | |
5115 | struct xstorm_vf_zone_data { | |
5116 | struct regpair reserved; | |
5117 | }; | |
5118 | ||
5119 | #endif /* BNX2X_HSI_H */ |