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4d22de3e DLR |
1 | /* |
2 | * This file is automatically generated --- any changes will be lost. | |
3 | */ | |
4 | ||
5 | #ifndef _SGE_DEFS_H | |
6 | #define _SGE_DEFS_H | |
7 | ||
8 | #define S_EC_CREDITS 0 | |
9 | #define M_EC_CREDITS 0x7FFF | |
10 | #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) | |
11 | #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) | |
12 | ||
13 | #define S_EC_GTS 15 | |
14 | #define V_EC_GTS(x) ((x) << S_EC_GTS) | |
15 | #define F_EC_GTS V_EC_GTS(1U) | |
16 | ||
17 | #define S_EC_INDEX 16 | |
18 | #define M_EC_INDEX 0xFFFF | |
19 | #define V_EC_INDEX(x) ((x) << S_EC_INDEX) | |
20 | #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) | |
21 | ||
22 | #define S_EC_SIZE 0 | |
23 | #define M_EC_SIZE 0xFFFF | |
24 | #define V_EC_SIZE(x) ((x) << S_EC_SIZE) | |
25 | #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) | |
26 | ||
27 | #define S_EC_BASE_LO 16 | |
28 | #define M_EC_BASE_LO 0xFFFF | |
29 | #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO) | |
30 | #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) | |
31 | ||
32 | #define S_EC_BASE_HI 0 | |
33 | #define M_EC_BASE_HI 0xF | |
34 | #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI) | |
35 | #define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI) | |
36 | ||
37 | #define S_EC_RESPQ 4 | |
38 | #define M_EC_RESPQ 0x7 | |
39 | #define V_EC_RESPQ(x) ((x) << S_EC_RESPQ) | |
40 | #define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ) | |
41 | ||
42 | #define S_EC_TYPE 7 | |
43 | #define M_EC_TYPE 0x7 | |
44 | #define V_EC_TYPE(x) ((x) << S_EC_TYPE) | |
45 | #define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE) | |
46 | ||
47 | #define S_EC_GEN 10 | |
48 | #define V_EC_GEN(x) ((x) << S_EC_GEN) | |
49 | #define F_EC_GEN V_EC_GEN(1U) | |
50 | ||
51 | #define S_EC_UP_TOKEN 11 | |
52 | #define M_EC_UP_TOKEN 0xFFFFF | |
53 | #define V_EC_UP_TOKEN(x) ((x) << S_EC_UP_TOKEN) | |
54 | #define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN) | |
55 | ||
56 | #define S_EC_VALID 31 | |
57 | #define V_EC_VALID(x) ((x) << S_EC_VALID) | |
58 | #define F_EC_VALID V_EC_VALID(1U) | |
59 | ||
60 | #define S_RQ_MSI_VEC 20 | |
61 | #define M_RQ_MSI_VEC 0x3F | |
62 | #define V_RQ_MSI_VEC(x) ((x) << S_RQ_MSI_VEC) | |
63 | #define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC) | |
64 | ||
65 | #define S_RQ_INTR_EN 26 | |
66 | #define V_RQ_INTR_EN(x) ((x) << S_RQ_INTR_EN) | |
67 | #define F_RQ_INTR_EN V_RQ_INTR_EN(1U) | |
68 | ||
69 | #define S_RQ_GEN 28 | |
70 | #define V_RQ_GEN(x) ((x) << S_RQ_GEN) | |
71 | #define F_RQ_GEN V_RQ_GEN(1U) | |
72 | ||
73 | #define S_CQ_INDEX 0 | |
74 | #define M_CQ_INDEX 0xFFFF | |
75 | #define V_CQ_INDEX(x) ((x) << S_CQ_INDEX) | |
76 | #define G_CQ_INDEX(x) (((x) >> S_CQ_INDEX) & M_CQ_INDEX) | |
77 | ||
78 | #define S_CQ_SIZE 16 | |
79 | #define M_CQ_SIZE 0xFFFF | |
80 | #define V_CQ_SIZE(x) ((x) << S_CQ_SIZE) | |
81 | #define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE) | |
82 | ||
83 | #define S_CQ_BASE_HI 0 | |
84 | #define M_CQ_BASE_HI 0xFFFFF | |
85 | #define V_CQ_BASE_HI(x) ((x) << S_CQ_BASE_HI) | |
86 | #define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI) | |
87 | ||
88 | #define S_CQ_RSPQ 20 | |
89 | #define M_CQ_RSPQ 0x3F | |
90 | #define V_CQ_RSPQ(x) ((x) << S_CQ_RSPQ) | |
91 | #define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ) | |
92 | ||
93 | #define S_CQ_ASYNC_NOTIF 26 | |
94 | #define V_CQ_ASYNC_NOTIF(x) ((x) << S_CQ_ASYNC_NOTIF) | |
95 | #define F_CQ_ASYNC_NOTIF V_CQ_ASYNC_NOTIF(1U) | |
96 | ||
97 | #define S_CQ_ARMED 27 | |
98 | #define V_CQ_ARMED(x) ((x) << S_CQ_ARMED) | |
99 | #define F_CQ_ARMED V_CQ_ARMED(1U) | |
100 | ||
101 | #define S_CQ_ASYNC_NOTIF_SOL 28 | |
102 | #define V_CQ_ASYNC_NOTIF_SOL(x) ((x) << S_CQ_ASYNC_NOTIF_SOL) | |
103 | #define F_CQ_ASYNC_NOTIF_SOL V_CQ_ASYNC_NOTIF_SOL(1U) | |
104 | ||
105 | #define S_CQ_GEN 29 | |
106 | #define V_CQ_GEN(x) ((x) << S_CQ_GEN) | |
107 | #define F_CQ_GEN V_CQ_GEN(1U) | |
108 | ||
1c17ae8a DLR |
109 | #define S_CQ_ERR 30 |
110 | #define V_CQ_ERR(x) ((x) << S_CQ_ERR) | |
111 | #define F_CQ_ERR V_CQ_ERR(1U) | |
112 | ||
4d22de3e DLR |
113 | #define S_CQ_OVERFLOW_MODE 31 |
114 | #define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE) | |
115 | #define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U) | |
116 | ||
117 | #define S_CQ_CREDITS 0 | |
118 | #define M_CQ_CREDITS 0xFFFF | |
119 | #define V_CQ_CREDITS(x) ((x) << S_CQ_CREDITS) | |
120 | #define G_CQ_CREDITS(x) (((x) >> S_CQ_CREDITS) & M_CQ_CREDITS) | |
121 | ||
122 | #define S_CQ_CREDIT_THRES 16 | |
123 | #define M_CQ_CREDIT_THRES 0x1FFF | |
124 | #define V_CQ_CREDIT_THRES(x) ((x) << S_CQ_CREDIT_THRES) | |
125 | #define G_CQ_CREDIT_THRES(x) (((x) >> S_CQ_CREDIT_THRES) & M_CQ_CREDIT_THRES) | |
126 | ||
127 | #define S_FL_BASE_HI 0 | |
128 | #define M_FL_BASE_HI 0xFFFFF | |
129 | #define V_FL_BASE_HI(x) ((x) << S_FL_BASE_HI) | |
130 | #define G_FL_BASE_HI(x) (((x) >> S_FL_BASE_HI) & M_FL_BASE_HI) | |
131 | ||
132 | #define S_FL_INDEX_LO 20 | |
133 | #define M_FL_INDEX_LO 0xFFF | |
134 | #define V_FL_INDEX_LO(x) ((x) << S_FL_INDEX_LO) | |
135 | #define G_FL_INDEX_LO(x) (((x) >> S_FL_INDEX_LO) & M_FL_INDEX_LO) | |
136 | ||
137 | #define S_FL_INDEX_HI 0 | |
138 | #define M_FL_INDEX_HI 0xF | |
139 | #define V_FL_INDEX_HI(x) ((x) << S_FL_INDEX_HI) | |
140 | #define G_FL_INDEX_HI(x) (((x) >> S_FL_INDEX_HI) & M_FL_INDEX_HI) | |
141 | ||
142 | #define S_FL_SIZE 4 | |
143 | #define M_FL_SIZE 0xFFFF | |
144 | #define V_FL_SIZE(x) ((x) << S_FL_SIZE) | |
145 | #define G_FL_SIZE(x) (((x) >> S_FL_SIZE) & M_FL_SIZE) | |
146 | ||
147 | #define S_FL_GEN 20 | |
148 | #define V_FL_GEN(x) ((x) << S_FL_GEN) | |
149 | #define F_FL_GEN V_FL_GEN(1U) | |
150 | ||
151 | #define S_FL_ENTRY_SIZE_LO 21 | |
152 | #define M_FL_ENTRY_SIZE_LO 0x7FF | |
153 | #define V_FL_ENTRY_SIZE_LO(x) ((x) << S_FL_ENTRY_SIZE_LO) | |
154 | #define G_FL_ENTRY_SIZE_LO(x) (((x) >> S_FL_ENTRY_SIZE_LO) & M_FL_ENTRY_SIZE_LO) | |
155 | ||
156 | #define S_FL_ENTRY_SIZE_HI 0 | |
157 | #define M_FL_ENTRY_SIZE_HI 0x1FFFFF | |
158 | #define V_FL_ENTRY_SIZE_HI(x) ((x) << S_FL_ENTRY_SIZE_HI) | |
159 | #define G_FL_ENTRY_SIZE_HI(x) (((x) >> S_FL_ENTRY_SIZE_HI) & M_FL_ENTRY_SIZE_HI) | |
160 | ||
161 | #define S_FL_CONG_THRES 21 | |
162 | #define M_FL_CONG_THRES 0x3FF | |
163 | #define V_FL_CONG_THRES(x) ((x) << S_FL_CONG_THRES) | |
164 | #define G_FL_CONG_THRES(x) (((x) >> S_FL_CONG_THRES) & M_FL_CONG_THRES) | |
165 | ||
166 | #define S_FL_GTS 31 | |
167 | #define V_FL_GTS(x) ((x) << S_FL_GTS) | |
168 | #define F_FL_GTS V_FL_GTS(1U) | |
169 | ||
170 | #define S_FLD_GEN1 31 | |
171 | #define V_FLD_GEN1(x) ((x) << S_FLD_GEN1) | |
172 | #define F_FLD_GEN1 V_FLD_GEN1(1U) | |
173 | ||
174 | #define S_FLD_GEN2 0 | |
175 | #define V_FLD_GEN2(x) ((x) << S_FLD_GEN2) | |
176 | #define F_FLD_GEN2 V_FLD_GEN2(1U) | |
177 | ||
178 | #define S_RSPD_TXQ1_CR 0 | |
179 | #define M_RSPD_TXQ1_CR 0x7F | |
180 | #define V_RSPD_TXQ1_CR(x) ((x) << S_RSPD_TXQ1_CR) | |
181 | #define G_RSPD_TXQ1_CR(x) (((x) >> S_RSPD_TXQ1_CR) & M_RSPD_TXQ1_CR) | |
182 | ||
183 | #define S_RSPD_TXQ1_GTS 7 | |
184 | #define V_RSPD_TXQ1_GTS(x) ((x) << S_RSPD_TXQ1_GTS) | |
185 | #define F_RSPD_TXQ1_GTS V_RSPD_TXQ1_GTS(1U) | |
186 | ||
187 | #define S_RSPD_TXQ2_CR 8 | |
188 | #define M_RSPD_TXQ2_CR 0x7F | |
189 | #define V_RSPD_TXQ2_CR(x) ((x) << S_RSPD_TXQ2_CR) | |
190 | #define G_RSPD_TXQ2_CR(x) (((x) >> S_RSPD_TXQ2_CR) & M_RSPD_TXQ2_CR) | |
191 | ||
192 | #define S_RSPD_TXQ2_GTS 15 | |
193 | #define V_RSPD_TXQ2_GTS(x) ((x) << S_RSPD_TXQ2_GTS) | |
194 | #define F_RSPD_TXQ2_GTS V_RSPD_TXQ2_GTS(1U) | |
195 | ||
196 | #define S_RSPD_TXQ0_CR 16 | |
197 | #define M_RSPD_TXQ0_CR 0x7F | |
198 | #define V_RSPD_TXQ0_CR(x) ((x) << S_RSPD_TXQ0_CR) | |
199 | #define G_RSPD_TXQ0_CR(x) (((x) >> S_RSPD_TXQ0_CR) & M_RSPD_TXQ0_CR) | |
200 | ||
201 | #define S_RSPD_TXQ0_GTS 23 | |
202 | #define V_RSPD_TXQ0_GTS(x) ((x) << S_RSPD_TXQ0_GTS) | |
203 | #define F_RSPD_TXQ0_GTS V_RSPD_TXQ0_GTS(1U) | |
204 | ||
205 | #define S_RSPD_EOP 24 | |
206 | #define V_RSPD_EOP(x) ((x) << S_RSPD_EOP) | |
207 | #define F_RSPD_EOP V_RSPD_EOP(1U) | |
208 | ||
209 | #define S_RSPD_SOP 25 | |
210 | #define V_RSPD_SOP(x) ((x) << S_RSPD_SOP) | |
211 | #define F_RSPD_SOP V_RSPD_SOP(1U) | |
212 | ||
213 | #define S_RSPD_ASYNC_NOTIF 26 | |
214 | #define V_RSPD_ASYNC_NOTIF(x) ((x) << S_RSPD_ASYNC_NOTIF) | |
215 | #define F_RSPD_ASYNC_NOTIF V_RSPD_ASYNC_NOTIF(1U) | |
216 | ||
217 | #define S_RSPD_FL0_GTS 27 | |
218 | #define V_RSPD_FL0_GTS(x) ((x) << S_RSPD_FL0_GTS) | |
219 | #define F_RSPD_FL0_GTS V_RSPD_FL0_GTS(1U) | |
220 | ||
221 | #define S_RSPD_FL1_GTS 28 | |
222 | #define V_RSPD_FL1_GTS(x) ((x) << S_RSPD_FL1_GTS) | |
223 | #define F_RSPD_FL1_GTS V_RSPD_FL1_GTS(1U) | |
224 | ||
225 | #define S_RSPD_IMM_DATA_VALID 29 | |
226 | #define V_RSPD_IMM_DATA_VALID(x) ((x) << S_RSPD_IMM_DATA_VALID) | |
227 | #define F_RSPD_IMM_DATA_VALID V_RSPD_IMM_DATA_VALID(1U) | |
228 | ||
229 | #define S_RSPD_OFFLOAD 30 | |
230 | #define V_RSPD_OFFLOAD(x) ((x) << S_RSPD_OFFLOAD) | |
231 | #define F_RSPD_OFFLOAD V_RSPD_OFFLOAD(1U) | |
232 | ||
233 | #define S_RSPD_GEN1 31 | |
234 | #define V_RSPD_GEN1(x) ((x) << S_RSPD_GEN1) | |
235 | #define F_RSPD_GEN1 V_RSPD_GEN1(1U) | |
236 | ||
237 | #define S_RSPD_LEN 0 | |
238 | #define M_RSPD_LEN 0x7FFFFFFF | |
239 | #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) | |
240 | #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) | |
241 | ||
242 | #define S_RSPD_FLQ 31 | |
243 | #define V_RSPD_FLQ(x) ((x) << S_RSPD_FLQ) | |
244 | #define F_RSPD_FLQ V_RSPD_FLQ(1U) | |
245 | ||
246 | #define S_RSPD_GEN2 0 | |
247 | #define V_RSPD_GEN2(x) ((x) << S_RSPD_GEN2) | |
248 | #define F_RSPD_GEN2 V_RSPD_GEN2(1U) | |
249 | ||
250 | #define S_RSPD_INR_VEC 1 | |
251 | #define M_RSPD_INR_VEC 0x7F | |
252 | #define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC) | |
253 | #define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC) | |
254 | ||
255 | #endif /* _SGE_DEFS_H */ |