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netdevice zd1201: Use after free
[deliverable/linux.git] / drivers / net / enc28j60.c
CommitLineData
3ec9c11d
CL		 1/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/slab.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/tcp.h>
29#include <linux/skbuff.h>
30#include <linux/delay.h>
31#include <linux/spi/spi.h>
32
33#include "enc28j60_hw.h"
34
35#define DRV_NAME "enc28j60"
36#define DRV_VERSION "1.01"
37
38#define SPI_OPLEN 1
39
40#define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
42
43/* Buffer size required for the largest SPI transfer (i.e., reading a
44 * frame). */
45#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
46
47#define TX_TIMEOUT (4 * HZ)
48
49/* Max TX retries in case of collision as suggested by errata datasheet */
50#define MAX_TX_RETRYCOUNT 16
51
52enum {
53 RXFILTER_NORMAL,
54 RXFILTER_MULTI,
55 RXFILTER_PROMISC
56};
57
58/* Driver local data */
59struct enc28j60_net {
60 struct net_device *netdev;
61 struct spi_device *spi;
62 struct mutex lock;
63 struct sk_buff *tx_skb;
64 struct work_struct tx_work;
65 struct work_struct irq_work;
66 struct work_struct setrx_work;
67 struct work_struct restart_work;
68 u8 bank; /* current register bank selected */
69 u16 next_pk_ptr; /* next packet pointer within FIFO */
70 u16 max_pk_counter; /* statistics: max packet counter */
71 u16 tx_retry_count;
72 bool hw_enable;
73 bool full_duplex;
74 int rxfilter;
75 u32 msg_enable;
76 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
77};
78
79/* use ethtool to change the level for any given device */
80static struct {
81 u32 msg_enable;
82} debug = { -1 };
83
84/*
85 * SPI read buffer
86 * wait for the SPI transfer and copy received data to destination
87 */
88static int
89spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
90{
91 u8 *rx_buf = priv->spi_transfer_buf + 4;
92 u8 *tx_buf = priv->spi_transfer_buf;
93 struct spi_transfer t = {
94 .tx_buf = tx_buf,
95 .rx_buf = rx_buf,
96 .len = SPI_OPLEN + len,
97 };
98 struct spi_message msg;
99 int ret;
100
101 tx_buf[0] = ENC28J60_READ_BUF_MEM;
102 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
103
104 spi_message_init(&msg);
105 spi_message_add_tail(&t, &msg);
106 ret = spi_sync(priv->spi, &msg);
107 if (ret == 0) {
108 memcpy(data, &rx_buf[SPI_OPLEN], len);
109 ret = msg.status;
110 }
111 if (ret && netif_msg_drv(priv))
112 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 113 __func__, ret);
3ec9c11d
CL		 114
115 return ret;
116}
117
118/*
119 * SPI write buffer
120 */
121static int spi_write_buf(struct enc28j60_net *priv, int len,
122 const u8 *data)
123{
124 int ret;
125
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127 ret = -EINVAL;
128 else {
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 134 __func__, ret);
3ec9c11d
CL		 135 }
136 return ret;
137}
138
139/*
140 * basic SPI read operation
141 */
142static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
143 u8 addr)
144{
145 u8 tx_buf[2];
146 u8 rx_buf[4];
147 u8 val = 0;
148 int ret;
149 int slen = SPI_OPLEN;
150
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
153 slen++;
154
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157 if (ret)
158 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 159 __func__, ret);
3ec9c11d
CL		 160 else
161 val = rx_buf[slen - 1];
162
163 return val;
164}
165
166/*
167 * basic SPI write operation
168 */
169static int spi_write_op(struct enc28j60_net *priv, u8 op,
170 u8 addr, u8 val)
171{
172 int ret;
173
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
b39d66a8 179 __func__, ret);
3ec9c11d
CL		 180 return ret;
181}
182
183static void enc28j60_soft_reset(struct enc28j60_net *priv)
184{
185 if (netif_msg_hw(priv))
b39d66a8 186 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 187
188 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
191 udelay(2000);
192}
193
194/*
195 * select the current register bank if necessary
196 */
197static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
198{
199 if ((addr & BANK_MASK) != priv->bank) {
200 u8 b = (addr & BANK_MASK) >> 5;
201
202 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204 ECON1_BSEL1 | ECON1_BSEL0);
205 if (b != 0)
206 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207 priv->bank = (addr & BANK_MASK);
208 }
209}
210
211/*
212 * Register access routines through the SPI bus.
213 * Every register access comes in two flavours:
214 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215 * atomically more than one register
216 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
217 *
218 * Some registers can be accessed through the bit field clear and
219 * bit field set to avoid a read modify write cycle.
220 */
221
222/*
223 * Register bit field Set
224 */
225static void nolock_reg_bfset(struct enc28j60_net *priv,
226 u8 addr, u8 mask)
227{
228 enc28j60_set_bank(priv, addr);
229 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
230}
231
232static void locked_reg_bfset(struct enc28j60_net *priv,
233 u8 addr, u8 mask)
234{
235 mutex_lock(&priv->lock);
236 nolock_reg_bfset(priv, addr, mask);
237 mutex_unlock(&priv->lock);
238}
239
240/*
241 * Register bit field Clear
242 */
243static void nolock_reg_bfclr(struct enc28j60_net *priv,
244 u8 addr, u8 mask)
245{
246 enc28j60_set_bank(priv, addr);
247 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
248}
249
250static void locked_reg_bfclr(struct enc28j60_net *priv,
251 u8 addr, u8 mask)
252{
253 mutex_lock(&priv->lock);
254 nolock_reg_bfclr(priv, addr, mask);
255 mutex_unlock(&priv->lock);
256}
257
258/*
259 * Register byte read
260 */
261static int nolock_regb_read(struct enc28j60_net *priv,
262 u8 address)
263{
264 enc28j60_set_bank(priv, address);
265 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
266}
267
268static int locked_regb_read(struct enc28j60_net *priv,
269 u8 address)
270{
271 int ret;
272
273 mutex_lock(&priv->lock);
274 ret = nolock_regb_read(priv, address);
275 mutex_unlock(&priv->lock);
276
277 return ret;
278}
279
280/*
281 * Register word read
282 */
283static int nolock_regw_read(struct enc28j60_net *priv,
284 u8 address)
285{
286 int rl, rh;
287
288 enc28j60_set_bank(priv, address);
289 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
291
292 return (rh << 8) | rl;
293}
294
295static int locked_regw_read(struct enc28j60_net *priv,
296 u8 address)
297{
298 int ret;
299
300 mutex_lock(&priv->lock);
301 ret = nolock_regw_read(priv, address);
302 mutex_unlock(&priv->lock);
303
304 return ret;
305}
306
307/*
308 * Register byte write
309 */
310static void nolock_regb_write(struct enc28j60_net *priv,
311 u8 address, u8 data)
312{
313 enc28j60_set_bank(priv, address);
314 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
315}
316
317static void locked_regb_write(struct enc28j60_net *priv,
318 u8 address, u8 data)
319{
320 mutex_lock(&priv->lock);
321 nolock_regb_write(priv, address, data);
322 mutex_unlock(&priv->lock);
323}
324
325/*
326 * Register word write
327 */
328static void nolock_regw_write(struct enc28j60_net *priv,
329 u8 address, u16 data)
330{
331 enc28j60_set_bank(priv, address);
332 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
334 (u8) (data >> 8));
335}
336
337static void locked_regw_write(struct enc28j60_net *priv,
338 u8 address, u16 data)
339{
340 mutex_lock(&priv->lock);
341 nolock_regw_write(priv, address, data);
342 mutex_unlock(&priv->lock);
343}
344
345/*
346 * Buffer memory read
347 * Select the starting address and execute a SPI buffer read
348 */
349static void enc28j60_mem_read(struct enc28j60_net *priv,
350 u16 addr, int len, u8 *data)
351{
352 mutex_lock(&priv->lock);
353 nolock_regw_write(priv, ERDPTL, addr);
354#ifdef CONFIG_ENC28J60_WRITEVERIFY
355 if (netif_msg_drv(priv)) {
356 u16 reg;
357 reg = nolock_regw_read(priv, ERDPTL);
358 if (reg != addr)
359 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
b39d66a8 360 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
3ec9c11d
CL		 361 }
362#endif
363 spi_read_buf(priv, len, data);
364 mutex_unlock(&priv->lock);
365}
366
367/*
368 * Write packet to enc28j60 TX buffer memory
369 */
370static void
371enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
372{
373 mutex_lock(&priv->lock);
374 /* Set the write pointer to start of transmit buffer area */
375 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376#ifdef CONFIG_ENC28J60_WRITEVERIFY
377 if (netif_msg_drv(priv)) {
378 u16 reg;
379 reg = nolock_regw_read(priv, EWRPTL);
380 if (reg != TXSTART_INIT)
381 printk(KERN_DEBUG DRV_NAME
382 ": %s() ERWPT:0x%04x != 0x%04x\n",
b39d66a8 383 __func__, reg, TXSTART_INIT);
3ec9c11d
CL		 384 }
385#endif
386 /* Set the TXND pointer to correspond to the packet size given */
387 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388 /* write per-packet control byte */
389 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390 if (netif_msg_hw(priv))
391 printk(KERN_DEBUG DRV_NAME
392 ": %s() after control byte ERWPT:0x%04x\n",
b39d66a8 393 __func__, nolock_regw_read(priv, EWRPTL));
3ec9c11d
CL		 394 /* copy the packet into the transmit buffer */
395 spi_write_buf(priv, len, data);
396 if (netif_msg_hw(priv))
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
b39d66a8 399 __func__, nolock_regw_read(priv, EWRPTL), len);
3ec9c11d
CL		 400 mutex_unlock(&priv->lock);
401}
402
7dac6f8d
DB		 403static unsigned long msec20_to_jiffies;
404
405static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
3ec9c11d 406{
7dac6f8d 407 unsigned long timeout = jiffies + msec20_to_jiffies;
3ec9c11d
CL		 408
409 /* 20 msec timeout read */
7dac6f8d 410 while ((nolock_regb_read(priv, reg) & mask) != val) {
3ec9c11d
CL		 411 if (time_after(jiffies, timeout)) {
412 if (netif_msg_drv(priv))
7dac6f8d
DB		 413 dev_dbg(&priv->spi->dev,
414 "reg %02x ready timeout!\n", reg);
415 return -ETIMEDOUT;
3ec9c11d
CL		 416 }
417 cpu_relax();
418 }
7dac6f8d
DB		 419 return 0;
420}
421
422/*
423 * Wait until the PHY operation is complete.
424 */
425static int wait_phy_ready(struct enc28j60_net *priv)
426{
427 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
3ec9c11d
CL		 428}
429
430/*
431 * PHY register read
432 * PHY registers are not accessed directly, but through the MII
433 */
434static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
435{
436 u16 ret;
437
438 mutex_lock(&priv->lock);
439 /* set the PHY register address */
440 nolock_regb_write(priv, MIREGADR, address);
441 /* start the register read operation */
442 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
443 /* wait until the PHY read completes */
444 wait_phy_ready(priv);
445 /* quit reading */
446 nolock_regb_write(priv, MICMD, 0x00);
447 /* return the data */
448 ret = nolock_regw_read(priv, MIRDL);
449 mutex_unlock(&priv->lock);
450
451 return ret;
452}
453
454static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
455{
456 int ret;
457
458 mutex_lock(&priv->lock);
459 /* set the PHY register address */
460 nolock_regb_write(priv, MIREGADR, address);
461 /* write the PHY data */
462 nolock_regw_write(priv, MIWRL, data);
463 /* wait until the PHY write completes and return */
464 ret = wait_phy_ready(priv);
465 mutex_unlock(&priv->lock);
466
467 return ret;
468}
469
470/*
471 * Program the hardware MAC address from dev->dev_addr.
472 */
473static int enc28j60_set_hw_macaddr(struct net_device *ndev)
474{
475 int ret;
476 struct enc28j60_net *priv = netdev_priv(ndev);
477
478 mutex_lock(&priv->lock);
479 if (!priv->hw_enable) {
e174961c 480 if (netif_msg_drv(priv))
3ec9c11d 481 printk(KERN_INFO DRV_NAME
e174961c
JB		 482 ": %s: Setting MAC address to %pM\n",
483 ndev->name, ndev->dev_addr);
3ec9c11d
CL		 484 /* NOTE: MAC address in ENC28J60 is byte-backward */
485 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
486 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
487 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
488 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
489 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
490 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
491 ret = 0;
492 } else {
493 if (netif_msg_drv(priv))
494 printk(KERN_DEBUG DRV_NAME
495 ": %s() Hardware must be disabled to set "
b39d66a8 496 "Mac address\n", __func__);
3ec9c11d
CL		 497 ret = -EBUSY;
498 }
499 mutex_unlock(&priv->lock);
500 return ret;
501}
502
503/*
504 * Store the new hardware address in dev->dev_addr, and update the MAC.
505 */
506static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
507{
508 struct sockaddr *address = addr;
509
510 if (netif_running(dev))
511 return -EBUSY;
512 if (!is_valid_ether_addr(address->sa_data))
513 return -EADDRNOTAVAIL;
514
515 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
516 return enc28j60_set_hw_macaddr(dev);
517}
518
519/*
520 * Debug routine to dump useful register contents
521 */
522static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
523{
524 mutex_lock(&priv->lock);
525 printk(KERN_DEBUG DRV_NAME " %s\n"
526 "HwRevID: 0x%02x\n"
527 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
528 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
529 "MAC : MACON1 MACON3 MACON4\n"
530 " 0x%02x 0x%02x 0x%02x\n"
531 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
532 " 0x%04x 0x%04x 0x%04x 0x%04x "
533 "0x%02x 0x%02x 0x%04x\n"
534 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
535 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
536 msg, nolock_regb_read(priv, EREVID),
537 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
538 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
539 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
540 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
541 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
542 nolock_regw_read(priv, ERXWRPTL),
543 nolock_regw_read(priv, ERXRDPTL),
544 nolock_regb_read(priv, ERXFCON),
545 nolock_regb_read(priv, EPKTCNT),
546 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
547 nolock_regw_read(priv, ETXNDL),
548 nolock_regb_read(priv, MACLCON1),
549 nolock_regb_read(priv, MACLCON2),
550 nolock_regb_read(priv, MAPHSUP));
551 mutex_unlock(&priv->lock);
552}
553
554/*
555 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
556 */
557static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
558{
559 u16 erxrdpt;
560
561 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
562 erxrdpt = end;
563 else
564 erxrdpt = next_packet_ptr - 1;
565
566 return erxrdpt;
567}
568
5176da7e
BS		 569/*
570 * Calculate wrap around when reading beyond the end of the RX buffer
571 */
572static u16 rx_packet_start(u16 ptr)
573{
574 if (ptr + RSV_SIZE > RXEND_INIT)
575 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
576 else
577 return ptr + RSV_SIZE;
578}
579
3ec9c11d
CL		 580static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
581{
582 u16 erxrdpt;
583
584 if (start > 0x1FFF || end > 0x1FFF || start > end) {
585 if (netif_msg_drv(priv))
586 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
b39d66a8 587 "bad parameters!\n", __func__, start, end);
3ec9c11d
CL		 588 return;
589 }
590 /* set receive buffer start + end */
591 priv->next_pk_ptr = start;
592 nolock_regw_write(priv, ERXSTL, start);
593 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
594 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
595 nolock_regw_write(priv, ERXNDL, end);
596}
597
598static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
599{
600 if (start > 0x1FFF || end > 0x1FFF || start > end) {
601 if (netif_msg_drv(priv))
602 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
b39d66a8 603 "bad parameters!\n", __func__, start, end);
3ec9c11d
CL		 604 return;
605 }
606 /* set transmit buffer start + end */
607 nolock_regw_write(priv, ETXSTL, start);
608 nolock_regw_write(priv, ETXNDL, end);
609}
610
7dac6f8d
DB		 611/*
612 * Low power mode shrinks power consumption about 100x, so we'd like
613 * the chip to be in that mode whenever it's inactive. (However, we
614 * can't stay in lowpower mode during suspend with WOL active.)
615 */
616static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
617{
618 if (netif_msg_drv(priv))
619 dev_dbg(&priv->spi->dev, "%s power...\n",
620 is_low ? "low" : "high");
621
622 mutex_lock(&priv->lock);
623 if (is_low) {
624 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
625 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
626 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
627 /* ECON2_VRPS was set during initialization */
628 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
629 } else {
630 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
631 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
632 /* caller sets ECON1_RXEN */
633 }
634 mutex_unlock(&priv->lock);
635}
636
3ec9c11d
CL		 637static int enc28j60_hw_init(struct enc28j60_net *priv)
638{
639 u8 reg;
640
641 if (netif_msg_drv(priv))
b39d66a8 642 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
3ec9c11d
CL		 643 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
644
645 mutex_lock(&priv->lock);
646 /* first reset the chip */
647 enc28j60_soft_reset(priv);
648 /* Clear ECON1 */
649 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
650 priv->bank = 0;
651 priv->hw_enable = false;
652 priv->tx_retry_count = 0;
653 priv->max_pk_counter = 0;
654 priv->rxfilter = RXFILTER_NORMAL;
7dac6f8d
DB		 655 /* enable address auto increment and voltage regulator powersave */
656 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
3ec9c11d
CL		 657
658 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
659 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
660 mutex_unlock(&priv->lock);
661
662 /*
663 * Check the RevID.
664 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
665 * damaged
666 */
667 reg = locked_regb_read(priv, EREVID);
668 if (netif_msg_drv(priv))
669 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
670 if (reg == 0x00 || reg == 0xff) {
671 if (netif_msg_drv(priv))
672 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
b39d66a8 673 __func__, reg);
3ec9c11d
CL		 674 return 0;
675 }
676
677 /* default filter mode: (unicast OR broadcast) AND crc valid */
678 locked_regb_write(priv, ERXFCON,
679 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
680
681 /* enable MAC receive */
682 locked_regb_write(priv, MACON1,
683 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
684 /* enable automatic padding and CRC operations */
685 if (priv->full_duplex) {
686 locked_regb_write(priv, MACON3,
687 MACON3_PADCFG0 | MACON3_TXCRCEN |
688 MACON3_FRMLNEN | MACON3_FULDPX);
689 /* set inter-frame gap (non-back-to-back) */
690 locked_regb_write(priv, MAIPGL, 0x12);
691 /* set inter-frame gap (back-to-back) */
692 locked_regb_write(priv, MABBIPG, 0x15);
693 } else {
694 locked_regb_write(priv, MACON3,
695 MACON3_PADCFG0 | MACON3_TXCRCEN |
696 MACON3_FRMLNEN);
697 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
698 /* set inter-frame gap (non-back-to-back) */
699 locked_regw_write(priv, MAIPGL, 0x0C12);
700 /* set inter-frame gap (back-to-back) */
701 locked_regb_write(priv, MABBIPG, 0x12);
702 }
703 /*
704 * MACLCON1 (default)
705 * MACLCON2 (default)
706 * Set the maximum packet size which the controller will accept
707 */
708 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
709
710 /* Configure LEDs */
711 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
712 return 0;
713
714 if (priv->full_duplex) {
715 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
716 return 0;
717 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
718 return 0;
719 } else {
720 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
721 return 0;
722 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
723 return 0;
724 }
725 if (netif_msg_hw(priv))
726 enc28j60_dump_regs(priv, "Hw initialized.");
727
728 return 1;
729}
730
731static void enc28j60_hw_enable(struct enc28j60_net *priv)
732{
7dac6f8d 733 /* enable interrupts */
3ec9c11d
CL		 734 if (netif_msg_hw(priv))
735 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
b39d66a8 736 __func__);
3ec9c11d
CL		 737
738 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
739
740 mutex_lock(&priv->lock);
741 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
742 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
743 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
744 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
745
746 /* enable receive logic */
747 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
748 priv->hw_enable = true;
749 mutex_unlock(&priv->lock);
750}
751
752static void enc28j60_hw_disable(struct enc28j60_net *priv)
753{
754 mutex_lock(&priv->lock);
755 /* disable interrutps and packet reception */
756 nolock_regb_write(priv, EIE, 0x00);
757 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
758 priv->hw_enable = false;
759 mutex_unlock(&priv->lock);
760}
761
762static int
763enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
764{
765 struct enc28j60_net *priv = netdev_priv(ndev);
766 int ret = 0;
767
768 if (!priv->hw_enable) {
7dac6f8d
DB		 769 /* link is in low power mode now; duplex setting
770 * will take effect on next enc28j60_hw_init().
771 */
772 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
3ec9c11d 773 priv->full_duplex = (duplex == DUPLEX_FULL);
7dac6f8d 774 else {
3ec9c11d
CL		 775 if (netif_msg_link(priv))
776 dev_warn(&ndev->dev,
777 "unsupported link setting\n");
778 ret = -EOPNOTSUPP;
779 }
780 } else {
781 if (netif_msg_link(priv))
782 dev_warn(&ndev->dev, "Warning: hw must be disabled "
783 "to set link mode\n");
784 ret = -EBUSY;
785 }
786 return ret;
787}
788
789/*
790 * Read the Transmit Status Vector
791 */
792static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
793{
794 int endptr;
795
796 endptr = locked_regw_read(priv, ETXNDL);
797 if (netif_msg_hw(priv))
798 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
799 endptr + 1);
800 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
801}
802
803static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
804 u8 tsv[TSV_SIZE])
805{
806 u16 tmp1, tmp2;
807
808 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
809 tmp1 = tsv[1];
810 tmp1 <<= 8;
811 tmp1 |= tsv[0];
812
813 tmp2 = tsv[5];
814 tmp2 <<= 8;
815 tmp2 |= tsv[4];
816
817 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
818 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
819 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
820 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
821 TSV_GETBIT(tsv, TSV_TXCRCERROR),
822 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
823 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
824 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
825 "PacketDefer: %d, ExDefer: %d\n",
826 TSV_GETBIT(tsv, TSV_TXMULTICAST),
827 TSV_GETBIT(tsv, TSV_TXBROADCAST),
828 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
829 TSV_GETBIT(tsv, TSV_TXEXDEFER));
830 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
831 "Giant: %d, Underrun: %d\n",
832 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
833 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
834 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
835 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
836 "BackPressApp: %d, VLanTagFrame: %d\n",
837 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
838 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
839 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
840 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
841}
842
843/*
844 * Receive Status vector
845 */
846static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
847 u16 pk_ptr, int len, u16 sts)
848{
849 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
850 msg, pk_ptr);
851 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
852 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
853 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
854 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
855 RSV_GETBIT(sts, RSV_CRCERROR),
856 RSV_GETBIT(sts, RSV_LENCHECKERR),
857 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
858 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
859 "LongDropEvent: %d, CarrierEvent: %d\n",
860 RSV_GETBIT(sts, RSV_RXMULTICAST),
861 RSV_GETBIT(sts, RSV_RXBROADCAST),
862 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
863 RSV_GETBIT(sts, RSV_CARRIEREV));
864 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
865 " UnknownOp: %d, VLanTagFrame: %d\n",
866 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
867 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
868 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
869 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
870}
871
872static void dump_packet(const char *msg, int len, const char *data)
873{
874 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
875 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
876 data, len, true);
877}
878
879/*
880 * Hardware receive function.
881 * Read the buffer memory, update the FIFO pointer to free the buffer,
882 * check the status vector and decrement the packet counter.
883 */
884static void enc28j60_hw_rx(struct net_device *ndev)
885{
886 struct enc28j60_net *priv = netdev_priv(ndev);
887 struct sk_buff *skb = NULL;
888 u16 erxrdpt, next_packet, rxstat;
889 u8 rsv[RSV_SIZE];
890 int len;
891
892 if (netif_msg_rx_status(priv))
893 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
894 priv->next_pk_ptr);
895
896 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
897 if (netif_msg_rx_err(priv))
898 dev_err(&ndev->dev,
899 "%s() Invalid packet address!! 0x%04x\n",
b39d66a8 900 __func__, priv->next_pk_ptr);
3ec9c11d
CL		 901 /* packet address corrupted: reset RX logic */
902 mutex_lock(&priv->lock);
903 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
904 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
905 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
906 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
907 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
908 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
909 mutex_unlock(&priv->lock);
910 ndev->stats.rx_errors++;
911 return;
912 }
913 /* Read next packet pointer and rx status vector */
914 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
915
916 next_packet = rsv[1];
917 next_packet <<= 8;
918 next_packet |= rsv[0];
919
920 len = rsv[3];
921 len <<= 8;
922 len |= rsv[2];
923
924 rxstat = rsv[5];
925 rxstat <<= 8;
926 rxstat |= rsv[4];
927
928 if (netif_msg_rx_status(priv))
b39d66a8 929 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
3ec9c11d
CL		 930
931 if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
932 if (netif_msg_rx_err(priv))
933 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
934 ndev->stats.rx_errors++;
935 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
936 ndev->stats.rx_crc_errors++;
937 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
938 ndev->stats.rx_frame_errors++;
939 } else {
02ff05c4 940 skb = dev_alloc_skb(len + NET_IP_ALIGN);
3ec9c11d
CL		 941 if (!skb) {
942 if (netif_msg_rx_err(priv))
943 dev_err(&ndev->dev,
944 "out of memory for Rx'd frame\n");
945 ndev->stats.rx_dropped++;
946 } else {
947 skb->dev = ndev;
02ff05c4 948 skb_reserve(skb, NET_IP_ALIGN);
3ec9c11d 949 /* copy the packet from the receive buffer */
5176da7e
BS		 950 enc28j60_mem_read(priv,
951 rx_packet_start(priv->next_pk_ptr),
952 len, skb_put(skb, len));
3ec9c11d 953 if (netif_msg_pktdata(priv))
b39d66a8 954 dump_packet(__func__, skb->len, skb->data);
3ec9c11d
CL		 955 skb->protocol = eth_type_trans(skb, ndev);
956 /* update statistics */
957 ndev->stats.rx_packets++;
958 ndev->stats.rx_bytes += len;
2c413a64 959 netif_rx_ni(skb);
3ec9c11d
CL		 960 }
961 }
962 /*
963 * Move the RX read pointer to the start of the next
964 * received packet.
965 * This frees the memory we just read out
966 */
967 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
968 if (netif_msg_hw(priv))
969 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
b39d66a8 970 __func__, erxrdpt);
3ec9c11d
CL		 971
972 mutex_lock(&priv->lock);
973 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
974#ifdef CONFIG_ENC28J60_WRITEVERIFY
975 if (netif_msg_drv(priv)) {
976 u16 reg;
977 reg = nolock_regw_read(priv, ERXRDPTL);
978 if (reg != erxrdpt)
979 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
b39d66a8 980 "error (0x%04x - 0x%04x)\n", __func__,
3ec9c11d
CL		 981 reg, erxrdpt);
982 }
983#endif
984 priv->next_pk_ptr = next_packet;
985 /* we are done with this packet, decrement the packet counter */
986 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
987 mutex_unlock(&priv->lock);
988}
989
990/*
991 * Calculate free space in RxFIFO
992 */
993static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
994{
995 int epkcnt, erxst, erxnd, erxwr, erxrd;
996 int free_space;
997
998 mutex_lock(&priv->lock);
999 epkcnt = nolock_regb_read(priv, EPKTCNT);
1000 if (epkcnt >= 255)
1001 free_space = -1;
1002 else {
1003 erxst = nolock_regw_read(priv, ERXSTL);
1004 erxnd = nolock_regw_read(priv, ERXNDL);
1005 erxwr = nolock_regw_read(priv, ERXWRPTL);
1006 erxrd = nolock_regw_read(priv, ERXRDPTL);
1007
1008 if (erxwr > erxrd)
1009 free_space = (erxnd - erxst) - (erxwr - erxrd);
1010 else if (erxwr == erxrd)
1011 free_space = (erxnd - erxst);
1012 else
1013 free_space = erxrd - erxwr - 1;
1014 }
1015 mutex_unlock(&priv->lock);
1016 if (netif_msg_rx_status(priv))
1017 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
b39d66a8 1018 __func__, free_space);
3ec9c11d
CL		 1019 return free_space;
1020}
1021
1022/*
1023 * Access the PHY to determine link status
1024 */
1025static void enc28j60_check_link_status(struct net_device *ndev)
1026{
1027 struct enc28j60_net *priv = netdev_priv(ndev);
1028 u16 reg;
1029 int duplex;
1030
1031 reg = enc28j60_phy_read(priv, PHSTAT2);
1032 if (netif_msg_hw(priv))
1033 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
b39d66a8 1034 "PHSTAT2: %04x\n", __func__,
3ec9c11d
CL		 1035 enc28j60_phy_read(priv, PHSTAT1), reg);
1036 duplex = reg & PHSTAT2_DPXSTAT;
1037
1038 if (reg & PHSTAT2_LSTAT) {
1039 netif_carrier_on(ndev);
1040 if (netif_msg_ifup(priv))
1041 dev_info(&ndev->dev, "link up - %s\n",
1042 duplex ? "Full duplex" : "Half duplex");
1043 } else {
1044 if (netif_msg_ifdown(priv))
1045 dev_info(&ndev->dev, "link down\n");
1046 netif_carrier_off(ndev);
1047 }
1048}
1049
1050static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1051{
1052 struct enc28j60_net *priv = netdev_priv(ndev);
1053
1054 if (err)
1055 ndev->stats.tx_errors++;
1056 else
1057 ndev->stats.tx_packets++;
1058
1059 if (priv->tx_skb) {
1060 if (!err)
1061 ndev->stats.tx_bytes += priv->tx_skb->len;
1062 dev_kfree_skb(priv->tx_skb);
1063 priv->tx_skb = NULL;
1064 }
1065 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1066 netif_wake_queue(ndev);
1067}
1068
1069/*
1070 * RX handler
1071 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1072 * check EPKTCNT is the suggested workaround.
1073 * We don't need to clear interrupt flag, automatically done when
1074 * enc28j60_hw_rx() decrements the packet counter.
1075 * Returns how many packet processed.
1076 */
1077static int enc28j60_rx_interrupt(struct net_device *ndev)
1078{
1079 struct enc28j60_net *priv = netdev_priv(ndev);
1080 int pk_counter, ret;
1081
1082 pk_counter = locked_regb_read(priv, EPKTCNT);
1083 if (pk_counter && netif_msg_intr(priv))
1084 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1085 if (pk_counter > priv->max_pk_counter) {
1086 /* update statistics */
1087 priv->max_pk_counter = pk_counter;
1088 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1089 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1090 priv->max_pk_counter);
1091 }
1092 ret = pk_counter;
1093 while (pk_counter-- > 0)
1094 enc28j60_hw_rx(ndev);
1095
1096 return ret;
1097}
1098
1099static void enc28j60_irq_work_handler(struct work_struct *work)
1100{
1101 struct enc28j60_net *priv =
1102 container_of(work, struct enc28j60_net, irq_work);
1103 struct net_device *ndev = priv->netdev;
1104 int intflags, loop;
1105
1106 if (netif_msg_intr(priv))
b39d66a8 1107 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1108 /* disable further interrupts */
1109 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1110
1111 do {
1112 loop = 0;
1113 intflags = locked_regb_read(priv, EIR);
1114 /* DMA interrupt handler (not currently used) */
1115 if ((intflags & EIR_DMAIF) != 0) {
1116 loop++;
1117 if (netif_msg_intr(priv))
1118 printk(KERN_DEBUG DRV_NAME
1119 ": intDMA(%d)\n", loop);
1120 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1121 }
1122 /* LINK changed handler */
1123 if ((intflags & EIR_LINKIF) != 0) {
1124 loop++;
1125 if (netif_msg_intr(priv))
1126 printk(KERN_DEBUG DRV_NAME
1127 ": intLINK(%d)\n", loop);
1128 enc28j60_check_link_status(ndev);
1129 /* read PHIR to clear the flag */
1130 enc28j60_phy_read(priv, PHIR);
1131 }
1132 /* TX complete handler */
1133 if ((intflags & EIR_TXIF) != 0) {
1134 bool err = false;
1135 loop++;
1136 if (netif_msg_intr(priv))
1137 printk(KERN_DEBUG DRV_NAME
1138 ": intTX(%d)\n", loop);
1139 priv->tx_retry_count = 0;
1140 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1141 if (netif_msg_tx_err(priv))
1142 dev_err(&ndev->dev,
1143 "Tx Error (aborted)\n");
1144 err = true;
1145 }
1146 if (netif_msg_tx_done(priv)) {
1147 u8 tsv[TSV_SIZE];
1148 enc28j60_read_tsv(priv, tsv);
1149 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1150 }
1151 enc28j60_tx_clear(ndev, err);
1152 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1153 }
1154 /* TX Error handler */
1155 if ((intflags & EIR_TXERIF) != 0) {
1156 u8 tsv[TSV_SIZE];
1157
1158 loop++;
1159 if (netif_msg_intr(priv))
1160 printk(KERN_DEBUG DRV_NAME
1161 ": intTXErr(%d)\n", loop);
1162 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1163 enc28j60_read_tsv(priv, tsv);
1164 if (netif_msg_tx_err(priv))
1165 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1166 /* Reset TX logic */
1167 mutex_lock(&priv->lock);
1168 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1169 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1170 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1171 mutex_unlock(&priv->lock);
1172 /* Transmit Late collision check for retransmit */
1173 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1174 if (netif_msg_tx_err(priv))
1175 printk(KERN_DEBUG DRV_NAME
1176 ": LateCollision TXErr (%d)\n",
1177 priv->tx_retry_count);
1178 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1179 locked_reg_bfset(priv, ECON1,
1180 ECON1_TXRTS);
1181 else
1182 enc28j60_tx_clear(ndev, true);
1183 } else
1184 enc28j60_tx_clear(ndev, true);
1185 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1186 }
1187 /* RX Error handler */
1188 if ((intflags & EIR_RXERIF) != 0) {
1189 loop++;
1190 if (netif_msg_intr(priv))
1191 printk(KERN_DEBUG DRV_NAME
1192 ": intRXErr(%d)\n", loop);
1193 /* Check free FIFO space to flag RX overrun */
1194 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1195 if (netif_msg_rx_err(priv))
1196 printk(KERN_DEBUG DRV_NAME
1197 ": RX Overrun\n");
1198 ndev->stats.rx_dropped++;
1199 }
1200 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1201 }
1202 /* RX handler */
1203 if (enc28j60_rx_interrupt(ndev))
1204 loop++;
1205 } while (loop);
1206
1207 /* re-enable interrupts */
1208 locked_reg_bfset(priv, EIE, EIE_INTIE);
1209 if (netif_msg_intr(priv))
b39d66a8 1210 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
3ec9c11d
CL		 1211}
1212
1213/*
1214 * Hardware transmit function.
1215 * Fill the buffer memory and send the contents of the transmit buffer
1216 * onto the network
1217 */
1218static void enc28j60_hw_tx(struct enc28j60_net *priv)
1219{
1220 if (netif_msg_tx_queued(priv))
1221 printk(KERN_DEBUG DRV_NAME
1222 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1223
1224 if (netif_msg_pktdata(priv))
b39d66a8 1225 dump_packet(__func__,
3ec9c11d
CL		 1226 priv->tx_skb->len, priv->tx_skb->data);
1227 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1228
1229#ifdef CONFIG_ENC28J60_WRITEVERIFY
1230 /* readback and verify written data */
1231 if (netif_msg_drv(priv)) {
1232 int test_len, k;
1233 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1234 int okflag;
1235
1236 test_len = priv->tx_skb->len;
1237 if (test_len > sizeof(test_buf))
1238 test_len = sizeof(test_buf);
1239
1240 /* + 1 to skip control byte */
1241 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1242 okflag = 1;
1243 for (k = 0; k < test_len; k++) {
1244 if (priv->tx_skb->data[k] != test_buf[k]) {
1245 printk(KERN_DEBUG DRV_NAME
1246 ": Error, %d location differ: "
1247 "0x%02x-0x%02x\n", k,
1248 priv->tx_skb->data[k], test_buf[k]);
1249 okflag = 0;
1250 }
1251 }
1252 if (!okflag)
1253 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1254 "verify ERROR!\n");
1255 }
1256#endif
1257 /* set TX request flag */
1258 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1259}
1260
1261static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1262{
1263 struct enc28j60_net *priv = netdev_priv(dev);
1264
1265 if (netif_msg_tx_queued(priv))
b39d66a8 1266 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1267
1268 /* If some error occurs while trying to transmit this
1269 * packet, you should return '1' from this function.
1270 * In such a case you _may not_ do anything to the
1271 * SKB, it is still owned by the network queueing
1272 * layer when an error is returned. This means you
1273 * may not modify any SKB fields, you may not free
1274 * the SKB, etc.
1275 */
1276 netif_stop_queue(dev);
1277
1278 /* save the timestamp */
1279 priv->netdev->trans_start = jiffies;
1280 /* Remember the skb for deferred processing */
1281 priv->tx_skb = skb;
1282 schedule_work(&priv->tx_work);
1283
1284 return 0;
1285}
1286
1287static void enc28j60_tx_work_handler(struct work_struct *work)
1288{
1289 struct enc28j60_net *priv =
1290 container_of(work, struct enc28j60_net, tx_work);
1291
1292 /* actual delivery of data */
1293 enc28j60_hw_tx(priv);
1294}
1295
1296static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1297{
1298 struct enc28j60_net *priv = dev_id;
1299
1300 /*
1301 * Can't do anything in interrupt context because we need to
1302 * block (spi_sync() is blocking) so fire of the interrupt
1303 * handling workqueue.
1304 * Remember that we access enc28j60 registers through SPI bus
1305 * via spi_sync() call.
1306 */
1307 schedule_work(&priv->irq_work);
1308
1309 return IRQ_HANDLED;
1310}
1311
1312static void enc28j60_tx_timeout(struct net_device *ndev)
1313{
1314 struct enc28j60_net *priv = netdev_priv(ndev);
1315
1316 if (netif_msg_timer(priv))
1317 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1318
1319 ndev->stats.tx_errors++;
1320 /* can't restart safely under softirq */
1321 schedule_work(&priv->restart_work);
1322}
1323
1324/*
1325 * Open/initialize the board. This is called (in the current kernel)
1326 * sometime after booting when the 'ifconfig' program is run.
1327 *
1328 * This routine should set everything up anew at each open, even
1329 * registers that "should" only need to be set once at boot, so that
1330 * there is non-reboot way to recover if something goes wrong.
1331 */
1332static int enc28j60_net_open(struct net_device *dev)
1333{
1334 struct enc28j60_net *priv = netdev_priv(dev);
1335
1336 if (netif_msg_drv(priv))
b39d66a8 1337 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1338
1339 if (!is_valid_ether_addr(dev->dev_addr)) {
e174961c
JB		 1340 if (netif_msg_ifup(priv))
1341 dev_err(&dev->dev, "invalid MAC address %pM\n",
1342 dev->dev_addr);
3ec9c11d
CL		 1343 return -EADDRNOTAVAIL;
1344 }
7dac6f8d
DB		 1345 /* Reset the hardware here (and take it out of low power mode) */
1346 enc28j60_lowpower(priv, false);
3ec9c11d
CL		 1347 enc28j60_hw_disable(priv);
1348 if (!enc28j60_hw_init(priv)) {
1349 if (netif_msg_ifup(priv))
1350 dev_err(&dev->dev, "hw_reset() failed\n");
1351 return -EINVAL;
1352 }
1353 /* Update the MAC address (in case user has changed it) */
1354 enc28j60_set_hw_macaddr(dev);
1355 /* Enable interrupts */
1356 enc28j60_hw_enable(priv);
1357 /* check link status */
1358 enc28j60_check_link_status(dev);
1359 /* We are now ready to accept transmit requests from
1360 * the queueing layer of the networking.
1361 */
1362 netif_start_queue(dev);
1363
1364 return 0;
1365}
1366
1367/* The inverse routine to net_open(). */
1368static int enc28j60_net_close(struct net_device *dev)
1369{
1370 struct enc28j60_net *priv = netdev_priv(dev);
1371
1372 if (netif_msg_drv(priv))
b39d66a8 1373 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
3ec9c11d
CL		 1374
1375 enc28j60_hw_disable(priv);
7dac6f8d 1376 enc28j60_lowpower(priv, true);
3ec9c11d
CL		 1377 netif_stop_queue(dev);
1378
1379 return 0;
1380}
1381
1382/*
1383 * Set or clear the multicast filter for this adapter
1384 * num_addrs == -1 Promiscuous mode, receive all packets
1385 * num_addrs == 0 Normal mode, filter out multicast packets
1386 * num_addrs > 0 Multicast mode, receive normal and MC packets
1387 */
1388static void enc28j60_set_multicast_list(struct net_device *dev)
1389{
1390 struct enc28j60_net *priv = netdev_priv(dev);
1391 int oldfilter = priv->rxfilter;
1392
1393 if (dev->flags & IFF_PROMISC) {
1394 if (netif_msg_link(priv))
1395 dev_info(&dev->dev, "promiscuous mode\n");
1396 priv->rxfilter = RXFILTER_PROMISC;
1397 } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1398 if (netif_msg_link(priv))
1399 dev_info(&dev->dev, "%smulticast mode\n",
1400 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1401 priv->rxfilter = RXFILTER_MULTI;
1402 } else {
1403 if (netif_msg_link(priv))
1404 dev_info(&dev->dev, "normal mode\n");
1405 priv->rxfilter = RXFILTER_NORMAL;
1406 }
1407
1408 if (oldfilter != priv->rxfilter)
1409 schedule_work(&priv->setrx_work);
1410}
1411
1412static void enc28j60_setrx_work_handler(struct work_struct *work)
1413{
1414 struct enc28j60_net *priv =
1415 container_of(work, struct enc28j60_net, setrx_work);
1416
1417 if (priv->rxfilter == RXFILTER_PROMISC) {
1418 if (netif_msg_drv(priv))
1419 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1420 locked_regb_write(priv, ERXFCON, 0x00);
1421 } else if (priv->rxfilter == RXFILTER_MULTI) {
1422 if (netif_msg_drv(priv))
1423 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1424 locked_regb_write(priv, ERXFCON,
1425 ERXFCON_UCEN | ERXFCON_CRCEN |
1426 ERXFCON_BCEN | ERXFCON_MCEN);
1427 } else {
1428 if (netif_msg_drv(priv))
1429 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1430 locked_regb_write(priv, ERXFCON,
1431 ERXFCON_UCEN | ERXFCON_CRCEN |
1432 ERXFCON_BCEN);
1433 }
1434}
1435
1436static void enc28j60_restart_work_handler(struct work_struct *work)
1437{
1438 struct enc28j60_net *priv =
1439 container_of(work, struct enc28j60_net, restart_work);
1440 struct net_device *ndev = priv->netdev;
1441 int ret;
1442
1443 rtnl_lock();
1444 if (netif_running(ndev)) {
1445 enc28j60_net_close(ndev);
1446 ret = enc28j60_net_open(ndev);
1447 if (unlikely(ret)) {
1448 dev_info(&ndev->dev, " could not restart %d\n", ret);
1449 dev_close(ndev);
1450 }
1451 }
1452 rtnl_unlock();
1453}
1454
1455/* ......................... ETHTOOL SUPPORT ........................... */
1456
1457static void
1458enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1459{
1460 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1461 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1462 strlcpy(info->bus_info,
fb28ad35 1463 dev_name(dev->dev.parent), sizeof(info->bus_info));
3ec9c11d
CL		 1464}
1465
1466static int
1467enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1468{
1469 struct enc28j60_net *priv = netdev_priv(dev);
1470
1471 cmd->transceiver = XCVR_INTERNAL;
1472 cmd->supported = SUPPORTED_10baseT_Half
1473 | SUPPORTED_10baseT_Full
1474 | SUPPORTED_TP;
1475 cmd->speed = SPEED_10;
1476 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1477 cmd->port = PORT_TP;
1478 cmd->autoneg = AUTONEG_DISABLE;
1479
1480 return 0;
1481}
1482
1483static int
1484enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1485{
1486 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1487}
1488
1489static u32 enc28j60_get_msglevel(struct net_device *dev)
1490{
1491 struct enc28j60_net *priv = netdev_priv(dev);
1492 return priv->msg_enable;
1493}
1494
1495static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1496{
1497 struct enc28j60_net *priv = netdev_priv(dev);
1498 priv->msg_enable = val;
1499}
1500
1501static const struct ethtool_ops enc28j60_ethtool_ops = {
1502 .get_settings = enc28j60_get_settings,
1503 .set_settings = enc28j60_set_settings,
1504 .get_drvinfo = enc28j60_get_drvinfo,
1505 .get_msglevel = enc28j60_get_msglevel,
1506 .set_msglevel = enc28j60_set_msglevel,
1507};
1508
1509static int enc28j60_chipset_init(struct net_device *dev)
1510{
1511 struct enc28j60_net *priv = netdev_priv(dev);
1512
1513 return enc28j60_hw_init(priv);
1514}
1515
1516static int __devinit enc28j60_probe(struct spi_device *spi)
1517{
1518 struct net_device *dev;
1519 struct enc28j60_net *priv;
1520 int ret = 0;
1521
1522 if (netif_msg_drv(&debug))
1523 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1524 DRV_VERSION);
1525
1526 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1527 if (!dev) {
1528 if (netif_msg_drv(&debug))
1529 dev_err(&spi->dev, DRV_NAME
1530 ": unable to alloc new ethernet\n");
1531 ret = -ENOMEM;
1532 goto error_alloc;
1533 }
1534 priv = netdev_priv(dev);
1535
1536 priv->netdev = dev; /* priv to netdev reference */
1537 priv->spi = spi; /* priv to spi reference */
1538 priv->msg_enable = netif_msg_init(debug.msg_enable,
1539 ENC28J60_MSG_DEFAULT);
1540 mutex_init(&priv->lock);
1541 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1542 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1543 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1544 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1545 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1546 SET_NETDEV_DEV(dev, &spi->dev);
1547
1548 if (!enc28j60_chipset_init(dev)) {
1549 if (netif_msg_probe(priv))
1550 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1551 ret = -EIO;
1552 goto error_irq;
1553 }
1554 random_ether_addr(dev->dev_addr);
1555 enc28j60_set_hw_macaddr(dev);
1556
c7b7b042
DB		 1557 /* Board setup must set the relevant edge trigger type;
1558 * level triggers won't currently work.
1559 */
1560 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
3ec9c11d
CL		 1561 if (ret < 0) {
1562 if (netif_msg_probe(priv))
1563 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1564 "(ret = %d)\n", spi->irq, ret);
1565 goto error_irq;
1566 }
1567
1568 dev->if_port = IF_PORT_10BASET;
1569 dev->irq = spi->irq;
1570 dev->open = enc28j60_net_open;
1571 dev->stop = enc28j60_net_close;
1572 dev->hard_start_xmit = enc28j60_send_packet;
1573 dev->set_multicast_list = &enc28j60_set_multicast_list;
1574 dev->set_mac_address = enc28j60_set_mac_address;
1575 dev->tx_timeout = &enc28j60_tx_timeout;
1576 dev->watchdog_timeo = TX_TIMEOUT;
1577 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1578
7dac6f8d
DB		 1579 enc28j60_lowpower(priv, true);
1580
3ec9c11d
CL		 1581 ret = register_netdev(dev);
1582 if (ret) {
1583 if (netif_msg_probe(priv))
1584 dev_err(&spi->dev, "register netdev " DRV_NAME
1585 " failed (ret = %d)\n", ret);
1586 goto error_register;
1587 }
1588 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1589
1590 return 0;
1591
1592error_register:
1593 free_irq(spi->irq, priv);
1594error_irq:
1595 free_netdev(dev);
1596error_alloc:
1597 return ret;
1598}
1599
6fd65882 1600static int __devexit enc28j60_remove(struct spi_device *spi)
3ec9c11d
CL		 1601{
1602 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1603
1604 if (netif_msg_drv(priv))
1605 printk(KERN_DEBUG DRV_NAME ": remove\n");
1606
1607 unregister_netdev(priv->netdev);
1608 free_irq(spi->irq, priv);
1609 free_netdev(priv->netdev);
1610
1611 return 0;
1612}
1613
1614static struct spi_driver enc28j60_driver = {
1615 .driver = {
1616 .name = DRV_NAME,
3ec9c11d 1617 .owner = THIS_MODULE,
6fd65882 1618 },
3ec9c11d
CL		 1619 .probe = enc28j60_probe,
1620 .remove = __devexit_p(enc28j60_remove),
1621};
1622
1623static int __init enc28j60_init(void)
1624{
7dac6f8d
DB		 1625 msec20_to_jiffies = msecs_to_jiffies(20);
1626
3ec9c11d
CL		 1627 return spi_register_driver(&enc28j60_driver);
1628}
1629
1630module_init(enc28j60_init);
1631
1632static void __exit enc28j60_exit(void)
1633{
1634 spi_unregister_driver(&enc28j60_driver);
1635}
1636
1637module_exit(enc28j60_exit);
1638
1639MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1640MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1641MODULE_LICENSE("GPL");
1642module_param_named(debug, debug.msg_enable, int, 0);
1643MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
Linux kernel - Deliverables
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