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1 | #ifndef BCM63XX_ENET_H_ |
2 | #define BCM63XX_ENET_H_ | |
3 | ||
4 | #include <linux/types.h> | |
5 | #include <linux/mii.h> | |
6 | #include <linux/mutex.h> | |
7 | #include <linux/phy.h> | |
8 | #include <linux/platform_device.h> | |
9 | ||
10 | #include <bcm63xx_regs.h> | |
11 | #include <bcm63xx_irq.h> | |
12 | #include <bcm63xx_io.h> | |
932e30b6 | 13 | #include <bcm63xx_iudma.h> |
9b1fc55a MB |
14 | |
15 | /* default number of descriptor */ | |
16 | #define BCMENET_DEF_RX_DESC 64 | |
17 | #define BCMENET_DEF_TX_DESC 32 | |
18 | ||
19 | /* maximum burst len for dma (4 bytes unit) */ | |
20 | #define BCMENET_DMA_MAXBURST 16 | |
6f00a022 | 21 | #define BCMENETSW_DMA_MAXBURST 8 |
9b1fc55a MB |
22 | |
23 | /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value | |
24 | * must be low enough so that a DMA transfer of above burst length can | |
25 | * not overflow the fifo */ | |
26 | #define BCMENET_TX_FIFO_TRESH 32 | |
27 | ||
28 | /* | |
29 | * hardware maximum rx/tx packet size including FCS, max mtu is | |
30 | * actually 2047, but if we set max rx size register to 2047 we won't | |
31 | * get overflow information if packet size is 2048 or above | |
32 | */ | |
33 | #define BCMENET_MAX_MTU 2046 | |
34 | ||
9b1fc55a MB |
35 | /* |
36 | * MIB Counters register definitions | |
37 | */ | |
38 | #define ETH_MIB_TX_GD_OCTETS 0 | |
39 | #define ETH_MIB_TX_GD_PKTS 1 | |
40 | #define ETH_MIB_TX_ALL_OCTETS 2 | |
41 | #define ETH_MIB_TX_ALL_PKTS 3 | |
42 | #define ETH_MIB_TX_BRDCAST 4 | |
43 | #define ETH_MIB_TX_MULT 5 | |
44 | #define ETH_MIB_TX_64 6 | |
45 | #define ETH_MIB_TX_65_127 7 | |
46 | #define ETH_MIB_TX_128_255 8 | |
47 | #define ETH_MIB_TX_256_511 9 | |
48 | #define ETH_MIB_TX_512_1023 10 | |
49 | #define ETH_MIB_TX_1024_MAX 11 | |
50 | #define ETH_MIB_TX_JAB 12 | |
51 | #define ETH_MIB_TX_OVR 13 | |
52 | #define ETH_MIB_TX_FRAG 14 | |
53 | #define ETH_MIB_TX_UNDERRUN 15 | |
54 | #define ETH_MIB_TX_COL 16 | |
55 | #define ETH_MIB_TX_1_COL 17 | |
56 | #define ETH_MIB_TX_M_COL 18 | |
57 | #define ETH_MIB_TX_EX_COL 19 | |
58 | #define ETH_MIB_TX_LATE 20 | |
59 | #define ETH_MIB_TX_DEF 21 | |
60 | #define ETH_MIB_TX_CRS 22 | |
61 | #define ETH_MIB_TX_PAUSE 23 | |
62 | ||
63 | #define ETH_MIB_RX_GD_OCTETS 32 | |
64 | #define ETH_MIB_RX_GD_PKTS 33 | |
65 | #define ETH_MIB_RX_ALL_OCTETS 34 | |
66 | #define ETH_MIB_RX_ALL_PKTS 35 | |
67 | #define ETH_MIB_RX_BRDCAST 36 | |
68 | #define ETH_MIB_RX_MULT 37 | |
69 | #define ETH_MIB_RX_64 38 | |
70 | #define ETH_MIB_RX_65_127 39 | |
71 | #define ETH_MIB_RX_128_255 40 | |
72 | #define ETH_MIB_RX_256_511 41 | |
73 | #define ETH_MIB_RX_512_1023 42 | |
74 | #define ETH_MIB_RX_1024_MAX 43 | |
75 | #define ETH_MIB_RX_JAB 44 | |
76 | #define ETH_MIB_RX_OVR 45 | |
77 | #define ETH_MIB_RX_FRAG 46 | |
78 | #define ETH_MIB_RX_DROP 47 | |
79 | #define ETH_MIB_RX_CRC_ALIGN 48 | |
80 | #define ETH_MIB_RX_UND 49 | |
81 | #define ETH_MIB_RX_CRC 50 | |
82 | #define ETH_MIB_RX_ALIGN 51 | |
83 | #define ETH_MIB_RX_SYM 52 | |
84 | #define ETH_MIB_RX_PAUSE 53 | |
85 | #define ETH_MIB_RX_CNTRL 54 | |
86 | ||
87 | ||
6f00a022 MB |
88 | /* |
89 | * SW MIB Counters register definitions | |
90 | */ | |
91 | #define ETHSW_MIB_TX_ALL_OCT 0 | |
92 | #define ETHSW_MIB_TX_DROP_PKTS 2 | |
93 | #define ETHSW_MIB_TX_QOS_PKTS 3 | |
94 | #define ETHSW_MIB_TX_BRDCAST 4 | |
95 | #define ETHSW_MIB_TX_MULT 5 | |
96 | #define ETHSW_MIB_TX_UNI 6 | |
97 | #define ETHSW_MIB_TX_COL 7 | |
98 | #define ETHSW_MIB_TX_1_COL 8 | |
99 | #define ETHSW_MIB_TX_M_COL 9 | |
100 | #define ETHSW_MIB_TX_DEF 10 | |
101 | #define ETHSW_MIB_TX_LATE 11 | |
102 | #define ETHSW_MIB_TX_EX_COL 12 | |
103 | #define ETHSW_MIB_TX_PAUSE 14 | |
104 | #define ETHSW_MIB_TX_QOS_OCT 15 | |
105 | ||
106 | #define ETHSW_MIB_RX_ALL_OCT 17 | |
107 | #define ETHSW_MIB_RX_UND 19 | |
108 | #define ETHSW_MIB_RX_PAUSE 20 | |
109 | #define ETHSW_MIB_RX_64 21 | |
110 | #define ETHSW_MIB_RX_65_127 22 | |
111 | #define ETHSW_MIB_RX_128_255 23 | |
112 | #define ETHSW_MIB_RX_256_511 24 | |
113 | #define ETHSW_MIB_RX_512_1023 25 | |
114 | #define ETHSW_MIB_RX_1024_1522 26 | |
115 | #define ETHSW_MIB_RX_OVR 27 | |
116 | #define ETHSW_MIB_RX_JAB 28 | |
117 | #define ETHSW_MIB_RX_ALIGN 29 | |
118 | #define ETHSW_MIB_RX_CRC 30 | |
119 | #define ETHSW_MIB_RX_GD_OCT 31 | |
120 | #define ETHSW_MIB_RX_DROP 33 | |
121 | #define ETHSW_MIB_RX_UNI 34 | |
122 | #define ETHSW_MIB_RX_MULT 35 | |
123 | #define ETHSW_MIB_RX_BRDCAST 36 | |
124 | #define ETHSW_MIB_RX_SA_CHANGE 37 | |
125 | #define ETHSW_MIB_RX_FRAG 38 | |
126 | #define ETHSW_MIB_RX_OVR_DISC 39 | |
127 | #define ETHSW_MIB_RX_SYM 40 | |
128 | #define ETHSW_MIB_RX_QOS_PKTS 41 | |
129 | #define ETHSW_MIB_RX_QOS_OCT 42 | |
130 | #define ETHSW_MIB_RX_1523_2047 44 | |
131 | #define ETHSW_MIB_RX_2048_4095 45 | |
132 | #define ETHSW_MIB_RX_4096_8191 46 | |
133 | #define ETHSW_MIB_RX_8192_9728 47 | |
134 | ||
135 | ||
9b1fc55a MB |
136 | struct bcm_enet_mib_counters { |
137 | u64 tx_gd_octets; | |
138 | u32 tx_gd_pkts; | |
139 | u32 tx_all_octets; | |
140 | u32 tx_all_pkts; | |
6f00a022 | 141 | u32 tx_unicast; |
9b1fc55a MB |
142 | u32 tx_brdcast; |
143 | u32 tx_mult; | |
144 | u32 tx_64; | |
145 | u32 tx_65_127; | |
146 | u32 tx_128_255; | |
147 | u32 tx_256_511; | |
148 | u32 tx_512_1023; | |
149 | u32 tx_1024_max; | |
6f00a022 MB |
150 | u32 tx_1523_2047; |
151 | u32 tx_2048_4095; | |
152 | u32 tx_4096_8191; | |
153 | u32 tx_8192_9728; | |
9b1fc55a | 154 | u32 tx_jab; |
6f00a022 | 155 | u32 tx_drop; |
9b1fc55a MB |
156 | u32 tx_ovr; |
157 | u32 tx_frag; | |
158 | u32 tx_underrun; | |
159 | u32 tx_col; | |
160 | u32 tx_1_col; | |
161 | u32 tx_m_col; | |
162 | u32 tx_ex_col; | |
163 | u32 tx_late; | |
164 | u32 tx_def; | |
165 | u32 tx_crs; | |
166 | u32 tx_pause; | |
167 | u64 rx_gd_octets; | |
168 | u32 rx_gd_pkts; | |
169 | u32 rx_all_octets; | |
170 | u32 rx_all_pkts; | |
171 | u32 rx_brdcast; | |
6f00a022 | 172 | u32 rx_unicast; |
9b1fc55a MB |
173 | u32 rx_mult; |
174 | u32 rx_64; | |
175 | u32 rx_65_127; | |
176 | u32 rx_128_255; | |
177 | u32 rx_256_511; | |
178 | u32 rx_512_1023; | |
179 | u32 rx_1024_max; | |
180 | u32 rx_jab; | |
181 | u32 rx_ovr; | |
182 | u32 rx_frag; | |
183 | u32 rx_drop; | |
184 | u32 rx_crc_align; | |
185 | u32 rx_und; | |
186 | u32 rx_crc; | |
187 | u32 rx_align; | |
188 | u32 rx_sym; | |
189 | u32 rx_pause; | |
190 | u32 rx_cntrl; | |
191 | }; | |
192 | ||
193 | ||
194 | struct bcm_enet_priv { | |
195 | ||
196 | /* mac id (from platform device id) */ | |
197 | int mac_id; | |
198 | ||
199 | /* base remapped address of device */ | |
200 | void __iomem *base; | |
201 | ||
202 | /* mac irq, rx_dma irq, tx_dma irq */ | |
203 | int irq; | |
204 | int irq_rx; | |
205 | int irq_tx; | |
206 | ||
207 | /* hw view of rx & tx dma ring */ | |
208 | dma_addr_t rx_desc_dma; | |
209 | dma_addr_t tx_desc_dma; | |
210 | ||
211 | /* allocated size (in bytes) for rx & tx dma ring */ | |
212 | unsigned int rx_desc_alloc_size; | |
213 | unsigned int tx_desc_alloc_size; | |
214 | ||
215 | ||
216 | struct napi_struct napi; | |
217 | ||
218 | /* dma channel id for rx */ | |
219 | int rx_chan; | |
220 | ||
221 | /* number of dma desc in rx ring */ | |
222 | int rx_ring_size; | |
223 | ||
224 | /* cpu view of rx dma ring */ | |
225 | struct bcm_enet_desc *rx_desc_cpu; | |
226 | ||
227 | /* current number of armed descriptor given to hardware for rx */ | |
228 | int rx_desc_count; | |
229 | ||
230 | /* next rx descriptor to fetch from hardware */ | |
231 | int rx_curr_desc; | |
232 | ||
233 | /* next dirty rx descriptor to refill */ | |
234 | int rx_dirty_desc; | |
235 | ||
236 | /* size of allocated rx skbs */ | |
237 | unsigned int rx_skb_size; | |
238 | ||
239 | /* list of skb given to hw for rx */ | |
240 | struct sk_buff **rx_skb; | |
241 | ||
242 | /* used when rx skb allocation failed, so we defer rx queue | |
243 | * refill */ | |
244 | struct timer_list rx_timeout; | |
245 | ||
246 | /* lock rx_timeout against rx normal operation */ | |
247 | spinlock_t rx_lock; | |
248 | ||
249 | ||
250 | /* dma channel id for tx */ | |
251 | int tx_chan; | |
252 | ||
253 | /* number of dma desc in tx ring */ | |
254 | int tx_ring_size; | |
255 | ||
6f00a022 MB |
256 | /* maximum dma burst size */ |
257 | int dma_maxburst; | |
258 | ||
9b1fc55a MB |
259 | /* cpu view of rx dma ring */ |
260 | struct bcm_enet_desc *tx_desc_cpu; | |
261 | ||
262 | /* number of available descriptor for tx */ | |
263 | int tx_desc_count; | |
264 | ||
265 | /* next tx descriptor avaiable */ | |
266 | int tx_curr_desc; | |
267 | ||
268 | /* next dirty tx descriptor to reclaim */ | |
269 | int tx_dirty_desc; | |
270 | ||
271 | /* list of skb given to hw for tx */ | |
272 | struct sk_buff **tx_skb; | |
273 | ||
274 | /* lock used by tx reclaim and xmit */ | |
275 | spinlock_t tx_lock; | |
276 | ||
277 | ||
278 | /* set if internal phy is ignored and external mii interface | |
279 | * is selected */ | |
280 | int use_external_mii; | |
281 | ||
282 | /* set if a phy is connected, phy address must be known, | |
283 | * probing is not possible */ | |
284 | int has_phy; | |
285 | int phy_id; | |
286 | ||
287 | /* set if connected phy has an associated irq */ | |
288 | int has_phy_interrupt; | |
289 | int phy_interrupt; | |
290 | ||
291 | /* used when a phy is connected (phylib used) */ | |
292 | struct mii_bus *mii_bus; | |
293 | struct phy_device *phydev; | |
294 | int old_link; | |
295 | int old_duplex; | |
296 | int old_pause; | |
297 | ||
298 | /* used when no phy is connected */ | |
299 | int force_speed_100; | |
300 | int force_duplex_full; | |
301 | ||
302 | /* pause parameters */ | |
303 | int pause_auto; | |
304 | int pause_rx; | |
305 | int pause_tx; | |
306 | ||
307 | /* stats */ | |
9b1fc55a MB |
308 | struct bcm_enet_mib_counters mib; |
309 | ||
310 | /* after mib interrupt, mib registers update is done in this | |
311 | * work queue */ | |
312 | struct work_struct mib_update_task; | |
313 | ||
314 | /* lock mib update between userspace request and workqueue */ | |
315 | struct mutex mib_update_lock; | |
316 | ||
317 | /* mac clock */ | |
318 | struct clk *mac_clk; | |
319 | ||
320 | /* phy clock if internal phy is used */ | |
321 | struct clk *phy_clk; | |
322 | ||
323 | /* network device reference */ | |
324 | struct net_device *net_dev; | |
325 | ||
326 | /* platform device reference */ | |
327 | struct platform_device *pdev; | |
328 | ||
329 | /* maximum hardware transmit/receive size */ | |
330 | unsigned int hw_mtu; | |
6f00a022 MB |
331 | |
332 | bool enet_is_sw; | |
333 | ||
334 | /* port mapping for switch devices */ | |
335 | int num_ports; | |
336 | struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; | |
337 | int sw_port_link[ENETSW_MAX_PORT]; | |
338 | ||
339 | /* used to poll switch port state */ | |
340 | struct timer_list swphy_poll; | |
341 | spinlock_t enetsw_mdio_lock; | |
3dc6475c FF |
342 | |
343 | /* dma channel enable mask */ | |
344 | u32 dma_chan_en_mask; | |
345 | ||
346 | /* dma channel interrupt mask */ | |
347 | u32 dma_chan_int_mask; | |
348 | ||
349 | /* DMA engine has internal SRAM */ | |
350 | bool dma_has_sram; | |
351 | ||
352 | /* dma channel width */ | |
353 | unsigned int dma_chan_width; | |
354 | ||
355 | /* dma descriptor shift value */ | |
356 | unsigned int dma_desc_shift; | |
9b1fc55a MB |
357 | }; |
358 | ||
6f00a022 | 359 | |
9b1fc55a | 360 | #endif /* ! BCM63XX_ENET_H_ */ |