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net: thunderx: Fix memory leak while tearing down interface
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nicvf_main.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/ethtool.h>
15#include <linux/log2.h>
16#include <linux/prefetch.h>
17#include <linux/irq.h>
18
19#include "nic_reg.h"
20#include "nic.h"
21#include "nicvf_queues.h"
22#include "thunder_bgx.h"
23
24#define DRV_NAME "thunder-nicvf"
25#define DRV_VERSION "1.0"
26
27/* Supported devices */
28static const struct pci_device_id nicvf_id_table[] = {
29 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
30 PCI_DEVICE_ID_THUNDER_NIC_VF,
31 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
32 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
33 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
34 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
35 { 0, } /* end of table */
36};
37
38MODULE_AUTHOR("Sunil Goutham");
39MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
40MODULE_LICENSE("GPL v2");
41MODULE_VERSION(DRV_VERSION);
42MODULE_DEVICE_TABLE(pci, nicvf_id_table);
43
44static int debug = 0x00;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "Debug message level bitmap");
47
48static int cpi_alg = CPI_ALG_NONE;
49module_param(cpi_alg, int, S_IRUGO);
50MODULE_PARM_DESC(cpi_alg,
51 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
52
4863dea3
SG		 53static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
54 struct sk_buff *skb)
55{
56 if (skb->len <= 64)
57 nic->drv_stats.rx_frames_64++;
58 else if (skb->len <= 127)
59 nic->drv_stats.rx_frames_127++;
60 else if (skb->len <= 255)
61 nic->drv_stats.rx_frames_255++;
62 else if (skb->len <= 511)
63 nic->drv_stats.rx_frames_511++;
64 else if (skb->len <= 1023)
65 nic->drv_stats.rx_frames_1023++;
66 else if (skb->len <= 1518)
67 nic->drv_stats.rx_frames_1518++;
68 else
69 nic->drv_stats.rx_frames_jumbo++;
70}
71
72/* The Cavium ThunderX network controller can *only* be found in SoCs
73 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
74 * registers on this platform are implicitly strongly ordered with respect
75 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
76 * with no memory barriers in this driver. The readq()/writeq() functions add
77 * explicit ordering operation which in this case are redundant, and only
78 * add overhead.
79 */
80
81/* Register read/write APIs */
82void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
83{
84 writeq_relaxed(val, nic->reg_base + offset);
85}
86
87u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
88{
89 return readq_relaxed(nic->reg_base + offset);
90}
91
92void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
93 u64 qidx, u64 val)
94{
95 void __iomem *addr = nic->reg_base + offset;
96
97 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
98}
99
100u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
101{
102 void __iomem *addr = nic->reg_base + offset;
103
104 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
105}
106
107/* VF -> PF mailbox communication */
108
2cd2a196
AM		 109static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
110{
111 u64 *msg = (u64 *)mbx;
112
113 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
114 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
115}
116
4863dea3
SG		 117int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
118{
119 int timeout = NIC_MBOX_MSG_TIMEOUT;
120 int sleep = 10;
4863dea3
SG		 121
122 nic->pf_acked = false;
123 nic->pf_nacked = false;
124
2cd2a196 125 nicvf_write_to_mbx(nic, mbx);
4863dea3
SG		 126
127 /* Wait for previous message to be acked, timeout 2sec */
128 while (!nic->pf_acked) {
129 if (nic->pf_nacked)
130 return -EINVAL;
131 msleep(sleep);
132 if (nic->pf_acked)
133 break;
134 timeout -= sleep;
135 if (!timeout) {
136 netdev_err(nic->netdev,
137 "PF didn't ack to mbox msg %d from VF%d\n",
138 (mbx->msg.msg & 0xFF), nic->vf_id);
139 return -EBUSY;
140 }
141 }
142 return 0;
143}
144
145/* Checks if VF is able to comminicate with PF
146* and also gets the VNIC number this VF is associated to.
147*/
148static int nicvf_check_pf_ready(struct nicvf *nic)
149{
150 int timeout = 5000, sleep = 20;
2cd2a196
AM		 151 union nic_mbx mbx = {};
152
153 mbx.msg.msg = NIC_MBOX_MSG_READY;
4863dea3
SG		 154
155 nic->pf_ready_to_rcv_msg = false;
156
2cd2a196 157 nicvf_write_to_mbx(nic, &mbx);
4863dea3
SG		 158
159 while (!nic->pf_ready_to_rcv_msg) {
160 msleep(sleep);
161 if (nic->pf_ready_to_rcv_msg)
162 break;
163 timeout -= sleep;
164 if (!timeout) {
165 netdev_err(nic->netdev,
166 "PF didn't respond to READY msg\n");
167 return 0;
168 }
169 }
170 return 1;
171}
172
fd7ec062
AM		 173static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
174{
175 if (bgx->rx)
176 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
177 else
178 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
179}
180
4863dea3
SG		 181static void nicvf_handle_mbx_intr(struct nicvf *nic)
182{
183 union nic_mbx mbx = {};
184 u64 *mbx_data;
185 u64 mbx_addr;
186 int i;
187
188 mbx_addr = NIC_VF_PF_MAILBOX_0_1;
189 mbx_data = (u64 *)&mbx;
190
191 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
192 *mbx_data = nicvf_reg_read(nic, mbx_addr);
193 mbx_data++;
194 mbx_addr += sizeof(u64);
195 }
196
197 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
198 switch (mbx.msg.msg) {
199 case NIC_MBOX_MSG_READY:
200 nic->pf_ready_to_rcv_msg = true;
201 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
202 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
203 nic->node = mbx.nic_cfg.node_id;
bd049a90
PF		 204 if (!nic->set_mac_pending)
205 ether_addr_copy(nic->netdev->dev_addr,
206 mbx.nic_cfg.mac_addr);
4863dea3
SG		 207 nic->link_up = false;
208 nic->duplex = 0;
209 nic->speed = 0;
210 break;
211 case NIC_MBOX_MSG_ACK:
212 nic->pf_acked = true;
213 break;
214 case NIC_MBOX_MSG_NACK:
215 nic->pf_nacked = true;
216 break;
217 case NIC_MBOX_MSG_RSS_SIZE:
218 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
219 nic->pf_acked = true;
220 break;
221 case NIC_MBOX_MSG_BGX_STATS:
222 nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
223 nic->pf_acked = true;
224 nic->bgx_stats_acked = true;
225 break;
226 case NIC_MBOX_MSG_BGX_LINK_CHANGE:
227 nic->pf_acked = true;
228 nic->link_up = mbx.link_status.link_up;
229 nic->duplex = mbx.link_status.duplex;
230 nic->speed = mbx.link_status.speed;
231 if (nic->link_up) {
232 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n",
233 nic->netdev->name, nic->speed,
234 nic->duplex == DUPLEX_FULL ?
235 "Full duplex" : "Half duplex");
236 netif_carrier_on(nic->netdev);
237 netif_tx_wake_all_queues(nic->netdev);
238 } else {
239 netdev_info(nic->netdev, "%s: Link is Down\n",
240 nic->netdev->name);
241 netif_carrier_off(nic->netdev);
242 netif_tx_stop_all_queues(nic->netdev);
243 }
244 break;
245 default:
246 netdev_err(nic->netdev,
247 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
248 break;
249 }
250 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
251}
252
253static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
254{
255 union nic_mbx mbx = {};
4863dea3
SG		 256
257 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
258 mbx.mac.vf_id = nic->vf_id;
e610cb32 259 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
4863dea3
SG		 260
261 return nicvf_send_msg_to_pf(nic, &mbx);
262}
263
fd7ec062 264static void nicvf_config_cpi(struct nicvf *nic)
4863dea3
SG		 265{
266 union nic_mbx mbx = {};
267
268 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
269 mbx.cpi_cfg.vf_id = nic->vf_id;
270 mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
271 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
272
273 nicvf_send_msg_to_pf(nic, &mbx);
274}
275
fd7ec062 276static void nicvf_get_rss_size(struct nicvf *nic)
4863dea3
SG		 277{
278 union nic_mbx mbx = {};
279
280 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
281 mbx.rss_size.vf_id = nic->vf_id;
282 nicvf_send_msg_to_pf(nic, &mbx);
283}
284
285void nicvf_config_rss(struct nicvf *nic)
286{
287 union nic_mbx mbx = {};
288 struct nicvf_rss_info *rss = &nic->rss_info;
289 int ind_tbl_len = rss->rss_size;
290 int i, nextq = 0;
291
292 mbx.rss_cfg.vf_id = nic->vf_id;
293 mbx.rss_cfg.hash_bits = rss->hash_bits;
294 while (ind_tbl_len) {
295 mbx.rss_cfg.tbl_offset = nextq;
296 mbx.rss_cfg.tbl_len = min(ind_tbl_len,
297 RSS_IND_TBL_LEN_PER_MBX_MSG);
298 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
299 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
300
301 for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
302 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
303
304 nicvf_send_msg_to_pf(nic, &mbx);
305
306 ind_tbl_len -= mbx.rss_cfg.tbl_len;
307 }
308}
309
310void nicvf_set_rss_key(struct nicvf *nic)
311{
312 struct nicvf_rss_info *rss = &nic->rss_info;
313 u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
314 int idx;
315
316 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
317 nicvf_reg_write(nic, key_addr, rss->key[idx]);
318 key_addr += sizeof(u64);
319 }
320}
321
322static int nicvf_rss_init(struct nicvf *nic)
323{
324 struct nicvf_rss_info *rss = &nic->rss_info;
325 int idx;
326
327 nicvf_get_rss_size(nic);
328
329 if ((nic->qs->rq_cnt <= 1) || (cpi_alg != CPI_ALG_NONE)) {
330 rss->enable = false;
331 rss->hash_bits = 0;
332 return 0;
333 }
334
335 rss->enable = true;
336
337 /* Using the HW reset value for now */
4a4f87d8
AM		 338 rss->key[0] = 0xFEED0BADFEED0BADULL;
339 rss->key[1] = 0xFEED0BADFEED0BADULL;
340 rss->key[2] = 0xFEED0BADFEED0BADULL;
341 rss->key[3] = 0xFEED0BADFEED0BADULL;
342 rss->key[4] = 0xFEED0BADFEED0BADULL;
4863dea3
SG		 343
344 nicvf_set_rss_key(nic);
345
346 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
347 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
348
349 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
350
351 for (idx = 0; idx < rss->rss_size; idx++)
352 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
353 nic->qs->rq_cnt);
354 nicvf_config_rss(nic);
355 return 1;
356}
357
358int nicvf_set_real_num_queues(struct net_device *netdev,
359 int tx_queues, int rx_queues)
360{
361 int err = 0;
362
363 err = netif_set_real_num_tx_queues(netdev, tx_queues);
364 if (err) {
365 netdev_err(netdev,
366 "Failed to set no of Tx queues: %d\n", tx_queues);
367 return err;
368 }
369
370 err = netif_set_real_num_rx_queues(netdev, rx_queues);
371 if (err)
372 netdev_err(netdev,
373 "Failed to set no of Rx queues: %d\n", rx_queues);
374 return err;
375}
376
377static int nicvf_init_resources(struct nicvf *nic)
378{
379 int err;
2cd2a196
AM		 380 union nic_mbx mbx = {};
381
382 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
4863dea3
SG		 383
384 /* Enable Qset */
385 nicvf_qset_config(nic, true);
386
387 /* Initialize queues and HW for data transfer */
388 err = nicvf_config_data_transfer(nic, true);
389 if (err) {
390 netdev_err(nic->netdev,
391 "Failed to alloc/config VF's QSet resources\n");
392 return err;
393 }
394
395 /* Send VF config done msg to PF */
2cd2a196 396 nicvf_write_to_mbx(nic, &mbx);
4863dea3
SG		 397
398 return 0;
399}
400
401static void nicvf_snd_pkt_handler(struct net_device *netdev,
402 struct cmp_queue *cq,
403 struct cqe_send_t *cqe_tx, int cqe_type)
404{
405 struct sk_buff *skb = NULL;
406 struct nicvf *nic = netdev_priv(netdev);
407 struct snd_queue *sq;
408 struct sq_hdr_subdesc *hdr;
409
410 sq = &nic->qs->sq[cqe_tx->sq_idx];
411
412 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
413 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
414 return;
415
416 netdev_dbg(nic->netdev,
417 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
418 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
419 cqe_tx->sqe_ptr, hdr->subdesc_cnt);
420
421 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
422 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
423 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
424 /* For TSO offloaded packets only one head SKB needs to be freed */
425 if (skb) {
426 prefetch(skb);
427 dev_consume_skb_any(skb);
143ceb0b 428 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
4863dea3
SG		 429 }
430}
431
432static void nicvf_rcv_pkt_handler(struct net_device *netdev,
433 struct napi_struct *napi,
434 struct cmp_queue *cq,
435 struct cqe_rx_t *cqe_rx, int cqe_type)
436{
437 struct sk_buff *skb;
438 struct nicvf *nic = netdev_priv(netdev);
439 int err = 0;
440
441 /* Check for errors */
442 err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx);
443 if (err && !cqe_rx->rb_cnt)
444 return;
445
446 skb = nicvf_get_rcv_skb(nic, cqe_rx);
447 if (!skb) {
448 netdev_dbg(nic->netdev, "Packet not received\n");
449 return;
450 }
451
452 if (netif_msg_pktdata(nic)) {
453 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name,
454 skb, skb->len);
455 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
456 skb->data, skb->len, true);
457 }
458
459 nicvf_set_rx_frame_cnt(nic, skb);
460
461 skb_record_rx_queue(skb, cqe_rx->rq_idx);
462 if (netdev->hw_features & NETIF_F_RXCSUM) {
463 /* HW by default verifies TCP/UDP/SCTP checksums */
464 skb->ip_summed = CHECKSUM_UNNECESSARY;
465 } else {
466 skb_checksum_none_assert(skb);
467 }
468
469 skb->protocol = eth_type_trans(skb, netdev);
470
471 if (napi && (netdev->features & NETIF_F_GRO))
472 napi_gro_receive(napi, skb);
473 else
474 netif_receive_skb(skb);
475}
476
477static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
478 struct napi_struct *napi, int budget)
479{
480 int processed_cqe, work_done = 0;
481 int cqe_count, cqe_head;
482 struct nicvf *nic = netdev_priv(netdev);
483 struct queue_set *qs = nic->qs;
484 struct cmp_queue *cq = &qs->cq[cq_idx];
485 struct cqe_rx_t *cq_desc;
486
487 spin_lock_bh(&cq->lock);
488loop:
489 processed_cqe = 0;
490 /* Get no of valid CQ entries to process */
491 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
492 cqe_count &= CQ_CQE_COUNT;
493 if (!cqe_count)
494 goto done;
495
496 /* Get head of the valid CQ entries */
497 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
498 cqe_head &= 0xFFFF;
499
500 netdev_dbg(nic->netdev, "%s cqe_count %d cqe_head %d\n",
501 __func__, cqe_count, cqe_head);
502 while (processed_cqe < cqe_count) {
503 /* Get the CQ descriptor */
504 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
505 cqe_head++;
506 cqe_head &= (cq->dmem.q_len - 1);
507 /* Initiate prefetch for next descriptor */
508 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
509
510 if ((work_done >= budget) && napi &&
511 (cq_desc->cqe_type != CQE_TYPE_SEND)) {
512 break;
513 }
514
515 netdev_dbg(nic->netdev, "cq_desc->cqe_type %d\n",
516 cq_desc->cqe_type);
517 switch (cq_desc->cqe_type) {
518 case CQE_TYPE_RX:
519 nicvf_rcv_pkt_handler(netdev, napi, cq,
520 cq_desc, CQE_TYPE_RX);
521 work_done++;
522 break;
523 case CQE_TYPE_SEND:
524 nicvf_snd_pkt_handler(netdev, cq,
525 (void *)cq_desc, CQE_TYPE_SEND);
526 break;
527 case CQE_TYPE_INVALID:
528 case CQE_TYPE_RX_SPLIT:
529 case CQE_TYPE_RX_TCP:
530 case CQE_TYPE_SEND_PTP:
531 /* Ignore for now */
532 break;
533 }
534 processed_cqe++;
535 }
536 netdev_dbg(nic->netdev, "%s processed_cqe %d work_done %d budget %d\n",
537 __func__, processed_cqe, work_done, budget);
538
539 /* Ring doorbell to inform H/W to reuse processed CQEs */
540 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
541 cq_idx, processed_cqe);
542
543 if ((work_done < budget) && napi)
544 goto loop;
545
546done:
547 spin_unlock_bh(&cq->lock);
548 return work_done;
549}
550
551static int nicvf_poll(struct napi_struct *napi, int budget)
552{
553 u64 cq_head;
554 int work_done = 0;
555 struct net_device *netdev = napi->dev;
556 struct nicvf *nic = netdev_priv(netdev);
557 struct nicvf_cq_poll *cq;
558 struct netdev_queue *txq;
559
560 cq = container_of(napi, struct nicvf_cq_poll, napi);
561 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
562
563 txq = netdev_get_tx_queue(netdev, cq->cq_idx);
564 if (netif_tx_queue_stopped(txq))
565 netif_tx_wake_queue(txq);
566
567 if (work_done < budget) {
568 /* Slow packet rate, exit polling */
569 napi_complete(napi);
570 /* Re-enable interrupts */
571 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
572 cq->cq_idx);
573 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
574 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
575 cq->cq_idx, cq_head);
576 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
577 }
578 return work_done;
579}
580
581/* Qset error interrupt handler
582 *
583 * As of now only CQ errors are handled
584 */
fd7ec062 585static void nicvf_handle_qs_err(unsigned long data)
4863dea3
SG		 586{
587 struct nicvf *nic = (struct nicvf *)data;
588 struct queue_set *qs = nic->qs;
589 int qidx;
590 u64 status;
591
592 netif_tx_disable(nic->netdev);
593
594 /* Check if it is CQ err */
595 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
596 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
597 qidx);
598 if (!(status & CQ_ERR_MASK))
599 continue;
600 /* Process already queued CQEs and reconfig CQ */
601 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
602 nicvf_sq_disable(nic, qidx);
603 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
604 nicvf_cmp_queue_config(nic, qs, qidx, true);
605 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
606 nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
607
608 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
609 }
610
611 netif_tx_start_all_queues(nic->netdev);
612 /* Re-enable Qset error interrupt */
613 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
614}
615
616static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
617{
618 struct nicvf *nic = (struct nicvf *)nicvf_irq;
619 u64 intr;
620
621 intr = nicvf_reg_read(nic, NIC_VF_INT);
622 /* Check for spurious interrupt */
623 if (!(intr & NICVF_INTR_MBOX_MASK))
624 return IRQ_HANDLED;
625
626 nicvf_handle_mbx_intr(nic);
627
628 return IRQ_HANDLED;
629}
630
631static irqreturn_t nicvf_intr_handler(int irq, void *nicvf_irq)
632{
633 u64 qidx, intr, clear_intr = 0;
634 u64 cq_intr, rbdr_intr, qs_err_intr;
635 struct nicvf *nic = (struct nicvf *)nicvf_irq;
636 struct queue_set *qs = nic->qs;
637 struct nicvf_cq_poll *cq_poll = NULL;
638
639 intr = nicvf_reg_read(nic, NIC_VF_INT);
640 if (netif_msg_intr(nic))
641 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n",
642 nic->netdev->name, intr);
643
644 qs_err_intr = intr & NICVF_INTR_QS_ERR_MASK;
645 if (qs_err_intr) {
646 /* Disable Qset err interrupt and schedule softirq */
647 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
648 tasklet_hi_schedule(&nic->qs_err_task);
649 clear_intr |= qs_err_intr;
650 }
651
652 /* Disable interrupts and start polling */
653 cq_intr = (intr & NICVF_INTR_CQ_MASK) >> NICVF_INTR_CQ_SHIFT;
654 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
655 if (!(cq_intr & (1 << qidx)))
656 continue;
657 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_CQ, qidx))
658 continue;
659
660 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
661 clear_intr |= ((1 << qidx) << NICVF_INTR_CQ_SHIFT);
662
663 cq_poll = nic->napi[qidx];
664 /* Schedule NAPI */
665 if (cq_poll)
666 napi_schedule(&cq_poll->napi);
667 }
668
669 /* Handle RBDR interrupts */
670 rbdr_intr = (intr & NICVF_INTR_RBDR_MASK) >> NICVF_INTR_RBDR_SHIFT;
671 if (rbdr_intr) {
672 /* Disable RBDR interrupt and schedule softirq */
673 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
674 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
675 continue;
676 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
677 tasklet_hi_schedule(&nic->rbdr_task);
678 clear_intr |= ((1 << qidx) << NICVF_INTR_RBDR_SHIFT);
679 }
680 }
681
682 /* Clear interrupts */
683 nicvf_reg_write(nic, NIC_VF_INT, clear_intr);
684 return IRQ_HANDLED;
685}
686
687static int nicvf_enable_msix(struct nicvf *nic)
688{
689 int ret, vec;
690
691 nic->num_vec = NIC_VF_MSIX_VECTORS;
692
693 for (vec = 0; vec < nic->num_vec; vec++)
694 nic->msix_entries[vec].entry = vec;
695
696 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
697 if (ret) {
698 netdev_err(nic->netdev,
699 "Req for #%d msix vectors failed\n", nic->num_vec);
700 return 0;
701 }
702 nic->msix_enabled = 1;
703 return 1;
704}
705
706static void nicvf_disable_msix(struct nicvf *nic)
707{
708 if (nic->msix_enabled) {
709 pci_disable_msix(nic->pdev);
710 nic->msix_enabled = 0;
711 nic->num_vec = 0;
712 }
713}
714
715static int nicvf_register_interrupts(struct nicvf *nic)
716{
717 int irq, free, ret = 0;
718 int vector;
719
720 for_each_cq_irq(irq)
721 sprintf(nic->irq_name[irq], "NICVF%d CQ%d",
722 nic->vf_id, irq);
723
724 for_each_sq_irq(irq)
725 sprintf(nic->irq_name[irq], "NICVF%d SQ%d",
726 nic->vf_id, irq - NICVF_INTR_ID_SQ);
727
728 for_each_rbdr_irq(irq)
729 sprintf(nic->irq_name[irq], "NICVF%d RBDR%d",
730 nic->vf_id, irq - NICVF_INTR_ID_RBDR);
731
732 /* Register all interrupts except mailbox */
733 for (irq = 0; irq < NICVF_INTR_ID_SQ; irq++) {
734 vector = nic->msix_entries[irq].vector;
735 ret = request_irq(vector, nicvf_intr_handler,
736 0, nic->irq_name[irq], nic);
737 if (ret)
738 break;
739 nic->irq_allocated[irq] = true;
740 }
741
742 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_MISC; irq++) {
743 vector = nic->msix_entries[irq].vector;
744 ret = request_irq(vector, nicvf_intr_handler,
745 0, nic->irq_name[irq], nic);
746 if (ret)
747 break;
748 nic->irq_allocated[irq] = true;
749 }
750
751 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR],
752 "NICVF%d Qset error", nic->vf_id);
753 if (!ret) {
754 vector = nic->msix_entries[NICVF_INTR_ID_QS_ERR].vector;
755 irq = NICVF_INTR_ID_QS_ERR;
756 ret = request_irq(vector, nicvf_intr_handler,
757 0, nic->irq_name[irq], nic);
758 if (!ret)
759 nic->irq_allocated[irq] = true;
760 }
761
762 if (ret) {
763 netdev_err(nic->netdev, "Request irq failed\n");
764 for (free = 0; free < irq; free++)
765 free_irq(nic->msix_entries[free].vector, nic);
766 return ret;
767 }
768
769 return 0;
770}
771
772static void nicvf_unregister_interrupts(struct nicvf *nic)
773{
774 int irq;
775
776 /* Free registered interrupts */
777 for (irq = 0; irq < nic->num_vec; irq++) {
778 if (nic->irq_allocated[irq])
779 free_irq(nic->msix_entries[irq].vector, nic);
780 nic->irq_allocated[irq] = false;
781 }
782
783 /* Disable MSI-X */
784 nicvf_disable_msix(nic);
785}
786
787/* Initialize MSIX vectors and register MISC interrupt.
788 * Send READY message to PF to check if its alive
789 */
790static int nicvf_register_misc_interrupt(struct nicvf *nic)
791{
792 int ret = 0;
793 int irq = NICVF_INTR_ID_MISC;
794
795 /* Return if mailbox interrupt is already registered */
796 if (nic->msix_enabled)
797 return 0;
798
799 /* Enable MSI-X */
800 if (!nicvf_enable_msix(nic))
801 return 1;
802
803 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
804 /* Register Misc interrupt */
805 ret = request_irq(nic->msix_entries[irq].vector,
806 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
807
808 if (ret)
809 return ret;
810 nic->irq_allocated[irq] = true;
811
812 /* Enable mailbox interrupt */
813 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
814
815 /* Check if VF is able to communicate with PF */
816 if (!nicvf_check_pf_ready(nic)) {
817 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
818 nicvf_unregister_interrupts(nic);
819 return 1;
820 }
821
822 return 0;
823}
824
825static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
826{
827 struct nicvf *nic = netdev_priv(netdev);
828 int qid = skb_get_queue_mapping(skb);
829 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
830
831 /* Check for minimum packet length */
832 if (skb->len <= ETH_HLEN) {
833 dev_kfree_skb(skb);
834 return NETDEV_TX_OK;
835 }
836
837 if (!nicvf_sq_append_skb(nic, skb) && !netif_tx_queue_stopped(txq)) {
838 netif_tx_stop_queue(txq);
839 nic->drv_stats.tx_busy++;
840 if (netif_msg_tx_err(nic))
841 netdev_warn(netdev,
842 "%s: Transmit ring full, stopping SQ%d\n",
843 netdev->name, qid);
844
845 return NETDEV_TX_BUSY;
846 }
847
848 return NETDEV_TX_OK;
849}
850
851int nicvf_stop(struct net_device *netdev)
852{
853 int irq, qidx;
854 struct nicvf *nic = netdev_priv(netdev);
855 struct queue_set *qs = nic->qs;
856 struct nicvf_cq_poll *cq_poll = NULL;
857 union nic_mbx mbx = {};
858
859 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
860 nicvf_send_msg_to_pf(nic, &mbx);
861
862 netif_carrier_off(netdev);
863 netif_tx_disable(netdev);
864
865 /* Disable RBDR & QS error interrupts */
866 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
867 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
868 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
869 }
870 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
871 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
872
873 /* Wait for pending IRQ handlers to finish */
874 for (irq = 0; irq < nic->num_vec; irq++)
875 synchronize_irq(nic->msix_entries[irq].vector);
876
877 tasklet_kill(&nic->rbdr_task);
878 tasklet_kill(&nic->qs_err_task);
879 if (nic->rb_work_scheduled)
880 cancel_delayed_work_sync(&nic->rbdr_work);
881
882 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
883 cq_poll = nic->napi[qidx];
884 if (!cq_poll)
885 continue;
886 nic->napi[qidx] = NULL;
887 napi_synchronize(&cq_poll->napi);
888 /* CQ intr is enabled while napi_complete,
889 * so disable it now
890 */
891 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
892 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
893 napi_disable(&cq_poll->napi);
894 netif_napi_del(&cq_poll->napi);
895 kfree(cq_poll);
896 }
897
898 /* Free resources */
899 nicvf_config_data_transfer(nic, false);
900
901 /* Disable HW Qset */
902 nicvf_qset_config(nic, false);
903
904 /* disable mailbox interrupt */
905 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
906
907 nicvf_unregister_interrupts(nic);
908
909 return 0;
910}
911
912int nicvf_open(struct net_device *netdev)
913{
914 int err, qidx;
915 struct nicvf *nic = netdev_priv(netdev);
916 struct queue_set *qs = nic->qs;
917 struct nicvf_cq_poll *cq_poll = NULL;
918
919 nic->mtu = netdev->mtu;
920
921 netif_carrier_off(netdev);
922
923 err = nicvf_register_misc_interrupt(nic);
924 if (err)
925 return err;
926
927 /* Register NAPI handler for processing CQEs */
928 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
929 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
930 if (!cq_poll) {
931 err = -ENOMEM;
932 goto napi_del;
933 }
934 cq_poll->cq_idx = qidx;
935 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
936 NAPI_POLL_WEIGHT);
937 napi_enable(&cq_poll->napi);
938 nic->napi[qidx] = cq_poll;
939 }
940
941 /* Check if we got MAC address from PF or else generate a radom MAC */
942 if (is_zero_ether_addr(netdev->dev_addr)) {
943 eth_hw_addr_random(netdev);
944 nicvf_hw_set_mac_addr(nic, netdev);
945 }
946
bd049a90
PF		 947 if (nic->set_mac_pending) {
948 nic->set_mac_pending = false;
949 nicvf_hw_set_mac_addr(nic, netdev);
950 }
951
4863dea3
SG		 952 /* Init tasklet for handling Qset err interrupt */
953 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
954 (unsigned long)nic);
955
956 /* Init RBDR tasklet which will refill RBDR */
957 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
958 (unsigned long)nic);
959 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
960
961 /* Configure CPI alorithm */
962 nic->cpi_alg = cpi_alg;
963 nicvf_config_cpi(nic);
964
965 /* Configure receive side scaling */
966 nicvf_rss_init(nic);
967
968 err = nicvf_register_interrupts(nic);
969 if (err)
970 goto cleanup;
971
972 /* Initialize the queues */
973 err = nicvf_init_resources(nic);
974 if (err)
975 goto cleanup;
976
977 /* Make sure queue initialization is written */
978 wmb();
979
980 nicvf_reg_write(nic, NIC_VF_INT, -1);
981 /* Enable Qset err interrupt */
982 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
983
984 /* Enable completion queue interrupt */
985 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
986 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
987
988 /* Enable RBDR threshold interrupt */
989 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
990 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
991
992 netif_carrier_on(netdev);
993 netif_tx_start_all_queues(netdev);
994
995 return 0;
996cleanup:
997 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
998 nicvf_unregister_interrupts(nic);
999napi_del:
1000 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1001 cq_poll = nic->napi[qidx];
1002 if (!cq_poll)
1003 continue;
1004 napi_disable(&cq_poll->napi);
1005 netif_napi_del(&cq_poll->napi);
1006 kfree(cq_poll);
1007 nic->napi[qidx] = NULL;
1008 }
1009 return err;
1010}
1011
1012static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1013{
1014 union nic_mbx mbx = {};
1015
1016 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1017 mbx.frs.max_frs = mtu;
1018 mbx.frs.vf_id = nic->vf_id;
1019
1020 return nicvf_send_msg_to_pf(nic, &mbx);
1021}
1022
1023static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1024{
1025 struct nicvf *nic = netdev_priv(netdev);
1026
1027 if (new_mtu > NIC_HW_MAX_FRS)
1028 return -EINVAL;
1029
1030 if (new_mtu < NIC_HW_MIN_FRS)
1031 return -EINVAL;
1032
1033 if (nicvf_update_hw_max_frs(nic, new_mtu))
1034 return -EINVAL;
1035 netdev->mtu = new_mtu;
1036 nic->mtu = new_mtu;
1037
1038 return 0;
1039}
1040
1041static int nicvf_set_mac_address(struct net_device *netdev, void *p)
1042{
1043 struct sockaddr *addr = p;
1044 struct nicvf *nic = netdev_priv(netdev);
1045
1046 if (!is_valid_ether_addr(addr->sa_data))
1047 return -EADDRNOTAVAIL;
1048
1049 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1050
bd049a90 1051 if (nic->msix_enabled) {
4863dea3
SG		 1052 if (nicvf_hw_set_mac_addr(nic, netdev))
1053 return -EBUSY;
bd049a90
PF		 1054 } else {
1055 nic->set_mac_pending = true;
1056 }
4863dea3
SG		 1057
1058 return 0;
1059}
1060
4863dea3
SG		 1061void nicvf_update_lmac_stats(struct nicvf *nic)
1062{
1063 int stat = 0;
1064 union nic_mbx mbx = {};
1065 int timeout;
1066
1067 if (!netif_running(nic->netdev))
1068 return;
1069
1070 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
1071 mbx.bgx_stats.vf_id = nic->vf_id;
1072 /* Rx stats */
1073 mbx.bgx_stats.rx = 1;
1074 while (stat < BGX_RX_STATS_COUNT) {
1075 nic->bgx_stats_acked = 0;
1076 mbx.bgx_stats.idx = stat;
1077 nicvf_send_msg_to_pf(nic, &mbx);
1078 timeout = 0;
1079 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1080 msleep(2);
1081 timeout++;
1082 }
1083 stat++;
1084 }
1085
1086 stat = 0;
1087
1088 /* Tx stats */
1089 mbx.bgx_stats.rx = 0;
1090 while (stat < BGX_TX_STATS_COUNT) {
1091 nic->bgx_stats_acked = 0;
1092 mbx.bgx_stats.idx = stat;
1093 nicvf_send_msg_to_pf(nic, &mbx);
1094 timeout = 0;
1095 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1096 msleep(2);
1097 timeout++;
1098 }
1099 stat++;
1100 }
1101}
1102
1103void nicvf_update_stats(struct nicvf *nic)
1104{
1105 int qidx;
1106 struct nicvf_hw_stats *stats = &nic->stats;
1107 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1108 struct queue_set *qs = nic->qs;
1109
1110#define GET_RX_STATS(reg) \
1111 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
1112#define GET_TX_STATS(reg) \
1113 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
1114
1115 stats->rx_bytes_ok = GET_RX_STATS(RX_OCTS);
1116 stats->rx_ucast_frames_ok = GET_RX_STATS(RX_UCAST);
1117 stats->rx_bcast_frames_ok = GET_RX_STATS(RX_BCAST);
1118 stats->rx_mcast_frames_ok = GET_RX_STATS(RX_MCAST);
1119 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
1120 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
1121 stats->rx_drop_red = GET_RX_STATS(RX_RED);
1122 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
1123 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
1124 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
1125 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1126 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1127
1128 stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);
1129 stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);
1130 stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);
1131 stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);
1132 stats->tx_drops = GET_TX_STATS(TX_DROP);
1133
1134 drv_stats->rx_frames_ok = stats->rx_ucast_frames_ok +
1135 stats->rx_bcast_frames_ok +
1136 stats->rx_mcast_frames_ok;
1137 drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +
1138 stats->tx_bcast_frames_ok +
1139 stats->tx_mcast_frames_ok;
1140 drv_stats->rx_drops = stats->rx_drop_red +
1141 stats->rx_drop_overrun;
1142 drv_stats->tx_drops = stats->tx_drops;
1143
1144 /* Update RQ and SQ stats */
1145 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1146 nicvf_update_rq_stats(nic, qidx);
1147 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1148 nicvf_update_sq_stats(nic, qidx);
1149}
1150
fd7ec062 1151static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev,
4863dea3
SG		 1152 struct rtnl_link_stats64 *stats)
1153{
1154 struct nicvf *nic = netdev_priv(netdev);
1155 struct nicvf_hw_stats *hw_stats = &nic->stats;
1156 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1157
1158 nicvf_update_stats(nic);
1159
1160 stats->rx_bytes = hw_stats->rx_bytes_ok;
1161 stats->rx_packets = drv_stats->rx_frames_ok;
1162 stats->rx_dropped = drv_stats->rx_drops;
1163
1164 stats->tx_bytes = hw_stats->tx_bytes_ok;
1165 stats->tx_packets = drv_stats->tx_frames_ok;
1166 stats->tx_dropped = drv_stats->tx_drops;
1167
1168 return stats;
1169}
1170
1171static void nicvf_tx_timeout(struct net_device *dev)
1172{
1173 struct nicvf *nic = netdev_priv(dev);
1174
1175 if (netif_msg_tx_err(nic))
1176 netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1177 dev->name);
1178
1179 schedule_work(&nic->reset_task);
1180}
1181
1182static void nicvf_reset_task(struct work_struct *work)
1183{
1184 struct nicvf *nic;
1185
1186 nic = container_of(work, struct nicvf, reset_task);
1187
1188 if (!netif_running(nic->netdev))
1189 return;
1190
1191 nicvf_stop(nic->netdev);
1192 nicvf_open(nic->netdev);
1193 nic->netdev->trans_start = jiffies;
1194}
1195
1196static const struct net_device_ops nicvf_netdev_ops = {
1197 .ndo_open = nicvf_open,
1198 .ndo_stop = nicvf_stop,
1199 .ndo_start_xmit = nicvf_xmit,
1200 .ndo_change_mtu = nicvf_change_mtu,
1201 .ndo_set_mac_address = nicvf_set_mac_address,
1202 .ndo_get_stats64 = nicvf_get_stats64,
1203 .ndo_tx_timeout = nicvf_tx_timeout,
1204};
1205
1206static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1207{
1208 struct device *dev = &pdev->dev;
1209 struct net_device *netdev;
1210 struct nicvf *nic;
1211 struct queue_set *qs;
1212 int err;
1213
1214 err = pci_enable_device(pdev);
1215 if (err) {
1216 dev_err(dev, "Failed to enable PCI device\n");
1217 return err;
1218 }
1219
1220 err = pci_request_regions(pdev, DRV_NAME);
1221 if (err) {
1222 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1223 goto err_disable_device;
1224 }
1225
1226 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1227 if (err) {
1228 dev_err(dev, "Unable to get usable DMA configuration\n");
1229 goto err_release_regions;
1230 }
1231
1232 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1233 if (err) {
1234 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
1235 goto err_release_regions;
1236 }
1237
1238 netdev = alloc_etherdev_mqs(sizeof(struct nicvf),
1239 MAX_RCV_QUEUES_PER_QS,
1240 MAX_SND_QUEUES_PER_QS);
1241 if (!netdev) {
1242 err = -ENOMEM;
1243 goto err_release_regions;
1244 }
1245
1246 pci_set_drvdata(pdev, netdev);
1247
1248 SET_NETDEV_DEV(netdev, &pdev->dev);
1249
1250 nic = netdev_priv(netdev);
1251 nic->netdev = netdev;
1252 nic->pdev = pdev;
1253
1254 /* MAP VF's configuration registers */
1255 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1256 if (!nic->reg_base) {
1257 dev_err(dev, "Cannot map config register space, aborting\n");
1258 err = -ENOMEM;
1259 goto err_free_netdev;
1260 }
1261
1262 err = nicvf_set_qset_resources(nic);
1263 if (err)
1264 goto err_free_netdev;
1265
1266 qs = nic->qs;
1267
1268 err = nicvf_set_real_num_queues(netdev, qs->sq_cnt, qs->rq_cnt);
1269 if (err)
1270 goto err_free_netdev;
1271
1272 /* Check if PF is alive and get MAC address for this VF */
1273 err = nicvf_register_misc_interrupt(nic);
1274 if (err)
1275 goto err_free_netdev;
1276
1277 netdev->features |= (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
1278 NETIF_F_TSO | NETIF_F_GRO);
1279 netdev->hw_features = netdev->features;
1280
1281 netdev->netdev_ops = &nicvf_netdev_ops;
1282
1283 INIT_WORK(&nic->reset_task, nicvf_reset_task);
1284
1285 err = register_netdev(netdev);
1286 if (err) {
1287 dev_err(dev, "Failed to register netdevice\n");
1288 goto err_unregister_interrupts;
1289 }
1290
1291 nic->msg_enable = debug;
1292
1293 nicvf_set_ethtool_ops(netdev);
1294
1295 return 0;
1296
1297err_unregister_interrupts:
1298 nicvf_unregister_interrupts(nic);
1299err_free_netdev:
1300 pci_set_drvdata(pdev, NULL);
1301 free_netdev(netdev);
1302err_release_regions:
1303 pci_release_regions(pdev);
1304err_disable_device:
1305 pci_disable_device(pdev);
1306 return err;
1307}
1308
1309static void nicvf_remove(struct pci_dev *pdev)
1310{
1311 struct net_device *netdev = pci_get_drvdata(pdev);
1312 struct nicvf *nic = netdev_priv(netdev);
1313
1314 unregister_netdev(netdev);
1315 nicvf_unregister_interrupts(nic);
1316 pci_set_drvdata(pdev, NULL);
1317 free_netdev(netdev);
1318 pci_release_regions(pdev);
1319 pci_disable_device(pdev);
1320}
1321
1322static struct pci_driver nicvf_driver = {
1323 .name = DRV_NAME,
1324 .id_table = nicvf_id_table,
1325 .probe = nicvf_probe,
1326 .remove = nicvf_remove,
1327};
1328
1329static int __init nicvf_init_module(void)
1330{
1331 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1332
1333 return pci_register_driver(&nicvf_driver);
1334}
1335
1336static void __exit nicvf_cleanup_module(void)
1337{
1338 pci_unregister_driver(&nicvf_driver);
1339}
1340
1341module_init(nicvf_init_module);
1342module_exit(nicvf_cleanup_module);
Linux kernel - Deliverables
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