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infiniband: pass rdma_cm module to netlink_dump_start
[deliverable/linux.git] / drivers / net / ethernet / freescale / ucc_geth.c
CommitLineData
ce973b14 1/*
047584ce 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
9d9779e7 20#include <linux/module.h>
ce973b14
LY		 21#include <linux/interrupt.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/spinlock.h>
26#include <linux/mm.h>
ce973b14 27#include <linux/dma-mapping.h>
ce973b14 28#include <linux/mii.h>
728de4c9 29#include <linux/phy.h>
df19b6b0 30#include <linux/workqueue.h>
0b9da337 31#include <linux/of_mdio.h>
4b6ba8aa 32#include <linux/of_net.h>
55b6c8e9 33#include <linux/of_platform.h>
ce973b14
LY		 34
35#include <asm/uaccess.h>
36#include <asm/irq.h>
37#include <asm/io.h>
38#include <asm/immap_qe.h>
39#include <asm/qe.h>
40#include <asm/ucc.h>
41#include <asm/ucc_fast.h>
81abb43a 42#include <asm/machdep.h>
ce973b14
LY		 43
44#include "ucc_geth.h"
ce973b14
LY		 45
46#undef DEBUG
47
ce973b14
LY		 48#define ugeth_printk(level, format, arg...) \
49 printk(level format "\n", ## arg)
50
51#define ugeth_dbg(format, arg...) \
52 ugeth_printk(KERN_DEBUG , format , ## arg)
53#define ugeth_err(format, arg...) \
54 ugeth_printk(KERN_ERR , format , ## arg)
55#define ugeth_info(format, arg...) \
56 ugeth_printk(KERN_INFO , format , ## arg)
57#define ugeth_warn(format, arg...) \
58 ugeth_printk(KERN_WARNING , format , ## arg)
59
60#ifdef UGETH_VERBOSE_DEBUG
61#define ugeth_vdbg ugeth_dbg
62#else
63#define ugeth_vdbg(fmt, args...) do { } while (0)
64#endif /* UGETH_VERBOSE_DEBUG */
890de95e 65#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 66
88a15f2e 67
ce973b14
LY		 68static DEFINE_SPINLOCK(ugeth_lock);
69
890de95e
LY		 70static struct {
71 u32 msg_enable;
72} debug = { -1 };
73
74module_param_named(debug, debug.msg_enable, int, 0);
75MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
76
18a8e864 77static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 78 .uf_info = {
79 .bd_mem_part = MEM_PART_SYSTEM,
80 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
81 .max_rx_buf_length = 1536,
728de4c9 82 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 83 .urfs = UCC_GETH_URFS_INIT,
84 .urfet = UCC_GETH_URFET_INIT,
85 .urfset = UCC_GETH_URFSET_INIT,
86 .utfs = UCC_GETH_UTFS_INIT,
87 .utfet = UCC_GETH_UTFET_INIT,
88 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 89 .ufpt = 256,
90 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
91 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
92 .tenc = UCC_FAST_TX_ENCODING_NRZ,
93 .renc = UCC_FAST_RX_ENCODING_NRZ,
94 .tcrc = UCC_FAST_16_BIT_CRC,
95 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
96 },
97 .numQueuesTx = 1,
98 .numQueuesRx = 1,
99 .extendedFilteringChainPointer = ((uint32_t) NULL),
100 .typeorlen = 3072 /*1536 */ ,
101 .nonBackToBackIfgPart1 = 0x40,
102 .nonBackToBackIfgPart2 = 0x60,
103 .miminumInterFrameGapEnforcement = 0x50,
104 .backToBackInterFrameGap = 0x60,
105 .mblinterval = 128,
106 .nortsrbytetime = 5,
107 .fracsiz = 1,
108 .strictpriorityq = 0xff,
109 .altBebTruncation = 0xa,
110 .excessDefer = 1,
111 .maxRetransmission = 0xf,
112 .collisionWindow = 0x37,
113 .receiveFlowControl = 1,
ac421852 114 .transmitFlowControl = 1,
ce973b14
LY		 115 .maxGroupAddrInHash = 4,
116 .maxIndAddrInHash = 4,
117 .prel = 7,
70f8002d 118 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
ce973b14 119 .minFrameLength = 64,
70f8002d
JT		 120 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
121 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
ce973b14
LY		 122 .vlantype = 0x8100,
123 .ecamptr = ((uint32_t) NULL),
124 .eventRegMask = UCCE_OTHER,
125 .pausePeriod = 0xf000,
126 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
127 .bdRingLenTx = {
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN,
135 TX_BD_RING_LEN},
136
137 .bdRingLenRx = {
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN,
145 RX_BD_RING_LEN},
146
147 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
148 .largestexternallookupkeysize =
149 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 150 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
152 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 153 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
154 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
155 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
156 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
157 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 158 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
159 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 160 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
162};
163
18a8e864 164static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 165
166#ifdef DEBUG
167static void mem_disp(u8 *addr, int size)
168{
169 u8 *i;
170 int size16Aling = (size >> 4) << 4;
171 int size4Aling = (size >> 2) << 2;
172 int notAlign = 0;
173 if (size % 16)
174 notAlign = 1;
175
176 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
177 printk("0x%08x: %08x %08x %08x %08x\r\n",
178 (u32) i,
179 *((u32 *) (i)),
180 *((u32 *) (i + 4)),
181 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
182 if (notAlign == 1)
183 printk("0x%08x: ", (u32) i);
184 for (; (u32) i < (u32) addr + size4Aling; i += 4)
185 printk("%08x ", *((u32 *) (i)));
186 for (; (u32) i < (u32) addr + size; i++)
64699336 187 printk("%02x", *((i)));
ce973b14
LY		 188 if (notAlign == 1)
189 printk("\r\n");
190}
191#endif /* DEBUG */
192
ce973b14
LY		 193static struct list_head *dequeue(struct list_head *lh)
194{
195 unsigned long flags;
196
1083cfe1 197 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 198 if (!list_empty(lh)) {
199 struct list_head *node = lh->next;
200 list_del(node);
1083cfe1 201 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 202 return node;
203 } else {
1083cfe1 204 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 205 return NULL;
206 }
207}
208
6fee40e9
AF		 209static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
210 u8 __iomem *bd)
ce973b14
LY		 211{
212 struct sk_buff *skb = NULL;
213
50f238fd
AV		 214 skb = __skb_dequeue(&ugeth->rx_recycle);
215 if (!skb)
21a4e469
PD		 216 skb = netdev_alloc_skb(ugeth->ndev,
217 ugeth->ug_info->uf_info.max_rx_buf_length +
218 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
ce973b14
LY		 219 if (skb == NULL)
220 return NULL;
221
222 /* We need the data buffer to be aligned properly. We will reserve
223 * as many bytes as needed to align the data properly
224 */
225 skb_reserve(skb,
226 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
227 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
228 1)));
229
6fee40e9 230 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 231 dma_map_single(ugeth->dev,
ce973b14
LY		 232 skb->data,
233 ugeth->ug_info->uf_info.max_rx_buf_length +
234 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
235 DMA_FROM_DEVICE));
236
6fee40e9
AF		 237 out_be32((u32 __iomem *)bd,
238 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 239
240 return skb;
241}
242
18a8e864 243static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 244{
6fee40e9 245 u8 __iomem *bd;
ce973b14
LY		 246 u32 bd_status;
247 struct sk_buff *skb;
248 int i;
249
250 bd = ugeth->p_rx_bd_ring[rxQ];
251 i = 0;
252
253 do {
6fee40e9 254 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 255 skb = get_new_skb(ugeth, bd);
256
257 if (!skb) /* If can not allocate data buffer,
258 abort. Cleanup will be elsewhere */
259 return -ENOMEM;
260
261 ugeth->rx_skbuff[rxQ][i] = skb;
262
263 /* advance the BD pointer */
18a8e864 264 bd += sizeof(struct qe_bd);
ce973b14
LY		 265 i++;
266 } while (!(bd_status & R_W));
267
268 return 0;
269}
270
18a8e864 271static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 272 u32 *p_start,
ce973b14
LY		 273 u8 num_entries,
274 u32 thread_size,
275 u32 thread_alignment,
345f8422 276 unsigned int risc,
ce973b14
LY		 277 int skip_page_for_first_entry)
278{
279 u32 init_enet_offset;
280 u8 i;
281 int snum;
282
283 for (i = 0; i < num_entries; i++) {
284 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 285 if (netif_msg_ifup(ugeth))
286 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 287 return snum;
288 }
289 if ((i == 0) && skip_page_for_first_entry)
290 /* First entry of Rx does not have page */
291 init_enet_offset = 0;
292 else {
293 init_enet_offset =
294 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 295 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 296 if (netif_msg_ifup(ugeth))
297 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 298 qe_put_snum((u8) snum);
299 return -ENOMEM;
300 }
301 }
302 *(p_start++) =
303 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
304 | risc;
305 }
306
307 return 0;
308}
309
18a8e864 310static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 311 u32 *p_start,
ce973b14 312 u8 num_entries,
345f8422 313 unsigned int risc,
ce973b14
LY		 314 int skip_page_for_first_entry)
315{
316 u32 init_enet_offset;
317 u8 i;
318 int snum;
319
320 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 321 u32 val = *p_start;
322
ce973b14
LY		 323 /* Check that this entry was actually valid --
324 needed in case failed in allocations */
6fee40e9 325 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 326 snum =
6fee40e9 327 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 328 ENET_INIT_PARAM_SNUM_SHIFT;
329 qe_put_snum((u8) snum);
330 if (!((i == 0) && skip_page_for_first_entry)) {
331 /* First entry of Rx does not have page */
332 init_enet_offset =
6fee40e9 333 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 334 qe_muram_free(init_enet_offset);
335 }
6fee40e9 336 *p_start++ = 0;
ce973b14
LY		 337 }
338 }
339
340 return 0;
341}
342
343#ifdef DEBUG
18a8e864 344static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 345 u32 __iomem *p_start,
ce973b14
LY		 346 u8 num_entries,
347 u32 thread_size,
345f8422 348 unsigned int risc,
ce973b14
LY		 349 int skip_page_for_first_entry)
350{
351 u32 init_enet_offset;
352 u8 i;
353 int snum;
354
355 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 356 u32 val = in_be32(p_start);
357
ce973b14
LY		 358 /* Check that this entry was actually valid --
359 needed in case failed in allocations */
6fee40e9 360 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 361 snum =
6fee40e9 362 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 363 ENET_INIT_PARAM_SNUM_SHIFT;
364 qe_put_snum((u8) snum);
365 if (!((i == 0) && skip_page_for_first_entry)) {
366 /* First entry of Rx does not have page */
367 init_enet_offset =
368 (in_be32(p_start) &
369 ENET_INIT_PARAM_PTR_MASK);
370 ugeth_info("Init enet entry %d:", i);
371 ugeth_info("Base address: 0x%08x",
372 (u32)
373 qe_muram_addr(init_enet_offset));
374 mem_disp(qe_muram_addr(init_enet_offset),
375 thread_size);
376 }
377 p_start++;
378 }
379 }
380
381 return 0;
382}
383#endif
384
18a8e864 385static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 386{
387 kfree(enet_addr_cont);
388}
389
df19b6b0 390static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 391{
392 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
393 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
394 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
395}
396
18a8e864 397static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 398{
6fee40e9 399 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 400
401 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 402 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 403 return -EINVAL;
404 }
405
406 p_82xx_addr_filt =
6fee40e9 407 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 408 addressfiltering;
409
410 /* Writing address ff.ff.ff.ff.ff.ff disables address
411 recognition for this register */
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
414 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
415
416 return 0;
417}
418
18a8e864
LY		 419static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
420 u8 *p_enet_addr)
ce973b14 421{
6fee40e9 422 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 423 u32 cecr_subblock;
424
425 p_82xx_addr_filt =
6fee40e9 426 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 427 addressfiltering;
428
429 cecr_subblock =
430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
431
432 /* Ethernet frames are defined in Little Endian mode,
3ad2f3fb 433 therefore to insert */
ce973b14 434 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 435
436 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 437
438 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 439 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 440}
441
18a8e864 442static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14 443{
b721e253 444 return memcmp(addr1, addr2, ETH_ALEN);
ce973b14
LY		 445}
446
447#ifdef DEBUG
18a8e864
LY		 448static void get_statistics(struct ucc_geth_private *ugeth,
449 struct ucc_geth_tx_firmware_statistics *
ce973b14 450 tx_firmware_statistics,
18a8e864 451 struct ucc_geth_rx_firmware_statistics *
ce973b14 452 rx_firmware_statistics,
18a8e864 453 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 454{
6fee40e9
AF		 455 struct ucc_fast __iomem *uf_regs;
456 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 457 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
458 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 459
460 ug_regs = ugeth->ug_regs;
6fee40e9 461 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 462 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
463 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
464
465 /* Tx firmware only if user handed pointer and driver actually
466 gathers Tx firmware statistics */
467 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
468 tx_firmware_statistics->sicoltx =
469 in_be32(&p_tx_fw_statistics_pram->sicoltx);
470 tx_firmware_statistics->mulcoltx =
471 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
472 tx_firmware_statistics->latecoltxfr =
473 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
474 tx_firmware_statistics->frabortduecol =
475 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
476 tx_firmware_statistics->frlostinmactxer =
477 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
478 tx_firmware_statistics->carriersenseertx =
479 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
480 tx_firmware_statistics->frtxok =
481 in_be32(&p_tx_fw_statistics_pram->frtxok);
482 tx_firmware_statistics->txfrexcessivedefer =
483 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
484 tx_firmware_statistics->txpkts256 =
485 in_be32(&p_tx_fw_statistics_pram->txpkts256);
486 tx_firmware_statistics->txpkts512 =
487 in_be32(&p_tx_fw_statistics_pram->txpkts512);
488 tx_firmware_statistics->txpkts1024 =
489 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
490 tx_firmware_statistics->txpktsjumbo =
491 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
492 }
493
494 /* Rx firmware only if user handed pointer and driver actually
495 * gathers Rx firmware statistics */
496 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
497 int i;
498 rx_firmware_statistics->frrxfcser =
499 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
500 rx_firmware_statistics->fraligner =
501 in_be32(&p_rx_fw_statistics_pram->fraligner);
502 rx_firmware_statistics->inrangelenrxer =
503 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
504 rx_firmware_statistics->outrangelenrxer =
505 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
506 rx_firmware_statistics->frtoolong =
507 in_be32(&p_rx_fw_statistics_pram->frtoolong);
508 rx_firmware_statistics->runt =
509 in_be32(&p_rx_fw_statistics_pram->runt);
510 rx_firmware_statistics->verylongevent =
511 in_be32(&p_rx_fw_statistics_pram->verylongevent);
512 rx_firmware_statistics->symbolerror =
513 in_be32(&p_rx_fw_statistics_pram->symbolerror);
514 rx_firmware_statistics->dropbsy =
515 in_be32(&p_rx_fw_statistics_pram->dropbsy);
516 for (i = 0; i < 0x8; i++)
517 rx_firmware_statistics->res0[i] =
518 p_rx_fw_statistics_pram->res0[i];
519 rx_firmware_statistics->mismatchdrop =
520 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
521 rx_firmware_statistics->underpkts =
522 in_be32(&p_rx_fw_statistics_pram->underpkts);
523 rx_firmware_statistics->pkts256 =
524 in_be32(&p_rx_fw_statistics_pram->pkts256);
525 rx_firmware_statistics->pkts512 =
526 in_be32(&p_rx_fw_statistics_pram->pkts512);
527 rx_firmware_statistics->pkts1024 =
528 in_be32(&p_rx_fw_statistics_pram->pkts1024);
529 rx_firmware_statistics->pktsjumbo =
530 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
531 rx_firmware_statistics->frlossinmacer =
532 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
533 rx_firmware_statistics->pausefr =
534 in_be32(&p_rx_fw_statistics_pram->pausefr);
535 for (i = 0; i < 0x4; i++)
536 rx_firmware_statistics->res1[i] =
537 p_rx_fw_statistics_pram->res1[i];
538 rx_firmware_statistics->removevlan =
539 in_be32(&p_rx_fw_statistics_pram->removevlan);
540 rx_firmware_statistics->replacevlan =
541 in_be32(&p_rx_fw_statistics_pram->replacevlan);
542 rx_firmware_statistics->insertvlan =
543 in_be32(&p_rx_fw_statistics_pram->insertvlan);
544 }
545
546 /* Hardware only if user handed pointer and driver actually
547 gathers hardware statistics */
3bc53427
TT		 548 if (hardware_statistics &&
549 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 550 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
551 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
552 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
553 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
554 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
555 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
556 hardware_statistics->txok = in_be32(&ug_regs->txok);
557 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
558 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
559 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
560 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
561 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
562 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
563 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
564 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
565 }
566}
567
18a8e864 568static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 569{
570 int i;
571 int length;
572
573 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
574 if (ugeth->p_tx_bd_ring[i]) {
575 length =
576 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 577 sizeof(struct qe_bd));
ce973b14
LY		 578 ugeth_info("TX BDs[%d]", i);
579 mem_disp(ugeth->p_tx_bd_ring[i], length);
580 }
581 }
582 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
583 if (ugeth->p_rx_bd_ring[i]) {
584 length =
585 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 586 sizeof(struct qe_bd));
ce973b14
LY		 587 ugeth_info("RX BDs[%d]", i);
588 mem_disp(ugeth->p_rx_bd_ring[i], length);
589 }
590 }
591}
592
18a8e864 593static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 594{
595 int i;
596
3ac37746 597 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1);
ce973b14
LY		 598 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
599
600 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
601 (u32) & ugeth->ug_regs->maccfg1,
602 in_be32(&ugeth->ug_regs->maccfg1));
603 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
604 (u32) & ugeth->ug_regs->maccfg2,
605 in_be32(&ugeth->ug_regs->maccfg2));
606 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
607 (u32) & ugeth->ug_regs->ipgifg,
608 in_be32(&ugeth->ug_regs->ipgifg));
609 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
610 (u32) & ugeth->ug_regs->hafdup,
611 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 612 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
613 (u32) & ugeth->ug_regs->ifctl,
614 in_be32(&ugeth->ug_regs->ifctl));
615 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
616 (u32) & ugeth->ug_regs->ifstat,
617 in_be32(&ugeth->ug_regs->ifstat));
618 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
619 (u32) & ugeth->ug_regs->macstnaddr1,
620 in_be32(&ugeth->ug_regs->macstnaddr1));
621 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
622 (u32) & ugeth->ug_regs->macstnaddr2,
623 in_be32(&ugeth->ug_regs->macstnaddr2));
624 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
625 (u32) & ugeth->ug_regs->uempr,
626 in_be32(&ugeth->ug_regs->uempr));
627 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
628 (u32) & ugeth->ug_regs->utbipar,
629 in_be32(&ugeth->ug_regs->utbipar));
630 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
631 (u32) & ugeth->ug_regs->uescr,
632 in_be16(&ugeth->ug_regs->uescr));
633 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
634 (u32) & ugeth->ug_regs->tx64,
635 in_be32(&ugeth->ug_regs->tx64));
636 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
637 (u32) & ugeth->ug_regs->tx127,
638 in_be32(&ugeth->ug_regs->tx127));
639 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
640 (u32) & ugeth->ug_regs->tx255,
641 in_be32(&ugeth->ug_regs->tx255));
642 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
643 (u32) & ugeth->ug_regs->rx64,
644 in_be32(&ugeth->ug_regs->rx64));
645 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
646 (u32) & ugeth->ug_regs->rx127,
647 in_be32(&ugeth->ug_regs->rx127));
648 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
649 (u32) & ugeth->ug_regs->rx255,
650 in_be32(&ugeth->ug_regs->rx255));
651 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
652 (u32) & ugeth->ug_regs->txok,
653 in_be32(&ugeth->ug_regs->txok));
654 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
655 (u32) & ugeth->ug_regs->txcf,
656 in_be16(&ugeth->ug_regs->txcf));
657 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
658 (u32) & ugeth->ug_regs->tmca,
659 in_be32(&ugeth->ug_regs->tmca));
660 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
661 (u32) & ugeth->ug_regs->tbca,
662 in_be32(&ugeth->ug_regs->tbca));
663 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
664 (u32) & ugeth->ug_regs->rxfok,
665 in_be32(&ugeth->ug_regs->rxfok));
666 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
667 (u32) & ugeth->ug_regs->rxbok,
668 in_be32(&ugeth->ug_regs->rxbok));
669 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
670 (u32) & ugeth->ug_regs->rbyt,
671 in_be32(&ugeth->ug_regs->rbyt));
672 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
673 (u32) & ugeth->ug_regs->rmca,
674 in_be32(&ugeth->ug_regs->rmca));
675 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
676 (u32) & ugeth->ug_regs->rbca,
677 in_be32(&ugeth->ug_regs->rbca));
678 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
679 (u32) & ugeth->ug_regs->scar,
680 in_be32(&ugeth->ug_regs->scar));
681 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
682 (u32) & ugeth->ug_regs->scam,
683 in_be32(&ugeth->ug_regs->scam));
684
685 if (ugeth->p_thread_data_tx) {
686 int numThreadsTxNumerical;
687 switch (ugeth->ug_info->numThreadsTx) {
688 case UCC_GETH_NUM_OF_THREADS_1:
689 numThreadsTxNumerical = 1;
690 break;
691 case UCC_GETH_NUM_OF_THREADS_2:
692 numThreadsTxNumerical = 2;
693 break;
694 case UCC_GETH_NUM_OF_THREADS_4:
695 numThreadsTxNumerical = 4;
696 break;
697 case UCC_GETH_NUM_OF_THREADS_6:
698 numThreadsTxNumerical = 6;
699 break;
700 case UCC_GETH_NUM_OF_THREADS_8:
701 numThreadsTxNumerical = 8;
702 break;
703 default:
704 numThreadsTxNumerical = 0;
705 break;
706 }
707
708 ugeth_info("Thread data TXs:");
709 ugeth_info("Base address: 0x%08x",
710 (u32) ugeth->p_thread_data_tx);
711 for (i = 0; i < numThreadsTxNumerical; i++) {
712 ugeth_info("Thread data TX[%d]:", i);
713 ugeth_info("Base address: 0x%08x",
714 (u32) & ugeth->p_thread_data_tx[i]);
715 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 716 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 717 }
718 }
719 if (ugeth->p_thread_data_rx) {
720 int numThreadsRxNumerical;
721 switch (ugeth->ug_info->numThreadsRx) {
722 case UCC_GETH_NUM_OF_THREADS_1:
723 numThreadsRxNumerical = 1;
724 break;
725 case UCC_GETH_NUM_OF_THREADS_2:
726 numThreadsRxNumerical = 2;
727 break;
728 case UCC_GETH_NUM_OF_THREADS_4:
729 numThreadsRxNumerical = 4;
730 break;
731 case UCC_GETH_NUM_OF_THREADS_6:
732 numThreadsRxNumerical = 6;
733 break;
734 case UCC_GETH_NUM_OF_THREADS_8:
735 numThreadsRxNumerical = 8;
736 break;
737 default:
738 numThreadsRxNumerical = 0;
739 break;
740 }
741
742 ugeth_info("Thread data RX:");
743 ugeth_info("Base address: 0x%08x",
744 (u32) ugeth->p_thread_data_rx);
745 for (i = 0; i < numThreadsRxNumerical; i++) {
746 ugeth_info("Thread data RX[%d]:", i);
747 ugeth_info("Base address: 0x%08x",
748 (u32) & ugeth->p_thread_data_rx[i]);
749 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 750 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 751 }
752 }
753 if (ugeth->p_exf_glbl_param) {
754 ugeth_info("EXF global param:");
755 ugeth_info("Base address: 0x%08x",
756 (u32) ugeth->p_exf_glbl_param);
757 mem_disp((u8 *) ugeth->p_exf_glbl_param,
758 sizeof(*ugeth->p_exf_glbl_param));
759 }
760 if (ugeth->p_tx_glbl_pram) {
761 ugeth_info("TX global param:");
762 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
763 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
764 (u32) & ugeth->p_tx_glbl_pram->temoder,
765 in_be16(&ugeth->p_tx_glbl_pram->temoder));
766 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
767 (u32) & ugeth->p_tx_glbl_pram->sqptr,
768 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
769 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
770 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
771 in_be32(&ugeth->p_tx_glbl_pram->
772 schedulerbasepointer));
773 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
774 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
775 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
776 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
777 (u32) & ugeth->p_tx_glbl_pram->tstate,
778 in_be32(&ugeth->p_tx_glbl_pram->tstate));
779 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
780 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
781 ugeth->p_tx_glbl_pram->iphoffset[0]);
782 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
783 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
784 ugeth->p_tx_glbl_pram->iphoffset[1]);
785 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
786 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
787 ugeth->p_tx_glbl_pram->iphoffset[2]);
788 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
789 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
790 ugeth->p_tx_glbl_pram->iphoffset[3]);
791 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
792 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
793 ugeth->p_tx_glbl_pram->iphoffset[4]);
794 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
795 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
796 ugeth->p_tx_glbl_pram->iphoffset[5]);
797 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
798 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
799 ugeth->p_tx_glbl_pram->iphoffset[6]);
800 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
801 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
802 ugeth->p_tx_glbl_pram->iphoffset[7]);
803 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
804 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
806 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
807 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
809 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
810 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
812 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
813 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
815 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
816 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
817 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
818 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
819 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
820 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
821 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
822 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
823 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
824 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
825 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
826 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
827 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
828 (u32) & ugeth->p_tx_glbl_pram->tqptr,
829 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
830 }
831 if (ugeth->p_rx_glbl_pram) {
832 ugeth_info("RX global param:");
833 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
834 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
835 (u32) & ugeth->p_rx_glbl_pram->remoder,
836 in_be32(&ugeth->p_rx_glbl_pram->remoder));
837 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
838 (u32) & ugeth->p_rx_glbl_pram->rqptr,
839 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
840 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
841 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
842 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
843 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
844 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
845 ugeth->p_rx_glbl_pram->rxgstpack);
846 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
847 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
848 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
849 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
850 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
851 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
852 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
853 (u32) & ugeth->p_rx_glbl_pram->rstate,
854 ugeth->p_rx_glbl_pram->rstate);
855 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
856 (u32) & ugeth->p_rx_glbl_pram->mrblr,
857 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
858 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
859 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
860 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
861 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
862 (u32) & ugeth->p_rx_glbl_pram->mflr,
863 in_be16(&ugeth->p_rx_glbl_pram->mflr));
864 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
865 (u32) & ugeth->p_rx_glbl_pram->minflr,
866 in_be16(&ugeth->p_rx_glbl_pram->minflr));
867 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
868 (u32) & ugeth->p_rx_glbl_pram->maxd1,
869 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
870 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
871 (u32) & ugeth->p_rx_glbl_pram->maxd2,
872 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
873 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
874 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
875 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
876 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
877 (u32) & ugeth->p_rx_glbl_pram->l2qt,
878 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
879 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
880 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
882 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
883 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
885 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
886 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
888 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
889 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
891 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
892 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
893 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
894 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
895 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
896 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
897 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
898 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
899 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
900 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
901 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
902 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
903 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
904 (u32) & ugeth->p_rx_glbl_pram->vlantype,
905 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
906 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
907 (u32) & ugeth->p_rx_glbl_pram->vlantci,
908 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
909 for (i = 0; i < 64; i++)
910 ugeth_info
911 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
912 i,
913 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
914 ugeth->p_rx_glbl_pram->addressfiltering[i]);
915 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
916 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
917 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
918 }
919 if (ugeth->p_send_q_mem_reg) {
920 ugeth_info("Send Q memory registers:");
921 ugeth_info("Base address: 0x%08x",
922 (u32) ugeth->p_send_q_mem_reg);
923 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
924 ugeth_info("SQQD[%d]:", i);
925 ugeth_info("Base address: 0x%08x",
926 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
927 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 928 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 929 }
930 }
931 if (ugeth->p_scheduler) {
932 ugeth_info("Scheduler:");
933 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
934 mem_disp((u8 *) ugeth->p_scheduler,
935 sizeof(*ugeth->p_scheduler));
936 }
937 if (ugeth->p_tx_fw_statistics_pram) {
938 ugeth_info("TX FW statistics pram:");
939 ugeth_info("Base address: 0x%08x",
940 (u32) ugeth->p_tx_fw_statistics_pram);
941 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
942 sizeof(*ugeth->p_tx_fw_statistics_pram));
943 }
944 if (ugeth->p_rx_fw_statistics_pram) {
945 ugeth_info("RX FW statistics pram:");
946 ugeth_info("Base address: 0x%08x",
947 (u32) ugeth->p_rx_fw_statistics_pram);
948 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
949 sizeof(*ugeth->p_rx_fw_statistics_pram));
950 }
951 if (ugeth->p_rx_irq_coalescing_tbl) {
952 ugeth_info("RX IRQ coalescing tables:");
953 ugeth_info("Base address: 0x%08x",
954 (u32) ugeth->p_rx_irq_coalescing_tbl);
955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
956 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
957 ugeth_info("Base address: 0x%08x",
958 (u32) & ugeth->p_rx_irq_coalescing_tbl->
959 coalescingentry[i]);
960 ugeth_info
961 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
962 (u32) & ugeth->p_rx_irq_coalescing_tbl->
963 coalescingentry[i].interruptcoalescingmaxvalue,
964 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
965 coalescingentry[i].
966 interruptcoalescingmaxvalue));
967 ugeth_info
968 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
969 (u32) & ugeth->p_rx_irq_coalescing_tbl->
970 coalescingentry[i].interruptcoalescingcounter,
971 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
972 coalescingentry[i].
973 interruptcoalescingcounter));
974 }
975 }
976 if (ugeth->p_rx_bd_qs_tbl) {
977 ugeth_info("RX BD QS tables:");
978 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
979 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
980 ugeth_info("RX BD QS table[%d]:", i);
981 ugeth_info("Base address: 0x%08x",
982 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
983 ugeth_info
984 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
985 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
986 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
987 ugeth_info
988 ("bdptr : addr - 0x%08x, val - 0x%08x",
989 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
990 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
991 ugeth_info
992 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
993 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
994 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
995 externalbdbaseptr));
996 ugeth_info
997 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
998 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
999 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1000 ugeth_info("ucode RX Prefetched BDs:");
1001 ugeth_info("Base address: 0x%08x",
1002 (u32)
1003 qe_muram_addr(in_be32
1004 (&ugeth->p_rx_bd_qs_tbl[i].
1005 bdbaseptr)));
1006 mem_disp((u8 *)
1007 qe_muram_addr(in_be32
1008 (&ugeth->p_rx_bd_qs_tbl[i].
1009 bdbaseptr)),
18a8e864 1010 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1011 }
1012 }
1013 if (ugeth->p_init_enet_param_shadow) {
1014 int size;
1015 ugeth_info("Init enet param shadow:");
1016 ugeth_info("Base address: 0x%08x",
1017 (u32) ugeth->p_init_enet_param_shadow);
1018 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1019 sizeof(*ugeth->p_init_enet_param_shadow));
1020
18a8e864 1021 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1022 if (ugeth->ug_info->rxExtendedFiltering) {
1023 size +=
1024 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1025 if (ugeth->ug_info->largestexternallookupkeysize ==
1026 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1027 size +=
1028 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1029 if (ugeth->ug_info->largestexternallookupkeysize ==
1030 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1031 size +=
1032 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1033 }
1034
1035 dump_init_enet_entries(ugeth,
1036 &(ugeth->p_init_enet_param_shadow->
1037 txthread[0]),
1038 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1039 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1040 ugeth->ug_info->riscTx, 0);
1041 dump_init_enet_entries(ugeth,
1042 &(ugeth->p_init_enet_param_shadow->
1043 rxthread[0]),
1044 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1045 ugeth->ug_info->riscRx, 1);
1046 }
1047}
1048#endif /* DEBUG */
1049
6fee40e9
AF		 1050static void init_default_reg_vals(u32 __iomem *upsmr_register,
1051 u32 __iomem *maccfg1_register,
1052 u32 __iomem *maccfg2_register)
ce973b14
LY		 1053{
1054 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1055 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1056 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1057}
1058
1059static int init_half_duplex_params(int alt_beb,
1060 int back_pressure_no_backoff,
1061 int no_backoff,
1062 int excess_defer,
1063 u8 alt_beb_truncation,
1064 u8 max_retransmissions,
1065 u8 collision_window,
6fee40e9 1066 u32 __iomem *hafdup_register)
ce973b14
LY		 1067{
1068 u32 value = 0;
1069
1070 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1071 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1072 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1073 return -EINVAL;
1074
1075 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1076
1077 if (alt_beb)
1078 value |= HALFDUP_ALT_BEB;
1079 if (back_pressure_no_backoff)
1080 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1081 if (no_backoff)
1082 value |= HALFDUP_NO_BACKOFF;
1083 if (excess_defer)
1084 value |= HALFDUP_EXCESSIVE_DEFER;
1085
1086 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1087
1088 value |= collision_window;
1089
1090 out_be32(hafdup_register, value);
1091 return 0;
1092}
1093
1094static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1095 u8 non_btb_ipg,
1096 u8 min_ifg,
1097 u8 btb_ipg,
6fee40e9 1098 u32 __iomem *ipgifg_register)
ce973b14
LY		 1099{
1100 u32 value = 0;
1101
1102 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1103 IPG part 2 */
1104 if (non_btb_cs_ipg > non_btb_ipg)
1105 return -EINVAL;
1106
1107 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1108 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1109 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1110 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1111 return -EINVAL;
1112
1113 value |=
1114 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1115 IPGIFG_NBTB_CS_IPG_MASK);
1116 value |=
1117 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1118 IPGIFG_NBTB_IPG_MASK);
1119 value |=
1120 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1121 IPGIFG_MIN_IFG_MASK);
1122 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1123
1124 out_be32(ipgifg_register, value);
1125 return 0;
1126}
1127
ac421852 1128int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1129 int rx_flow_control_enable,
1130 int tx_flow_control_enable,
1131 u16 pause_period,
1132 u16 extension_field,
6fee40e9
AF		 1133 u32 __iomem *upsmr_register,
1134 u32 __iomem *uempr_register,
1135 u32 __iomem *maccfg1_register)
ce973b14
LY		 1136{
1137 u32 value = 0;
1138
1139 /* Set UEMPR register */
1140 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1141 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1142 out_be32(uempr_register, value);
1143
1144 /* Set UPSMR register */
3bc53427 1145 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1146
1147 value = in_be32(maccfg1_register);
1148 if (rx_flow_control_enable)
1149 value |= MACCFG1_FLOW_RX;
1150 if (tx_flow_control_enable)
1151 value |= MACCFG1_FLOW_TX;
1152 out_be32(maccfg1_register, value);
1153
1154 return 0;
1155}
1156
1157static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1158 int auto_zero_hardware_statistics,
6fee40e9
AF		 1159 u32 __iomem *upsmr_register,
1160 u16 __iomem *uescr_register)
ce973b14 1161{
ce973b14 1162 u16 uescr_value = 0;
3bc53427 1163
ce973b14 1164 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1165 if (enable_hardware_statistics)
1166 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1167
1168 /* Clear hardware statistics counters */
1169 uescr_value = in_be16(uescr_register);
1170 uescr_value |= UESCR_CLRCNT;
1171 /* Automatically zero hardware statistics counters on read,
1172 if requested */
1173 if (auto_zero_hardware_statistics)
1174 uescr_value |= UESCR_AUTOZ;
1175 out_be16(uescr_register, uescr_value);
1176
1177 return 0;
1178}
1179
1180static int init_firmware_statistics_gathering_mode(int
1181 enable_tx_firmware_statistics,
1182 int enable_rx_firmware_statistics,
6fee40e9 1183 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1184 u32 tx_firmware_statistics_structure_address,
6fee40e9 1185 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1186 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1187 u16 __iomem *temoder_register,
1188 u32 __iomem *remoder_register)
ce973b14
LY		 1189{
1190 /* Note: this function does not check if */
1191 /* the parameters it receives are NULL */
ce973b14
LY		 1192
1193 if (enable_tx_firmware_statistics) {
1194 out_be32(tx_rmon_base_ptr,
1195 tx_firmware_statistics_structure_address);
3bc53427 1196 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1197 }
1198
1199 if (enable_rx_firmware_statistics) {
1200 out_be32(rx_rmon_base_ptr,
1201 rx_firmware_statistics_structure_address);
3bc53427 1202 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1203 }
1204
1205 return 0;
1206}
1207
1208static int init_mac_station_addr_regs(u8 address_byte_0,
1209 u8 address_byte_1,
1210 u8 address_byte_2,
1211 u8 address_byte_3,
1212 u8 address_byte_4,
1213 u8 address_byte_5,
6fee40e9
AF		 1214 u32 __iomem *macstnaddr1_register,
1215 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1216{
1217 u32 value = 0;
1218
1219 /* Example: for a station address of 0x12345678ABCD, */
1220 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1221
1222 /* MACSTNADDR1 Register: */
1223
1224 /* 0 7 8 15 */
1225 /* station address byte 5 station address byte 4 */
1226 /* 16 23 24 31 */
1227 /* station address byte 3 station address byte 2 */
1228 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1229 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1230 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1231 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1232
1233 out_be32(macstnaddr1_register, value);
1234
1235 /* MACSTNADDR2 Register: */
1236
1237 /* 0 7 8 15 */
1238 /* station address byte 1 station address byte 0 */
1239 /* 16 23 24 31 */
1240 /* reserved reserved */
1241 value = 0;
1242 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1243 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1244
1245 out_be32(macstnaddr2_register, value);
1246
1247 return 0;
1248}
1249
ce973b14 1250static int init_check_frame_length_mode(int length_check,
6fee40e9 1251 u32 __iomem *maccfg2_register)
ce973b14
LY		 1252{
1253 u32 value = 0;
1254
1255 value = in_be32(maccfg2_register);
1256
1257 if (length_check)
1258 value |= MACCFG2_LC;
1259 else
1260 value &= ~MACCFG2_LC;
1261
1262 out_be32(maccfg2_register, value);
1263 return 0;
1264}
1265
1266static int init_preamble_length(u8 preamble_length,
6fee40e9 1267 u32 __iomem *maccfg2_register)
ce973b14 1268{
ce973b14
LY		 1269 if ((preamble_length < 3) || (preamble_length > 7))
1270 return -EINVAL;
1271
3bc53427
TT		 1272 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1273 preamble_length << MACCFG2_PREL_SHIFT);
1274
ce973b14
LY		 1275 return 0;
1276}
1277
ce973b14
LY		 1278static int init_rx_parameters(int reject_broadcast,
1279 int receive_short_frames,
6fee40e9 1280 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1281{
1282 u32 value = 0;
1283
1284 value = in_be32(upsmr_register);
1285
1286 if (reject_broadcast)
3bc53427 1287 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1288 else
3bc53427 1289 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1290
1291 if (receive_short_frames)
3bc53427 1292 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1293 else
3bc53427 1294 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1295
1296 if (promiscuous)
3bc53427 1297 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1298 else
3bc53427 1299 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1300
1301 out_be32(upsmr_register, value);
1302
1303 return 0;
1304}
1305
1306static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1307 u16 __iomem *mrblr_register)
ce973b14
LY		 1308{
1309 /* max_rx_buf_len value must be a multiple of 128 */
8e95a202
JP		 1310 if ((max_rx_buf_len == 0) ||
1311 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
ce973b14
LY		 1312 return -EINVAL;
1313
1314 out_be16(mrblr_register, max_rx_buf_len);
1315 return 0;
1316}
1317
1318static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1319 u16 __iomem *minflr_register,
1320 u16 __iomem *mrblr_register)
ce973b14
LY		 1321{
1322 u16 mrblr_value = 0;
1323
1324 mrblr_value = in_be16(mrblr_register);
1325 if (min_frame_length >= (mrblr_value - 4))
1326 return -EINVAL;
1327
1328 out_be16(minflr_register, min_frame_length);
1329 return 0;
1330}
1331
18a8e864 1332static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1333{
18a8e864 1334 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1335 struct ucc_geth __iomem *ug_regs;
1336 struct ucc_fast __iomem *uf_regs;
728de4c9 1337 int ret_val;
81abb43a 1338 u32 upsmr, maccfg2;
ce973b14
LY		 1339 u16 value;
1340
b39d66a8 1341 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1342
1343 ug_info = ugeth->ug_info;
1344 ug_regs = ugeth->ug_regs;
1345 uf_regs = ugeth->uccf->uf_regs;
1346
ce973b14
LY		 1347 /* Set MACCFG2 */
1348 maccfg2 = in_be32(&ug_regs->maccfg2);
1349 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1350 if ((ugeth->max_speed == SPEED_10) ||
1351 (ugeth->max_speed == SPEED_100))
ce973b14 1352 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1353 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1354 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1355 maccfg2 |= ug_info->padAndCrc;
1356 out_be32(&ug_regs->maccfg2, maccfg2);
1357
1358 /* Set UPSMR */
1359 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1360 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1361 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1362 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1367 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1368 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1369 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1370 switch (ugeth->max_speed) {
1371 case SPEED_10:
3bc53427 1372 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1373 /* FALLTHROUGH */
1374 case SPEED_100:
1375 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1376 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1377 }
1378 }
1379 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1380 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1381 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1382 }
047584ce
HW		 1383 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1384 upsmr |= UCC_GETH_UPSMR_SGMM;
1385
ce973b14
LY		 1386 out_be32(&uf_regs->upsmr, upsmr);
1387
ce973b14
LY		 1388 /* Disable autonegotiation in tbi mode, because by default it
1389 comes up in autonegotiation mode. */
1390 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1391 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1392 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
81abb43a
LYB		 1393 struct ucc_geth_info *ug_info = ugeth->ug_info;
1394 struct phy_device *tbiphy;
1395
1396 if (!ug_info->tbi_node)
1397 ugeth_warn("TBI mode requires that the device "
1398 "tree specify a tbi-handle\n");
1399
1400 tbiphy = of_phy_find_device(ug_info->tbi_node);
1401 if (!tbiphy)
1402 ugeth_warn("Could not get TBI device\n");
1403
1404 value = phy_read(tbiphy, ENET_TBI_MII_CR);
ce973b14 1405 value &= ~0x1000; /* Turn off autonegotiation */
81abb43a 1406 phy_write(tbiphy, ENET_TBI_MII_CR, value);
ce973b14
LY		 1407 }
1408
1409 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1410
1411 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1412 if (ret_val != 0) {
890de95e
LY		 1413 if (netif_msg_probe(ugeth))
1414 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1415 __func__);
ce973b14
LY		 1416 return ret_val;
1417 }
1418
1419 return 0;
1420}
1421
7de8ee78
AV		 1422static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1423{
1424 struct ucc_fast_private *uccf;
1425 u32 cecr_subblock;
1426 u32 temp;
1427 int i = 10;
1428
1429 uccf = ugeth->uccf;
1430
1431 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1432 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1433 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1434
1435 /* Issue host command */
1436 cecr_subblock =
1437 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1438 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1439 QE_CR_PROTOCOL_ETHERNET, 0);
1440
1441 /* Wait for command to complete */
1442 do {
1443 msleep(10);
1444 temp = in_be32(uccf->p_ucce);
1445 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1446
1447 uccf->stopped_tx = 1;
1448
1449 return 0;
1450}
1451
1452static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1453{
1454 struct ucc_fast_private *uccf;
1455 u32 cecr_subblock;
1456 u8 temp;
1457 int i = 10;
1458
1459 uccf = ugeth->uccf;
1460
1461 /* Clear acknowledge bit */
1462 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1463 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1464 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1465
1466 /* Keep issuing command and checking acknowledge bit until
1467 it is asserted, according to spec */
1468 do {
1469 /* Issue host command */
1470 cecr_subblock =
1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1472 ucc_num);
1473 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1474 QE_CR_PROTOCOL_ETHERNET, 0);
1475 msleep(10);
1476 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1477 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1478
1479 uccf->stopped_rx = 1;
1480
1481 return 0;
1482}
1483
1484static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1485{
1486 struct ucc_fast_private *uccf;
1487 u32 cecr_subblock;
1488
1489 uccf = ugeth->uccf;
1490
1491 cecr_subblock =
1492 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1493 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1494 uccf->stopped_tx = 0;
1495
1496 return 0;
1497}
1498
1499static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1500{
1501 struct ucc_fast_private *uccf;
1502 u32 cecr_subblock;
1503
1504 uccf = ugeth->uccf;
1505
1506 cecr_subblock =
1507 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1508 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1509 0);
1510 uccf->stopped_rx = 0;
1511
1512 return 0;
1513}
1514
1515static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1516{
1517 struct ucc_fast_private *uccf;
1518 int enabled_tx, enabled_rx;
1519
1520 uccf = ugeth->uccf;
1521
1522 /* check if the UCC number is in range. */
1523 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1524 if (netif_msg_probe(ugeth))
1525 ugeth_err("%s: ucc_num out of range.", __func__);
1526 return -EINVAL;
1527 }
1528
1529 enabled_tx = uccf->enabled_tx;
1530 enabled_rx = uccf->enabled_rx;
1531
1532 /* Get Tx and Rx going again, in case this channel was actively
1533 disabled. */
1534 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1535 ugeth_restart_tx(ugeth);
1536 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1537 ugeth_restart_rx(ugeth);
1538
1539 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1540
1541 return 0;
1542
1543}
1544
1545static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1546{
1547 struct ucc_fast_private *uccf;
1548
1549 uccf = ugeth->uccf;
1550
1551 /* check if the UCC number is in range. */
1552 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1553 if (netif_msg_probe(ugeth))
1554 ugeth_err("%s: ucc_num out of range.", __func__);
1555 return -EINVAL;
1556 }
1557
1558 /* Stop any transmissions */
1559 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1560 ugeth_graceful_stop_tx(ugeth);
1561
1562 /* Stop any receptions */
1563 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1564 ugeth_graceful_stop_rx(ugeth);
1565
1566 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1567
1568 return 0;
1569}
1570
864fdf88
AV		 1571static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1572{
08b5e1c9
AV		 1573 /* Prevent any further xmits, plus detach the device. */
1574 netif_device_detach(ugeth->ndev);
1575
1576 /* Wait for any current xmits to finish. */
864fdf88
AV		 1577 netif_tx_disable(ugeth->ndev);
1578
1579 /* Disable the interrupt to avoid NAPI rescheduling. */
1580 disable_irq(ugeth->ug_info->uf_info.irq);
1581
1582 /* Stop NAPI, and possibly wait for its completion. */
1583 napi_disable(&ugeth->napi);
1584}
1585
1586static void ugeth_activate(struct ucc_geth_private *ugeth)
1587{
1588 napi_enable(&ugeth->napi);
1589 enable_irq(ugeth->ug_info->uf_info.irq);
08b5e1c9 1590 netif_device_attach(ugeth->ndev);
864fdf88
AV		 1591}
1592
ce973b14
LY		 1593/* Called every time the controller might need to be made
1594 * aware of new link state. The PHY code conveys this
1595 * information through variables in the ugeth structure, and this
1596 * function converts those variables into the appropriate
1597 * register values, and can bring down the device if needed.
1598 */
728de4c9 1599
ce973b14
LY		 1600static void adjust_link(struct net_device *dev)
1601{
18a8e864 1602 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1603 struct ucc_geth __iomem *ug_regs;
1604 struct ucc_fast __iomem *uf_regs;
728de4c9 1605 struct phy_device *phydev = ugeth->phydev;
728de4c9 1606 int new_state = 0;
ce973b14
LY		 1607
1608 ug_regs = ugeth->ug_regs;
728de4c9 1609 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1610
728de4c9
KP		 1611 if (phydev->link) {
1612 u32 tempval = in_be32(&ug_regs->maccfg2);
1613 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1614 /* Now we make sure that we can be in full duplex mode.
1615 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1616 if (phydev->duplex != ugeth->oldduplex) {
1617 new_state = 1;
1618 if (!(phydev->duplex))
ce973b14 1619 tempval &= ~(MACCFG2_FDX);
728de4c9 1620 else
ce973b14 1621 tempval |= MACCFG2_FDX;
728de4c9 1622 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1623 }
1624
728de4c9
KP		 1625 if (phydev->speed != ugeth->oldspeed) {
1626 new_state = 1;
1627 switch (phydev->speed) {
1628 case SPEED_1000:
1629 tempval = ((tempval &
1630 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1631 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1632 break;
728de4c9
KP		 1633 case SPEED_100:
1634 case SPEED_10:
1635 tempval = ((tempval &
1636 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1637 MACCFG2_INTERFACE_MODE_NIBBLE);
1638 /* if reduced mode, re-set UPSMR.R10M */
1639 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1640 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1641 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1642 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1643 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1644 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1645 if (phydev->speed == SPEED_10)
3bc53427 1646 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1647 else
3bc53427 1648 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1649 }
ce973b14
LY		 1650 break;
1651 default:
728de4c9
KP		 1652 if (netif_msg_link(ugeth))
1653 ugeth_warn(
1654 "%s: Ack! Speed (%d) is not 10/100/1000!",
1655 dev->name, phydev->speed);
ce973b14
LY		 1656 break;
1657 }
728de4c9 1658 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1659 }
1660
1661 if (!ugeth->oldlink) {
728de4c9 1662 new_state = 1;
ce973b14 1663 ugeth->oldlink = 1;
ce973b14 1664 }
08fafd84
AV		 1665
1666 if (new_state) {
1667 /*
1668 * To change the MAC configuration we need to disable
1669 * the controller. To do so, we have to either grab
1670 * ugeth->lock, which is a bad idea since 'graceful
1671 * stop' commands might take quite a while, or we can
1672 * quiesce driver's activity.
1673 */
1674 ugeth_quiesce(ugeth);
1675 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1676
1677 out_be32(&ug_regs->maccfg2, tempval);
1678 out_be32(&uf_regs->upsmr, upsmr);
1679
1680 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1681 ugeth_activate(ugeth);
1682 }
728de4c9
KP		 1683 } else if (ugeth->oldlink) {
1684 new_state = 1;
ce973b14
LY		 1685 ugeth->oldlink = 0;
1686 ugeth->oldspeed = 0;
1687 ugeth->oldduplex = -1;
ce973b14 1688 }
728de4c9
KP		 1689
1690 if (new_state && netif_msg_link(ugeth))
1691 phy_print_status(phydev);
ce973b14
LY		 1692}
1693
fb1001f3
HW		 1694/* Initialize TBI PHY interface for communicating with the
1695 * SERDES lynx PHY on the chip. We communicate with this PHY
1696 * through the MDIO bus on each controller, treating it as a
1697 * "normal" PHY at the address found in the UTBIPA register. We assume
1698 * that the UTBIPA register is valid. Either the MDIO bus code will set
1699 * it to a value that doesn't conflict with other PHYs on the bus, or the
1700 * value doesn't matter, as there are no other PHYs on the bus.
1701 */
1702static void uec_configure_serdes(struct net_device *dev)
1703{
1704 struct ucc_geth_private *ugeth = netdev_priv(dev);
1705 struct ucc_geth_info *ug_info = ugeth->ug_info;
1706 struct phy_device *tbiphy;
1707
1708 if (!ug_info->tbi_node) {
1709 dev_warn(&dev->dev, "SGMII mode requires that the device "
1710 "tree specify a tbi-handle\n");
1711 return;
1712 }
1713
1714 tbiphy = of_phy_find_device(ug_info->tbi_node);
1715 if (!tbiphy) {
1716 dev_err(&dev->dev, "error: Could not get TBI device\n");
1717 return;
1718 }
1719
1720 /*
1721 * If the link is already up, we must already be ok, and don't need to
1722 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1723 * everything for us? Resetting it takes the link down and requires
1724 * several seconds for it to come back.
1725 */
1726 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1727 return;
1728
1729 /* Single clk mode, mii mode off(for serdes communication) */
1730 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1731
1732 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1733
1734 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1735}
1736
ce973b14
LY		 1737/* Configure the PHY for dev.
1738 * returns 0 if success. -1 if failure
1739 */
1740static int init_phy(struct net_device *dev)
1741{
728de4c9 1742 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1743 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1744 struct phy_device *phydev;
ce973b14 1745
728de4c9
KP		 1746 priv->oldlink = 0;
1747 priv->oldspeed = 0;
1748 priv->oldduplex = -1;
ce973b14 1749
0b9da337
GL		 1750 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1751 priv->phy_interface);
3104a6ff
AV		 1752 if (!phydev)
1753 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1754 priv->phy_interface);
0b9da337 1755 if (!phydev) {
3104a6ff 1756 dev_err(&dev->dev, "Could not attach to PHY\n");
0b9da337 1757 return -ENODEV;
ce973b14
LY		 1758 }
1759
047584ce
HW		 1760 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1761 uec_configure_serdes(dev);
1762
bb24fd6a
JT		 1763 phydev->supported &= (SUPPORTED_MII |
1764 SUPPORTED_Autoneg |
1765 ADVERTISED_10baseT_Half |
1766 ADVERTISED_10baseT_Full |
1767 ADVERTISED_100baseT_Half |
1768 ADVERTISED_100baseT_Full);
ce973b14 1769
728de4c9
KP		 1770 if (priv->max_speed == SPEED_1000)
1771 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1772
728de4c9 1773 phydev->advertising = phydev->supported;
68dc44af 1774
728de4c9 1775 priv->phydev = phydev;
ce973b14
LY		 1776
1777 return 0;
ce973b14
LY		 1778}
1779
18a8e864 1780static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1781{
1782#ifdef DEBUG
1783 ucc_fast_dump_regs(ugeth->uccf);
1784 dump_regs(ugeth);
1785 dump_bds(ugeth);
1786#endif
1787}
1788
18a8e864 1789static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1790 ugeth,
18a8e864 1791 enum enet_addr_type
ce973b14
LY		 1792 enet_addr_type)
1793{
6fee40e9 1794 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1795 struct ucc_fast_private *uccf;
1796 enum comm_dir comm_dir;
ce973b14
LY		 1797 struct list_head *p_lh;
1798 u16 i, num;
6fee40e9
AF		 1799 u32 __iomem *addr_h;
1800 u32 __iomem *addr_l;
ce973b14
LY		 1801 u8 *p_counter;
1802
1803 uccf = ugeth->uccf;
1804
1805 p_82xx_addr_filt =
6fee40e9
AF		 1806 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1807 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1808
1809 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1810 addr_h = &(p_82xx_addr_filt->gaddr_h);
1811 addr_l = &(p_82xx_addr_filt->gaddr_l);
1812 p_lh = &ugeth->group_hash_q;
1813 p_counter = &(ugeth->numGroupAddrInHash);
1814 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1815 addr_h = &(p_82xx_addr_filt->iaddr_h);
1816 addr_l = &(p_82xx_addr_filt->iaddr_l);
1817 p_lh = &ugeth->ind_hash_q;
1818 p_counter = &(ugeth->numIndAddrInHash);
1819 } else
1820 return -EINVAL;
1821
1822 comm_dir = 0;
1823 if (uccf->enabled_tx)
1824 comm_dir |= COMM_DIR_TX;
1825 if (uccf->enabled_rx)
1826 comm_dir |= COMM_DIR_RX;
1827 if (comm_dir)
1828 ugeth_disable(ugeth, comm_dir);
1829
1830 /* Clear the hash table. */
1831 out_be32(addr_h, 0x00000000);
1832 out_be32(addr_l, 0x00000000);
1833
1834 if (!p_lh)
1835 return 0;
1836
1837 num = *p_counter;
1838
1839 /* Delete all remaining CQ elements */
1840 for (i = 0; i < num; i++)
1841 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1842
1843 *p_counter = 0;
1844
1845 if (comm_dir)
1846 ugeth_enable(ugeth, comm_dir);
1847
1848 return 0;
1849}
1850
18a8e864 1851static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1852 u8 paddr_num)
1853{
1854 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1855 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1856}
1857
e19a82c1
PG		 1858static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1859{
1860 struct ucc_geth_info *ug_info;
1861 struct ucc_fast_info *uf_info;
1862 u16 i, j;
1863 u8 __iomem *bd;
1864
1865
1866 ug_info = ugeth->ug_info;
1867 uf_info = &ug_info->uf_info;
1868
1869 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1870 if (ugeth->p_rx_bd_ring[i]) {
1871 /* Return existing data buffers in ring */
1872 bd = ugeth->p_rx_bd_ring[i];
1873 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1874 if (ugeth->rx_skbuff[i][j]) {
1875 dma_unmap_single(ugeth->dev,
1876 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1877 ugeth->ug_info->
1878 uf_info.max_rx_buf_length +
1879 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1880 DMA_FROM_DEVICE);
1881 dev_kfree_skb_any(
1882 ugeth->rx_skbuff[i][j]);
1883 ugeth->rx_skbuff[i][j] = NULL;
1884 }
1885 bd += sizeof(struct qe_bd);
1886 }
1887
1888 kfree(ugeth->rx_skbuff[i]);
1889
1890 if (ugeth->ug_info->uf_info.bd_mem_part ==
1891 MEM_PART_SYSTEM)
1892 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1893 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1894 MEM_PART_MURAM)
1895 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1896 ugeth->p_rx_bd_ring[i] = NULL;
1897 }
1898 }
1899
1900}
1901
1902static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
ce973b14 1903{
e19a82c1
PG		 1904 struct ucc_geth_info *ug_info;
1905 struct ucc_fast_info *uf_info;
ce973b14 1906 u16 i, j;
6fee40e9 1907 u8 __iomem *bd;
ce973b14 1908
e19a82c1
PG		 1909 ug_info = ugeth->ug_info;
1910 uf_info = &ug_info->uf_info;
1911
1912 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1913 bd = ugeth->p_tx_bd_ring[i];
1914 if (!bd)
1915 continue;
1916 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1917 if (ugeth->tx_skbuff[i][j]) {
1918 dma_unmap_single(ugeth->dev,
1919 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1920 (in_be32((u32 __iomem *)bd) &
1921 BD_LENGTH_MASK),
1922 DMA_TO_DEVICE);
1923 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1924 ugeth->tx_skbuff[i][j] = NULL;
1925 }
1926 }
1927
1928 kfree(ugeth->tx_skbuff[i]);
1929
1930 if (ugeth->p_tx_bd_ring[i]) {
1931 if (ugeth->ug_info->uf_info.bd_mem_part ==
1932 MEM_PART_SYSTEM)
1933 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1934 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1935 MEM_PART_MURAM)
1936 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1937 ugeth->p_tx_bd_ring[i] = NULL;
1938 }
1939 }
1940
1941}
1942
1943static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1944{
ce973b14
LY		 1945 if (!ugeth)
1946 return;
1947
80a9fad8 1948 if (ugeth->uccf) {
ce973b14 1949 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1950 ugeth->uccf = NULL;
1951 }
ce973b14
LY		 1952
1953 if (ugeth->p_thread_data_tx) {
1954 qe_muram_free(ugeth->thread_dat_tx_offset);
1955 ugeth->p_thread_data_tx = NULL;
1956 }
1957 if (ugeth->p_thread_data_rx) {
1958 qe_muram_free(ugeth->thread_dat_rx_offset);
1959 ugeth->p_thread_data_rx = NULL;
1960 }
1961 if (ugeth->p_exf_glbl_param) {
1962 qe_muram_free(ugeth->exf_glbl_param_offset);
1963 ugeth->p_exf_glbl_param = NULL;
1964 }
1965 if (ugeth->p_rx_glbl_pram) {
1966 qe_muram_free(ugeth->rx_glbl_pram_offset);
1967 ugeth->p_rx_glbl_pram = NULL;
1968 }
1969 if (ugeth->p_tx_glbl_pram) {
1970 qe_muram_free(ugeth->tx_glbl_pram_offset);
1971 ugeth->p_tx_glbl_pram = NULL;
1972 }
1973 if (ugeth->p_send_q_mem_reg) {
1974 qe_muram_free(ugeth->send_q_mem_reg_offset);
1975 ugeth->p_send_q_mem_reg = NULL;
1976 }
1977 if (ugeth->p_scheduler) {
1978 qe_muram_free(ugeth->scheduler_offset);
1979 ugeth->p_scheduler = NULL;
1980 }
1981 if (ugeth->p_tx_fw_statistics_pram) {
1982 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1983 ugeth->p_tx_fw_statistics_pram = NULL;
1984 }
1985 if (ugeth->p_rx_fw_statistics_pram) {
1986 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1987 ugeth->p_rx_fw_statistics_pram = NULL;
1988 }
1989 if (ugeth->p_rx_irq_coalescing_tbl) {
1990 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1991 ugeth->p_rx_irq_coalescing_tbl = NULL;
1992 }
1993 if (ugeth->p_rx_bd_qs_tbl) {
1994 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1995 ugeth->p_rx_bd_qs_tbl = NULL;
1996 }
1997 if (ugeth->p_init_enet_param_shadow) {
1998 return_init_enet_entries(ugeth,
1999 &(ugeth->p_init_enet_param_shadow->
2000 rxthread[0]),
2001 ENET_INIT_PARAM_MAX_ENTRIES_RX,
2002 ugeth->ug_info->riscRx, 1);
2003 return_init_enet_entries(ugeth,
2004 &(ugeth->p_init_enet_param_shadow->
2005 txthread[0]),
2006 ENET_INIT_PARAM_MAX_ENTRIES_TX,
2007 ugeth->ug_info->riscTx, 0);
2008 kfree(ugeth->p_init_enet_param_shadow);
2009 ugeth->p_init_enet_param_shadow = NULL;
2010 }
e19a82c1
PG		 2011 ucc_geth_free_tx(ugeth);
2012 ucc_geth_free_rx(ugeth);
ce973b14
LY		 2013 while (!list_empty(&ugeth->group_hash_q))
2014 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2015 (dequeue(&ugeth->group_hash_q)));
2016 while (!list_empty(&ugeth->ind_hash_q))
2017 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2018 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 2019 if (ugeth->ug_regs) {
2020 iounmap(ugeth->ug_regs);
2021 ugeth->ug_regs = NULL;
2022 }
50f238fd
AV		 2023
2024 skb_queue_purge(&ugeth->rx_recycle);
ce973b14
LY		 2025}
2026
2027static void ucc_geth_set_multi(struct net_device *dev)
2028{
18a8e864 2029 struct ucc_geth_private *ugeth;
22bedad3 2030 struct netdev_hw_addr *ha;
6fee40e9
AF		 2031 struct ucc_fast __iomem *uf_regs;
2032 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 2033
2034 ugeth = netdev_priv(dev);
2035
2036 uf_regs = ugeth->uccf->uf_regs;
2037
2038 if (dev->flags & IFF_PROMISC) {
3bc53427 2039 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 2040 } else {
3bc53427 2041 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 2042
2043 p_82xx_addr_filt =
6fee40e9 2044 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2045 p_rx_glbl_pram->addressfiltering;
2046
2047 if (dev->flags & IFF_ALLMULTI) {
2048 /* Catch all multicast addresses, so set the
2049 * filter to all 1's.
2050 */
2051 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2052 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2053 } else {
2054 /* Clear filter and add the addresses in the list.
2055 */
2056 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2057 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2058
22bedad3 2059 netdev_for_each_mc_addr(ha, dev) {
ce973b14
LY		 2060 /* Ask CPM to run CRC and set bit in
2061 * filter mask.
2062 */
22bedad3 2063 hw_add_addr_in_hash(ugeth, ha->addr);
ce973b14
LY		 2064 }
2065 }
2066 }
2067}
2068
18a8e864 2069static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2070{
6fee40e9 2071 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2072 struct phy_device *phydev = ugeth->phydev;
ce973b14 2073
b39d66a8 2074 ugeth_vdbg("%s: IN", __func__);
ce973b14 2075
75e60474
JT		 2076 /*
2077 * Tell the kernel the link is down.
2078 * Must be done before disabling the controller
2079 * or deadlock may happen.
2080 */
2081 phy_stop(phydev);
2082
ce973b14
LY		 2083 /* Disable the controller */
2084 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2085
ce973b14 2086 /* Mask all interrupts */
c6f5047b 2087 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2088
2089 /* Clear all interrupts */
2090 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2091
2092 /* Disable Rx and Tx */
3bc53427 2093 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2094
ce973b14
LY		 2095 ucc_geth_memclean(ugeth);
2096}
2097
728de4c9 2098static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2099{
18a8e864
LY		 2100 struct ucc_geth_info *ug_info;
2101 struct ucc_fast_info *uf_info;
728de4c9 2102 int i;
ce973b14
LY		 2103
2104 ug_info = ugeth->ug_info;
2105 uf_info = &ug_info->uf_info;
2106
2107 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2108 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2109 if (netif_msg_probe(ugeth))
2110 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2111 __func__);
ce973b14
LY		 2112 return -EINVAL;
2113 }
2114
2115 /* Rx BD lengths */
2116 for (i = 0; i < ug_info->numQueuesRx; i++) {
2117 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2118 (ug_info->bdRingLenRx[i] %
2119 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2120 if (netif_msg_probe(ugeth))
2121 ugeth_err
2122 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2123 __func__);
ce973b14
LY		 2124 return -EINVAL;
2125 }
2126 }
2127
2128 /* Tx BD lengths */
2129 for (i = 0; i < ug_info->numQueuesTx; i++) {
2130 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2131 if (netif_msg_probe(ugeth))
2132 ugeth_err
2133 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2134 __func__);
ce973b14
LY		 2135 return -EINVAL;
2136 }
2137 }
2138
2139 /* mrblr */
2140 if ((uf_info->max_rx_buf_length == 0) ||
2141 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2142 if (netif_msg_probe(ugeth))
2143 ugeth_err
2144 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2145 __func__);
ce973b14
LY		 2146 return -EINVAL;
2147 }
2148
2149 /* num Tx queues */
2150 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2151 if (netif_msg_probe(ugeth))
b39d66a8 2152 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2153 return -EINVAL;
2154 }
2155
2156 /* num Rx queues */
2157 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2158 if (netif_msg_probe(ugeth))
b39d66a8 2159 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2160 return -EINVAL;
2161 }
2162
2163 /* l2qt */
2164 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2165 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2166 if (netif_msg_probe(ugeth))
2167 ugeth_err
2168 ("%s: VLAN priority table entry must not be"
2169 " larger than number of Rx queues.",
b39d66a8 2170 __func__);
ce973b14
LY		 2171 return -EINVAL;
2172 }
2173 }
2174
2175 /* l3qt */
2176 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2177 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2178 if (netif_msg_probe(ugeth))
2179 ugeth_err
2180 ("%s: IP priority table entry must not be"
2181 " larger than number of Rx queues.",
b39d66a8 2182 __func__);
ce973b14
LY		 2183 return -EINVAL;
2184 }
2185 }
2186
2187 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2188 if (netif_msg_probe(ugeth))
2189 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2190 __func__);
ce973b14
LY		 2191 return -EINVAL;
2192 }
2193
2194 if ((ug_info->numStationAddresses !=
8e95a202
JP		 2195 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2196 ug_info->rxExtendedFiltering) {
890de95e
LY		 2197 if (netif_msg_probe(ugeth))
2198 ugeth_err("%s: Number of station addresses greater than 1 "
2199 "not allowed in extended parsing mode.",
b39d66a8 2200 __func__);
ce973b14
LY		 2201 return -EINVAL;
2202 }
2203
2204 /* Generate uccm_mask for receive */
2205 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2206 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2207 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2208
2209 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2210 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2211 /* Initialize the general fast UCC block. */
728de4c9 2212 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2213 if (netif_msg_probe(ugeth))
b39d66a8 2214 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2215 return -ENOMEM;
2216 }
728de4c9 2217
345f8422
HW		 2218 /* read the number of risc engines, update the riscTx and riscRx
2219 * if there are 4 riscs in QE
2220 */
2221 if (qe_get_num_of_risc() == 4) {
2222 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2223 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2224 }
2225
3e73fc9a
AV		 2226 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2227 if (!ugeth->ug_regs) {
2228 if (netif_msg_probe(ugeth))
2229 ugeth_err("%s: Failed to ioremap regs.", __func__);
2230 return -ENOMEM;
2231 }
728de4c9 2232
50f238fd
AV		 2233 skb_queue_head_init(&ugeth->rx_recycle);
2234
728de4c9
KP		 2235 return 0;
2236}
2237
e19a82c1
PG		 2238static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2239{
2240 struct ucc_geth_info *ug_info;
2241 struct ucc_fast_info *uf_info;
2242 int length;
2243 u16 i, j;
2244 u8 __iomem *bd;
2245
2246 ug_info = ugeth->ug_info;
2247 uf_info = &ug_info->uf_info;
2248
2249 /* Allocate Tx bds */
2250 for (j = 0; j < ug_info->numQueuesTx; j++) {
2251 /* Allocate in multiple of
2252 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2253 according to spec */
2254 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2255 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2256 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2257 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2258 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2259 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2260 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2261 u32 align = 4;
2262 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2263 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2264 ugeth->tx_bd_ring_offset[j] =
2265 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2266
2267 if (ugeth->tx_bd_ring_offset[j] != 0)
2268 ugeth->p_tx_bd_ring[j] =
2269 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2270 align) & ~(align - 1));
2271 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2272 ugeth->tx_bd_ring_offset[j] =
2273 qe_muram_alloc(length,
2274 UCC_GETH_TX_BD_RING_ALIGNMENT);
2275 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2276 ugeth->p_tx_bd_ring[j] =
2277 (u8 __iomem *) qe_muram_addr(ugeth->
2278 tx_bd_ring_offset[j]);
2279 }
2280 if (!ugeth->p_tx_bd_ring[j]) {
2281 if (netif_msg_ifup(ugeth))
2282 ugeth_err
2283 ("%s: Can not allocate memory for Tx bd rings.",
2284 __func__);
2285 return -ENOMEM;
2286 }
2287 /* Zero unused end of bd ring, according to spec */
2288 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2289 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2290 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2291 }
2292
2293 /* Init Tx bds */
2294 for (j = 0; j < ug_info->numQueuesTx; j++) {
2295 /* Setup the skbuff rings */
2296 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2297 ugeth->ug_info->bdRingLenTx[j],
2298 GFP_KERNEL);
2299
2300 if (ugeth->tx_skbuff[j] == NULL) {
2301 if (netif_msg_ifup(ugeth))
2302 ugeth_err("%s: Could not allocate tx_skbuff",
2303 __func__);
2304 return -ENOMEM;
2305 }
2306
2307 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2308 ugeth->tx_skbuff[j][i] = NULL;
2309
2310 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2311 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2312 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2313 /* clear bd buffer */
2314 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2315 /* set bd status and length */
2316 out_be32((u32 __iomem *)bd, 0);
2317 bd += sizeof(struct qe_bd);
2318 }
2319 bd -= sizeof(struct qe_bd);
2320 /* set bd status and length */
2321 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2322 }
2323
2324 return 0;
2325}
2326
2327static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2328{
2329 struct ucc_geth_info *ug_info;
2330 struct ucc_fast_info *uf_info;
2331 int length;
2332 u16 i, j;
2333 u8 __iomem *bd;
2334
2335 ug_info = ugeth->ug_info;
2336 uf_info = &ug_info->uf_info;
2337
2338 /* Allocate Rx bds */
2339 for (j = 0; j < ug_info->numQueuesRx; j++) {
2340 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2341 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2342 u32 align = 4;
2343 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2344 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2345 ugeth->rx_bd_ring_offset[j] =
2346 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2347 if (ugeth->rx_bd_ring_offset[j] != 0)
2348 ugeth->p_rx_bd_ring[j] =
2349 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2350 align) & ~(align - 1));
2351 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2352 ugeth->rx_bd_ring_offset[j] =
2353 qe_muram_alloc(length,
2354 UCC_GETH_RX_BD_RING_ALIGNMENT);
2355 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2356 ugeth->p_rx_bd_ring[j] =
2357 (u8 __iomem *) qe_muram_addr(ugeth->
2358 rx_bd_ring_offset[j]);
2359 }
2360 if (!ugeth->p_rx_bd_ring[j]) {
2361 if (netif_msg_ifup(ugeth))
2362 ugeth_err
2363 ("%s: Can not allocate memory for Rx bd rings.",
2364 __func__);
2365 return -ENOMEM;
2366 }
2367 }
2368
2369 /* Init Rx bds */
2370 for (j = 0; j < ug_info->numQueuesRx; j++) {
2371 /* Setup the skbuff rings */
2372 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2373 ugeth->ug_info->bdRingLenRx[j],
2374 GFP_KERNEL);
2375
2376 if (ugeth->rx_skbuff[j] == NULL) {
2377 if (netif_msg_ifup(ugeth))
2378 ugeth_err("%s: Could not allocate rx_skbuff",
2379 __func__);
2380 return -ENOMEM;
2381 }
2382
2383 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2384 ugeth->rx_skbuff[j][i] = NULL;
2385
2386 ugeth->skb_currx[j] = 0;
2387 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2388 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2389 /* set bd status and length */
2390 out_be32((u32 __iomem *)bd, R_I);
2391 /* clear bd buffer */
2392 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2393 bd += sizeof(struct qe_bd);
2394 }
2395 bd -= sizeof(struct qe_bd);
2396 /* set bd status and length */
2397 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2398 }
2399
2400 return 0;
2401}
2402
728de4c9
KP		 2403static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2404{
6fee40e9
AF		 2405 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2406 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2407 struct ucc_fast_private *uccf;
2408 struct ucc_geth_info *ug_info;
2409 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2410 struct ucc_fast __iomem *uf_regs;
2411 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2412 int ret_val = -EINVAL;
2413 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2414 u32 init_enet_pram_offset, cecr_subblock, command;
e19a82c1 2415 u32 ifstat, i, j, size, l2qt, l3qt;
728de4c9
KP		 2416 u16 temoder = UCC_GETH_TEMODER_INIT;
2417 u16 test;
2418 u8 function_code = 0;
6fee40e9 2419 u8 __iomem *endOfRing;
728de4c9
KP		 2420 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2421
b39d66a8 2422 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2423 uccf = ugeth->uccf;
2424 ug_info = ugeth->ug_info;
2425 uf_info = &ug_info->uf_info;
2426 uf_regs = uccf->uf_regs;
2427 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2428
2429 switch (ug_info->numThreadsRx) {
2430 case UCC_GETH_NUM_OF_THREADS_1:
2431 numThreadsRxNumerical = 1;
2432 break;
2433 case UCC_GETH_NUM_OF_THREADS_2:
2434 numThreadsRxNumerical = 2;
2435 break;
2436 case UCC_GETH_NUM_OF_THREADS_4:
2437 numThreadsRxNumerical = 4;
2438 break;
2439 case UCC_GETH_NUM_OF_THREADS_6:
2440 numThreadsRxNumerical = 6;
2441 break;
2442 case UCC_GETH_NUM_OF_THREADS_8:
2443 numThreadsRxNumerical = 8;
2444 break;
2445 default:
890de95e
LY		 2446 if (netif_msg_ifup(ugeth))
2447 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2448 __func__);
ce973b14
LY		 2449 return -EINVAL;
2450 break;
2451 }
2452
2453 switch (ug_info->numThreadsTx) {
2454 case UCC_GETH_NUM_OF_THREADS_1:
2455 numThreadsTxNumerical = 1;
2456 break;
2457 case UCC_GETH_NUM_OF_THREADS_2:
2458 numThreadsTxNumerical = 2;
2459 break;
2460 case UCC_GETH_NUM_OF_THREADS_4:
2461 numThreadsTxNumerical = 4;
2462 break;
2463 case UCC_GETH_NUM_OF_THREADS_6:
2464 numThreadsTxNumerical = 6;
2465 break;
2466 case UCC_GETH_NUM_OF_THREADS_8:
2467 numThreadsTxNumerical = 8;
2468 break;
2469 default:
890de95e
LY		 2470 if (netif_msg_ifup(ugeth))
2471 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2472 __func__);
ce973b14
LY		 2473 return -EINVAL;
2474 break;
2475 }
2476
2477 /* Calculate rx_extended_features */
2478 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2479 ug_info->ipAddressAlignment ||
2480 (ug_info->numStationAddresses !=
2481 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2482
2483 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
8e95a202
JP		 2484 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2485 (ug_info->vlanOperationNonTagged !=
2486 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
ce973b14 2487
ce973b14
LY		 2488 init_default_reg_vals(&uf_regs->upsmr,
2489 &ug_regs->maccfg1, &ug_regs->maccfg2);
2490
2491 /* Set UPSMR */
2492 /* For more details see the hardware spec. */
2493 init_rx_parameters(ug_info->bro,
2494 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2495
2496 /* We're going to ignore other registers for now, */
2497 /* except as needed to get up and running */
2498
2499 /* Set MACCFG1 */
2500 /* For more details see the hardware spec. */
2501 init_flow_control_params(ug_info->aufc,
2502 ug_info->receiveFlowControl,
ac421852 2503 ug_info->transmitFlowControl,
ce973b14
LY		 2504 ug_info->pausePeriod,
2505 ug_info->extensionField,
2506 &uf_regs->upsmr,
2507 &ug_regs->uempr, &ug_regs->maccfg1);
2508
3bc53427 2509 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2510
2511 /* Set IPGIFG */
2512 /* For more details see the hardware spec. */
2513 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2514 ug_info->nonBackToBackIfgPart2,
2515 ug_info->
2516 miminumInterFrameGapEnforcement,
2517 ug_info->backToBackInterFrameGap,
2518 &ug_regs->ipgifg);
2519 if (ret_val != 0) {
890de95e
LY		 2520 if (netif_msg_ifup(ugeth))
2521 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2522 __func__);
ce973b14
LY		 2523 return ret_val;
2524 }
2525
2526 /* Set HAFDUP */
2527 /* For more details see the hardware spec. */
2528 ret_val = init_half_duplex_params(ug_info->altBeb,
2529 ug_info->backPressureNoBackoff,
2530 ug_info->noBackoff,
2531 ug_info->excessDefer,
2532 ug_info->altBebTruncation,
2533 ug_info->maxRetransmission,
2534 ug_info->collisionWindow,
2535 &ug_regs->hafdup);
2536 if (ret_val != 0) {
890de95e
LY		 2537 if (netif_msg_ifup(ugeth))
2538 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2539 __func__);
ce973b14
LY		 2540 return ret_val;
2541 }
2542
2543 /* Set IFSTAT */
2544 /* For more details see the hardware spec. */
2545 /* Read only - resets upon read */
2546 ifstat = in_be32(&ug_regs->ifstat);
2547
2548 /* Clear UEMPR */
2549 /* For more details see the hardware spec. */
2550 out_be32(&ug_regs->uempr, 0);
2551
2552 /* Set UESCR */
2553 /* For more details see the hardware spec. */
2554 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2555 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2556 0, &uf_regs->upsmr, &ug_regs->uescr);
2557
e19a82c1
PG		 2558 ret_val = ucc_geth_alloc_tx(ugeth);
2559 if (ret_val != 0)
2560 return ret_val;
ce973b14 2561
e19a82c1
PG		 2562 ret_val = ucc_geth_alloc_rx(ugeth);
2563 if (ret_val != 0)
2564 return ret_val;
ce973b14
LY		 2565
2566 /*
2567 * Global PRAM
2568 */
2569 /* Tx global PRAM */
2570 /* Allocate global tx parameter RAM page */
2571 ugeth->tx_glbl_pram_offset =
18a8e864 2572 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2573 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2574 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2575 if (netif_msg_ifup(ugeth))
2576 ugeth_err
2577 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2578 __func__);
ce973b14
LY		 2579 return -ENOMEM;
2580 }
2581 ugeth->p_tx_glbl_pram =
6fee40e9 2582 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2583 tx_glbl_pram_offset);
2584 /* Zero out p_tx_glbl_pram */
6fee40e9 2585 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2586
2587 /* Fill global PRAM */
2588
2589 /* TQPTR */
2590 /* Size varies with number of Tx threads */
2591 ugeth->thread_dat_tx_offset =
2592 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2593 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2594 32 * (numThreadsTxNumerical == 1),
2595 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2596 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2597 if (netif_msg_ifup(ugeth))
2598 ugeth_err
2599 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2600 __func__);
ce973b14
LY		 2601 return -ENOMEM;
2602 }
2603
2604 ugeth->p_thread_data_tx =
6fee40e9 2605 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2606 thread_dat_tx_offset);
2607 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2608
2609 /* vtagtable */
2610 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2611 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2612 ug_info->vtagtable[i]);
2613
2614 /* iphoffset */
2615 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2616 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2617 ug_info->iphoffset[i]);
ce973b14
LY		 2618
2619 /* SQPTR */
2620 /* Size varies with number of Tx queues */
2621 ugeth->send_q_mem_reg_offset =
2622 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2623 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2624 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2625 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2626 if (netif_msg_ifup(ugeth))
2627 ugeth_err
2628 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2629 __func__);
ce973b14
LY		 2630 return -ENOMEM;
2631 }
2632
2633 ugeth->p_send_q_mem_reg =
6fee40e9 2634 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2635 send_q_mem_reg_offset);
2636 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2637
2638 /* Setup the table */
2639 /* Assume BD rings are already established */
2640 for (i = 0; i < ug_info->numQueuesTx; i++) {
2641 endOfRing =
2642 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2643 1) * sizeof(struct qe_bd);
ce973b14
LY		 2644 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2645 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2646 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2647 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2648 last_bd_completed_address,
2649 (u32) virt_to_phys(endOfRing));
2650 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2651 MEM_PART_MURAM) {
2652 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2653 (u32) immrbar_virt_to_phys(ugeth->
2654 p_tx_bd_ring[i]));
2655 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2656 last_bd_completed_address,
2657 (u32) immrbar_virt_to_phys(endOfRing));
2658 }
2659 }
2660
2661 /* schedulerbasepointer */
2662
2663 if (ug_info->numQueuesTx > 1) {
2664 /* scheduler exists only if more than 1 tx queue */
2665 ugeth->scheduler_offset =
18a8e864 2666 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2667 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2668 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2669 if (netif_msg_ifup(ugeth))
2670 ugeth_err
2671 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2672 __func__);
ce973b14
LY		 2673 return -ENOMEM;
2674 }
2675
2676 ugeth->p_scheduler =
6fee40e9 2677 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2678 scheduler_offset);
2679 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2680 ugeth->scheduler_offset);
2681 /* Zero out p_scheduler */
6fee40e9 2682 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2683
2684 /* Set values in scheduler */
2685 out_be32(&ugeth->p_scheduler->mblinterval,
2686 ug_info->mblinterval);
2687 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2688 ug_info->nortsrbytetime);
6fee40e9
AF		 2689 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2690 out_8(&ugeth->p_scheduler->strictpriorityq,
2691 ug_info->strictpriorityq);
2692 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2693 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2694 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2695 out_8(&ugeth->p_scheduler->weightfactor[i],
2696 ug_info->weightfactor[i]);
ce973b14
LY		 2697
2698 /* Set pointers to cpucount registers in scheduler */
2699 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2700 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2701 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2702 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2703 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2704 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2705 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2706 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2707 }
2708
2709 /* schedulerbasepointer */
2710 /* TxRMON_PTR (statistics) */
2711 if (ug_info->
2712 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2713 ugeth->tx_fw_statistics_pram_offset =
2714 qe_muram_alloc(sizeof
18a8e864 2715 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2716 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2717 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2718 if (netif_msg_ifup(ugeth))
2719 ugeth_err
2720 ("%s: Can not allocate DPRAM memory for"
2721 " p_tx_fw_statistics_pram.",
b39d66a8 2722 __func__);
ce973b14
LY		 2723 return -ENOMEM;
2724 }
2725 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2726 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2727 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2728 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2729 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2730 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2731 }
2732
2733 /* temoder */
2734 /* Already has speed set */
2735
2736 if (ug_info->numQueuesTx > 1)
2737 temoder |= TEMODER_SCHEDULER_ENABLE;
2738 if (ug_info->ipCheckSumGenerate)
2739 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2740 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2741 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2742
2743 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2744
2745 /* Function code register value to be used later */
6b0b594b 2746 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2747 /* Required for QE */
2748
2749 /* function code register */
2750 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2751
2752 /* Rx global PRAM */
2753 /* Allocate global rx parameter RAM page */
2754 ugeth->rx_glbl_pram_offset =
18a8e864 2755 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2756 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2757 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2758 if (netif_msg_ifup(ugeth))
2759 ugeth_err
2760 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2761 __func__);
ce973b14
LY		 2762 return -ENOMEM;
2763 }
2764 ugeth->p_rx_glbl_pram =
6fee40e9 2765 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2766 rx_glbl_pram_offset);
2767 /* Zero out p_rx_glbl_pram */
6fee40e9 2768 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2769
2770 /* Fill global PRAM */
2771
2772 /* RQPTR */
2773 /* Size varies with number of Rx threads */
2774 ugeth->thread_dat_rx_offset =
2775 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2776 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2777 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2778 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2779 if (netif_msg_ifup(ugeth))
2780 ugeth_err
2781 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2782 __func__);
ce973b14
LY		 2783 return -ENOMEM;
2784 }
2785
2786 ugeth->p_thread_data_rx =
6fee40e9 2787 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2788 thread_dat_rx_offset);
2789 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2790
2791 /* typeorlen */
2792 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2793
2794 /* rxrmonbaseptr (statistics) */
2795 if (ug_info->
2796 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2797 ugeth->rx_fw_statistics_pram_offset =
2798 qe_muram_alloc(sizeof
18a8e864 2799 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2800 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2801 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2802 if (netif_msg_ifup(ugeth))
2803 ugeth_err
2804 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2805 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2806 return -ENOMEM;
2807 }
2808 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2809 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2810 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2811 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2812 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2813 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2814 }
2815
2816 /* intCoalescingPtr */
2817
2818 /* Size varies with number of Rx queues */
2819 ugeth->rx_irq_coalescing_tbl_offset =
2820 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2821 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2822 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2823 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 2824 if (netif_msg_ifup(ugeth))
2825 ugeth_err
2826 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2827 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 2828 return -ENOMEM;
2829 }
2830
2831 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2832 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2833 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2834 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2835 ugeth->rx_irq_coalescing_tbl_offset);
2836
2837 /* Fill interrupt coalescing table */
2838 for (i = 0; i < ug_info->numQueuesRx; i++) {
2839 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2840 interruptcoalescingmaxvalue,
2841 ug_info->interruptcoalescingmaxvalue[i]);
2842 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2843 interruptcoalescingcounter,
2844 ug_info->interruptcoalescingmaxvalue[i]);
2845 }
2846
2847 /* MRBLR */
2848 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2849 &ugeth->p_rx_glbl_pram->mrblr);
2850 /* MFLR */
2851 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2852 /* MINFLR */
2853 init_min_frame_len(ug_info->minFrameLength,
2854 &ugeth->p_rx_glbl_pram->minflr,
2855 &ugeth->p_rx_glbl_pram->mrblr);
2856 /* MAXD1 */
2857 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2858 /* MAXD2 */
2859 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2860
2861 /* l2qt */
2862 l2qt = 0;
2863 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2864 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2865 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2866
2867 /* l3qt */
2868 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2869 l3qt = 0;
2870 for (i = 0; i < 8; i++)
2871 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2872 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2873 }
2874
2875 /* vlantype */
2876 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2877
2878 /* vlantci */
2879 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2880
2881 /* ecamptr */
2882 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2883
2884 /* RBDQPTR */
2885 /* Size varies with number of Rx queues */
2886 ugeth->rx_bd_qs_tbl_offset =
2887 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2888 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2889 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2890 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2891 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 2892 if (netif_msg_ifup(ugeth))
2893 ugeth_err
2894 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 2895 __func__);
ce973b14
LY		 2896 return -ENOMEM;
2897 }
2898
2899 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2900 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2901 rx_bd_qs_tbl_offset);
2902 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2903 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2904 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2905 0,
18a8e864
LY		 2906 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2907 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2908
2909 /* Setup the table */
2910 /* Assume BD rings are already established */
2911 for (i = 0; i < ug_info->numQueuesRx; i++) {
2912 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2913 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2914 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2915 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2916 MEM_PART_MURAM) {
2917 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2918 (u32) immrbar_virt_to_phys(ugeth->
2919 p_rx_bd_ring[i]));
2920 }
2921 /* rest of fields handled by QE */
2922 }
2923
2924 /* remoder */
2925 /* Already has speed set */
2926
2927 if (ugeth->rx_extended_features)
2928 remoder |= REMODER_RX_EXTENDED_FEATURES;
2929 if (ug_info->rxExtendedFiltering)
2930 remoder |= REMODER_RX_EXTENDED_FILTERING;
2931 if (ug_info->dynamicMaxFrameLength)
2932 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2933 if (ug_info->dynamicMinFrameLength)
2934 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2935 remoder |=
2936 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2937 remoder |=
2938 ug_info->
2939 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2940 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2941 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2942 if (ug_info->ipCheckSumCheck)
2943 remoder |= REMODER_IP_CHECKSUM_CHECK;
2944 if (ug_info->ipAddressAlignment)
2945 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2946 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2947
2948 /* Note that this function must be called */
2949 /* ONLY AFTER p_tx_fw_statistics_pram */
2950 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2951 init_firmware_statistics_gathering_mode((ug_info->
2952 statisticsMode &
2953 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2954 (ug_info->statisticsMode &
2955 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2956 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2957 ugeth->tx_fw_statistics_pram_offset,
2958 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2959 ugeth->rx_fw_statistics_pram_offset,
2960 &ugeth->p_tx_glbl_pram->temoder,
2961 &ugeth->p_rx_glbl_pram->remoder);
2962
2963 /* function code register */
6fee40e9 2964 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2965
2966 /* initialize extended filtering */
2967 if (ug_info->rxExtendedFiltering) {
2968 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 2969 if (netif_msg_ifup(ugeth))
2970 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 2971 __func__);
ce973b14
LY		 2972 return -EINVAL;
2973 }
2974
2975 /* Allocate memory for extended filtering Mode Global
2976 Parameters */
2977 ugeth->exf_glbl_param_offset =
18a8e864 2978 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2979 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2980 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 2981 if (netif_msg_ifup(ugeth))
2982 ugeth_err
2983 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2984 " p_exf_glbl_param.", __func__);
ce973b14
LY		 2985 return -ENOMEM;
2986 }
2987
2988 ugeth->p_exf_glbl_param =
6fee40e9 2989 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2990 exf_glbl_param_offset);
2991 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2992 ugeth->exf_glbl_param_offset);
2993 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2994 (u32) ug_info->extendedFilteringChainPointer);
2995
2996 } else { /* initialize 82xx style address filtering */
2997
2998 /* Init individual address recognition registers to disabled */
2999
3000 for (j = 0; j < NUM_OF_PADDRS; j++)
3001 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3002
ce973b14 3003 p_82xx_addr_filt =
6fee40e9 3004 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 3005 p_rx_glbl_pram->addressfiltering;
3006
3007 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3008 ENET_ADDR_TYPE_GROUP);
3009 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3010 ENET_ADDR_TYPE_INDIVIDUAL);
3011 }
3012
3013 /*
3014 * Initialize UCC at QE level
3015 */
3016
3017 command = QE_INIT_TX_RX;
3018
3019 /* Allocate shadow InitEnet command parameter structure.
3020 * This is needed because after the InitEnet command is executed,
3021 * the structure in DPRAM is released, because DPRAM is a premium
3022 * resource.
3023 * This shadow structure keeps a copy of what was done so that the
3024 * allocated resources can be released when the channel is freed.
3025 */
3026 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 3027 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 3028 if (netif_msg_ifup(ugeth))
3029 ugeth_err
3030 ("%s: Can not allocate memory for"
b39d66a8 3031 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 3032 return -ENOMEM;
3033 }
3034 /* Zero out *p_init_enet_param_shadow */
3035 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 3036 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 3037
3038 /* Fill shadow InitEnet command parameter structure */
3039
3040 ugeth->p_init_enet_param_shadow->resinit1 =
3041 ENET_INIT_PARAM_MAGIC_RES_INIT1;
3042 ugeth->p_init_enet_param_shadow->resinit2 =
3043 ENET_INIT_PARAM_MAGIC_RES_INIT2;
3044 ugeth->p_init_enet_param_shadow->resinit3 =
3045 ENET_INIT_PARAM_MAGIC_RES_INIT3;
3046 ugeth->p_init_enet_param_shadow->resinit4 =
3047 ENET_INIT_PARAM_MAGIC_RES_INIT4;
3048 ugeth->p_init_enet_param_shadow->resinit5 =
3049 ENET_INIT_PARAM_MAGIC_RES_INIT5;
3050 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3051 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3052 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3053 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3054
3055 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3056 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3057 if ((ug_info->largestexternallookupkeysize !=
8e95a202
JP		 3058 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
3059 (ug_info->largestexternallookupkeysize !=
3060 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
3061 (ug_info->largestexternallookupkeysize !=
3062 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 3063 if (netif_msg_ifup(ugeth))
3064 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 3065 __func__);
ce973b14
LY		 3066 return -EINVAL;
3067 }
3068 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3069 ug_info->largestexternallookupkeysize;
18a8e864 3070 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 3071 if (ug_info->rxExtendedFiltering) {
3072 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3073 if (ug_info->largestexternallookupkeysize ==
3074 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3075 size +=
3076 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3077 if (ug_info->largestexternallookupkeysize ==
3078 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3079 size +=
3080 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3081 }
3082
3083 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3084 p_init_enet_param_shadow->rxthread[0]),
3085 (u8) (numThreadsRxNumerical + 1)
3086 /* Rx needs one extra for terminator */
3087 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3088 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 3089 if (netif_msg_ifup(ugeth))
3090 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3091 __func__);
ce973b14
LY		 3092 return ret_val;
3093 }
3094
3095 ugeth->p_init_enet_param_shadow->txglobal =
3096 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3097 if ((ret_val =
3098 fill_init_enet_entries(ugeth,
3099 &(ugeth->p_init_enet_param_shadow->
3100 txthread[0]), numThreadsTxNumerical,
18a8e864 3101 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3102 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3103 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 3104 if (netif_msg_ifup(ugeth))
3105 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3106 __func__);
ce973b14
LY		 3107 return ret_val;
3108 }
3109
3110 /* Load Rx bds with buffers */
3111 for (i = 0; i < ug_info->numQueuesRx; i++) {
3112 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 3113 if (netif_msg_ifup(ugeth))
3114 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 3115 __func__);
ce973b14
LY		 3116 return ret_val;
3117 }
3118 }
3119
3120 /* Allocate InitEnet command parameter structure */
18a8e864 3121 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3122 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3123 if (netif_msg_ifup(ugeth))
3124 ugeth_err
3125 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3126 __func__);
ce973b14
LY		 3127 return -ENOMEM;
3128 }
3129 p_init_enet_pram =
6fee40e9 3130 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3131
3132 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3133 out_8(&p_init_enet_pram->resinit1,
3134 ugeth->p_init_enet_param_shadow->resinit1);
3135 out_8(&p_init_enet_pram->resinit2,
3136 ugeth->p_init_enet_param_shadow->resinit2);
3137 out_8(&p_init_enet_pram->resinit3,
3138 ugeth->p_init_enet_param_shadow->resinit3);
3139 out_8(&p_init_enet_pram->resinit4,
3140 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3141 out_be16(&p_init_enet_pram->resinit5,
3142 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3143 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3144 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3145 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3146 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3147 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3148 out_be32(&p_init_enet_pram->rxthread[i],
3149 ugeth->p_init_enet_param_shadow->rxthread[i]);
3150 out_be32(&p_init_enet_pram->txglobal,
3151 ugeth->p_init_enet_param_shadow->txglobal);
3152 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3153 out_be32(&p_init_enet_pram->txthread[i],
3154 ugeth->p_init_enet_param_shadow->txthread[i]);
3155
3156 /* Issue QE command */
3157 cecr_subblock =
3158 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3159 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3160 init_enet_pram_offset);
3161
3162 /* Free InitEnet command parameter */
3163 qe_muram_free(init_enet_pram_offset);
3164
3165 return 0;
3166}
3167
ce973b14
LY		 3168/* This is called by the kernel when a frame is ready for transmission. */
3169/* It is pointed to by the dev->hard_start_xmit function pointer */
3170static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3171{
18a8e864 3172 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3173#ifdef CONFIG_UGETH_TX_ON_DEMAND
3174 struct ucc_fast_private *uccf;
3175#endif
6fee40e9 3176 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3177 u32 bd_status;
3178 u8 txQ = 0;
22580f89 3179 unsigned long flags;
ce973b14 3180
b39d66a8 3181 ugeth_vdbg("%s: IN", __func__);
ce973b14 3182
22580f89 3183 spin_lock_irqsave(&ugeth->lock, flags);
ce973b14 3184
09f75cd7 3185 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3186
3187 /* Start from the next BD that should be filled */
3188 bd = ugeth->txBd[txQ];
6fee40e9 3189 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3190 /* Save the skb pointer so we can free it later */
3191 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3192
3193 /* Update the current skb pointer (wrapping if this was the last) */
3194 ugeth->skb_curtx[txQ] =
3195 (ugeth->skb_curtx[txQ] +
3196 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3197
3198 /* set up the buffer descriptor */
6fee40e9 3199 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3200 dma_map_single(ugeth->dev, skb->data,
7f80202b 3201 skb->len, DMA_TO_DEVICE));
ce973b14 3202
18a8e864 3203 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3204
3205 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3206
18a8e864 3207 /* set bd status and length */
6fee40e9 3208 out_be32((u32 __iomem *)bd, bd_status);
ce973b14 3209
ce973b14
LY		 3210 /* Move to next BD in the ring */
3211 if (!(bd_status & T_W))
a394f013 3212 bd += sizeof(struct qe_bd);
ce973b14 3213 else
a394f013 3214 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3215
3216 /* If the next BD still needs to be cleaned up, then the bds
3217 are full. We need to tell the kernel to stop sending us stuff. */
3218 if (bd == ugeth->confBd[txQ]) {
3219 if (!netif_queue_stopped(dev))
3220 netif_stop_queue(dev);
3221 }
3222
a394f013
LY		 3223 ugeth->txBd[txQ] = bd;
3224
d13d6bff
RC		 3225 skb_tx_timestamp(skb);
3226
ce973b14
LY		 3227 if (ugeth->p_scheduler) {
3228 ugeth->cpucount[txQ]++;
3229 /* Indicate to QE that there are more Tx bds ready for
3230 transmission */
3231 /* This is done by writing a running counter of the bd
3232 count to the scheduler PRAM. */
3233 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3234 }
3235
d5b9049d
MR		 3236#ifdef CONFIG_UGETH_TX_ON_DEMAND
3237 uccf = ugeth->uccf;
3238 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3239#endif
22580f89 3240 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14 3241
6ed10654 3242 return NETDEV_TX_OK;
ce973b14
LY		 3243}
3244
18a8e864 3245static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3246{
3247 struct sk_buff *skb;
6fee40e9 3248 u8 __iomem *bd;
ce973b14
LY		 3249 u16 length, howmany = 0;
3250 u32 bd_status;
3251 u8 *bdBuffer;
4b8fdefa 3252 struct net_device *dev;
ce973b14 3253
b39d66a8 3254 ugeth_vdbg("%s: IN", __func__);
ce973b14 3255
da1aa63e 3256 dev = ugeth->ndev;
88a15f2e 3257
ce973b14
LY		 3258 /* collect received buffers */
3259 bd = ugeth->rxBd[rxQ];
3260
6fee40e9 3261 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3262
3263 /* while there are received buffers and BD is full (~R_E) */
3264 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3265 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3266 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3267 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3268
3269 /* determine whether buffer is first, last, first and last
3270 (single buffer frame) or middle (not first and not last) */
3271 if (!skb ||
3272 (!(bd_status & (R_F | R_L))) ||
3273 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3274 if (netif_msg_rx_err(ugeth))
3275 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3276 __func__, __LINE__, (u32) skb);
50f238fd
AV		 3277 if (skb) {
3278 skb->data = skb->head + NET_SKB_PAD;
db176edc
SM		 3279 skb->len = 0;
3280 skb_reset_tail_pointer(skb);
50f238fd
AV		 3281 __skb_queue_head(&ugeth->rx_recycle, skb);
3282 }
ce973b14
LY		 3283
3284 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3285 dev->stats.rx_dropped++;
ce973b14 3286 } else {
09f75cd7 3287 dev->stats.rx_packets++;
ce973b14
LY		 3288 howmany++;
3289
3290 /* Prep the skb for the packet */
3291 skb_put(skb, length);
3292
3293 /* Tell the skb what kind of packet this is */
da1aa63e 3294 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3295
09f75cd7 3296 dev->stats.rx_bytes += length;
ce973b14 3297 /* Send the packet up the stack */
ce973b14 3298 netif_receive_skb(skb);
ce973b14
LY		 3299 }
3300
ce973b14
LY		 3301 skb = get_new_skb(ugeth, bd);
3302 if (!skb) {
890de95e 3303 if (netif_msg_rx_err(ugeth))
b39d66a8 3304 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3305 dev->stats.rx_dropped++;
ce973b14
LY		 3306 break;
3307 }
3308
3309 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3310
3311 /* update to point at the next skb */
3312 ugeth->skb_currx[rxQ] =
3313 (ugeth->skb_currx[rxQ] +
3314 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3315
3316 if (bd_status & R_W)
3317 bd = ugeth->p_rx_bd_ring[rxQ];
3318 else
18a8e864 3319 bd += sizeof(struct qe_bd);
ce973b14 3320
6fee40e9 3321 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3322 }
3323
3324 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3325 return howmany;
3326}
3327
3328static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3329{
3330 /* Start from the next BD that should be filled */
18a8e864 3331 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3332 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3333 u32 bd_status;
3334
3335 bd = ugeth->confBd[txQ];
6fee40e9 3336 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3337
3338 /* Normal processing. */
3339 while ((bd_status & T_R) == 0) {
50f238fd
AV		 3340 struct sk_buff *skb;
3341
ce973b14
LY		 3342 /* BD contains already transmitted buffer. */
3343 /* Handle the transmitted buffer and release */
3344 /* the BD to be used with the current frame */
3345
34692421
JW		 3346 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3347 if (!skb)
ce973b14
LY		 3348 break;
3349
09f75cd7 3350 dev->stats.tx_packets++;
ce973b14 3351
50f238fd
AV		 3352 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3353 skb_recycle_check(skb,
3354 ugeth->ug_info->uf_info.max_rx_buf_length +
3355 UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3356 __skb_queue_head(&ugeth->rx_recycle, skb);
3357 else
3358 dev_kfree_skb(skb);
3359
ce973b14
LY		 3360 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3361 ugeth->skb_dirtytx[txQ] =
3362 (ugeth->skb_dirtytx[txQ] +
3363 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3364
3365 /* We freed a buffer, so now we can restart transmission */
3366 if (netif_queue_stopped(dev))
3367 netif_wake_queue(dev);
3368
3369 /* Advance the confirmation BD pointer */
3370 if (!(bd_status & T_W))
a394f013 3371 bd += sizeof(struct qe_bd);
ce973b14 3372 else
a394f013 3373 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3374 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3375 }
a394f013 3376 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3377 return 0;
3378}
3379
bea3348e 3380static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3381{
bea3348e 3382 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3383 struct ucc_geth_info *ug_info;
bea3348e 3384 int howmany, i;
ce973b14 3385
702ff12c
MR		 3386 ug_info = ugeth->ug_info;
3387
0cededf3
JT		 3388 /* Tx event processing */
3389 spin_lock(&ugeth->lock);
3390 for (i = 0; i < ug_info->numQueuesTx; i++)
3391 ucc_geth_tx(ugeth->ndev, i);
3392 spin_unlock(&ugeth->lock);
3393
50f238fd
AV		 3394 howmany = 0;
3395 for (i = 0; i < ug_info->numQueuesRx; i++)
3396 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3397
bea3348e 3398 if (howmany < budget) {
288379f0 3399 napi_complete(napi);
0cededf3 3400 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3401 }
ce973b14 3402
bea3348e 3403 return howmany;
ce973b14 3404}
ce973b14 3405
7d12e780 3406static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3407{
06efcad0 3408 struct net_device *dev = info;
18a8e864
LY		 3409 struct ucc_geth_private *ugeth = netdev_priv(dev);
3410 struct ucc_fast_private *uccf;
3411 struct ucc_geth_info *ug_info;
702ff12c
MR		 3412 register u32 ucce;
3413 register u32 uccm;
ce973b14 3414
b39d66a8 3415 ugeth_vdbg("%s: IN", __func__);
ce973b14 3416
ce973b14
LY		 3417 uccf = ugeth->uccf;
3418 ug_info = ugeth->ug_info;
3419
702ff12c
MR		 3420 /* read and clear events */
3421 ucce = (u32) in_be32(uccf->p_ucce);
3422 uccm = (u32) in_be32(uccf->p_uccm);
3423 ucce &= uccm;
3424 out_be32(uccf->p_ucce, ucce);
ce973b14 3425
702ff12c 3426 /* check for receive events that require processing */
0cededf3 3427 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3428 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3429 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3430 out_be32(uccf->p_uccm, uccm);
288379f0 3431 __napi_schedule(&ugeth->napi);
702ff12c 3432 }
702ff12c 3433 }
ce973b14 3434
702ff12c
MR		 3435 /* Errors and other events */
3436 if (ucce & UCCE_OTHER) {
3bc53427 3437 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3438 dev->stats.rx_errors++;
3bc53427 3439 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3440 dev->stats.tx_errors++;
ce973b14 3441 }
ce973b14
LY		 3442
3443 return IRQ_HANDLED;
3444}
3445
26d29ea7
AV		 3446#ifdef CONFIG_NET_POLL_CONTROLLER
3447/*
3448 * Polling 'interrupt' - used by things like netconsole to send skbs
3449 * without having to re-enable interrupts. It's not called while
3450 * the interrupt routine is executing.
3451 */
3452static void ucc_netpoll(struct net_device *dev)
3453{
3454 struct ucc_geth_private *ugeth = netdev_priv(dev);
3455 int irq = ugeth->ug_info->uf_info.irq;
3456
3457 disable_irq(irq);
3458 ucc_geth_irq_handler(irq, dev);
3459 enable_irq(irq);
3460}
3461#endif /* CONFIG_NET_POLL_CONTROLLER */
3462
3d6593e9
KH		 3463static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3464{
3465 struct ucc_geth_private *ugeth = netdev_priv(dev);
3466 struct sockaddr *addr = p;
3467
3468 if (!is_valid_ether_addr(addr->sa_data))
3469 return -EADDRNOTAVAIL;
3470
3471 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3472
3473 /*
3474 * If device is not running, we will set mac addr register
3475 * when opening the device.
3476 */
3477 if (!netif_running(dev))
3478 return 0;
3479
3480 spin_lock_irq(&ugeth->lock);
3481 init_mac_station_addr_regs(dev->dev_addr[0],
3482 dev->dev_addr[1],
3483 dev->dev_addr[2],
3484 dev->dev_addr[3],
3485 dev->dev_addr[4],
3486 dev->dev_addr[5],
3487 &ugeth->ug_regs->macstnaddr1,
3488 &ugeth->ug_regs->macstnaddr2);
3489 spin_unlock_irq(&ugeth->lock);
3490
3491 return 0;
3492}
3493
54b15983 3494static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
ce973b14 3495{
54b15983 3496 struct net_device *dev = ugeth->ndev;
ce973b14
LY		 3497 int err;
3498
728de4c9
KP		 3499 err = ucc_struct_init(ugeth);
3500 if (err) {
890de95e 3501 if (netif_msg_ifup(ugeth))
54b15983
AV		 3502 ugeth_err("%s: Cannot configure internal struct, "
3503 "aborting.", dev->name);
3504 goto err;
728de4c9
KP		 3505 }
3506
ce973b14
LY		 3507 err = ucc_geth_startup(ugeth);
3508 if (err) {
890de95e
LY		 3509 if (netif_msg_ifup(ugeth))
3510 ugeth_err("%s: Cannot configure net device, aborting.",
3511 dev->name);
54b15983 3512 goto err;
ce973b14
LY		 3513 }
3514
3515 err = adjust_enet_interface(ugeth);
3516 if (err) {
890de95e
LY		 3517 if (netif_msg_ifup(ugeth))
3518 ugeth_err("%s: Cannot configure net device, aborting.",
3519 dev->name);
54b15983 3520 goto err;
ce973b14
LY		 3521 }
3522
3523 /* Set MACSTNADDR1, MACSTNADDR2 */
3524 /* For more details see the hardware spec. */
3525 init_mac_station_addr_regs(dev->dev_addr[0],
3526 dev->dev_addr[1],
3527 dev->dev_addr[2],
3528 dev->dev_addr[3],
3529 dev->dev_addr[4],
3530 dev->dev_addr[5],
3531 &ugeth->ug_regs->macstnaddr1,
3532 &ugeth->ug_regs->macstnaddr2);
3533
67c2fb8f 3534 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3535 if (err) {
890de95e 3536 if (netif_msg_ifup(ugeth))
67c2fb8f 3537 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
54b15983
AV		 3538 goto err;
3539 }
3540
3541 return 0;
3542err:
3543 ucc_geth_stop(ugeth);
3544 return err;
3545}
3546
3547/* Called when something needs to use the ethernet device */
3548/* Returns 0 for success. */
3549static int ucc_geth_open(struct net_device *dev)
3550{
3551 struct ucc_geth_private *ugeth = netdev_priv(dev);
3552 int err;
3553
3554 ugeth_vdbg("%s: IN", __func__);
3555
3556 /* Test station address */
3557 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3558 if (netif_msg_ifup(ugeth))
3559 ugeth_err("%s: Multicast address used for station "
3560 "address - is this what you wanted?",
3561 __func__);
3562 return -EINVAL;
3563 }
3564
3565 err = init_phy(dev);
3566 if (err) {
3567 if (netif_msg_ifup(ugeth))
3568 ugeth_err("%s: Cannot initialize PHY, aborting.",
3569 dev->name);
3570 return err;
3571 }
3572
3573 err = ucc_geth_init_mac(ugeth);
3574 if (err) {
3575 if (netif_msg_ifup(ugeth))
3576 ugeth_err("%s: Cannot initialize MAC, aborting.",
3577 dev->name);
3578 goto err;
ce973b14 3579 }
ce973b14 3580
67c2fb8f
AV		 3581 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3582 0, "UCC Geth", dev);
ce973b14 3583 if (err) {
890de95e 3584 if (netif_msg_ifup(ugeth))
67c2fb8f
AV		 3585 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3586 dev->name);
54b15983 3587 goto err;
ce973b14
LY		 3588 }
3589
54b15983
AV		 3590 phy_start(ugeth->phydev);
3591 napi_enable(&ugeth->napi);
ce973b14
LY		 3592 netif_start_queue(dev);
3593
2394905f
AV		 3594 device_set_wakeup_capable(&dev->dev,
3595 qe_alive_during_sleep() || ugeth->phydev->irq);
3596 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3597
ce973b14 3598 return err;
bea3348e 3599
54b15983 3600err:
ba574696 3601 ucc_geth_stop(ugeth);
bea3348e 3602 return err;
ce973b14
LY		 3603}
3604
3605/* Stops the kernel queue, and halts the controller */
3606static int ucc_geth_close(struct net_device *dev)
3607{
18a8e864 3608 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3609
b39d66a8 3610 ugeth_vdbg("%s: IN", __func__);
ce973b14 3611
bea3348e 3612 napi_disable(&ugeth->napi);
bea3348e 3613
2040bd57 3614 cancel_work_sync(&ugeth->timeout_work);
ce973b14 3615 ucc_geth_stop(ugeth);
2040bd57
JT		 3616 phy_disconnect(ugeth->phydev);
3617 ugeth->phydev = NULL;
ce973b14 3618
da1aa63e 3619 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3620
ce973b14
LY		 3621 netif_stop_queue(dev);
3622
3623 return 0;
3624}
3625
fdb614c2
AV		 3626/* Reopen device. This will reset the MAC and PHY. */
3627static void ucc_geth_timeout_work(struct work_struct *work)
3628{
3629 struct ucc_geth_private *ugeth;
3630 struct net_device *dev;
3631
3632 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3633 dev = ugeth->ndev;
fdb614c2
AV		 3634
3635 ugeth_vdbg("%s: IN", __func__);
3636
3637 dev->stats.tx_errors++;
3638
3639 ugeth_dump_regs(ugeth);
3640
3641 if (dev->flags & IFF_UP) {
3642 /*
3643 * Must reset MAC *and* PHY. This is done by reopening
3644 * the device.
3645 */
2040bd57
JT		 3646 netif_tx_stop_all_queues(dev);
3647 ucc_geth_stop(ugeth);
3648 ucc_geth_init_mac(ugeth);
3649 /* Must start PHY here */
3650 phy_start(ugeth->phydev);
3651 netif_tx_start_all_queues(dev);
fdb614c2
AV		 3652 }
3653
3654 netif_tx_schedule_all(dev);
3655}
3656
3657/*
3658 * ucc_geth_timeout gets called when a packet has not been
3659 * transmitted after a set amount of time.
3660 */
3661static void ucc_geth_timeout(struct net_device *dev)
3662{
3663 struct ucc_geth_private *ugeth = netdev_priv(dev);
3664
fdb614c2
AV		 3665 schedule_work(&ugeth->timeout_work);
3666}
3667
2394905f
AV		 3668
3669#ifdef CONFIG_PM
3670
2dc11581 3671static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
2394905f
AV		 3672{
3673 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3674 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3675
3676 if (!netif_running(ndev))
3677 return 0;
3678
29fb00e0 3679 netif_device_detach(ndev);
2394905f
AV		 3680 napi_disable(&ugeth->napi);
3681
3682 /*
3683 * Disable the controller, otherwise we'll wakeup on any network
3684 * activity.
3685 */
3686 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3687
3688 if (ugeth->wol_en & WAKE_MAGIC) {
3689 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3690 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3691 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3692 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3693 phy_stop(ugeth->phydev);
3694 }
3695
3696 return 0;
3697}
3698
2dc11581 3699static int ucc_geth_resume(struct platform_device *ofdev)
2394905f
AV		 3700{
3701 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3702 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3703 int err;
3704
3705 if (!netif_running(ndev))
3706 return 0;
3707
3708 if (qe_alive_during_sleep()) {
3709 if (ugeth->wol_en & WAKE_MAGIC) {
3710 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3711 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3712 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3713 }
3714 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3715 } else {
3716 /*
3717 * Full reinitialization is required if QE shuts down
3718 * during sleep.
3719 */
3720 ucc_geth_memclean(ugeth);
3721
3722 err = ucc_geth_init_mac(ugeth);
3723 if (err) {
3724 ugeth_err("%s: Cannot initialize MAC, aborting.",
3725 ndev->name);
3726 return err;
3727 }
3728 }
3729
3730 ugeth->oldlink = 0;
3731 ugeth->oldspeed = 0;
3732 ugeth->oldduplex = -1;
3733
3734 phy_stop(ugeth->phydev);
3735 phy_start(ugeth->phydev);
3736
3737 napi_enable(&ugeth->napi);
29fb00e0 3738 netif_device_attach(ndev);
2394905f
AV		 3739
3740 return 0;
3741}
3742
3743#else
3744#define ucc_geth_suspend NULL
3745#define ucc_geth_resume NULL
3746#endif
3747
4e19b5c1 3748static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3749{
4e19b5c1 3750 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3751 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3752 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3753 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3754 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3755 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3756 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3757 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3758 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3759 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3760 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3761 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3762 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3763 return PHY_INTERFACE_MODE_RGMII_TXID;
3764 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3765 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3766 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9 3767 return PHY_INTERFACE_MODE_RTBI;
047584ce
HW		 3768 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3769 return PHY_INTERFACE_MODE_SGMII;
728de4c9
KP		 3770
3771 return PHY_INTERFACE_MODE_MII;
3772}
3773
d19b5149
SM		 3774static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3775{
3776 struct ucc_geth_private *ugeth = netdev_priv(dev);
3777
3778 if (!netif_running(dev))
3779 return -EINVAL;
3780
3781 if (!ugeth->phydev)
3782 return -ENODEV;
3783
28b04113 3784 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
d19b5149
SM		 3785}
3786
a9dbae78
JT		 3787static const struct net_device_ops ucc_geth_netdev_ops = {
3788 .ndo_open = ucc_geth_open,
3789 .ndo_stop = ucc_geth_close,
3790 .ndo_start_xmit = ucc_geth_start_xmit,
3791 .ndo_validate_addr = eth_validate_addr,
3d6593e9 3792 .ndo_set_mac_address = ucc_geth_set_mac_addr,
a9dbae78 3793 .ndo_change_mtu = eth_change_mtu,
afc4b13d 3794 .ndo_set_rx_mode = ucc_geth_set_multi,
a9dbae78 3795 .ndo_tx_timeout = ucc_geth_timeout,
d19b5149 3796 .ndo_do_ioctl = ucc_geth_ioctl,
a9dbae78
JT		 3797#ifdef CONFIG_NET_POLL_CONTROLLER
3798 .ndo_poll_controller = ucc_netpoll,
3799#endif
3800};
3801
74888760 3802static int ucc_geth_probe(struct platform_device* ofdev)
ce973b14 3803{
18a8e864 3804 struct device *device = &ofdev->dev;
61c7a080 3805 struct device_node *np = ofdev->dev.of_node;
ce973b14
LY		 3806 struct net_device *dev = NULL;
3807 struct ucc_geth_private *ugeth = NULL;
3808 struct ucc_geth_info *ug_info;
18a8e864 3809 struct resource res;
728de4c9 3810 int err, ucc_num, max_speed = 0;
18a8e864 3811 const unsigned int *prop;
9fb1e350 3812 const char *sprop;
9b4c7a4e 3813 const void *mac_addr;
728de4c9
KP		 3814 phy_interface_t phy_interface;
3815 static const int enet_to_speed[] = {
3816 SPEED_10, SPEED_10, SPEED_10,
3817 SPEED_100, SPEED_100, SPEED_100,
3818 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3819 };
3820 static const phy_interface_t enet_to_phy_interface[] = {
3821 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3822 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3823 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3824 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3825 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
047584ce 3826 PHY_INTERFACE_MODE_SGMII,
728de4c9 3827 };
ce973b14 3828
b39d66a8 3829 ugeth_vdbg("%s: IN", __func__);
ce973b14 3830
56626f33
AV		 3831 prop = of_get_property(np, "cell-index", NULL);
3832 if (!prop) {
3833 prop = of_get_property(np, "device-id", NULL);
3834 if (!prop)
3835 return -ENODEV;
3836 }
3837
18a8e864
LY		 3838 ucc_num = *prop - 1;
3839 if ((ucc_num < 0) || (ucc_num > 7))
3840 return -ENODEV;
3841
3842 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3843 if (ug_info == NULL) {
3844 if (netif_msg_probe(&debug))
3845 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3846 __func__, ucc_num);
890de95e
LY		 3847 return -ENODEV;
3848 }
3849
18a8e864 3850 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3851
9fb1e350
TT		 3852 sprop = of_get_property(np, "rx-clock-name", NULL);
3853 if (sprop) {
3854 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3855 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3856 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3857 printk(KERN_ERR
3858 "ucc_geth: invalid rx-clock-name property\n");
3859 return -EINVAL;
3860 }
3861 } else {
3862 prop = of_get_property(np, "rx-clock", NULL);
3863 if (!prop) {
3864 /* If both rx-clock-name and rx-clock are missing,
3865 we want to tell people to use rx-clock-name. */
3866 printk(KERN_ERR
3867 "ucc_geth: missing rx-clock-name property\n");
3868 return -EINVAL;
3869 }
3870 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3871 printk(KERN_ERR
3872 "ucc_geth: invalid rx-clock propperty\n");
3873 return -EINVAL;
3874 }
3875 ug_info->uf_info.rx_clock = *prop;
3876 }
3877
3878 sprop = of_get_property(np, "tx-clock-name", NULL);
3879 if (sprop) {
3880 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3881 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3882 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3883 printk(KERN_ERR
3884 "ucc_geth: invalid tx-clock-name property\n");
3885 return -EINVAL;
3886 }
3887 } else {
e410553f 3888 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3889 if (!prop) {
3890 printk(KERN_ERR
af901ca1 3891 "ucc_geth: missing tx-clock-name property\n");
9fb1e350
TT		 3892 return -EINVAL;
3893 }
3894 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3895 printk(KERN_ERR
3896 "ucc_geth: invalid tx-clock property\n");
3897 return -EINVAL;
3898 }
3899 ug_info->uf_info.tx_clock = *prop;
3900 }
3901
18a8e864
LY		 3902 err = of_address_to_resource(np, 0, &res);
3903 if (err)
3904 return -EINVAL;
3905
3906 ug_info->uf_info.regs = res.start;
3907 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3104a6ff
AV		 3908
3909 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
728de4c9 3910
fb1001f3
HW		 3911 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3912 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3913
728de4c9 3914 /* get the phy interface type, or default to MII */
4e19b5c1 3915 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3916 if (!prop) {
3917 /* handle interface property present in old trees */
3104a6ff 3918 prop = of_get_property(ug_info->phy_node, "interface", NULL);
4e19b5c1 3919 if (prop != NULL) {
728de4c9 3920 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3921 max_speed = enet_to_speed[*prop];
3922 } else
728de4c9
KP		 3923 phy_interface = PHY_INTERFACE_MODE_MII;
3924 } else {
3925 phy_interface = to_phy_interface((const char *)prop);
3926 }
3927
4e19b5c1
KP		 3928 /* get speed, or derive from PHY interface */
3929 if (max_speed == 0)
728de4c9
KP		 3930 switch (phy_interface) {
3931 case PHY_INTERFACE_MODE_GMII:
3932 case PHY_INTERFACE_MODE_RGMII:
3933 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3934 case PHY_INTERFACE_MODE_RGMII_RXID:
3935 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3936 case PHY_INTERFACE_MODE_TBI:
3937 case PHY_INTERFACE_MODE_RTBI:
047584ce 3938 case PHY_INTERFACE_MODE_SGMII:
728de4c9
KP		 3939 max_speed = SPEED_1000;
3940 break;
3941 default:
3942 max_speed = SPEED_100;
3943 break;
3944 }
728de4c9
KP		 3945
3946 if (max_speed == SPEED_1000) {
fa1b42b4
DL		 3947 unsigned int snums = qe_get_num_of_snums();
3948
4e19b5c1 3949 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3950 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3951 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3952 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3953 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3954 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3955 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed 3956 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
674e4f93 3957
fa1b42b4 3958 /* If QE's snum number is 46/76 which means we need to support
674e4f93
HW		 3959 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3960 * more Threads to Rx.
3961 */
fa1b42b4 3962 if ((snums == 76) || (snums == 46))
674e4f93
HW		 3963 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3964 else
3965 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3966 }
3967
890de95e 3968 if (netif_msg_probe(&debug))
2381a55c 3969 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d)\n",
890de95e
LY		 3970 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3971 ug_info->uf_info.irq);
ce973b14 3972
ce973b14
LY		 3973 /* Create an ethernet device instance */
3974 dev = alloc_etherdev(sizeof(*ugeth));
3975
3976 if (dev == NULL)
3977 return -ENOMEM;
3978
3979 ugeth = netdev_priv(dev);
3980 spin_lock_init(&ugeth->lock);
3981
80a9fad8
AV		 3982 /* Create CQs for hash tables */
3983 INIT_LIST_HEAD(&ugeth->group_hash_q);
3984 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3985
ce973b14
LY		 3986 dev_set_drvdata(device, dev);
3987
3988 /* Set the dev->base_addr to the gfar reg region */
3989 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3990
ce973b14
LY		 3991 SET_NETDEV_DEV(dev, device);
3992
3993 /* Fill in the dev structure */
ac421852 3994 uec_set_ethtool_ops(dev);
a9dbae78 3995 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3996 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3997 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3998 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3999 dev->mtu = 1500;
ce973b14 4000
890de95e 4001 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 4002 ugeth->phy_interface = phy_interface;
4003 ugeth->max_speed = max_speed;
4004
ce973b14
LY		 4005 err = register_netdev(dev);
4006 if (err) {
890de95e
LY		 4007 if (netif_msg_probe(ugeth))
4008 ugeth_err("%s: Cannot register net device, aborting.",
4009 dev->name);
ce973b14
LY		 4010 free_netdev(dev);
4011 return err;
4012 }
4013
e9eb70c9 4014 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 4015 if (mac_addr)
4016 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 4017
728de4c9 4018 ugeth->ug_info = ug_info;
da1aa63e
AV		 4019 ugeth->dev = device;
4020 ugeth->ndev = dev;
b1c4a9dd 4021 ugeth->node = np;
728de4c9 4022
ce973b14
LY		 4023 return 0;
4024}
4025
2dc11581 4026static int ucc_geth_remove(struct platform_device* ofdev)
ce973b14 4027{
18a8e864 4028 struct device *device = &ofdev->dev;
ce973b14
LY		 4029 struct net_device *dev = dev_get_drvdata(device);
4030 struct ucc_geth_private *ugeth = netdev_priv(dev);
4031
80a9fad8 4032 unregister_netdev(dev);
ce973b14 4033 free_netdev(dev);
80a9fad8
AV		 4034 ucc_geth_memclean(ugeth);
4035 dev_set_drvdata(device, NULL);
ce973b14
LY		 4036
4037 return 0;
4038}
4039
18a8e864
LY		 4040static struct of_device_id ucc_geth_match[] = {
4041 {
4042 .type = "network",
4043 .compatible = "ucc_geth",
4044 },
4045 {},
4046};
4047
4048MODULE_DEVICE_TABLE(of, ucc_geth_match);
4049
74888760 4050static struct platform_driver ucc_geth_driver = {
4018294b
GL		 4051 .driver = {
4052 .name = DRV_NAME,
4053 .owner = THIS_MODULE,
4054 .of_match_table = ucc_geth_match,
4055 },
18a8e864
LY		 4056 .probe = ucc_geth_probe,
4057 .remove = ucc_geth_remove,
2394905f
AV		 4058 .suspend = ucc_geth_suspend,
4059 .resume = ucc_geth_resume,
ce973b14
LY		 4060};
4061
4062static int __init ucc_geth_init(void)
4063{
728de4c9
KP		 4064 int i, ret;
4065
890de95e
LY		 4066 if (netif_msg_drv(&debug))
4067 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 4068 for (i = 0; i < 8; i++)
4069 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4070 sizeof(ugeth_primary_info));
4071
74888760 4072 ret = platform_driver_register(&ucc_geth_driver);
728de4c9 4073
728de4c9 4074 return ret;
ce973b14
LY		 4075}
4076
4077static void __exit ucc_geth_exit(void)
4078{
74888760 4079 platform_driver_unregister(&ucc_geth_driver);
ce973b14
LY		 4080}
4081
4082module_init(ucc_geth_init);
4083module_exit(ucc_geth_exit);
4084
4085MODULE_AUTHOR("Freescale Semiconductor, Inc");
4086MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 4087MODULE_VERSION(DRV_VERSION);
ce973b14 4088MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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