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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/netdevice.h> | |
af22d9de | 37 | #include <linux/mlx4/driver.h> |
7202da8b | 38 | #include <linux/mlx4/device.h> |
f90a3673 HHZ |
39 | #include <linux/in.h> |
40 | #include <net/ip.h> | |
c27a02cd YP |
41 | |
42 | #include "mlx4_en.h" | |
43 | #include "en_port.h" | |
44 | ||
82067281 | 45 | #define EN_ETHTOOL_QP_ATTACH (1ull << 63) |
82067281 HHZ |
46 | #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) |
47 | #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) | |
c27a02cd | 48 | |
79c54b6b AV |
49 | static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) |
50 | { | |
51 | int i; | |
52 | int err = 0; | |
53 | ||
54 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
55 | priv->tx_cq[i]->moder_cnt = priv->tx_frames; |
56 | priv->tx_cq[i]->moder_time = priv->tx_usecs; | |
38463e2c | 57 | if (priv->port_up) { |
41d942d5 | 58 | err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]); |
38463e2c EE |
59 | if (err) |
60 | return err; | |
61 | } | |
79c54b6b AV |
62 | } |
63 | ||
64 | if (priv->adaptive_rx_coal) | |
65 | return 0; | |
66 | ||
67 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
68 | priv->rx_cq[i]->moder_cnt = priv->rx_frames; |
69 | priv->rx_cq[i]->moder_time = priv->rx_usecs; | |
79c54b6b | 70 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
38463e2c | 71 | if (priv->port_up) { |
41d942d5 | 72 | err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); |
38463e2c EE |
73 | if (err) |
74 | return err; | |
75 | } | |
79c54b6b AV |
76 | } |
77 | ||
78 | return err; | |
79 | } | |
80 | ||
c27a02cd YP |
81 | static void |
82 | mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) | |
83 | { | |
84 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
85 | struct mlx4_en_dev *mdev = priv->mdev; | |
86 | ||
612a94d6 RJ |
87 | strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); |
88 | strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")", | |
89 | sizeof(drvinfo->version)); | |
90 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
91 | "%d.%d.%d", | |
c27a02cd YP |
92 | (u16) (mdev->dev->caps.fw_ver >> 32), |
93 | (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), | |
94 | (u16) (mdev->dev->caps.fw_ver & 0xffff)); | |
612a94d6 RJ |
95 | strlcpy(drvinfo->bus_info, pci_name(mdev->dev->pdev), |
96 | sizeof(drvinfo->bus_info)); | |
c27a02cd YP |
97 | drvinfo->n_stats = 0; |
98 | drvinfo->regdump_len = 0; | |
99 | drvinfo->eedump_len = 0; | |
100 | } | |
101 | ||
0fef9d03 AV |
102 | static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { |
103 | "blueflame", | |
104 | }; | |
105 | ||
c27a02cd YP |
106 | static const char main_strings[][ETH_GSTRING_LEN] = { |
107 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", | |
108 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", | |
109 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", | |
110 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", | |
111 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", | |
112 | "tx_heartbeat_errors", "tx_window_errors", | |
113 | ||
114 | /* port statistics */ | |
fa37a958 | 115 | "tso_packets", |
9fab426d | 116 | "xmit_more", |
c27a02cd | 117 | "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed", |
f8c6455b | 118 | "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", |
c27a02cd YP |
119 | |
120 | /* packet statistics */ | |
121 | "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3", | |
122 | "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0", | |
123 | "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5", | |
124 | "tx_prio_6", "tx_prio_7", | |
125 | }; | |
d61702f1 | 126 | #define NUM_MAIN_STATS 21 |
c27a02cd YP |
127 | #define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + NUM_PERF_STATS) |
128 | ||
e7c1c2c4 | 129 | static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { |
fd9071ec | 130 | "Interrupt Test", |
e7c1c2c4 YP |
131 | "Link Test", |
132 | "Speed Test", | |
133 | "Register Test", | |
134 | "Loopback Test", | |
135 | }; | |
136 | ||
c27a02cd YP |
137 | static u32 mlx4_en_get_msglevel(struct net_device *dev) |
138 | { | |
139 | return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; | |
140 | } | |
141 | ||
142 | static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) | |
143 | { | |
144 | ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; | |
145 | } | |
146 | ||
147 | static void mlx4_en_get_wol(struct net_device *netdev, | |
148 | struct ethtool_wolinfo *wol) | |
149 | { | |
14c07b13 YP |
150 | struct mlx4_en_priv *priv = netdev_priv(netdev); |
151 | int err = 0; | |
152 | u64 config = 0; | |
559a9f1d | 153 | u64 mask; |
14c07b13 | 154 | |
559a9f1d OD |
155 | if ((priv->port < 1) || (priv->port > 2)) { |
156 | en_err(priv, "Failed to get WoL information\n"); | |
157 | return; | |
158 | } | |
159 | ||
160 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
161 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
162 | ||
163 | if (!(priv->mdev->dev->caps.flags & mask)) { | |
14c07b13 YP |
164 | wol->supported = 0; |
165 | wol->wolopts = 0; | |
166 | return; | |
167 | } | |
168 | ||
169 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | |
170 | if (err) { | |
171 | en_err(priv, "Failed to get WoL information\n"); | |
172 | return; | |
173 | } | |
174 | ||
175 | if (config & MLX4_EN_WOL_MAGIC) | |
176 | wol->supported = WAKE_MAGIC; | |
177 | else | |
178 | wol->supported = 0; | |
179 | ||
180 | if (config & MLX4_EN_WOL_ENABLED) | |
181 | wol->wolopts = WAKE_MAGIC; | |
182 | else | |
183 | wol->wolopts = 0; | |
184 | } | |
185 | ||
186 | static int mlx4_en_set_wol(struct net_device *netdev, | |
187 | struct ethtool_wolinfo *wol) | |
188 | { | |
189 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
190 | u64 config = 0; | |
191 | int err = 0; | |
559a9f1d OD |
192 | u64 mask; |
193 | ||
194 | if ((priv->port < 1) || (priv->port > 2)) | |
195 | return -EOPNOTSUPP; | |
196 | ||
197 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
198 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
14c07b13 | 199 | |
559a9f1d | 200 | if (!(priv->mdev->dev->caps.flags & mask)) |
14c07b13 YP |
201 | return -EOPNOTSUPP; |
202 | ||
203 | if (wol->supported & ~WAKE_MAGIC) | |
204 | return -EINVAL; | |
205 | ||
206 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | |
207 | if (err) { | |
208 | en_err(priv, "Failed to get WoL info, unable to modify\n"); | |
209 | return err; | |
210 | } | |
211 | ||
212 | if (wol->wolopts & WAKE_MAGIC) { | |
213 | config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | | |
214 | MLX4_EN_WOL_MAGIC; | |
215 | } else { | |
216 | config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); | |
217 | config |= MLX4_EN_WOL_DO_MODIFY; | |
218 | } | |
219 | ||
220 | err = mlx4_wol_write(priv->mdev->dev, config, priv->port); | |
221 | if (err) | |
222 | en_err(priv, "Failed to set WoL information\n"); | |
223 | ||
224 | return err; | |
c27a02cd YP |
225 | } |
226 | ||
227 | static int mlx4_en_get_sset_count(struct net_device *dev, int sset) | |
228 | { | |
229 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
93ece0c1 | 230 | int bit_count = hweight64(priv->stats_bitmap); |
c27a02cd | 231 | |
e7c1c2c4 YP |
232 | switch (sset) { |
233 | case ETH_SS_STATS: | |
93ece0c1 | 234 | return (priv->stats_bitmap ? bit_count : NUM_ALL_STATS) + |
8501841a | 235 | (priv->tx_ring_num * 2) + |
e0d1095a | 236 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8501841a AV |
237 | (priv->rx_ring_num * 5); |
238 | #else | |
239 | (priv->rx_ring_num * 2); | |
240 | #endif | |
e7c1c2c4 | 241 | case ETH_SS_TEST: |
ccf86321 OG |
242 | return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags |
243 | & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; | |
0fef9d03 AV |
244 | case ETH_SS_PRIV_FLAGS: |
245 | return ARRAY_SIZE(mlx4_en_priv_flags); | |
e7c1c2c4 | 246 | default: |
c27a02cd | 247 | return -EOPNOTSUPP; |
e7c1c2c4 | 248 | } |
c27a02cd YP |
249 | } |
250 | ||
251 | static void mlx4_en_get_ethtool_stats(struct net_device *dev, | |
252 | struct ethtool_stats *stats, uint64_t *data) | |
253 | { | |
254 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
255 | int index = 0; | |
93ece0c1 | 256 | int i, j = 0; |
c27a02cd YP |
257 | |
258 | spin_lock_bh(&priv->stats_lock); | |
259 | ||
93ece0c1 EE |
260 | if (!(priv->stats_bitmap)) { |
261 | for (i = 0; i < NUM_MAIN_STATS; i++) | |
262 | data[index++] = | |
263 | ((unsigned long *) &priv->stats)[i]; | |
264 | for (i = 0; i < NUM_PORT_STATS; i++) | |
265 | data[index++] = | |
266 | ((unsigned long *) &priv->port_stats)[i]; | |
267 | for (i = 0; i < NUM_PKT_STATS; i++) | |
268 | data[index++] = | |
269 | ((unsigned long *) &priv->pkstats)[i]; | |
270 | } else { | |
271 | for (i = 0; i < NUM_MAIN_STATS; i++) { | |
272 | if ((priv->stats_bitmap >> j) & 1) | |
273 | data[index++] = | |
274 | ((unsigned long *) &priv->stats)[i]; | |
275 | j++; | |
276 | } | |
277 | for (i = 0; i < NUM_PORT_STATS; i++) { | |
278 | if ((priv->stats_bitmap >> j) & 1) | |
279 | data[index++] = | |
280 | ((unsigned long *) &priv->port_stats)[i]; | |
281 | j++; | |
282 | } | |
283 | } | |
c27a02cd | 284 | for (i = 0; i < priv->tx_ring_num; i++) { |
41d942d5 EE |
285 | data[index++] = priv->tx_ring[i]->packets; |
286 | data[index++] = priv->tx_ring[i]->bytes; | |
c27a02cd YP |
287 | } |
288 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
289 | data[index++] = priv->rx_ring[i]->packets; |
290 | data[index++] = priv->rx_ring[i]->bytes; | |
e0d1095a | 291 | #ifdef CONFIG_NET_RX_BUSY_POLL |
41d942d5 EE |
292 | data[index++] = priv->rx_ring[i]->yields; |
293 | data[index++] = priv->rx_ring[i]->misses; | |
294 | data[index++] = priv->rx_ring[i]->cleaned; | |
8501841a | 295 | #endif |
c27a02cd | 296 | } |
c27a02cd YP |
297 | spin_unlock_bh(&priv->stats_lock); |
298 | ||
299 | } | |
300 | ||
e7c1c2c4 YP |
301 | static void mlx4_en_self_test(struct net_device *dev, |
302 | struct ethtool_test *etest, u64 *buf) | |
303 | { | |
304 | mlx4_en_ex_selftest(dev, &etest->flags, buf); | |
305 | } | |
306 | ||
c27a02cd YP |
307 | static void mlx4_en_get_strings(struct net_device *dev, |
308 | uint32_t stringset, uint8_t *data) | |
309 | { | |
310 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
311 | int index = 0; | |
312 | int i; | |
313 | ||
e7c1c2c4 YP |
314 | switch (stringset) { |
315 | case ETH_SS_TEST: | |
316 | for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) | |
317 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
ccf86321 | 318 | if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) |
e7c1c2c4 YP |
319 | for (; i < MLX4_EN_NUM_SELF_TEST; i++) |
320 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
321 | break; | |
322 | ||
323 | case ETH_SS_STATS: | |
324 | /* Add main counters */ | |
93ece0c1 EE |
325 | if (!priv->stats_bitmap) { |
326 | for (i = 0; i < NUM_MAIN_STATS; i++) | |
327 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
328 | main_strings[i]); | |
329 | for (i = 0; i < NUM_PORT_STATS; i++) | |
330 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
331 | main_strings[i + | |
332 | NUM_MAIN_STATS]); | |
333 | for (i = 0; i < NUM_PKT_STATS; i++) | |
334 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
335 | main_strings[i + | |
336 | NUM_MAIN_STATS + | |
337 | NUM_PORT_STATS]); | |
338 | } else | |
339 | for (i = 0; i < NUM_MAIN_STATS + NUM_PORT_STATS; i++) { | |
340 | if ((priv->stats_bitmap >> i) & 1) { | |
341 | strcpy(data + | |
342 | (index++) * ETH_GSTRING_LEN, | |
343 | main_strings[i]); | |
344 | } | |
345 | if (!(priv->stats_bitmap >> i)) | |
346 | break; | |
347 | } | |
e7c1c2c4 YP |
348 | for (i = 0; i < priv->tx_ring_num; i++) { |
349 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
350 | "tx%d_packets", i); | |
351 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
352 | "tx%d_bytes", i); | |
353 | } | |
354 | for (i = 0; i < priv->rx_ring_num; i++) { | |
355 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
356 | "rx%d_packets", i); | |
357 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
358 | "rx%d_bytes", i); | |
e0d1095a | 359 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8501841a AV |
360 | sprintf(data + (index++) * ETH_GSTRING_LEN, |
361 | "rx%d_napi_yield", i); | |
362 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
363 | "rx%d_misses", i); | |
364 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
365 | "rx%d_cleaned", i); | |
366 | #endif | |
e7c1c2c4 | 367 | } |
e7c1c2c4 | 368 | break; |
0fef9d03 AV |
369 | case ETH_SS_PRIV_FLAGS: |
370 | for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) | |
371 | strcpy(data + i * ETH_GSTRING_LEN, | |
372 | mlx4_en_priv_flags[i]); | |
373 | break; | |
374 | ||
e7c1c2c4 | 375 | } |
c27a02cd YP |
376 | } |
377 | ||
2c762679 SM |
378 | static u32 mlx4_en_autoneg_get(struct net_device *dev) |
379 | { | |
380 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
381 | struct mlx4_en_dev *mdev = priv->mdev; | |
382 | u32 autoneg = AUTONEG_DISABLE; | |
383 | ||
384 | if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && | |
385 | (priv->port_state.flags & MLX4_EN_PORT_ANE)) | |
386 | autoneg = AUTONEG_ENABLE; | |
387 | ||
388 | return autoneg; | |
389 | } | |
390 | ||
391 | static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg) | |
392 | { | |
393 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
394 | ||
395 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
396 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
397 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
398 | return SUPPORTED_TP; | |
399 | } | |
400 | ||
401 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
402 | | MLX4_PROT_MASK(MLX4_10GBASE_SR) | |
403 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
404 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4) | |
405 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
406 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
407 | return SUPPORTED_FIBRE; | |
408 | } | |
409 | ||
410 | if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
411 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) | |
412 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
413 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
414 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
415 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
416 | return SUPPORTED_Backplane; | |
417 | } | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) | |
422 | { | |
423 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); | |
424 | ||
425 | if (!eth_proto) /* link down */ | |
426 | eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
427 | ||
428 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
429 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
430 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
431 | return PORT_TP; | |
432 | } | |
433 | ||
434 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) | |
435 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
436 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
437 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
438 | return PORT_FIBRE; | |
439 | } | |
440 | ||
441 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
442 | | MLX4_PROT_MASK(MLX4_56GBASE_CR4) | |
443 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { | |
444 | return PORT_DA; | |
445 | } | |
446 | ||
447 | if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
448 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) | |
449 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
450 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
451 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
452 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
453 | return PORT_NONE; | |
454 | } | |
455 | return PORT_OTHER; | |
456 | } | |
457 | ||
458 | #define MLX4_LINK_MODES_SZ \ | |
459 | (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) | |
460 | ||
461 | enum ethtool_report { | |
462 | SUPPORTED = 0, | |
463 | ADVERTISED = 1, | |
464 | SPEED = 2 | |
465 | }; | |
466 | ||
467 | /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ | |
468 | static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = { | |
469 | [MLX4_100BASE_TX] = { | |
470 | SUPPORTED_100baseT_Full, | |
471 | ADVERTISED_100baseT_Full, | |
472 | SPEED_100 | |
473 | }, | |
474 | ||
475 | [MLX4_1000BASE_T] = { | |
476 | SUPPORTED_1000baseT_Full, | |
477 | ADVERTISED_1000baseT_Full, | |
478 | SPEED_1000 | |
479 | }, | |
480 | [MLX4_1000BASE_CX_SGMII] = { | |
481 | SUPPORTED_1000baseKX_Full, | |
482 | ADVERTISED_1000baseKX_Full, | |
483 | SPEED_1000 | |
484 | }, | |
485 | [MLX4_1000BASE_KX] = { | |
486 | SUPPORTED_1000baseKX_Full, | |
487 | ADVERTISED_1000baseKX_Full, | |
488 | SPEED_1000 | |
489 | }, | |
490 | ||
491 | [MLX4_10GBASE_T] = { | |
492 | SUPPORTED_10000baseT_Full, | |
493 | ADVERTISED_10000baseT_Full, | |
494 | SPEED_10000 | |
495 | }, | |
496 | [MLX4_10GBASE_CX4] = { | |
497 | SUPPORTED_10000baseKX4_Full, | |
498 | ADVERTISED_10000baseKX4_Full, | |
499 | SPEED_10000 | |
500 | }, | |
501 | [MLX4_10GBASE_KX4] = { | |
502 | SUPPORTED_10000baseKX4_Full, | |
503 | ADVERTISED_10000baseKX4_Full, | |
504 | SPEED_10000 | |
505 | }, | |
506 | [MLX4_10GBASE_KR] = { | |
507 | SUPPORTED_10000baseKR_Full, | |
508 | ADVERTISED_10000baseKR_Full, | |
509 | SPEED_10000 | |
510 | }, | |
511 | [MLX4_10GBASE_CR] = { | |
512 | SUPPORTED_10000baseKR_Full, | |
513 | ADVERTISED_10000baseKR_Full, | |
514 | SPEED_10000 | |
515 | }, | |
516 | [MLX4_10GBASE_SR] = { | |
517 | SUPPORTED_10000baseKR_Full, | |
518 | ADVERTISED_10000baseKR_Full, | |
519 | SPEED_10000 | |
520 | }, | |
521 | ||
522 | [MLX4_20GBASE_KR2] = { | |
523 | SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full, | |
524 | ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full, | |
525 | SPEED_20000 | |
526 | }, | |
527 | ||
528 | [MLX4_40GBASE_CR4] = { | |
529 | SUPPORTED_40000baseCR4_Full, | |
530 | ADVERTISED_40000baseCR4_Full, | |
531 | SPEED_40000 | |
532 | }, | |
533 | [MLX4_40GBASE_KR4] = { | |
534 | SUPPORTED_40000baseKR4_Full, | |
535 | ADVERTISED_40000baseKR4_Full, | |
536 | SPEED_40000 | |
537 | }, | |
538 | [MLX4_40GBASE_SR4] = { | |
539 | SUPPORTED_40000baseSR4_Full, | |
540 | ADVERTISED_40000baseSR4_Full, | |
541 | SPEED_40000 | |
542 | }, | |
543 | ||
544 | [MLX4_56GBASE_KR4] = { | |
545 | SUPPORTED_56000baseKR4_Full, | |
546 | ADVERTISED_56000baseKR4_Full, | |
547 | SPEED_56000 | |
548 | }, | |
549 | [MLX4_56GBASE_CR4] = { | |
550 | SUPPORTED_56000baseCR4_Full, | |
551 | ADVERTISED_56000baseCR4_Full, | |
552 | SPEED_56000 | |
553 | }, | |
554 | [MLX4_56GBASE_SR4] = { | |
555 | SUPPORTED_56000baseSR4_Full, | |
556 | ADVERTISED_56000baseSR4_Full, | |
557 | SPEED_56000 | |
558 | }, | |
559 | }; | |
560 | ||
561 | static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report) | |
562 | { | |
563 | int i; | |
564 | u32 link_modes = 0; | |
565 | ||
566 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
567 | if (eth_proto & MLX4_PROT_MASK(i)) | |
568 | link_modes |= ptys2ethtool_map[i][report]; | |
569 | } | |
570 | return link_modes; | |
571 | } | |
572 | ||
d48b3ab4 SM |
573 | static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report) |
574 | { | |
575 | int i; | |
576 | u32 ptys_modes = 0; | |
577 | ||
578 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
579 | if (ptys2ethtool_map[i][report] & link_modes) | |
580 | ptys_modes |= 1 << i; | |
581 | } | |
582 | return ptys_modes; | |
583 | } | |
584 | ||
585 | /* Convert actual speed (SPEED_XXX) to ptys link modes */ | |
586 | static u32 speed2ptys_link_modes(u32 speed) | |
587 | { | |
588 | int i; | |
589 | u32 ptys_modes = 0; | |
590 | ||
591 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
592 | if (ptys2ethtool_map[i][SPEED] == speed) | |
593 | ptys_modes |= 1 << i; | |
594 | } | |
595 | return ptys_modes; | |
596 | } | |
597 | ||
2c762679 SM |
598 | static int ethtool_get_ptys_settings(struct net_device *dev, |
599 | struct ethtool_cmd *cmd) | |
600 | { | |
601 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
602 | struct mlx4_ptys_reg ptys_reg; | |
603 | u32 eth_proto; | |
604 | int ret; | |
605 | ||
606 | memset(&ptys_reg, 0, sizeof(ptys_reg)); | |
607 | ptys_reg.local_port = priv->port; | |
608 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
609 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
610 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
611 | if (ret) { | |
612 | en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", | |
613 | ret); | |
614 | return ret; | |
615 | } | |
616 | en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", | |
617 | ptys_reg.proto_mask); | |
618 | en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", | |
619 | be32_to_cpu(ptys_reg.eth_proto_cap)); | |
620 | en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", | |
621 | be32_to_cpu(ptys_reg.eth_proto_admin)); | |
622 | en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", | |
623 | be32_to_cpu(ptys_reg.eth_proto_oper)); | |
624 | en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", | |
625 | be32_to_cpu(ptys_reg.eth_proto_lp_adv)); | |
626 | ||
627 | cmd->supported = 0; | |
628 | cmd->advertising = 0; | |
629 | ||
630 | cmd->supported |= ptys_get_supported_port(&ptys_reg); | |
631 | ||
632 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); | |
633 | cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED); | |
634 | ||
635 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); | |
636 | cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED); | |
637 | ||
638 | cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; | |
639 | cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0; | |
640 | ||
641 | cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ? | |
642 | ADVERTISED_Asym_Pause : 0; | |
643 | ||
644 | cmd->port = ptys_get_active_port(&ptys_reg); | |
645 | cmd->transceiver = (SUPPORTED_TP & cmd->supported) ? | |
646 | XCVR_EXTERNAL : XCVR_INTERNAL; | |
647 | ||
648 | if (mlx4_en_autoneg_get(dev)) { | |
649 | cmd->supported |= SUPPORTED_Autoneg; | |
650 | cmd->advertising |= ADVERTISED_Autoneg; | |
651 | } | |
652 | ||
653 | cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? | |
654 | AUTONEG_ENABLE : AUTONEG_DISABLE; | |
655 | ||
656 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); | |
657 | cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED); | |
658 | ||
659 | cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ? | |
660 | ADVERTISED_Autoneg : 0; | |
661 | ||
662 | cmd->phy_address = 0; | |
663 | cmd->mdio_support = 0; | |
664 | cmd->maxtxpkt = 0; | |
665 | cmd->maxrxpkt = 0; | |
666 | cmd->eth_tp_mdix = ETH_TP_MDI_INVALID; | |
667 | cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
672 | static void ethtool_get_default_settings(struct net_device *dev, | |
673 | struct ethtool_cmd *cmd) | |
c27a02cd | 674 | { |
7699517d YP |
675 | struct mlx4_en_priv *priv = netdev_priv(dev); |
676 | int trans_type; | |
677 | ||
c27a02cd YP |
678 | cmd->autoneg = AUTONEG_DISABLE; |
679 | cmd->supported = SUPPORTED_10000baseT_Full; | |
7699517d | 680 | cmd->advertising = ADVERTISED_10000baseT_Full; |
2c762679 | 681 | trans_type = priv->port_state.transceiver; |
7699517d YP |
682 | |
683 | if (trans_type > 0 && trans_type <= 0xC) { | |
684 | cmd->port = PORT_FIBRE; | |
685 | cmd->transceiver = XCVR_EXTERNAL; | |
686 | cmd->supported |= SUPPORTED_FIBRE; | |
687 | cmd->advertising |= ADVERTISED_FIBRE; | |
688 | } else if (trans_type == 0x80 || trans_type == 0) { | |
689 | cmd->port = PORT_TP; | |
690 | cmd->transceiver = XCVR_INTERNAL; | |
691 | cmd->supported |= SUPPORTED_TP; | |
692 | cmd->advertising |= ADVERTISED_TP; | |
693 | } else { | |
694 | cmd->port = -1; | |
695 | cmd->transceiver = -1; | |
696 | } | |
2c762679 SM |
697 | } |
698 | ||
699 | static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
700 | { | |
701 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
702 | int ret = -EINVAL; | |
703 | ||
704 | if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) | |
705 | return -ENOMEM; | |
706 | ||
707 | en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", | |
708 | priv->port_state.flags & MLX4_EN_PORT_ANC, | |
709 | priv->port_state.flags & MLX4_EN_PORT_ANE); | |
710 | ||
711 | if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) | |
712 | ret = ethtool_get_ptys_settings(dev, cmd); | |
713 | if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ | |
714 | ethtool_get_default_settings(dev, cmd); | |
715 | ||
716 | if (netif_carrier_ok(dev)) { | |
717 | ethtool_cmd_speed_set(cmd, priv->port_state.link_speed); | |
718 | cmd->duplex = DUPLEX_FULL; | |
719 | } else { | |
720 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); | |
721 | cmd->duplex = DUPLEX_UNKNOWN; | |
722 | } | |
c27a02cd YP |
723 | return 0; |
724 | } | |
725 | ||
d48b3ab4 SM |
726 | /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ |
727 | static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, | |
728 | __be32 proto_cap) | |
729 | { | |
730 | __be32 proto_admin = 0; | |
731 | ||
732 | if (!speed) { /* Speed = 0 ==> Reset Link modes */ | |
733 | proto_admin = proto_cap; | |
734 | en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", | |
735 | be32_to_cpu(proto_cap)); | |
736 | } else { | |
737 | u32 ptys_link_modes = speed2ptys_link_modes(speed); | |
738 | ||
739 | proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; | |
740 | en_info(priv, "Setting Speed to %d\n", speed); | |
741 | } | |
742 | return proto_admin; | |
743 | } | |
744 | ||
c27a02cd YP |
745 | static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
746 | { | |
d48b3ab4 SM |
747 | struct mlx4_en_priv *priv = netdev_priv(dev); |
748 | struct mlx4_ptys_reg ptys_reg; | |
749 | __be32 proto_admin; | |
750 | int ret; | |
751 | ||
752 | u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED); | |
753 | int speed = ethtool_cmd_speed(cmd); | |
754 | ||
755 | en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n", | |
756 | speed, cmd->advertising, cmd->autoneg, cmd->duplex); | |
757 | ||
758 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || | |
312df74c | 759 | (cmd->duplex == DUPLEX_HALF)) |
c27a02cd YP |
760 | return -EINVAL; |
761 | ||
d48b3ab4 SM |
762 | memset(&ptys_reg, 0, sizeof(ptys_reg)); |
763 | ptys_reg.local_port = priv->port; | |
764 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
765 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
766 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
767 | if (ret) { | |
768 | en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", | |
769 | ret); | |
770 | return 0; | |
771 | } | |
772 | ||
773 | proto_admin = cpu_to_be32(ptys_adv); | |
774 | if (speed >= 0 && speed != priv->port_state.link_speed) | |
775 | /* If speed was set then speed decides :-) */ | |
776 | proto_admin = speed_set_ptys_admin(priv, speed, | |
777 | ptys_reg.eth_proto_cap); | |
778 | ||
779 | proto_admin &= ptys_reg.eth_proto_cap; | |
780 | ||
781 | if (proto_admin == ptys_reg.eth_proto_admin) | |
782 | return 0; /* Nothing to change */ | |
783 | ||
784 | if (!proto_admin) { | |
785 | en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); | |
786 | return -EINVAL; /* nothing to change due to bad input */ | |
787 | } | |
788 | ||
789 | en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", | |
790 | be32_to_cpu(proto_admin)); | |
791 | ||
792 | ptys_reg.eth_proto_admin = proto_admin; | |
793 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, | |
794 | &ptys_reg); | |
795 | if (ret) { | |
796 | en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", | |
797 | be32_to_cpu(ptys_reg.eth_proto_admin), ret); | |
798 | return ret; | |
799 | } | |
800 | ||
801 | en_warn(priv, "Port link mode changed, restarting port...\n"); | |
802 | mutex_lock(&priv->mdev->state_lock); | |
803 | if (priv->port_up) { | |
804 | mlx4_en_stop_port(dev, 1); | |
805 | if (mlx4_en_start_port(dev)) | |
806 | en_err(priv, "Failed restarting port %d\n", priv->port); | |
807 | } | |
808 | mutex_unlock(&priv->mdev->state_lock); | |
c27a02cd YP |
809 | return 0; |
810 | } | |
811 | ||
812 | static int mlx4_en_get_coalesce(struct net_device *dev, | |
813 | struct ethtool_coalesce *coal) | |
814 | { | |
815 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
816 | ||
a19a848a YP |
817 | coal->tx_coalesce_usecs = priv->tx_usecs; |
818 | coal->tx_max_coalesced_frames = priv->tx_frames; | |
fbc6daf1 AV |
819 | coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; |
820 | ||
c27a02cd YP |
821 | coal->rx_coalesce_usecs = priv->rx_usecs; |
822 | coal->rx_max_coalesced_frames = priv->rx_frames; | |
823 | ||
824 | coal->pkt_rate_low = priv->pkt_rate_low; | |
825 | coal->rx_coalesce_usecs_low = priv->rx_usecs_low; | |
826 | coal->pkt_rate_high = priv->pkt_rate_high; | |
827 | coal->rx_coalesce_usecs_high = priv->rx_usecs_high; | |
828 | coal->rate_sample_interval = priv->sample_interval; | |
829 | coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; | |
fbc6daf1 | 830 | |
c27a02cd YP |
831 | return 0; |
832 | } | |
833 | ||
834 | static int mlx4_en_set_coalesce(struct net_device *dev, | |
835 | struct ethtool_coalesce *coal) | |
836 | { | |
837 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 838 | |
fbc6daf1 AV |
839 | if (!coal->tx_max_coalesced_frames_irq) |
840 | return -EINVAL; | |
841 | ||
c27a02cd YP |
842 | priv->rx_frames = (coal->rx_max_coalesced_frames == |
843 | MLX4_EN_AUTO_CONF) ? | |
3db36fb2 | 844 | MLX4_EN_RX_COAL_TARGET : |
c27a02cd YP |
845 | coal->rx_max_coalesced_frames; |
846 | priv->rx_usecs = (coal->rx_coalesce_usecs == | |
847 | MLX4_EN_AUTO_CONF) ? | |
848 | MLX4_EN_RX_COAL_TIME : | |
849 | coal->rx_coalesce_usecs; | |
850 | ||
a19a848a YP |
851 | /* Setting TX coalescing parameters */ |
852 | if (coal->tx_coalesce_usecs != priv->tx_usecs || | |
853 | coal->tx_max_coalesced_frames != priv->tx_frames) { | |
854 | priv->tx_usecs = coal->tx_coalesce_usecs; | |
855 | priv->tx_frames = coal->tx_max_coalesced_frames; | |
a19a848a YP |
856 | } |
857 | ||
c27a02cd YP |
858 | /* Set adaptive coalescing params */ |
859 | priv->pkt_rate_low = coal->pkt_rate_low; | |
860 | priv->rx_usecs_low = coal->rx_coalesce_usecs_low; | |
861 | priv->pkt_rate_high = coal->pkt_rate_high; | |
862 | priv->rx_usecs_high = coal->rx_coalesce_usecs_high; | |
863 | priv->sample_interval = coal->rate_sample_interval; | |
864 | priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; | |
fbc6daf1 | 865 | priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; |
c27a02cd | 866 | |
79c54b6b | 867 | return mlx4_en_moderation_update(priv); |
c27a02cd YP |
868 | } |
869 | ||
870 | static int mlx4_en_set_pauseparam(struct net_device *dev, | |
871 | struct ethtool_pauseparam *pause) | |
872 | { | |
873 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
874 | struct mlx4_en_dev *mdev = priv->mdev; | |
875 | int err; | |
876 | ||
278d436a IV |
877 | if (pause->autoneg) |
878 | return -EINVAL; | |
879 | ||
d53b93f2 YP |
880 | priv->prof->tx_pause = pause->tx_pause != 0; |
881 | priv->prof->rx_pause = pause->rx_pause != 0; | |
c27a02cd YP |
882 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
883 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
884 | priv->prof->tx_pause, |
885 | priv->prof->tx_ppp, | |
886 | priv->prof->rx_pause, | |
887 | priv->prof->rx_ppp); | |
c27a02cd | 888 | if (err) |
453a6082 | 889 | en_err(priv, "Failed setting pause params\n"); |
c27a02cd YP |
890 | |
891 | return err; | |
892 | } | |
893 | ||
894 | static void mlx4_en_get_pauseparam(struct net_device *dev, | |
895 | struct ethtool_pauseparam *pause) | |
896 | { | |
897 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 898 | |
d53b93f2 YP |
899 | pause->tx_pause = priv->prof->tx_pause; |
900 | pause->rx_pause = priv->prof->rx_pause; | |
c27a02cd YP |
901 | } |
902 | ||
18cc42a3 YP |
903 | static int mlx4_en_set_ringparam(struct net_device *dev, |
904 | struct ethtool_ringparam *param) | |
905 | { | |
906 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
907 | struct mlx4_en_dev *mdev = priv->mdev; | |
908 | u32 rx_size, tx_size; | |
909 | int port_up = 0; | |
910 | int err = 0; | |
911 | ||
912 | if (param->rx_jumbo_pending || param->rx_mini_pending) | |
913 | return -EINVAL; | |
914 | ||
915 | rx_size = roundup_pow_of_two(param->rx_pending); | |
916 | rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); | |
bd531e36 | 917 | rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); |
18cc42a3 YP |
918 | tx_size = roundup_pow_of_two(param->tx_pending); |
919 | tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); | |
bd531e36 | 920 | tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); |
18cc42a3 | 921 | |
41d942d5 EE |
922 | if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : |
923 | priv->rx_ring[0]->size) && | |
924 | tx_size == priv->tx_ring[0]->size) | |
18cc42a3 YP |
925 | return 0; |
926 | ||
927 | mutex_lock(&mdev->state_lock); | |
928 | if (priv->port_up) { | |
929 | port_up = 1; | |
3484aac1 | 930 | mlx4_en_stop_port(dev, 1); |
18cc42a3 YP |
931 | } |
932 | ||
fe0af03c | 933 | mlx4_en_free_resources(priv); |
18cc42a3 YP |
934 | |
935 | priv->prof->tx_ring_size = tx_size; | |
936 | priv->prof->rx_ring_size = rx_size; | |
937 | ||
938 | err = mlx4_en_alloc_resources(priv); | |
939 | if (err) { | |
453a6082 | 940 | en_err(priv, "Failed reallocating port resources\n"); |
18cc42a3 YP |
941 | goto out; |
942 | } | |
943 | if (port_up) { | |
944 | err = mlx4_en_start_port(dev); | |
945 | if (err) | |
453a6082 | 946 | en_err(priv, "Failed starting port\n"); |
18cc42a3 YP |
947 | } |
948 | ||
79c54b6b | 949 | err = mlx4_en_moderation_update(priv); |
6b4d8d9f | 950 | |
18cc42a3 YP |
951 | out: |
952 | mutex_unlock(&mdev->state_lock); | |
953 | return err; | |
954 | } | |
955 | ||
c27a02cd YP |
956 | static void mlx4_en_get_ringparam(struct net_device *dev, |
957 | struct ethtool_ringparam *param) | |
958 | { | |
959 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
960 | |
961 | memset(param, 0, sizeof(*param)); | |
bd531e36 YP |
962 | param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; |
963 | param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; | |
bc081cec | 964 | param->rx_pending = priv->port_up ? |
41d942d5 EE |
965 | priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; |
966 | param->tx_pending = priv->tx_ring[0]->size; | |
c27a02cd YP |
967 | } |
968 | ||
93d3e367 YP |
969 | static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) |
970 | { | |
971 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
972 | ||
973 | return priv->rx_ring_num; | |
974 | } | |
975 | ||
b9d1ab7e ED |
976 | static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) |
977 | { | |
978 | return MLX4_EN_RSS_KEY_SIZE; | |
979 | } | |
980 | ||
fe62d001 | 981 | static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key) |
93d3e367 YP |
982 | { |
983 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
984 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
985 | int rss_rings; | |
986 | size_t n = priv->rx_ring_num; | |
987 | int err = 0; | |
988 | ||
989 | rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num; | |
d5ec899a | 990 | rss_rings = 1 << ilog2(rss_rings); |
93d3e367 YP |
991 | |
992 | while (n--) { | |
993 | ring_index[n] = rss_map->qps[n % rss_rings].qpn - | |
994 | rss_map->base_qpn; | |
995 | } | |
b9d1ab7e ED |
996 | if (key) |
997 | netdev_rss_key_fill(key, MLX4_EN_RSS_KEY_SIZE); | |
93d3e367 YP |
998 | return err; |
999 | } | |
1000 | ||
fe62d001 BH |
1001 | static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, |
1002 | const u8 *key) | |
93d3e367 YP |
1003 | { |
1004 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1005 | struct mlx4_en_dev *mdev = priv->mdev; | |
1006 | int port_up = 0; | |
1007 | int err = 0; | |
1008 | int i; | |
1009 | int rss_rings = 0; | |
1010 | ||
1011 | /* Calculate RSS table size and make sure flows are spread evenly | |
1012 | * between rings | |
1013 | */ | |
1014 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1015 | if (i > 0 && !ring_index[i] && !rss_rings) | |
1016 | rss_rings = i; | |
1017 | ||
1018 | if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num))) | |
1019 | return -EINVAL; | |
1020 | } | |
1021 | ||
1022 | if (!rss_rings) | |
1023 | rss_rings = priv->rx_ring_num; | |
1024 | ||
1025 | /* RSS table size must be an order of 2 */ | |
1026 | if (!is_power_of_2(rss_rings)) | |
1027 | return -EINVAL; | |
1028 | ||
1029 | mutex_lock(&mdev->state_lock); | |
1030 | if (priv->port_up) { | |
1031 | port_up = 1; | |
3484aac1 | 1032 | mlx4_en_stop_port(dev, 1); |
93d3e367 YP |
1033 | } |
1034 | ||
1035 | priv->prof->rss_rings = rss_rings; | |
1036 | ||
1037 | if (port_up) { | |
1038 | err = mlx4_en_start_port(dev); | |
1039 | if (err) | |
1040 | en_err(priv, "Failed starting port\n"); | |
1041 | } | |
1042 | ||
1043 | mutex_unlock(&mdev->state_lock); | |
1044 | return err; | |
1045 | } | |
1046 | ||
82067281 HHZ |
1047 | #define all_zeros_or_all_ones(field) \ |
1048 | ((field) == 0 || (field) == (__force typeof(field))-1) | |
1049 | ||
1050 | static int mlx4_en_validate_flow(struct net_device *dev, | |
1051 | struct ethtool_rxnfc *cmd) | |
1052 | { | |
1053 | struct ethtool_usrip4_spec *l3_mask; | |
1054 | struct ethtool_tcpip4_spec *l4_mask; | |
1055 | struct ethhdr *eth_mask; | |
82067281 HHZ |
1056 | |
1057 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1058 | return -EINVAL; | |
1059 | ||
520dfe3a YB |
1060 | if (cmd->fs.flow_type & FLOW_MAC_EXT) { |
1061 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
1062 | if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { | |
82067281 HHZ |
1067 | case TCP_V4_FLOW: |
1068 | case UDP_V4_FLOW: | |
1069 | if (cmd->fs.m_u.tcp_ip4_spec.tos) | |
1070 | return -EINVAL; | |
1071 | l4_mask = &cmd->fs.m_u.tcp_ip4_spec; | |
1072 | /* don't allow mask which isn't all 0 or 1 */ | |
1073 | if (!all_zeros_or_all_ones(l4_mask->ip4src) || | |
1074 | !all_zeros_or_all_ones(l4_mask->ip4dst) || | |
1075 | !all_zeros_or_all_ones(l4_mask->psrc) || | |
1076 | !all_zeros_or_all_ones(l4_mask->pdst)) | |
1077 | return -EINVAL; | |
1078 | break; | |
1079 | case IP_USER_FLOW: | |
1080 | l3_mask = &cmd->fs.m_u.usr_ip4_spec; | |
1081 | if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || | |
1082 | cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || | |
1083 | (!l3_mask->ip4src && !l3_mask->ip4dst) || | |
1084 | !all_zeros_or_all_ones(l3_mask->ip4src) || | |
1085 | !all_zeros_or_all_ones(l3_mask->ip4dst)) | |
1086 | return -EINVAL; | |
1087 | break; | |
1088 | case ETHER_FLOW: | |
1089 | eth_mask = &cmd->fs.m_u.ether_spec; | |
1090 | /* source mac mask must not be set */ | |
c402b947 | 1091 | if (!is_zero_ether_addr(eth_mask->h_source)) |
82067281 HHZ |
1092 | return -EINVAL; |
1093 | ||
1094 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
c402b947 | 1095 | if (!is_broadcast_ether_addr(eth_mask->h_dest)) |
82067281 HHZ |
1096 | return -EINVAL; |
1097 | ||
1098 | if (!all_zeros_or_all_ones(eth_mask->h_proto)) | |
1099 | return -EINVAL; | |
1100 | break; | |
1101 | default: | |
1102 | return -EINVAL; | |
1103 | } | |
1104 | ||
1105 | if ((cmd->fs.flow_type & FLOW_EXT)) { | |
1106 | if (cmd->fs.m_ext.vlan_etype || | |
8258bd27 HHZ |
1107 | !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == |
1108 | 0 || | |
1109 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == | |
1110 | cpu_to_be16(VLAN_VID_MASK))) | |
82067281 | 1111 | return -EINVAL; |
8258bd27 | 1112 | |
69d7126b HHZ |
1113 | if (cmd->fs.m_ext.vlan_tci) { |
1114 | if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) | |
1115 | return -EINVAL; | |
8258bd27 | 1116 | |
69d7126b | 1117 | } |
82067281 HHZ |
1118 | } |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
f90a3673 HHZ |
1123 | static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, |
1124 | struct list_head *rule_list_h, | |
1125 | struct mlx4_spec_list *spec_l2, | |
1126 | unsigned char *mac) | |
1127 | { | |
1128 | int err = 0; | |
1129 | __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); | |
1130 | ||
1131 | spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; | |
1132 | memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); | |
1133 | memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); | |
1134 | ||
8258bd27 HHZ |
1135 | if ((cmd->fs.flow_type & FLOW_EXT) && |
1136 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { | |
f90a3673 | 1137 | spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; |
8258bd27 | 1138 | spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); |
f90a3673 HHZ |
1139 | } |
1140 | ||
1141 | list_add_tail(&spec_l2->list, rule_list_h); | |
1142 | ||
1143 | return err; | |
1144 | } | |
1145 | ||
1146 | static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, | |
1147 | struct ethtool_rxnfc *cmd, | |
1148 | struct list_head *rule_list_h, | |
1149 | struct mlx4_spec_list *spec_l2, | |
1150 | __be32 ipv4_dst) | |
1151 | { | |
f9d96862 | 1152 | #ifdef CONFIG_INET |
f90a3673 HHZ |
1153 | unsigned char mac[ETH_ALEN]; |
1154 | ||
1155 | if (!ipv4_is_multicast(ipv4_dst)) { | |
6bbb6d99 | 1156 | if (cmd->fs.flow_type & FLOW_MAC_EXT) |
f90a3673 | 1157 | memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); |
6bbb6d99 YB |
1158 | else |
1159 | memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); | |
f90a3673 HHZ |
1160 | } else { |
1161 | ip_eth_mc_map(ipv4_dst, mac); | |
1162 | } | |
1163 | ||
1164 | return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); | |
f9d96862 HHZ |
1165 | #else |
1166 | return -EINVAL; | |
1167 | #endif | |
f90a3673 HHZ |
1168 | } |
1169 | ||
82067281 | 1170 | static int add_ip_rule(struct mlx4_en_priv *priv, |
f90a3673 HHZ |
1171 | struct ethtool_rxnfc *cmd, |
1172 | struct list_head *list_h) | |
82067281 | 1173 | { |
377d9739 | 1174 | int err; |
f90a3673 HHZ |
1175 | struct mlx4_spec_list *spec_l2 = NULL; |
1176 | struct mlx4_spec_list *spec_l3 = NULL; | |
82067281 HHZ |
1177 | struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; |
1178 | ||
f90a3673 HHZ |
1179 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); |
1180 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); | |
1181 | if (!spec_l2 || !spec_l3) { | |
377d9739 HHZ |
1182 | err = -ENOMEM; |
1183 | goto free_spec; | |
82067281 HHZ |
1184 | } |
1185 | ||
377d9739 HHZ |
1186 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, |
1187 | cmd->fs.h_u. | |
1188 | usr_ip4_spec.ip4dst); | |
1189 | if (err) | |
1190 | goto free_spec; | |
82067281 HHZ |
1191 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; |
1192 | spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; | |
1193 | if (l3_mask->ip4src) | |
1194 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1195 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; | |
1196 | if (l3_mask->ip4dst) | |
1197 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1198 | list_add_tail(&spec_l3->list, list_h); | |
1199 | ||
1200 | return 0; | |
377d9739 HHZ |
1201 | |
1202 | free_spec: | |
1203 | kfree(spec_l2); | |
1204 | kfree(spec_l3); | |
1205 | return err; | |
82067281 HHZ |
1206 | } |
1207 | ||
1208 | static int add_tcp_udp_rule(struct mlx4_en_priv *priv, | |
1209 | struct ethtool_rxnfc *cmd, | |
1210 | struct list_head *list_h, int proto) | |
1211 | { | |
377d9739 | 1212 | int err; |
f90a3673 HHZ |
1213 | struct mlx4_spec_list *spec_l2 = NULL; |
1214 | struct mlx4_spec_list *spec_l3 = NULL; | |
1215 | struct mlx4_spec_list *spec_l4 = NULL; | |
82067281 HHZ |
1216 | struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; |
1217 | ||
f90a3673 HHZ |
1218 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1219 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); | |
1220 | spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); | |
1221 | if (!spec_l2 || !spec_l3 || !spec_l4) { | |
377d9739 HHZ |
1222 | err = -ENOMEM; |
1223 | goto free_spec; | |
82067281 HHZ |
1224 | } |
1225 | ||
1226 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; | |
1227 | ||
1228 | if (proto == TCP_V4_FLOW) { | |
377d9739 HHZ |
1229 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1230 | spec_l2, | |
1231 | cmd->fs.h_u. | |
1232 | tcp_ip4_spec.ip4dst); | |
1233 | if (err) | |
1234 | goto free_spec; | |
82067281 HHZ |
1235 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; |
1236 | spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; | |
1237 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; | |
1238 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; | |
1239 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; | |
1240 | } else { | |
377d9739 HHZ |
1241 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1242 | spec_l2, | |
1243 | cmd->fs.h_u. | |
1244 | udp_ip4_spec.ip4dst); | |
1245 | if (err) | |
1246 | goto free_spec; | |
82067281 HHZ |
1247 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; |
1248 | spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; | |
1249 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; | |
1250 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; | |
1251 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; | |
1252 | } | |
1253 | ||
1254 | if (l4_mask->ip4src) | |
1255 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1256 | if (l4_mask->ip4dst) | |
1257 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1258 | ||
1259 | if (l4_mask->psrc) | |
1260 | spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1261 | if (l4_mask->pdst) | |
1262 | spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1263 | ||
1264 | list_add_tail(&spec_l3->list, list_h); | |
1265 | list_add_tail(&spec_l4->list, list_h); | |
1266 | ||
1267 | return 0; | |
377d9739 HHZ |
1268 | |
1269 | free_spec: | |
1270 | kfree(spec_l2); | |
1271 | kfree(spec_l3); | |
1272 | kfree(spec_l4); | |
1273 | return err; | |
82067281 HHZ |
1274 | } |
1275 | ||
1276 | static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, | |
1277 | struct ethtool_rxnfc *cmd, | |
1278 | struct list_head *rule_list_h) | |
1279 | { | |
1280 | int err; | |
82067281 | 1281 | struct ethhdr *eth_spec; |
82067281 | 1282 | struct mlx4_spec_list *spec_l2; |
f90a3673 | 1283 | struct mlx4_en_priv *priv = netdev_priv(dev); |
82067281 HHZ |
1284 | |
1285 | err = mlx4_en_validate_flow(dev, cmd); | |
1286 | if (err) | |
1287 | return err; | |
1288 | ||
520dfe3a | 1289 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { |
82067281 | 1290 | case ETHER_FLOW: |
f90a3673 HHZ |
1291 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1292 | if (!spec_l2) | |
1293 | return -ENOMEM; | |
1294 | ||
82067281 | 1295 | eth_spec = &cmd->fs.h_u.ether_spec; |
f90a3673 HHZ |
1296 | mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, |
1297 | ð_spec->h_dest[0]); | |
82067281 HHZ |
1298 | spec_l2->eth.ether_type = eth_spec->h_proto; |
1299 | if (eth_spec->h_proto) | |
1300 | spec_l2->eth.ether_type_enable = 1; | |
1301 | break; | |
1302 | case IP_USER_FLOW: | |
1303 | err = add_ip_rule(priv, cmd, rule_list_h); | |
1304 | break; | |
1305 | case TCP_V4_FLOW: | |
1306 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); | |
1307 | break; | |
1308 | case UDP_V4_FLOW: | |
1309 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); | |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | return err; | |
1314 | } | |
1315 | ||
1316 | static int mlx4_en_flow_replace(struct net_device *dev, | |
1317 | struct ethtool_rxnfc *cmd) | |
1318 | { | |
1319 | int err; | |
1320 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1321 | struct ethtool_flow_id *loc_rule; | |
1322 | struct mlx4_spec_list *spec, *tmp_spec; | |
1323 | u32 qpn; | |
1324 | u64 reg_id; | |
1325 | ||
1326 | struct mlx4_net_trans_rule rule = { | |
1327 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
1328 | .exclusive = 0, | |
1329 | .allow_loopback = 1, | |
f9162539 | 1330 | .promisc_mode = MLX4_FS_REGULAR, |
82067281 HHZ |
1331 | }; |
1332 | ||
1333 | rule.port = priv->port; | |
1334 | rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; | |
1335 | INIT_LIST_HEAD(&rule.list); | |
1336 | ||
1337 | /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ | |
1338 | if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) | |
cabdc8ee | 1339 | qpn = priv->drop_qp.qpn; |
82067281 HHZ |
1340 | else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { |
1341 | qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); | |
1342 | } else { | |
1343 | if (cmd->fs.ring_cookie >= priv->rx_ring_num) { | |
1a91de28 | 1344 | en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", |
82067281 HHZ |
1345 | cmd->fs.ring_cookie); |
1346 | return -EINVAL; | |
1347 | } | |
1348 | qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; | |
1349 | if (!qpn) { | |
1a91de28 | 1350 | en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", |
82067281 HHZ |
1351 | cmd->fs.ring_cookie); |
1352 | return -EINVAL; | |
1353 | } | |
1354 | } | |
1355 | rule.qpn = qpn; | |
1356 | err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); | |
1357 | if (err) | |
1358 | goto out_free_list; | |
1359 | ||
1360 | loc_rule = &priv->ethtool_rules[cmd->fs.location]; | |
1361 | if (loc_rule->id) { | |
1362 | err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); | |
1363 | if (err) { | |
1364 | en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", | |
1365 | cmd->fs.location, loc_rule->id); | |
1366 | goto out_free_list; | |
1367 | } | |
1368 | loc_rule->id = 0; | |
1369 | memset(&loc_rule->flow_spec, 0, | |
1370 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1371 | list_del(&loc_rule->list); |
82067281 HHZ |
1372 | } |
1373 | err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); | |
1374 | if (err) { | |
1a91de28 | 1375 | en_err(priv, "Fail to attach network rule at location %d\n", |
82067281 HHZ |
1376 | cmd->fs.location); |
1377 | goto out_free_list; | |
1378 | } | |
1379 | loc_rule->id = reg_id; | |
1380 | memcpy(&loc_rule->flow_spec, &cmd->fs, | |
1381 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1382 | list_add_tail(&loc_rule->list, &priv->ethtool_list); |
82067281 HHZ |
1383 | |
1384 | out_free_list: | |
1385 | list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { | |
1386 | list_del(&spec->list); | |
1387 | kfree(spec); | |
1388 | } | |
1389 | return err; | |
1390 | } | |
1391 | ||
1392 | static int mlx4_en_flow_detach(struct net_device *dev, | |
1393 | struct ethtool_rxnfc *cmd) | |
1394 | { | |
1395 | int err = 0; | |
1396 | struct ethtool_flow_id *rule; | |
1397 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1398 | ||
1399 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1400 | return -EINVAL; | |
1401 | ||
1402 | rule = &priv->ethtool_rules[cmd->fs.location]; | |
1403 | if (!rule->id) { | |
1404 | err = -ENOENT; | |
1405 | goto out; | |
1406 | } | |
1407 | ||
1408 | err = mlx4_flow_detach(priv->mdev->dev, rule->id); | |
1409 | if (err) { | |
1410 | en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", | |
1411 | cmd->fs.location, rule->id); | |
1412 | goto out; | |
1413 | } | |
1414 | rule->id = 0; | |
1415 | memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1416 | list_del(&rule->list); |
82067281 HHZ |
1417 | out: |
1418 | return err; | |
1419 | ||
1420 | } | |
1421 | ||
1422 | static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, | |
1423 | int loc) | |
1424 | { | |
1425 | int err = 0; | |
1426 | struct ethtool_flow_id *rule; | |
1427 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1428 | ||
1429 | if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) | |
1430 | return -EINVAL; | |
1431 | ||
1432 | rule = &priv->ethtool_rules[loc]; | |
1433 | if (rule->id) | |
1434 | memcpy(&cmd->fs, &rule->flow_spec, | |
1435 | sizeof(struct ethtool_rx_flow_spec)); | |
1436 | else | |
1437 | err = -ENOENT; | |
1438 | ||
1439 | return err; | |
1440 | } | |
1441 | ||
1442 | static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) | |
1443 | { | |
1444 | ||
1445 | int i, res = 0; | |
1446 | for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { | |
1447 | if (priv->ethtool_rules[i].id) | |
1448 | res++; | |
1449 | } | |
1450 | return res; | |
1451 | ||
1452 | } | |
1453 | ||
93d3e367 YP |
1454 | static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
1455 | u32 *rule_locs) | |
1456 | { | |
1457 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
82067281 | 1458 | struct mlx4_en_dev *mdev = priv->mdev; |
93d3e367 | 1459 | int err = 0; |
82067281 HHZ |
1460 | int i = 0, priority = 0; |
1461 | ||
1462 | if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || | |
1463 | cmd->cmd == ETHTOOL_GRXCLSRULE || | |
1464 | cmd->cmd == ETHTOOL_GRXCLSRLALL) && | |
280fce1e HHZ |
1465 | (mdev->dev->caps.steering_mode != |
1466 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) | |
82067281 | 1467 | return -EINVAL; |
93d3e367 YP |
1468 | |
1469 | switch (cmd->cmd) { | |
1470 | case ETHTOOL_GRXRINGS: | |
1471 | cmd->data = priv->rx_ring_num; | |
1472 | break; | |
82067281 HHZ |
1473 | case ETHTOOL_GRXCLSRLCNT: |
1474 | cmd->rule_cnt = mlx4_en_get_num_flows(priv); | |
1475 | break; | |
1476 | case ETHTOOL_GRXCLSRULE: | |
1477 | err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); | |
1478 | break; | |
1479 | case ETHTOOL_GRXCLSRLALL: | |
1480 | while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { | |
1481 | err = mlx4_en_get_flow(dev, cmd, i); | |
1482 | if (!err) | |
1483 | rule_locs[priority++] = i; | |
1484 | i++; | |
1485 | } | |
1486 | err = 0; | |
1487 | break; | |
93d3e367 YP |
1488 | default: |
1489 | err = -EOPNOTSUPP; | |
1490 | break; | |
1491 | } | |
1492 | ||
1493 | return err; | |
1494 | } | |
1495 | ||
82067281 HHZ |
1496 | static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
1497 | { | |
1498 | int err = 0; | |
1499 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1500 | struct mlx4_en_dev *mdev = priv->mdev; | |
1501 | ||
280fce1e HHZ |
1502 | if (mdev->dev->caps.steering_mode != |
1503 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) | |
82067281 HHZ |
1504 | return -EINVAL; |
1505 | ||
1506 | switch (cmd->cmd) { | |
1507 | case ETHTOOL_SRXCLSRLINS: | |
1508 | err = mlx4_en_flow_replace(dev, cmd); | |
1509 | break; | |
1510 | case ETHTOOL_SRXCLSRLDEL: | |
1511 | err = mlx4_en_flow_detach(dev, cmd); | |
1512 | break; | |
1513 | default: | |
1514 | en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); | |
1515 | return -EINVAL; | |
1516 | } | |
1517 | ||
1518 | return err; | |
1519 | } | |
1520 | ||
d317966b AV |
1521 | static void mlx4_en_get_channels(struct net_device *dev, |
1522 | struct ethtool_channels *channel) | |
1523 | { | |
1524 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1525 | ||
1526 | memset(channel, 0, sizeof(*channel)); | |
1527 | ||
1528 | channel->max_rx = MAX_RX_RINGS; | |
1529 | channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; | |
1530 | ||
1531 | channel->rx_count = priv->rx_ring_num; | |
1532 | channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP; | |
1533 | } | |
1534 | ||
1535 | static int mlx4_en_set_channels(struct net_device *dev, | |
1536 | struct ethtool_channels *channel) | |
1537 | { | |
1538 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1539 | struct mlx4_en_dev *mdev = priv->mdev; | |
da26a625 | 1540 | int port_up = 0; |
d317966b AV |
1541 | int err = 0; |
1542 | ||
1543 | if (channel->other_count || channel->combined_count || | |
1544 | channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP || | |
1545 | channel->rx_count > MAX_RX_RINGS || | |
1546 | !channel->tx_count || !channel->rx_count) | |
1547 | return -EINVAL; | |
1548 | ||
1549 | mutex_lock(&mdev->state_lock); | |
1550 | if (priv->port_up) { | |
1551 | port_up = 1; | |
3484aac1 | 1552 | mlx4_en_stop_port(dev, 1); |
d317966b AV |
1553 | } |
1554 | ||
1555 | mlx4_en_free_resources(priv); | |
1556 | ||
1557 | priv->num_tx_rings_p_up = channel->tx_count; | |
1558 | priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP; | |
1559 | priv->rx_ring_num = channel->rx_count; | |
1560 | ||
1561 | err = mlx4_en_alloc_resources(priv); | |
1562 | if (err) { | |
1563 | en_err(priv, "Failed reallocating port resources\n"); | |
1564 | goto out; | |
1565 | } | |
1566 | ||
1567 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num); | |
1568 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); | |
1569 | ||
f5b6345b IS |
1570 | if (dev->num_tc) |
1571 | mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP); | |
d317966b AV |
1572 | |
1573 | en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num); | |
1574 | en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); | |
1575 | ||
1576 | if (port_up) { | |
1577 | err = mlx4_en_start_port(dev); | |
1578 | if (err) | |
1579 | en_err(priv, "Failed starting port\n"); | |
1580 | } | |
1581 | ||
1582 | err = mlx4_en_moderation_update(priv); | |
1583 | ||
1584 | out: | |
1585 | mutex_unlock(&mdev->state_lock); | |
1586 | return err; | |
1587 | } | |
1588 | ||
ec693d47 AV |
1589 | static int mlx4_en_get_ts_info(struct net_device *dev, |
1590 | struct ethtool_ts_info *info) | |
1591 | { | |
1592 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1593 | struct mlx4_en_dev *mdev = priv->mdev; | |
1594 | int ret; | |
1595 | ||
1596 | ret = ethtool_op_get_ts_info(dev, info); | |
1597 | if (ret) | |
1598 | return ret; | |
1599 | ||
1600 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1601 | info->so_timestamping |= | |
1602 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1603 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1604 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1605 | ||
1606 | info->tx_types = | |
1607 | (1 << HWTSTAMP_TX_OFF) | | |
1608 | (1 << HWTSTAMP_TX_ON); | |
1609 | ||
1610 | info->rx_filters = | |
1611 | (1 << HWTSTAMP_FILTER_NONE) | | |
1612 | (1 << HWTSTAMP_FILTER_ALL); | |
ad7d4eae SB |
1613 | |
1614 | if (mdev->ptp_clock) | |
1615 | info->phc_index = ptp_clock_index(mdev->ptp_clock); | |
ec693d47 AV |
1616 | } |
1617 | ||
1618 | return ret; | |
1619 | } | |
1620 | ||
3f6148e7 | 1621 | static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) |
0fef9d03 AV |
1622 | { |
1623 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1624 | bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
1625 | bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
1626 | int i; | |
1627 | ||
1628 | if (bf_enabled_new == bf_enabled_old) | |
1629 | return 0; /* Nothing to do */ | |
1630 | ||
1631 | if (bf_enabled_new) { | |
1632 | bool bf_supported = true; | |
1633 | ||
1634 | for (i = 0; i < priv->tx_ring_num; i++) | |
1635 | bf_supported &= priv->tx_ring[i]->bf_alloced; | |
1636 | ||
1637 | if (!bf_supported) { | |
1638 | en_err(priv, "BlueFlame is not supported\n"); | |
1639 | return -EINVAL; | |
1640 | } | |
1641 | ||
1642 | priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
1643 | } else { | |
1644 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
1645 | } | |
1646 | ||
1647 | for (i = 0; i < priv->tx_ring_num; i++) | |
1648 | priv->tx_ring[i]->bf_enabled = bf_enabled_new; | |
1649 | ||
1650 | en_info(priv, "BlueFlame %s\n", | |
1651 | bf_enabled_new ? "Enabled" : "Disabled"); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
3f6148e7 | 1656 | static u32 mlx4_en_get_priv_flags(struct net_device *dev) |
0fef9d03 AV |
1657 | { |
1658 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1659 | ||
1660 | return priv->pflags; | |
1661 | } | |
1662 | ||
1556b874 ED |
1663 | static int mlx4_en_get_tunable(struct net_device *dev, |
1664 | const struct ethtool_tunable *tuna, | |
1665 | void *data) | |
1666 | { | |
1667 | const struct mlx4_en_priv *priv = netdev_priv(dev); | |
1668 | int ret = 0; | |
1669 | ||
1670 | switch (tuna->id) { | |
1671 | case ETHTOOL_TX_COPYBREAK: | |
1672 | *(u32 *)data = priv->prof->inline_thold; | |
1673 | break; | |
1674 | default: | |
1675 | ret = -EINVAL; | |
1676 | break; | |
1677 | } | |
1678 | ||
1679 | return ret; | |
1680 | } | |
1681 | ||
1682 | static int mlx4_en_set_tunable(struct net_device *dev, | |
1683 | const struct ethtool_tunable *tuna, | |
1684 | const void *data) | |
1685 | { | |
1686 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1687 | int val, ret = 0; | |
1688 | ||
1689 | switch (tuna->id) { | |
1690 | case ETHTOOL_TX_COPYBREAK: | |
1691 | val = *(u32 *)data; | |
1692 | if (val < MIN_PKT_LEN || val > MAX_INLINE) | |
1693 | ret = -EINVAL; | |
1694 | else | |
1695 | priv->prof->inline_thold = val; | |
1696 | break; | |
1697 | default: | |
1698 | ret = -EINVAL; | |
1699 | break; | |
1700 | } | |
1701 | ||
1702 | return ret; | |
1703 | } | |
1704 | ||
7202da8b SM |
1705 | static int mlx4_en_get_module_info(struct net_device *dev, |
1706 | struct ethtool_modinfo *modinfo) | |
1707 | { | |
1708 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1709 | struct mlx4_en_dev *mdev = priv->mdev; | |
1710 | int ret; | |
1711 | u8 data[4]; | |
1712 | ||
1713 | /* Read first 2 bytes to get Module & REV ID */ | |
1714 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
1715 | 0/*offset*/, 2/*size*/, data); | |
1716 | if (ret < 2) | |
1717 | return -EIO; | |
1718 | ||
1719 | switch (data[0] /* identifier */) { | |
1720 | case MLX4_MODULE_ID_QSFP: | |
1721 | modinfo->type = ETH_MODULE_SFF_8436; | |
1722 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1723 | break; | |
1724 | case MLX4_MODULE_ID_QSFP_PLUS: | |
1725 | if (data[1] >= 0x3) { /* revision id */ | |
1726 | modinfo->type = ETH_MODULE_SFF_8636; | |
1727 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1728 | } else { | |
1729 | modinfo->type = ETH_MODULE_SFF_8436; | |
1730 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1731 | } | |
1732 | break; | |
1733 | case MLX4_MODULE_ID_QSFP28: | |
1734 | modinfo->type = ETH_MODULE_SFF_8636; | |
1735 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1736 | break; | |
1737 | case MLX4_MODULE_ID_SFP: | |
1738 | modinfo->type = ETH_MODULE_SFF_8472; | |
1739 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1740 | break; | |
1741 | default: | |
1742 | return -ENOSYS; | |
1743 | } | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | static int mlx4_en_get_module_eeprom(struct net_device *dev, | |
1749 | struct ethtool_eeprom *ee, | |
1750 | u8 *data) | |
1751 | { | |
1752 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1753 | struct mlx4_en_dev *mdev = priv->mdev; | |
1754 | int offset = ee->offset; | |
1755 | int i = 0, ret; | |
1756 | ||
1757 | if (ee->len == 0) | |
1758 | return -EINVAL; | |
1759 | ||
1760 | memset(data, 0, ee->len); | |
1761 | ||
1762 | while (i < ee->len) { | |
1763 | en_dbg(DRV, priv, | |
1764 | "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", | |
1765 | i, offset, ee->len - i); | |
1766 | ||
1767 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
1768 | offset, ee->len - i, data + i); | |
1769 | ||
1770 | if (!ret) /* Done reading */ | |
1771 | return 0; | |
1772 | ||
1773 | if (ret < 0) { | |
1774 | en_err(priv, | |
1775 | "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", | |
1776 | i, offset, ee->len - i, ret); | |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | i += ret; | |
1781 | offset += ret; | |
1782 | } | |
1783 | return 0; | |
1784 | } | |
0fef9d03 | 1785 | |
c27a02cd YP |
1786 | const struct ethtool_ops mlx4_en_ethtool_ops = { |
1787 | .get_drvinfo = mlx4_en_get_drvinfo, | |
1788 | .get_settings = mlx4_en_get_settings, | |
1789 | .set_settings = mlx4_en_set_settings, | |
c27a02cd | 1790 | .get_link = ethtool_op_get_link, |
c27a02cd YP |
1791 | .get_strings = mlx4_en_get_strings, |
1792 | .get_sset_count = mlx4_en_get_sset_count, | |
1793 | .get_ethtool_stats = mlx4_en_get_ethtool_stats, | |
e7c1c2c4 | 1794 | .self_test = mlx4_en_self_test, |
c27a02cd | 1795 | .get_wol = mlx4_en_get_wol, |
14c07b13 | 1796 | .set_wol = mlx4_en_set_wol, |
c27a02cd YP |
1797 | .get_msglevel = mlx4_en_get_msglevel, |
1798 | .set_msglevel = mlx4_en_set_msglevel, | |
1799 | .get_coalesce = mlx4_en_get_coalesce, | |
1800 | .set_coalesce = mlx4_en_set_coalesce, | |
1801 | .get_pauseparam = mlx4_en_get_pauseparam, | |
1802 | .set_pauseparam = mlx4_en_set_pauseparam, | |
1803 | .get_ringparam = mlx4_en_get_ringparam, | |
18cc42a3 | 1804 | .set_ringparam = mlx4_en_set_ringparam, |
93d3e367 | 1805 | .get_rxnfc = mlx4_en_get_rxnfc, |
82067281 | 1806 | .set_rxnfc = mlx4_en_set_rxnfc, |
93d3e367 | 1807 | .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, |
b9d1ab7e | 1808 | .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, |
fe62d001 BH |
1809 | .get_rxfh = mlx4_en_get_rxfh, |
1810 | .set_rxfh = mlx4_en_set_rxfh, | |
d317966b AV |
1811 | .get_channels = mlx4_en_get_channels, |
1812 | .set_channels = mlx4_en_set_channels, | |
ec693d47 | 1813 | .get_ts_info = mlx4_en_get_ts_info, |
0fef9d03 AV |
1814 | .set_priv_flags = mlx4_en_set_priv_flags, |
1815 | .get_priv_flags = mlx4_en_get_priv_flags, | |
1556b874 ED |
1816 | .get_tunable = mlx4_en_get_tunable, |
1817 | .set_tunable = mlx4_en_set_tunable, | |
7202da8b SM |
1818 | .get_module_info = mlx4_en_get_module_info, |
1819 | .get_module_eeprom = mlx4_en_get_module_eeprom | |
c27a02cd YP |
1820 | }; |
1821 | ||
1822 | ||
1823 | ||
1824 | ||
1825 |