Merge branches 'pm-core', 'pm-clk', 'pm-domains' and 'pm-pci'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h
CommitLineData
9218b44d
GP
1/*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef __MLX5_EN_STATS_H__
33#define __MLX5_EN_STATS_H__
34
35#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
42 be64_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
43
44#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
bfe6d8d1
GP
45#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
9218b44d
GP
47
48struct counter_desc {
bfe6d8d1 49 char format[ETH_GSTRING_LEN];
9218b44d
GP
50 int offset; /* Byte offset */
51};
52
53struct mlx5e_sw_stats {
54 u64 rx_packets;
55 u64 rx_bytes;
56 u64 tx_packets;
57 u64 tx_bytes;
bfe6d8d1
GP
58 u64 tx_tso_packets;
59 u64 tx_tso_bytes;
60 u64 tx_tso_inner_packets;
61 u64 tx_tso_inner_bytes;
62 u64 rx_lro_packets;
63 u64 rx_lro_bytes;
64 u64 rx_csum_unnecessary;
9218b44d 65 u64 rx_csum_none;
bfe6d8d1
GP
66 u64 rx_csum_complete;
67 u64 rx_csum_unnecessary_inner;
68 u64 tx_csum_partial;
69 u64 tx_csum_partial_inner;
9218b44d
GP
70 u64 tx_queue_stopped;
71 u64 tx_queue_wake;
72 u64 tx_queue_dropped;
73 u64 rx_wqe_err;
74 u64 rx_mpwqe_filler;
75 u64 rx_mpwqe_frag;
76 u64 rx_buff_alloc_err;
7219ab34
TT
77 u64 rx_cqe_compress_blks;
78 u64 rx_cqe_compress_pkts;
121fcdc8
GP
79
80 /* Special handling counters */
bfe6d8d1 81 u64 link_down_events_phy;
9218b44d
GP
82};
83
84static const struct counter_desc sw_stats_desc[] = {
85 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
86 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
87 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
88 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
bfe6d8d1
GP
89 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
90 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
91 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
92 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
93 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
94 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
9218b44d 96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
bfe6d8d1
GP
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
9218b44d
GP
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_frag) },
107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
7219ab34
TT
108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
bfe6d8d1 110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
9218b44d
GP
111};
112
113struct mlx5e_qcounter_stats {
114 u32 rx_out_of_buffer;
115};
116
117static const struct counter_desc q_stats_desc[] = {
118 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
119};
120
121#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
122#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
123 vstats->query_vport_out, c)
124
125struct mlx5e_vport_stats {
126 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
127};
128
129static const struct counter_desc vport_stats_desc[] = {
8075cb72 130 { "rx_vport_unicast_packets",
9218b44d 131 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
8075cb72
GP
132 { "rx_vport_unicast_bytes",
133 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
134 { "tx_vport_unicast_packets",
9218b44d 135 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
8075cb72 136 { "tx_vport_unicast_bytes",
9218b44d 137 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
8075cb72 138 { "rx_vport_multicast_packets",
9218b44d 139 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
8075cb72 140 { "rx_vport_multicast_bytes",
9218b44d 141 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
8075cb72 142 { "tx_vport_multicast_packets",
9218b44d 143 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
8075cb72 144 { "tx_vport_multicast_bytes",
9218b44d 145 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
8075cb72 146 { "rx_vport_broadcast_packets",
9218b44d 147 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
8075cb72 148 { "rx_vport_broadcast_bytes",
9218b44d 149 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
8075cb72 150 { "tx_vport_broadcast_packets",
9218b44d 151 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
8075cb72 152 { "tx_vport_broadcast_bytes",
9218b44d
GP
153 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
154};
155
156#define PPORT_802_3_OFF(c) \
157 MLX5_BYTE_OFF(ppcnt_reg, \
158 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
159#define PPORT_802_3_GET(pstats, c) \
160 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
161 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
162#define PPORT_2863_OFF(c) \
163 MLX5_BYTE_OFF(ppcnt_reg, \
164 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
165#define PPORT_2863_GET(pstats, c) \
166 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
167 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
168#define PPORT_2819_OFF(c) \
169 MLX5_BYTE_OFF(ppcnt_reg, \
170 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
171#define PPORT_2819_GET(pstats, c) \
172 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
173 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
cf678570
GP
174#define PPORT_PER_PRIO_OFF(c) \
175 MLX5_BYTE_OFF(ppcnt_reg, \
176 counter_set.eth_per_prio_grp_data_layout.c##_high)
177#define PPORT_PER_PRIO_GET(pstats, prio, c) \
178 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
179 counter_set.eth_per_prio_grp_data_layout.c##_high)
180#define NUM_PPORT_PRIO 8
9218b44d
GP
181
182struct mlx5e_pport_stats {
183 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
184 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
185 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
cf678570 186 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
121fcdc8 187 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
9218b44d
GP
188};
189
190static const struct counter_desc pport_802_3_stats_desc[] = {
bfe6d8d1
GP
191 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
192 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
193 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
194 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
195 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
196 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
197 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
198 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
199 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
200 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
201 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
202 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
203 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
204 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
205 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
206 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
207 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
208 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
9218b44d
GP
209};
210
211static const struct counter_desc pport_2863_stats_desc[] = {
bfe6d8d1
GP
212 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
213 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
214 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
9218b44d
GP
215};
216
217static const struct counter_desc pport_2819_stats_desc[] = {
bfe6d8d1
GP
218 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
219 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
220 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
221 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
222 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
223 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
224 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
225 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
226 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
227 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
228 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
229 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
230 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
9218b44d
GP
231};
232
cf678570 233static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
bfe6d8d1
GP
234 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
235 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
236 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
237 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
cf678570
GP
238};
239
240static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
bfe6d8d1
GP
241 { "rx_prio%d_pause", PPORT_PER_PRIO_OFF(rx_pause) },
242 { "rx_prio%d_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
243 { "tx_prio%d_pause", PPORT_PER_PRIO_OFF(tx_pause) },
244 { "tx_prio%d_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
245 { "rx_prio%d_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
cf678570
GP
246};
247
9218b44d
GP
248struct mlx5e_rq_stats {
249 u64 packets;
250 u64 bytes;
bfe6d8d1
GP
251 u64 csum_complete;
252 u64 csum_unnecessary_inner;
1b223dd3 253 u64 csum_none;
9218b44d
GP
254 u64 lro_packets;
255 u64 lro_bytes;
256 u64 wqe_err;
257 u64 mpwqe_filler;
258 u64 mpwqe_frag;
259 u64 buff_alloc_err;
7219ab34
TT
260 u64 cqe_compress_blks;
261 u64 cqe_compress_pkts;
9218b44d
GP
262};
263
264static const struct counter_desc rq_stats_desc[] = {
bfe6d8d1
GP
265 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
266 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
267 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
268 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
269 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
270 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
271 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
272 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
273 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
274 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_frag) },
275 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
276 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
277 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
9218b44d
GP
278};
279
280struct mlx5e_sq_stats {
281 /* commonly accessed in data path */
282 u64 packets;
283 u64 bytes;
284 u64 tso_packets;
285 u64 tso_bytes;
286 u64 tso_inner_packets;
287 u64 tso_inner_bytes;
bfe6d8d1 288 u64 csum_partial_inner;
9218b44d
GP
289 u64 nop;
290 /* less likely accessed in data path */
bfe6d8d1 291 u64 csum_none;
9218b44d
GP
292 u64 stopped;
293 u64 wake;
294 u64 dropped;
295};
296
297static const struct counter_desc sq_stats_desc[] = {
bfe6d8d1
GP
298 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
299 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
300 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
301 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
302 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
303 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
304 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
305 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
306 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
307 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
308 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
309 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
9218b44d
GP
310};
311
312#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
313#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
314#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
315#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
316#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
317#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
cf678570
GP
318#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
319 ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
320#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
321 ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
9218b44d
GP
322#define NUM_PPORT_COUNTERS (NUM_PPORT_802_3_COUNTERS + \
323 NUM_PPORT_2863_COUNTERS + \
cf678570
GP
324 NUM_PPORT_2819_COUNTERS + \
325 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
326 NUM_PPORT_PRIO)
9218b44d
GP
327#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
328#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
329
330struct mlx5e_stats {
331 struct mlx5e_sw_stats sw;
332 struct mlx5e_qcounter_stats qcnt;
333 struct mlx5e_vport_stats vport;
334 struct mlx5e_pport_stats pport;
335};
336
337#endif /* __MLX5_EN_STATS_H__ */
This page took 0.058947 seconds and 5 git commands to generate.