Commit | Line | Data |
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48257c4f PA |
1 | /* |
2 | * FCC driver for Motorola MPC82xx (PQ2). | |
3 | * | |
9b8ee8e7 | 4 | * Copyright (c) 2003 Intracom S.A. |
48257c4f PA |
5 | * by Pantelis Antoniou <panto@intracom.gr> |
6 | * | |
9b8ee8e7 | 7 | * 2005 (c) MontaVista Software, Inc. |
48257c4f PA |
8 | * Vitaly Bordug <vbordug@ru.mvista.com> |
9 | * | |
9b8ee8e7 VB |
10 | * This file is licensed under the terms of the GNU General Public License |
11 | * version 2. This program is licensed "as is" without any warranty of any | |
48257c4f PA |
12 | * kind, whether express or implied. |
13 | */ | |
14 | ||
48257c4f PA |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
48257c4f PA |
18 | #include <linux/string.h> |
19 | #include <linux/ptrace.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/ioport.h> | |
48257c4f | 22 | #include <linux/interrupt.h> |
48257c4f PA |
23 | #include <linux/init.h> |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/mii.h> | |
30 | #include <linux/ethtool.h> | |
31 | #include <linux/bitops.h> | |
32 | #include <linux/fs.h> | |
f7b99969 | 33 | #include <linux/platform_device.h> |
5b4b8454 | 34 | #include <linux/phy.h> |
b219108c | 35 | #include <linux/of_device.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
48257c4f PA |
37 | |
38 | #include <asm/immap_cpm2.h> | |
39 | #include <asm/mpc8260.h> | |
40 | #include <asm/cpm2.h> | |
41 | ||
42 | #include <asm/pgtable.h> | |
43 | #include <asm/irq.h> | |
44 | #include <asm/uaccess.h> | |
45 | ||
46 | #include "fs_enet.h" | |
47 | ||
48 | /*************************************************/ | |
49 | ||
50 | /* FCC access macros */ | |
51 | ||
48257c4f | 52 | /* write, read, set bits, clear bits */ |
c6565331 SW |
53 | #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v)) |
54 | #define R32(_p, _m) in_be32(&(_p)->_m) | |
48257c4f PA |
55 | #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) |
56 | #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) | |
57 | ||
c6565331 SW |
58 | #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v)) |
59 | #define R16(_p, _m) in_be16(&(_p)->_m) | |
48257c4f PA |
60 | #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) |
61 | #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) | |
62 | ||
c6565331 SW |
63 | #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v)) |
64 | #define R8(_p, _m) in_8(&(_p)->_m) | |
48257c4f PA |
65 | #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) |
66 | #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) | |
67 | ||
68 | /*************************************************/ | |
69 | ||
70 | #define FCC_MAX_MULTICAST_ADDRS 64 | |
71 | ||
72 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
73 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) | |
74 | #define mk_mii_end 0 | |
75 | ||
76 | #define MAX_CR_CMD_LOOPS 10000 | |
77 | ||
976de6a8 | 78 | static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op) |
48257c4f PA |
79 | { |
80 | const struct fs_platform_info *fpi = fep->fpi; | |
48257c4f | 81 | |
362f9b6f | 82 | return cpm_command(fpi->cp_command, op); |
48257c4f PA |
83 | } |
84 | ||
85 | static int do_pd_setup(struct fs_enet_private *fep) | |
86 | { | |
976de6a8 SW |
87 | struct of_device *ofdev = to_of_device(fep->dev); |
88 | struct fs_platform_info *fpi = fep->fpi; | |
89 | int ret = -EINVAL; | |
90 | ||
61c7a080 | 91 | fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL); |
976de6a8 SW |
92 | if (fep->interrupt == NO_IRQ) |
93 | goto out; | |
94 | ||
61c7a080 | 95 | fep->fcc.fccp = of_iomap(ofdev->dev.of_node, 0); |
976de6a8 SW |
96 | if (!fep->fcc.fccp) |
97 | goto out; | |
98 | ||
61c7a080 | 99 | fep->fcc.ep = of_iomap(ofdev->dev.of_node, 1); |
976de6a8 SW |
100 | if (!fep->fcc.ep) |
101 | goto out_fccp; | |
102 | ||
61c7a080 | 103 | fep->fcc.fcccp = of_iomap(ofdev->dev.of_node, 2); |
976de6a8 SW |
104 | if (!fep->fcc.fcccp) |
105 | goto out_ep; | |
106 | ||
31a5bb04 SW |
107 | fep->fcc.mem = (void __iomem *)cpm2_immr; |
108 | fpi->dpram_offset = cpm_dpalloc(128, 8); | |
976de6a8 SW |
109 | if (IS_ERR_VALUE(fpi->dpram_offset)) { |
110 | ret = fpi->dpram_offset; | |
111 | goto out_fcccp; | |
112 | } | |
113 | ||
114 | return 0; | |
115 | ||
116 | out_fcccp: | |
117 | iounmap(fep->fcc.fcccp); | |
118 | out_ep: | |
119 | iounmap(fep->fcc.ep); | |
120 | out_fccp: | |
121 | iounmap(fep->fcc.fccp); | |
122 | out: | |
123 | return ret; | |
48257c4f PA |
124 | } |
125 | ||
126 | #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB) | |
127 | #define FCC_RX_EVENT (FCC_ENET_RXF) | |
128 | #define FCC_TX_EVENT (FCC_ENET_TXB) | |
5b1c29b4 | 129 | #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE) |
48257c4f PA |
130 | |
131 | static int setup_data(struct net_device *dev) | |
132 | { | |
133 | struct fs_enet_private *fep = netdev_priv(dev); | |
48257c4f | 134 | |
48257c4f PA |
135 | if (do_pd_setup(fep) != 0) |
136 | return -EINVAL; | |
137 | ||
138 | fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK; | |
139 | fep->ev_rx = FCC_RX_EVENT; | |
140 | fep->ev_tx = FCC_TX_EVENT; | |
141 | fep->ev_err = FCC_ERR_EVENT_MSK; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
146 | static int allocate_bd(struct net_device *dev) | |
147 | { | |
148 | struct fs_enet_private *fep = netdev_priv(dev); | |
149 | const struct fs_platform_info *fpi = fep->fpi; | |
150 | ||
31a5bb04 | 151 | fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev, |
48257c4f PA |
152 | (fpi->tx_ring + fpi->rx_ring) * |
153 | sizeof(cbd_t), &fep->ring_mem_addr, | |
154 | GFP_KERNEL); | |
155 | if (fep->ring_base == NULL) | |
156 | return -ENOMEM; | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static void free_bd(struct net_device *dev) | |
162 | { | |
163 | struct fs_enet_private *fep = netdev_priv(dev); | |
164 | const struct fs_platform_info *fpi = fep->fpi; | |
165 | ||
166 | if (fep->ring_base) | |
167 | dma_free_coherent(fep->dev, | |
168 | (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), | |
31a5bb04 | 169 | (void __force *)fep->ring_base, fep->ring_mem_addr); |
48257c4f PA |
170 | } |
171 | ||
172 | static void cleanup_data(struct net_device *dev) | |
173 | { | |
174 | /* nothing */ | |
175 | } | |
176 | ||
177 | static void set_promiscuous_mode(struct net_device *dev) | |
178 | { | |
179 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 180 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
181 | |
182 | S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); | |
183 | } | |
184 | ||
185 | static void set_multicast_start(struct net_device *dev) | |
186 | { | |
187 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 188 | fcc_enet_t __iomem *ep = fep->fcc.ep; |
48257c4f PA |
189 | |
190 | W32(ep, fen_gaddrh, 0); | |
191 | W32(ep, fen_gaddrl, 0); | |
192 | } | |
193 | ||
194 | static void set_multicast_one(struct net_device *dev, const u8 *mac) | |
195 | { | |
196 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 197 | fcc_enet_t __iomem *ep = fep->fcc.ep; |
48257c4f PA |
198 | u16 taddrh, taddrm, taddrl; |
199 | ||
200 | taddrh = ((u16)mac[5] << 8) | mac[4]; | |
201 | taddrm = ((u16)mac[3] << 8) | mac[2]; | |
202 | taddrl = ((u16)mac[1] << 8) | mac[0]; | |
203 | ||
204 | W16(ep, fen_taddrh, taddrh); | |
205 | W16(ep, fen_taddrm, taddrm); | |
206 | W16(ep, fen_taddrl, taddrl); | |
976de6a8 | 207 | fcc_cr_cmd(fep, CPM_CR_SET_GADDR); |
48257c4f PA |
208 | } |
209 | ||
210 | static void set_multicast_finish(struct net_device *dev) | |
211 | { | |
212 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 SW |
213 | fcc_t __iomem *fccp = fep->fcc.fccp; |
214 | fcc_enet_t __iomem *ep = fep->fcc.ep; | |
48257c4f PA |
215 | |
216 | /* clear promiscuous always */ | |
217 | C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); | |
218 | ||
219 | /* if all multi or too many multicasts; just enable all */ | |
220 | if ((dev->flags & IFF_ALLMULTI) != 0 || | |
4cd24eaf | 221 | netdev_mc_count(dev) > FCC_MAX_MULTICAST_ADDRS) { |
48257c4f PA |
222 | |
223 | W32(ep, fen_gaddrh, 0xffffffff); | |
224 | W32(ep, fen_gaddrl, 0xffffffff); | |
225 | } | |
226 | ||
227 | /* read back */ | |
228 | fep->fcc.gaddrh = R32(ep, fen_gaddrh); | |
229 | fep->fcc.gaddrl = R32(ep, fen_gaddrl); | |
230 | } | |
231 | ||
232 | static void set_multicast_list(struct net_device *dev) | |
233 | { | |
234 | struct dev_mc_list *pmc; | |
235 | ||
236 | if ((dev->flags & IFF_PROMISC) == 0) { | |
237 | set_multicast_start(dev); | |
48e2f183 | 238 | netdev_for_each_mc_addr(pmc, dev) |
48257c4f PA |
239 | set_multicast_one(dev, pmc->dmi_addr); |
240 | set_multicast_finish(dev); | |
241 | } else | |
242 | set_promiscuous_mode(dev); | |
243 | } | |
244 | ||
245 | static void restart(struct net_device *dev) | |
246 | { | |
247 | struct fs_enet_private *fep = netdev_priv(dev); | |
248 | const struct fs_platform_info *fpi = fep->fpi; | |
31a5bb04 SW |
249 | fcc_t __iomem *fccp = fep->fcc.fccp; |
250 | fcc_c_t __iomem *fcccp = fep->fcc.fcccp; | |
251 | fcc_enet_t __iomem *ep = fep->fcc.ep; | |
48257c4f PA |
252 | dma_addr_t rx_bd_base_phys, tx_bd_base_phys; |
253 | u16 paddrh, paddrm, paddrl; | |
48257c4f PA |
254 | const unsigned char *mac; |
255 | int i; | |
256 | ||
257 | C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | |
258 | ||
259 | /* clear everything (slow & steady does it) */ | |
260 | for (i = 0; i < sizeof(*ep); i++) | |
976de6a8 | 261 | out_8((u8 __iomem *)ep + i, 0); |
48257c4f PA |
262 | |
263 | /* get physical address */ | |
264 | rx_bd_base_phys = fep->ring_mem_addr; | |
265 | tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; | |
266 | ||
267 | /* point to bds */ | |
268 | W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); | |
269 | W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); | |
270 | ||
271 | /* Set maximum bytes per receive buffer. | |
272 | * It must be a multiple of 32. | |
273 | */ | |
274 | W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); | |
275 | ||
276 | W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); | |
277 | W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); | |
278 | ||
279 | /* Allocate space in the reserved FCC area of DPRAM for the | |
280 | * internal buffers. No one uses this space (yet), so we | |
281 | * can do this. Later, we will add resource management for | |
282 | * this area. | |
283 | */ | |
284 | ||
31a5bb04 SW |
285 | W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset); |
286 | W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32); | |
287 | ||
288 | W16(ep, fen_padptr, fpi->dpram_offset + 64); | |
48257c4f PA |
289 | |
290 | /* fill with special symbol... */ | |
31a5bb04 | 291 | memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); |
48257c4f PA |
292 | |
293 | W32(ep, fen_genfcc.fcc_rbptr, 0); | |
294 | W32(ep, fen_genfcc.fcc_tbptr, 0); | |
295 | W32(ep, fen_genfcc.fcc_rcrc, 0); | |
296 | W32(ep, fen_genfcc.fcc_tcrc, 0); | |
297 | W16(ep, fen_genfcc.fcc_res1, 0); | |
298 | W32(ep, fen_genfcc.fcc_res2, 0); | |
299 | ||
300 | /* no CAM */ | |
301 | W32(ep, fen_camptr, 0); | |
302 | ||
303 | /* Set CRC preset and mask */ | |
304 | W32(ep, fen_cmask, 0xdebb20e3); | |
305 | W32(ep, fen_cpres, 0xffffffff); | |
306 | ||
307 | W32(ep, fen_crcec, 0); /* CRC Error counter */ | |
308 | W32(ep, fen_alec, 0); /* alignment error counter */ | |
309 | W32(ep, fen_disfc, 0); /* discard frame counter */ | |
310 | W16(ep, fen_retlim, 15); /* Retry limit threshold */ | |
311 | W16(ep, fen_pper, 0); /* Normal persistence */ | |
312 | ||
313 | /* set group address */ | |
314 | W32(ep, fen_gaddrh, fep->fcc.gaddrh); | |
315 | W32(ep, fen_gaddrl, fep->fcc.gaddrh); | |
316 | ||
317 | /* Clear hash filter tables */ | |
318 | W32(ep, fen_iaddrh, 0); | |
319 | W32(ep, fen_iaddrl, 0); | |
320 | ||
321 | /* Clear the Out-of-sequence TxBD */ | |
322 | W16(ep, fen_tfcstat, 0); | |
323 | W16(ep, fen_tfclen, 0); | |
324 | W32(ep, fen_tfcptr, 0); | |
325 | ||
326 | W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ | |
327 | W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ | |
328 | ||
329 | /* set address */ | |
330 | mac = dev->dev_addr; | |
331 | paddrh = ((u16)mac[5] << 8) | mac[4]; | |
332 | paddrm = ((u16)mac[3] << 8) | mac[2]; | |
333 | paddrl = ((u16)mac[1] << 8) | mac[0]; | |
334 | ||
335 | W16(ep, fen_paddrh, paddrh); | |
336 | W16(ep, fen_paddrm, paddrm); | |
337 | W16(ep, fen_paddrl, paddrl); | |
338 | ||
339 | W16(ep, fen_taddrh, 0); | |
340 | W16(ep, fen_taddrm, 0); | |
341 | W16(ep, fen_taddrl, 0); | |
342 | ||
343 | W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ | |
344 | W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ | |
345 | ||
346 | /* Clear stat counters, in case we ever enable RMON */ | |
347 | W32(ep, fen_octc, 0); | |
348 | W32(ep, fen_colc, 0); | |
349 | W32(ep, fen_broc, 0); | |
350 | W32(ep, fen_mulc, 0); | |
351 | W32(ep, fen_uspc, 0); | |
352 | W32(ep, fen_frgc, 0); | |
353 | W32(ep, fen_ospc, 0); | |
354 | W32(ep, fen_jbrc, 0); | |
355 | W32(ep, fen_p64c, 0); | |
356 | W32(ep, fen_p65c, 0); | |
357 | W32(ep, fen_p128c, 0); | |
358 | W32(ep, fen_p256c, 0); | |
359 | W32(ep, fen_p512c, 0); | |
360 | W32(ep, fen_p1024c, 0); | |
361 | ||
362 | W16(ep, fen_rfthr, 0); /* Suggested by manual */ | |
363 | W16(ep, fen_rfcnt, 0); | |
364 | W16(ep, fen_cftype, 0); | |
365 | ||
366 | fs_init_bds(dev); | |
367 | ||
368 | /* adjust to speed (for RMII mode) */ | |
369 | if (fpi->use_rmii) { | |
5b4b8454 | 370 | if (fep->phydev->speed == 100) |
48257c4f PA |
371 | C8(fcccp, fcc_gfemr, 0x20); |
372 | else | |
373 | S8(fcccp, fcc_gfemr, 0x20); | |
374 | } | |
375 | ||
976de6a8 | 376 | fcc_cr_cmd(fep, CPM_CR_INIT_TRX); |
48257c4f PA |
377 | |
378 | /* clear events */ | |
379 | W16(fccp, fcc_fcce, 0xffff); | |
380 | ||
381 | /* Enable interrupts we wish to service */ | |
382 | W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); | |
383 | ||
384 | /* Set GFMR to enable Ethernet operating mode */ | |
385 | W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); | |
386 | ||
387 | /* set sync/delimiters */ | |
388 | W16(fccp, fcc_fdsr, 0xd555); | |
389 | ||
390 | W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); | |
391 | ||
392 | if (fpi->use_rmii) | |
393 | S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); | |
394 | ||
395 | /* adjust to duplex mode */ | |
5b4b8454 | 396 | if (fep->phydev->duplex) |
48257c4f PA |
397 | S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); |
398 | else | |
399 | C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); | |
400 | ||
c5a78ac0 LP |
401 | /* Restore multicast and promiscuous settings */ |
402 | set_multicast_list(dev); | |
403 | ||
48257c4f PA |
404 | S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); |
405 | } | |
406 | ||
407 | static void stop(struct net_device *dev) | |
408 | { | |
409 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 410 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
411 | |
412 | /* stop ethernet */ | |
413 | C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | |
414 | ||
415 | /* clear events */ | |
416 | W16(fccp, fcc_fcce, 0xffff); | |
417 | ||
418 | /* clear interrupt mask */ | |
419 | W16(fccp, fcc_fccm, 0); | |
420 | ||
421 | fs_cleanup_bds(dev); | |
422 | } | |
423 | ||
48257c4f PA |
424 | static void napi_clear_rx_event(struct net_device *dev) |
425 | { | |
426 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 427 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
428 | |
429 | W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK); | |
430 | } | |
431 | ||
432 | static void napi_enable_rx(struct net_device *dev) | |
433 | { | |
434 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 435 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
436 | |
437 | S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); | |
438 | } | |
439 | ||
440 | static void napi_disable_rx(struct net_device *dev) | |
441 | { | |
442 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 443 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
444 | |
445 | C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); | |
446 | } | |
447 | ||
448 | static void rx_bd_done(struct net_device *dev) | |
449 | { | |
450 | /* nothing */ | |
451 | } | |
452 | ||
453 | static void tx_kickstart(struct net_device *dev) | |
454 | { | |
5b4b8454 | 455 | struct fs_enet_private *fep = netdev_priv(dev); |
31a5bb04 | 456 | fcc_t __iomem *fccp = fep->fcc.fccp; |
5b4b8454 | 457 | |
c6565331 | 458 | S16(fccp, fcc_ftodr, 0x8000); |
48257c4f PA |
459 | } |
460 | ||
461 | static u32 get_int_events(struct net_device *dev) | |
462 | { | |
463 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 464 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
465 | |
466 | return (u32)R16(fccp, fcc_fcce); | |
467 | } | |
468 | ||
469 | static void clear_int_events(struct net_device *dev, u32 int_events) | |
470 | { | |
471 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 472 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
473 | |
474 | W16(fccp, fcc_fcce, int_events & 0xffff); | |
475 | } | |
476 | ||
477 | static void ev_error(struct net_device *dev, u32 int_events) | |
478 | { | |
fcb6a1c8 AG |
479 | struct fs_enet_private *fep = netdev_priv(dev); |
480 | ||
481 | dev_warn(fep->dev, "FS_ENET ERROR(s) 0x%x\n", int_events); | |
48257c4f PA |
482 | } |
483 | ||
31a5bb04 | 484 | static int get_regs(struct net_device *dev, void *p, int *sizep) |
48257c4f PA |
485 | { |
486 | struct fs_enet_private *fep = netdev_priv(dev); | |
487 | ||
976de6a8 | 488 | if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1) |
48257c4f PA |
489 | return -EINVAL; |
490 | ||
491 | memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); | |
492 | p = (char *)p + sizeof(fcc_t); | |
493 | ||
48257c4f | 494 | memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); |
976de6a8 | 495 | p = (char *)p + sizeof(fcc_enet_t); |
48257c4f | 496 | |
976de6a8 | 497 | memcpy_fromio(p, fep->fcc.fcccp, 1); |
48257c4f PA |
498 | return 0; |
499 | } | |
500 | ||
31a5bb04 | 501 | static int get_regs_len(struct net_device *dev) |
48257c4f | 502 | { |
976de6a8 | 503 | return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1; |
48257c4f PA |
504 | } |
505 | ||
506 | /* Some transmit errors cause the transmitter to shut | |
507 | * down. We now issue a restart transmit. Since the | |
508 | * errors close the BD and update the pointers, the restart | |
509 | * _should_ pick up without having to reset any of our | |
9b8ee8e7 | 510 | * pointers either. Also, To workaround 8260 device erratum |
48257c4f PA |
511 | * CPM37, we must disable and then re-enable the transmitter |
512 | * following a Late Collision, Underrun, or Retry Limit error. | |
513 | */ | |
31a5bb04 | 514 | static void tx_restart(struct net_device *dev) |
48257c4f PA |
515 | { |
516 | struct fs_enet_private *fep = netdev_priv(dev); | |
31a5bb04 | 517 | fcc_t __iomem *fccp = fep->fcc.fccp; |
48257c4f PA |
518 | |
519 | C32(fccp, fcc_gfmr, FCC_GFMR_ENT); | |
520 | udelay(10); | |
521 | S32(fccp, fcc_gfmr, FCC_GFMR_ENT); | |
522 | ||
976de6a8 | 523 | fcc_cr_cmd(fep, CPM_CR_RESTART_TX); |
48257c4f PA |
524 | } |
525 | ||
526 | /*************************************************************************/ | |
527 | ||
528 | const struct fs_ops fs_fcc_ops = { | |
529 | .setup_data = setup_data, | |
530 | .cleanup_data = cleanup_data, | |
531 | .set_multicast_list = set_multicast_list, | |
532 | .restart = restart, | |
533 | .stop = stop, | |
48257c4f PA |
534 | .napi_clear_rx_event = napi_clear_rx_event, |
535 | .napi_enable_rx = napi_enable_rx, | |
536 | .napi_disable_rx = napi_disable_rx, | |
537 | .rx_bd_done = rx_bd_done, | |
538 | .tx_kickstart = tx_kickstart, | |
539 | .get_int_events = get_int_events, | |
540 | .clear_int_events = clear_int_events, | |
541 | .ev_error = ev_error, | |
542 | .get_regs = get_regs, | |
543 | .get_regs_len = get_regs_len, | |
544 | .tx_restart = tx_restart, | |
545 | .allocate_bd = allocate_bd, | |
546 | .free_bd = free_bd, | |
547 | }; |