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1577ecef AF |
1 | /* |
2 | * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation | |
3 | * Provides Bus interface for MIIM regs | |
4 | * | |
5 | * Author: Andy Fleming <afleming@freescale.com> | |
6 | * | |
7 | * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/unistd.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <linux/skbuff.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/crc32.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/phy.h> | |
36 | #include <linux/of.h> | |
37 | #include <linux/of_platform.h> | |
38 | ||
39 | #include <asm/io.h> | |
40 | #include <asm/irq.h> | |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/ucc.h> | |
43 | ||
44 | #include "gianfar.h" | |
45 | #include "fsl_pq_mdio.h" | |
46 | ||
47 | /* | |
48 | * Write value to the PHY at mii_id at register regnum, | |
49 | * on the bus attached to the local interface, which may be different from the | |
50 | * generic mdio bus (tied to a single interface), waiting until the write is | |
51 | * done before returning. This is helpful in programming interfaces like | |
52 | * the TBI which control interfaces like onchip SERDES and are always tied to | |
53 | * the local mdio pins, which may not be the same as system mdio bus, used for | |
54 | * controlling the external PHYs, for example. | |
55 | */ | |
56 | int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id, | |
57 | int regnum, u16 value) | |
58 | { | |
59 | /* Set the PHY address and the register address we want to write */ | |
60 | out_be32(®s->miimadd, (mii_id << 8) | regnum); | |
61 | ||
62 | /* Write out the value we want */ | |
63 | out_be32(®s->miimcon, value); | |
64 | ||
65 | /* Wait for the transaction to finish */ | |
66 | while (in_be32(®s->miimind) & MIIMIND_BUSY) | |
67 | cpu_relax(); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
72 | /* | |
73 | * Read the bus for PHY at addr mii_id, register regnum, and | |
74 | * return the value. Clears miimcom first. All PHY operation | |
75 | * done on the bus attached to the local interface, | |
76 | * which may be different from the generic mdio bus | |
77 | * This is helpful in programming interfaces like | |
78 | * the TBI which, in turn, control interfaces like onchip SERDES | |
79 | * and are always tied to the local mdio pins, which may not be the | |
80 | * same as system mdio bus, used for controlling the external PHYs, for eg. | |
81 | */ | |
82 | int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, | |
83 | int mii_id, int regnum) | |
84 | { | |
85 | u16 value; | |
86 | ||
87 | /* Set the PHY address and the register address we want to read */ | |
88 | out_be32(®s->miimadd, (mii_id << 8) | regnum); | |
89 | ||
90 | /* Clear miimcom, and then initiate a read */ | |
91 | out_be32(®s->miimcom, 0); | |
92 | out_be32(®s->miimcom, MII_READ_COMMAND); | |
93 | ||
94 | /* Wait for the transaction to finish */ | |
95 | while (in_be32(®s->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)) | |
96 | cpu_relax(); | |
97 | ||
98 | /* Grab the value of the register from miimstat */ | |
99 | value = in_be32(®s->miimstat); | |
100 | ||
101 | return value; | |
102 | } | |
103 | ||
104 | /* | |
105 | * Write value to the PHY at mii_id at register regnum, | |
106 | * on the bus, waiting until the write is done before returning. | |
107 | */ | |
108 | int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) | |
109 | { | |
110 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
111 | ||
112 | /* Write to the local MII regs */ | |
113 | return(fsl_pq_local_mdio_write(regs, mii_id, regnum, value)); | |
114 | } | |
115 | ||
116 | /* | |
117 | * Read the bus for PHY at addr mii_id, register regnum, and | |
118 | * return the value. Clears miimcom first. | |
119 | */ | |
120 | int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |
121 | { | |
122 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
123 | ||
124 | /* Read the local MII regs */ | |
125 | return(fsl_pq_local_mdio_read(regs, mii_id, regnum)); | |
126 | } | |
127 | ||
128 | /* Reset the MIIM registers, and wait for the bus to free */ | |
129 | static int fsl_pq_mdio_reset(struct mii_bus *bus) | |
130 | { | |
131 | struct fsl_pq_mdio __iomem *regs = (void __iomem *)bus->priv; | |
508827ff | 132 | int timeout = PHY_INIT_TIMEOUT; |
1577ecef AF |
133 | |
134 | mutex_lock(&bus->mdio_lock); | |
135 | ||
136 | /* Reset the management interface */ | |
137 | out_be32(®s->miimcfg, MIIMCFG_RESET); | |
138 | ||
139 | /* Setup the MII Mgmt clock speed */ | |
140 | out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE); | |
141 | ||
142 | /* Wait until the bus is free */ | |
143 | while ((in_be32(®s->miimind) & MIIMIND_BUSY) && timeout--) | |
144 | cpu_relax(); | |
145 | ||
146 | mutex_unlock(&bus->mdio_lock); | |
147 | ||
508827ff | 148 | if (timeout < 0) { |
1577ecef AF |
149 | printk(KERN_ERR "%s: The MII Bus is stuck!\n", |
150 | bus->name); | |
151 | return -EBUSY; | |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | /* Allocate an array which provides irq #s for each PHY on the given bus */ | |
158 | static int *create_irq_map(struct device_node *np) | |
159 | { | |
160 | int *irqs; | |
161 | int i; | |
162 | struct device_node *child = NULL; | |
163 | ||
164 | irqs = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); | |
165 | ||
166 | if (!irqs) | |
167 | return NULL; | |
168 | ||
169 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
170 | irqs[i] = PHY_POLL; | |
171 | ||
172 | while ((child = of_get_next_child(np, child)) != NULL) { | |
173 | int irq = irq_of_parse_and_map(child, 0); | |
174 | const u32 *id; | |
175 | ||
176 | if (irq == NO_IRQ) | |
177 | continue; | |
178 | ||
179 | id = of_get_property(child, "reg", NULL); | |
180 | ||
181 | if (!id) | |
182 | continue; | |
183 | ||
184 | if (*id < PHY_MAX_ADDR && *id >= 0) | |
185 | irqs[*id] = irq; | |
186 | else | |
187 | printk(KERN_WARNING "%s: " | |
188 | "%d is not a valid PHY address\n", | |
189 | np->full_name, *id); | |
190 | } | |
191 | ||
192 | return irqs; | |
193 | } | |
194 | ||
195 | void fsl_pq_mdio_bus_name(char *name, struct device_node *np) | |
196 | { | |
18f27383 AV |
197 | const u32 *addr; |
198 | u64 taddr = OF_BAD_ADDR; | |
1577ecef | 199 | |
18f27383 AV |
200 | addr = of_get_address(np, 0, NULL, NULL); |
201 | if (addr) | |
202 | taddr = of_translate_address(np, addr); | |
1577ecef | 203 | |
18f27383 AV |
204 | snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name, |
205 | (unsigned long long)taddr); | |
1577ecef AF |
206 | } |
207 | ||
208 | /* Scan the bus in reverse, looking for an empty spot */ | |
209 | static int fsl_pq_mdio_find_free(struct mii_bus *new_bus) | |
210 | { | |
211 | int i; | |
212 | ||
213 | for (i = PHY_MAX_ADDR; i > 0; i--) { | |
214 | u32 phy_id; | |
215 | ||
216 | if (get_phy_id(new_bus, i, &phy_id)) | |
217 | return -1; | |
218 | ||
219 | if (phy_id == 0xffffffff) | |
220 | break; | |
221 | } | |
222 | ||
223 | return i; | |
224 | } | |
225 | ||
226 | ||
227 | #ifdef CONFIG_GIANFAR | |
228 | static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs) | |
229 | { | |
230 | struct gfar __iomem *enet_regs; | |
231 | ||
232 | /* | |
233 | * This is mildly evil, but so is our hardware for doing this. | |
234 | * Also, we have to cast back to struct gfar because of | |
235 | * definition weirdness done in gianfar.h. | |
236 | */ | |
237 | enet_regs = (struct gfar __iomem *) | |
238 | ((char __iomem *)regs - offsetof(struct gfar, gfar_mii_regs)); | |
239 | ||
240 | return &enet_regs->tbipa; | |
241 | } | |
242 | #endif | |
243 | ||
244 | ||
245 | #ifdef CONFIG_UCC_GETH | |
246 | static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id) | |
247 | { | |
248 | struct device_node *np = NULL; | |
249 | int err = 0; | |
250 | ||
251 | for_each_compatible_node(np, NULL, "ucc_geth") { | |
252 | struct resource tempres; | |
253 | ||
254 | err = of_address_to_resource(np, 0, &tempres); | |
255 | if (err) | |
256 | continue; | |
257 | ||
258 | /* if our mdio regs fall within this UCC regs range */ | |
259 | if ((start >= tempres.start) && (end <= tempres.end)) { | |
260 | /* Find the id of the UCC */ | |
261 | const u32 *id; | |
262 | ||
263 | id = of_get_property(np, "cell-index", NULL); | |
264 | if (!id) { | |
265 | id = of_get_property(np, "device-id", NULL); | |
266 | if (!id) | |
267 | continue; | |
268 | } | |
269 | ||
270 | *ucc_id = *id; | |
271 | ||
272 | return 0; | |
273 | } | |
274 | } | |
275 | ||
276 | if (err) | |
277 | return err; | |
278 | else | |
279 | return -EINVAL; | |
280 | } | |
281 | #endif | |
282 | ||
283 | ||
284 | static int fsl_pq_mdio_probe(struct of_device *ofdev, | |
285 | const struct of_device_id *match) | |
286 | { | |
287 | struct device_node *np = ofdev->node; | |
288 | struct device_node *tbi; | |
289 | struct fsl_pq_mdio __iomem *regs; | |
290 | u32 __iomem *tbipa; | |
291 | struct mii_bus *new_bus; | |
292 | int tbiaddr = -1; | |
293 | u64 addr, size; | |
294 | int err = 0; | |
295 | ||
296 | new_bus = mdiobus_alloc(); | |
297 | if (NULL == new_bus) | |
298 | return -ENOMEM; | |
299 | ||
300 | new_bus->name = "Freescale PowerQUICC MII Bus", | |
301 | new_bus->read = &fsl_pq_mdio_read, | |
302 | new_bus->write = &fsl_pq_mdio_write, | |
303 | new_bus->reset = &fsl_pq_mdio_reset, | |
304 | fsl_pq_mdio_bus_name(new_bus->id, np); | |
305 | ||
306 | /* Set the PHY base address */ | |
307 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
308 | regs = ioremap(addr, size); | |
309 | ||
310 | if (NULL == regs) { | |
311 | err = -ENOMEM; | |
312 | goto err_free_bus; | |
313 | } | |
314 | ||
315 | new_bus->priv = (void __force *)regs; | |
316 | ||
317 | new_bus->irq = create_irq_map(np); | |
318 | ||
319 | if (NULL == new_bus->irq) { | |
320 | err = -ENOMEM; | |
321 | goto err_unmap_regs; | |
322 | } | |
323 | ||
324 | new_bus->parent = &ofdev->dev; | |
325 | dev_set_drvdata(&ofdev->dev, new_bus); | |
326 | ||
327 | if (of_device_is_compatible(np, "fsl,gianfar-mdio") || | |
30196845 | 328 | of_device_is_compatible(np, "fsl,gianfar-tbi") || |
1577ecef AF |
329 | of_device_is_compatible(np, "gianfar")) { |
330 | #ifdef CONFIG_GIANFAR | |
331 | tbipa = get_gfar_tbipa(regs); | |
332 | #else | |
333 | err = -ENODEV; | |
334 | goto err_free_irqs; | |
335 | #endif | |
336 | } else if (of_device_is_compatible(np, "fsl,ucc-mdio") || | |
337 | of_device_is_compatible(np, "ucc_geth_phy")) { | |
338 | #ifdef CONFIG_UCC_GETH | |
339 | u32 id; | |
340 | ||
341 | tbipa = ®s->utbipar; | |
342 | ||
343 | if ((err = get_ucc_id_for_range(addr, addr + size, &id))) | |
344 | goto err_free_irqs; | |
345 | ||
346 | ucc_set_qe_mux_mii_mng(id - 1); | |
347 | #else | |
348 | err = -ENODEV; | |
349 | goto err_free_irqs; | |
350 | #endif | |
351 | } else { | |
352 | err = -ENODEV; | |
353 | goto err_free_irqs; | |
354 | } | |
355 | ||
356 | for_each_child_of_node(np, tbi) { | |
357 | if (!strncmp(tbi->type, "tbi-phy", 8)) | |
358 | break; | |
359 | } | |
360 | ||
361 | if (tbi) { | |
362 | const u32 *prop = of_get_property(tbi, "reg", NULL); | |
363 | ||
364 | if (prop) | |
365 | tbiaddr = *prop; | |
366 | } | |
367 | ||
368 | if (tbiaddr == -1) { | |
369 | out_be32(tbipa, 0); | |
370 | ||
371 | tbiaddr = fsl_pq_mdio_find_free(new_bus); | |
372 | } | |
373 | ||
374 | /* | |
375 | * We define TBIPA at 0 to be illegal, opting to fail for boards that | |
376 | * have PHYs at 1-31, rather than change tbipa and rescan. | |
377 | */ | |
378 | if (tbiaddr == 0) { | |
379 | err = -EBUSY; | |
380 | ||
381 | goto err_free_irqs; | |
382 | } | |
383 | ||
384 | out_be32(tbipa, tbiaddr); | |
385 | ||
386 | /* | |
387 | * The TBIPHY-only buses will find PHYs at every address, | |
388 | * so we mask them all but the TBI | |
389 | */ | |
390 | if (!of_device_is_compatible(np, "fsl,gianfar-mdio")) | |
391 | new_bus->phy_mask = ~(1 << tbiaddr); | |
392 | ||
393 | err = mdiobus_register(new_bus); | |
394 | ||
395 | if (err) { | |
396 | printk (KERN_ERR "%s: Cannot register as MDIO bus\n", | |
397 | new_bus->name); | |
398 | goto err_free_irqs; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | ||
403 | err_free_irqs: | |
404 | kfree(new_bus->irq); | |
405 | err_unmap_regs: | |
406 | iounmap(regs); | |
407 | err_free_bus: | |
408 | kfree(new_bus); | |
409 | ||
410 | return err; | |
411 | } | |
412 | ||
413 | ||
414 | static int fsl_pq_mdio_remove(struct of_device *ofdev) | |
415 | { | |
416 | struct device *device = &ofdev->dev; | |
417 | struct mii_bus *bus = dev_get_drvdata(device); | |
418 | ||
419 | mdiobus_unregister(bus); | |
420 | ||
421 | dev_set_drvdata(device, NULL); | |
422 | ||
423 | iounmap((void __iomem *)bus->priv); | |
424 | bus->priv = NULL; | |
425 | mdiobus_free(bus); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static struct of_device_id fsl_pq_mdio_match[] = { | |
431 | { | |
432 | .type = "mdio", | |
433 | .compatible = "ucc_geth_phy", | |
434 | }, | |
435 | { | |
436 | .type = "mdio", | |
437 | .compatible = "gianfar", | |
438 | }, | |
439 | { | |
440 | .compatible = "fsl,ucc-mdio", | |
441 | }, | |
442 | { | |
443 | .compatible = "fsl,gianfar-tbi", | |
444 | }, | |
445 | { | |
446 | .compatible = "fsl,gianfar-mdio", | |
447 | }, | |
448 | {}, | |
449 | }; | |
450 | ||
451 | static struct of_platform_driver fsl_pq_mdio_driver = { | |
452 | .name = "fsl-pq_mdio", | |
453 | .probe = fsl_pq_mdio_probe, | |
454 | .remove = fsl_pq_mdio_remove, | |
455 | .match_table = fsl_pq_mdio_match, | |
456 | }; | |
457 | ||
458 | int __init fsl_pq_mdio_init(void) | |
459 | { | |
460 | return of_register_platform_driver(&fsl_pq_mdio_driver); | |
461 | } | |
462 | ||
463 | void fsl_pq_mdio_exit(void) | |
464 | { | |
465 | of_unregister_platform_driver(&fsl_pq_mdio_driver); | |
466 | } | |
467 | subsys_initcall_sync(fsl_pq_mdio_init); | |
468 | module_exit(fsl_pq_mdio_exit); |