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af19b491 AKS |
1 | /* |
2 | * Copyright (C) 2009 - QLogic Corporation. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called "COPYING". | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _QLCNIC_H_ | |
26 | #define _QLCNIC_H_ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/in.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/firmware.h> | |
40 | ||
41 | #include <linux/ethtool.h> | |
42 | #include <linux/mii.h> | |
43 | #include <linux/timer.h> | |
44 | ||
45 | #include <linux/vmalloc.h> | |
46 | ||
47 | #include <linux/io.h> | |
48 | #include <asm/byteorder.h> | |
49 | ||
50 | #include "qlcnic_hdr.h" | |
51 | ||
52 | #define _QLCNIC_LINUX_MAJOR 5 | |
53 | #define _QLCNIC_LINUX_MINOR 0 | |
91fe8173 AKS |
54 | #define _QLCNIC_LINUX_SUBVERSION 8 |
55 | #define QLCNIC_LINUX_VERSIONID "5.0.8" | |
96f8118c | 56 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
57 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
58 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
59 | |
60 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
61 | #define _major(v) (((v) >> 24) & 0xff) | |
62 | #define _minor(v) (((v) >> 16) & 0xff) | |
63 | #define _build(v) ((v) & 0xffff) | |
64 | ||
65 | /* version in image has weird encoding: | |
66 | * 7:0 - major | |
67 | * 15:8 - minor | |
68 | * 31:16 - build (little endian) | |
69 | */ | |
70 | #define QLCNIC_DECODE_VERSION(v) \ | |
71 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
72 | ||
8f891387 | 73 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
74 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
75 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
76 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
77 | * QLCNIC_FLASH_SECTOR_SIZE) | |
78 | ||
79 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
80 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
81 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
82 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
83 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
84 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
85 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
86 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
87 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
88 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
89 | ||
90 | #define QLCNIC_P3P_A0 0x50 | |
91 | ||
92 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
93 | ||
94 | #define FIRST_PAGE_GROUP_START 0 | |
95 | #define FIRST_PAGE_GROUP_END 0x100000 | |
96 | ||
97 | #define P3_MAX_MTU (9600) | |
98 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ | |
99 | ||
100 | #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) | |
101 | #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU) | |
102 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 | |
103 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
104 | ||
af19b491 AKS |
105 | /* Opcodes to be used with the commands */ |
106 | #define TX_ETHER_PKT 0x01 | |
107 | #define TX_TCP_PKT 0x02 | |
108 | #define TX_UDP_PKT 0x03 | |
109 | #define TX_IP_PKT 0x04 | |
110 | #define TX_TCP_LSO 0x05 | |
111 | #define TX_TCP_LSO6 0x06 | |
112 | #define TX_IPSEC 0x07 | |
113 | #define TX_IPSEC_CMD 0x0a | |
114 | #define TX_TCPV6_PKT 0x0b | |
115 | #define TX_UDPV6_PKT 0x0c | |
116 | ||
117 | /* Tx defines */ | |
ef71ff83 RB |
118 | #define MAX_TSO_HEADER_DESC 2 |
119 | #define MGMT_CMD_DESC_RESV 4 | |
120 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
121 | + MGMT_CMD_DESC_RESV) | |
af19b491 AKS |
122 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
123 | ||
124 | /* | |
125 | * Following are the states of the Phantom. Phantom will set them and | |
126 | * Host will read to check if the fields are correct. | |
127 | */ | |
128 | #define PHAN_INITIALIZE_FAILED 0xffff | |
129 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
130 | ||
131 | /* Host writes the following to notify that it has done the init-handshake */ | |
132 | #define PHAN_INITIALIZE_ACK 0xf00f | |
133 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
134 | ||
135 | #define NUM_RCV_DESC_RINGS 3 | |
136 | #define NUM_STS_DESC_RINGS 4 | |
137 | ||
138 | #define RCV_RING_NORMAL 0 | |
139 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
140 | |
141 | #define MIN_CMD_DESCRIPTORS 64 | |
142 | #define MIN_RCV_DESCRIPTORS 64 | |
143 | #define MIN_JUMBO_DESCRIPTORS 32 | |
144 | ||
145 | #define MAX_CMD_DESCRIPTORS 1024 | |
146 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
147 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
148 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 | |
149 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
150 | |
151 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
152 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
251b036a | 153 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
154 | |
155 | #define get_next_index(index, length) \ | |
156 | (((index) + 1) & ((length) - 1)) | |
157 | ||
af19b491 AKS |
158 | /* |
159 | * Following data structures describe the descriptors that will be used. | |
160 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
161 | * we are doing LSO (above the 1500 size packet) only. | |
162 | */ | |
163 | ||
164 | #define FLAGS_VLAN_TAGGED 0x10 | |
165 | #define FLAGS_VLAN_OOB 0x40 | |
166 | ||
167 | #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \ | |
168 | (cmd_desc)->vlan_TCI = cpu_to_le16(v); | |
169 | #define qlcnic_set_cmd_desc_port(cmd_desc, var) \ | |
170 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
171 | #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \ | |
172 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) | |
173 | ||
174 | #define qlcnic_set_tx_port(_desc, _port) \ | |
175 | ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) | |
176 | ||
177 | #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
178 | ((_desc)->flags_opcode = \ | |
179 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))) | |
180 | ||
181 | #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \ | |
182 | ((_desc)->nfrags__length = \ | |
183 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))) | |
184 | ||
185 | struct cmd_desc_type0 { | |
186 | u8 tcp_hdr_offset; /* For LSO only */ | |
187 | u8 ip_hdr_offset; /* For LSO only */ | |
188 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
189 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
190 | ||
191 | __le64 addr_buffer2; | |
192 | ||
193 | __le16 reference_handle; | |
194 | __le16 mss; | |
195 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
196 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
197 | __le16 conn_id; /* IPSec offoad only */ | |
198 | ||
199 | __le64 addr_buffer3; | |
200 | __le64 addr_buffer1; | |
201 | ||
202 | __le16 buffer_length[4]; | |
203 | ||
204 | __le64 addr_buffer4; | |
205 | ||
2e9d722d | 206 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
207 | __le16 vlan_TCI; |
208 | ||
209 | } __attribute__ ((aligned(64))); | |
210 | ||
211 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
212 | struct rcv_desc { | |
213 | __le16 reference_handle; | |
214 | __le16 reserved; | |
215 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
216 | __le64 addr_buffer; | |
217 | }; | |
218 | ||
219 | /* opcode field in status_desc */ | |
220 | #define QLCNIC_SYN_OFFLOAD 0x03 | |
221 | #define QLCNIC_RXPKT_DESC 0x04 | |
222 | #define QLCNIC_OLD_RXPKT_DESC 0x3f | |
223 | #define QLCNIC_RESPONSE_DESC 0x05 | |
224 | #define QLCNIC_LRO_DESC 0x12 | |
225 | ||
226 | /* for status field in status_desc */ | |
227 | #define STATUS_CKSUM_OK (2) | |
228 | ||
229 | /* owner bits of status_desc */ | |
230 | #define STATUS_OWNER_HOST (0x1ULL << 56) | |
231 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
232 | ||
233 | /* Status descriptor: | |
234 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length | |
235 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset | |
236 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
237 | */ | |
238 | #define qlcnic_get_sts_port(sts_data) \ | |
239 | ((sts_data) & 0x0F) | |
240 | #define qlcnic_get_sts_status(sts_data) \ | |
241 | (((sts_data) >> 4) & 0x0F) | |
242 | #define qlcnic_get_sts_type(sts_data) \ | |
243 | (((sts_data) >> 8) & 0x0F) | |
244 | #define qlcnic_get_sts_totallength(sts_data) \ | |
245 | (((sts_data) >> 12) & 0xFFFF) | |
246 | #define qlcnic_get_sts_refhandle(sts_data) \ | |
247 | (((sts_data) >> 28) & 0xFFFF) | |
248 | #define qlcnic_get_sts_prot(sts_data) \ | |
249 | (((sts_data) >> 44) & 0x0F) | |
250 | #define qlcnic_get_sts_pkt_offset(sts_data) \ | |
251 | (((sts_data) >> 48) & 0x1F) | |
252 | #define qlcnic_get_sts_desc_cnt(sts_data) \ | |
253 | (((sts_data) >> 53) & 0x7) | |
254 | #define qlcnic_get_sts_opcode(sts_data) \ | |
255 | (((sts_data) >> 58) & 0x03F) | |
256 | ||
257 | #define qlcnic_get_lro_sts_refhandle(sts_data) \ | |
258 | ((sts_data) & 0x0FFFF) | |
259 | #define qlcnic_get_lro_sts_length(sts_data) \ | |
260 | (((sts_data) >> 16) & 0x0FFFF) | |
261 | #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \ | |
262 | (((sts_data) >> 32) & 0x0FF) | |
263 | #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \ | |
264 | (((sts_data) >> 40) & 0x0FF) | |
265 | #define qlcnic_get_lro_sts_timestamp(sts_data) \ | |
266 | (((sts_data) >> 48) & 0x1) | |
267 | #define qlcnic_get_lro_sts_type(sts_data) \ | |
268 | (((sts_data) >> 49) & 0x7) | |
269 | #define qlcnic_get_lro_sts_push_flag(sts_data) \ | |
270 | (((sts_data) >> 52) & 0x1) | |
271 | #define qlcnic_get_lro_sts_seq_number(sts_data) \ | |
272 | ((sts_data) & 0x0FFFFFFFF) | |
273 | ||
274 | ||
275 | struct status_desc { | |
276 | __le64 status_desc_data[2]; | |
277 | } __attribute__ ((aligned(16))); | |
278 | ||
279 | /* UNIFIED ROMIMAGE */ | |
280 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
281 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
282 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
283 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
284 | ||
285 | /*Offsets */ | |
286 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
287 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
288 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
289 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
290 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
291 | ||
292 | struct uni_table_desc{ | |
293 | u32 findex; | |
294 | u32 num_entries; | |
295 | u32 entry_size; | |
296 | u32 reserved[5]; | |
297 | }; | |
298 | ||
299 | struct uni_data_desc{ | |
300 | u32 findex; | |
301 | u32 size; | |
302 | u32 reserved[5]; | |
303 | }; | |
304 | ||
305 | /* Magic number to let user know flash is programmed */ | |
306 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
307 | ||
308 | #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021 | |
309 | #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022 | |
310 | #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023 | |
311 | #define QLCNIC_BRDTYPE_P3_4_GB 0x0024 | |
312 | #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025 | |
313 | #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026 | |
314 | #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027 | |
315 | #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028 | |
316 | #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029 | |
317 | #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a | |
318 | #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b | |
319 | #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031 | |
320 | #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032 | |
321 | #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080 | |
322 | ||
2e9d722d AC |
323 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
324 | ||
af19b491 AKS |
325 | /* Flash memory map */ |
326 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
327 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
328 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
329 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
330 | ||
331 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
332 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
333 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
334 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
335 | ||
336 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
337 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
338 | ||
339 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
340 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
341 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
342 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
343 | ||
344 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
345 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
346 | ||
347 | extern char qlcnic_driver_name[]; | |
348 | ||
349 | /* Number of status descriptors to handle per interrupt */ | |
350 | #define MAX_STATUS_HANDLE (64) | |
351 | ||
352 | /* | |
353 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
354 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
355 | */ | |
356 | struct qlcnic_skb_frag { | |
357 | u64 dma; | |
358 | u64 length; | |
359 | }; | |
360 | ||
361 | struct qlcnic_recv_crb { | |
362 | u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; | |
363 | u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; | |
364 | u32 sw_int_mask[NUM_STS_DESC_RINGS]; | |
365 | }; | |
366 | ||
367 | /* Following defines are for the state of the buffers */ | |
368 | #define QLCNIC_BUFFER_FREE 0 | |
369 | #define QLCNIC_BUFFER_BUSY 1 | |
370 | ||
371 | /* | |
372 | * There will be one qlcnic_buffer per skb packet. These will be | |
373 | * used to save the dma info for pci_unmap_page() | |
374 | */ | |
375 | struct qlcnic_cmd_buffer { | |
376 | struct sk_buff *skb; | |
ef71ff83 | 377 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
378 | u32 frag_count; |
379 | }; | |
380 | ||
381 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
382 | struct qlcnic_rx_buffer { | |
383 | struct list_head list; | |
384 | struct sk_buff *skb; | |
385 | u64 dma; | |
386 | u16 ref_handle; | |
af19b491 AKS |
387 | }; |
388 | ||
389 | /* Board types */ | |
390 | #define QLCNIC_GBE 0x01 | |
391 | #define QLCNIC_XGBE 0x02 | |
392 | ||
393 | /* | |
394 | * One hardware_context{} per adapter | |
395 | * contains interrupt info as well shared hardware info. | |
396 | */ | |
397 | struct qlcnic_hardware_context { | |
398 | void __iomem *pci_base0; | |
399 | void __iomem *ocm_win_crb; | |
400 | ||
401 | unsigned long pci_len0; | |
402 | ||
af19b491 AKS |
403 | rwlock_t crb_lock; |
404 | struct mutex mem_lock; | |
405 | ||
af19b491 AKS |
406 | u8 revision_id; |
407 | u8 pci_func; | |
408 | u8 linkup; | |
409 | u16 port_type; | |
410 | u16 board_type; | |
411 | }; | |
412 | ||
413 | struct qlcnic_adapter_stats { | |
414 | u64 xmitcalled; | |
415 | u64 xmitfinished; | |
416 | u64 rxdropped; | |
417 | u64 txdropped; | |
418 | u64 csummed; | |
419 | u64 rx_pkts; | |
420 | u64 lro_pkts; | |
421 | u64 rxbytes; | |
422 | u64 txbytes; | |
8bfe8b91 SC |
423 | u64 lrobytes; |
424 | u64 lso_frames; | |
425 | u64 xmit_on; | |
426 | u64 xmit_off; | |
427 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
428 | u64 null_rxbuf; |
429 | u64 rx_dma_map_error; | |
430 | u64 tx_dma_map_error; | |
af19b491 AKS |
431 | }; |
432 | ||
433 | /* | |
434 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
435 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
436 | */ | |
437 | struct qlcnic_host_rds_ring { | |
438 | u32 producer; | |
439 | u32 num_desc; | |
440 | u32 dma_size; | |
441 | u32 skb_size; | |
442 | u32 flags; | |
443 | void __iomem *crb_rcv_producer; | |
444 | struct rcv_desc *desc_head; | |
445 | struct qlcnic_rx_buffer *rx_buf_arr; | |
446 | struct list_head free_list; | |
447 | spinlock_t lock; | |
448 | dma_addr_t phys_addr; | |
449 | }; | |
450 | ||
451 | struct qlcnic_host_sds_ring { | |
452 | u32 consumer; | |
453 | u32 num_desc; | |
454 | void __iomem *crb_sts_consumer; | |
455 | void __iomem *crb_intr_mask; | |
456 | ||
457 | struct status_desc *desc_head; | |
458 | struct qlcnic_adapter *adapter; | |
459 | struct napi_struct napi; | |
460 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
461 | ||
462 | int irq; | |
463 | ||
464 | dma_addr_t phys_addr; | |
465 | char name[IFNAMSIZ+4]; | |
466 | }; | |
467 | ||
468 | struct qlcnic_host_tx_ring { | |
469 | u32 producer; | |
470 | __le32 *hw_consumer; | |
471 | u32 sw_consumer; | |
472 | void __iomem *crb_cmd_producer; | |
473 | u32 num_desc; | |
474 | ||
475 | struct netdev_queue *txq; | |
476 | ||
477 | struct qlcnic_cmd_buffer *cmd_buf_arr; | |
478 | struct cmd_desc_type0 *desc_head; | |
479 | dma_addr_t phys_addr; | |
480 | dma_addr_t hw_cons_phys_addr; | |
481 | }; | |
482 | ||
483 | /* | |
484 | * Receive context. There is one such structure per instance of the | |
485 | * receive processing. Any state information that is relevant to | |
486 | * the receive, and is must be in this structure. The global data may be | |
487 | * present elsewhere. | |
488 | */ | |
489 | struct qlcnic_recv_context { | |
490 | u32 state; | |
491 | u16 context_id; | |
492 | u16 virt_port; | |
493 | ||
494 | struct qlcnic_host_rds_ring *rds_rings; | |
495 | struct qlcnic_host_sds_ring *sds_rings; | |
496 | }; | |
497 | ||
498 | /* HW context creation */ | |
499 | ||
500 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
501 | #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
502 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
503 | ||
504 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
505 | ||
506 | /* | |
507 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
508 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
509 | */ | |
510 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
511 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
512 | ||
513 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
514 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
515 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
516 | ||
517 | /* | |
518 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
519 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
520 | */ | |
521 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
522 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
523 | ||
524 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
525 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
526 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
527 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
528 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
529 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
530 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
531 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
532 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
533 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
534 | #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
535 | #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f | |
536 | #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
537 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 | |
538 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
539 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
540 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
541 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
542 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
543 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
544 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
545 | #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a | |
546 | #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b | |
547 | #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c | |
548 | #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d | |
549 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e | |
2e9d722d AC |
550 | #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
551 | ||
552 | #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 | |
553 | #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 | |
554 | #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 | |
555 | #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023 | |
556 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 | |
557 | #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 | |
558 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 | |
559 | #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 | |
560 | #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 | |
4e8acb01 | 561 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
b6021212 | 562 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
af19b491 AKS |
563 | |
564 | #define QLCNIC_RCODE_SUCCESS 0 | |
565 | #define QLCNIC_RCODE_TIMEOUT 17 | |
566 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
567 | ||
568 | /* | |
569 | * Capabilities Announced | |
570 | */ | |
571 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
572 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
573 | #define QLCNIC_CAP0_LSO (1 << 6) | |
574 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
575 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 576 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
af19b491 AKS |
577 | |
578 | /* | |
579 | * Context state | |
580 | */ | |
d626ad4d | 581 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
582 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
583 | ||
584 | /* | |
585 | * Rx context | |
586 | */ | |
587 | ||
588 | struct qlcnic_hostrq_sds_ring { | |
589 | __le64 host_phys_addr; /* Ring base addr */ | |
590 | __le32 ring_size; /* Ring entries */ | |
591 | __le16 msi_index; | |
592 | __le16 rsvd; /* Padding */ | |
593 | }; | |
594 | ||
595 | struct qlcnic_hostrq_rds_ring { | |
596 | __le64 host_phys_addr; /* Ring base addr */ | |
597 | __le64 buff_size; /* Packet buffer size */ | |
598 | __le32 ring_size; /* Ring entries */ | |
599 | __le32 ring_kind; /* Class of ring */ | |
600 | }; | |
601 | ||
602 | struct qlcnic_hostrq_rx_ctx { | |
603 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
604 | __le32 capabilities[4]; /* Flag bit vector */ | |
605 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
606 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
607 | /* These ring offsets are relative to data[0] below */ | |
608 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
609 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
610 | __le16 num_rds_rings; /* Count of RDS rings */ | |
611 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 612 | __le16 valid_field_offset; |
613 | u8 txrx_sds_binding; | |
614 | u8 msix_handler; | |
615 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
616 | /* MUST BE 64-bit aligned. |
617 | The following is packed: | |
618 | - N hostrq_rds_rings | |
619 | - N hostrq_sds_rings */ | |
620 | char data[0]; | |
621 | }; | |
622 | ||
623 | struct qlcnic_cardrsp_rds_ring{ | |
624 | __le32 host_producer_crb; /* Crb to use */ | |
625 | __le32 rsvd1; /* Padding */ | |
626 | }; | |
627 | ||
628 | struct qlcnic_cardrsp_sds_ring { | |
629 | __le32 host_consumer_crb; /* Crb to use */ | |
630 | __le32 interrupt_crb; /* Crb to use */ | |
631 | }; | |
632 | ||
633 | struct qlcnic_cardrsp_rx_ctx { | |
634 | /* These ring offsets are relative to data[0] below */ | |
635 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
636 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
637 | __le32 host_ctx_state; /* Starting State */ | |
638 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
639 | __le16 num_rds_rings; /* Count of RDS rings */ | |
640 | __le16 num_sds_rings; /* Count of SDS rings */ | |
641 | __le16 context_id; /* Handle for context */ | |
642 | u8 phys_port; /* Physical id of port */ | |
643 | u8 virt_port; /* Virtual/Logical id of port */ | |
644 | u8 reserved[128]; /* save space for future expansion */ | |
645 | /* MUST BE 64-bit aligned. | |
646 | The following is packed: | |
647 | - N cardrsp_rds_rings | |
648 | - N cardrs_sds_rings */ | |
649 | char data[0]; | |
650 | }; | |
651 | ||
652 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
653 | (sizeof(HOSTRQ_RX) + \ | |
654 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
655 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
656 | ||
657 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
658 | (sizeof(CARDRSP_RX) + \ | |
659 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
660 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
661 | ||
662 | /* | |
663 | * Tx context | |
664 | */ | |
665 | ||
666 | struct qlcnic_hostrq_cds_ring { | |
667 | __le64 host_phys_addr; /* Ring base addr */ | |
668 | __le32 ring_size; /* Ring entries */ | |
669 | __le32 rsvd; /* Padding */ | |
670 | }; | |
671 | ||
672 | struct qlcnic_hostrq_tx_ctx { | |
673 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
674 | __le64 cmd_cons_dma_addr; /* */ | |
675 | __le64 dummy_dma_addr; /* */ | |
676 | __le32 capabilities[4]; /* Flag bit vector */ | |
677 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
678 | __le32 rsvd1; /* Padding */ | |
679 | __le16 rsvd2; /* Padding */ | |
680 | __le16 interrupt_ctl; | |
681 | __le16 msi_index; | |
682 | __le16 rsvd3; /* Padding */ | |
683 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
684 | u8 reserved[128]; /* future expansion */ | |
685 | }; | |
686 | ||
687 | struct qlcnic_cardrsp_cds_ring { | |
688 | __le32 host_producer_crb; /* Crb to use */ | |
689 | __le32 interrupt_crb; /* Crb to use */ | |
690 | }; | |
691 | ||
692 | struct qlcnic_cardrsp_tx_ctx { | |
693 | __le32 host_ctx_state; /* Starting state */ | |
694 | __le16 context_id; /* Handle for context */ | |
695 | u8 phys_port; /* Physical id of port */ | |
696 | u8 virt_port; /* Virtual/Logical id of port */ | |
697 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
698 | u8 reserved[128]; /* future expansion */ | |
699 | }; | |
700 | ||
701 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
702 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
703 | ||
704 | /* CRB */ | |
705 | ||
706 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
707 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
708 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
709 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
710 | ||
711 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
712 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
713 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
714 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
715 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
716 | ||
717 | ||
718 | /* MAC */ | |
719 | ||
720 | #define MC_COUNT_P3 38 | |
721 | ||
722 | #define QLCNIC_MAC_NOOP 0 | |
723 | #define QLCNIC_MAC_ADD 1 | |
724 | #define QLCNIC_MAC_DEL 2 | |
725 | ||
726 | struct qlcnic_mac_list_s { | |
727 | struct list_head list; | |
728 | uint8_t mac_addr[ETH_ALEN+2]; | |
729 | }; | |
730 | ||
731 | /* | |
732 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
733 | * adjusted based on configured MTU. | |
734 | */ | |
735 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
736 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
737 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
738 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
739 | ||
740 | #define QLCNIC_INTR_DEFAULT 0x04 | |
741 | ||
742 | union qlcnic_nic_intr_coalesce_data { | |
743 | struct { | |
744 | u16 rx_packets; | |
745 | u16 rx_time_us; | |
746 | u16 tx_packets; | |
747 | u16 tx_time_us; | |
748 | } data; | |
749 | u64 word; | |
750 | }; | |
751 | ||
752 | struct qlcnic_nic_intr_coalesce { | |
753 | u16 stats_time_us; | |
754 | u16 rate_sample_time; | |
755 | u16 flags; | |
756 | u16 rsvd_1; | |
757 | u32 low_threshold; | |
758 | u32 high_threshold; | |
759 | union qlcnic_nic_intr_coalesce_data normal; | |
760 | union qlcnic_nic_intr_coalesce_data low; | |
761 | union qlcnic_nic_intr_coalesce_data high; | |
762 | union qlcnic_nic_intr_coalesce_data irq; | |
763 | }; | |
764 | ||
765 | #define QLCNIC_HOST_REQUEST 0x13 | |
766 | #define QLCNIC_REQUEST 0x14 | |
767 | ||
768 | #define QLCNIC_MAC_EVENT 0x1 | |
769 | ||
770 | #define QLCNIC_IP_UP 2 | |
771 | #define QLCNIC_IP_DOWN 3 | |
772 | ||
773 | /* | |
774 | * Driver --> Firmware | |
775 | */ | |
776 | #define QLCNIC_H2C_OPCODE_START 0 | |
777 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1 | |
778 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2 | |
779 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 | |
780 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 4 | |
781 | #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 | |
782 | #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6 | |
783 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7 | |
784 | #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8 | |
785 | #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9 | |
786 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 | |
787 | #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11 | |
788 | #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 | |
789 | #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 | |
790 | #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 | |
791 | #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 | |
792 | #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16 | |
793 | #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 | |
794 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18 | |
795 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19 | |
796 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20 | |
797 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21 | |
798 | #define QLCNIC_C2C_OPCODE 22 | |
799 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23 | |
800 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24 | |
801 | #define QLCNIC_H2C_OPCODE_LAST 25 | |
802 | /* | |
803 | * Firmware --> Driver | |
804 | */ | |
805 | ||
806 | #define QLCNIC_C2H_OPCODE_START 128 | |
807 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 | |
808 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 | |
809 | #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 | |
810 | #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 | |
811 | #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 | |
812 | #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 | |
813 | #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 | |
814 | #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136 | |
815 | #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 | |
816 | #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 | |
817 | #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 | |
818 | #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 | |
819 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 | |
820 | #define QLCNIC_C2H_OPCODE_LAST 142 | |
821 | ||
822 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
823 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
824 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
825 | ||
826 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
827 | ||
828 | /* Capabilites received */ | |
ac8d0c4f AC |
829 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
830 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
831 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
832 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
af19b491 AKS |
833 | |
834 | /* module types */ | |
835 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
836 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
837 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
838 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
839 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
840 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
841 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
842 | #define LINKEVENT_MODULE_TWINAX 8 | |
843 | ||
844 | #define LINKSPEED_10GBPS 10000 | |
845 | #define LINKSPEED_1GBPS 1000 | |
846 | #define LINKSPEED_100MBPS 100 | |
847 | #define LINKSPEED_10MBPS 10 | |
848 | ||
849 | #define LINKSPEED_ENCODED_10MBPS 0 | |
850 | #define LINKSPEED_ENCODED_100MBPS 1 | |
851 | #define LINKSPEED_ENCODED_1GBPS 2 | |
852 | ||
853 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
854 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
855 | ||
856 | #define LINKEVENT_HALF_DUPLEX 0 | |
857 | #define LINKEVENT_FULL_DUPLEX 1 | |
858 | ||
859 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
860 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
861 | ||
862 | #define AUTO_FW_RESET_ENABLED 0x01 | |
863 | /* firmware response header: | |
864 | * 63:58 - message type | |
865 | * 57:56 - owner | |
866 | * 55:53 - desc count | |
867 | * 52:48 - reserved | |
868 | * 47:40 - completion id | |
869 | * 39:32 - opcode | |
870 | * 31:16 - error code | |
871 | * 15:00 - reserved | |
872 | */ | |
873 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
874 | ((msg_hdr >> 32) & 0xFF) | |
875 | ||
876 | struct qlcnic_fw_msg { | |
877 | union { | |
878 | struct { | |
879 | u64 hdr; | |
880 | u64 body[7]; | |
881 | }; | |
882 | u64 words[8]; | |
883 | }; | |
884 | }; | |
885 | ||
886 | struct qlcnic_nic_req { | |
887 | __le64 qhdr; | |
888 | __le64 req_hdr; | |
889 | __le64 words[6]; | |
890 | }; | |
891 | ||
892 | struct qlcnic_mac_req { | |
893 | u8 op; | |
894 | u8 tag; | |
895 | u8 mac_addr[6]; | |
896 | }; | |
897 | ||
898 | #define QLCNIC_MSI_ENABLED 0x02 | |
899 | #define QLCNIC_MSIX_ENABLED 0x04 | |
900 | #define QLCNIC_LRO_ENABLED 0x08 | |
24763d80 | 901 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
902 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
903 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 904 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
fe4d434d | 905 | #define QLCNIC_MACSPOOF 0x200 |
af19b491 AKS |
906 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
907 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
908 | ||
909 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS | |
910 | #define QLCNIC_MSIX_TBL_SPACE 8192 | |
911 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 912 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
913 | |
914 | #define QLCNIC_NETDEV_WEIGHT 128 | |
915 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
916 | ||
917 | #define __QLCNIC_FW_ATTACHED 0 | |
918 | #define __QLCNIC_DEV_UP 1 | |
919 | #define __QLCNIC_RESETTING 2 | |
920 | #define __QLCNIC_START_FW 4 | |
451724c8 | 921 | #define __QLCNIC_AER 5 |
af19b491 | 922 | |
7eb9855d | 923 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 924 | #define QLCNIC_LOOPBACK_TEST 2 |
7eb9855d | 925 | |
af19b491 AKS |
926 | struct qlcnic_adapter { |
927 | struct qlcnic_hardware_context ahw; | |
928 | ||
929 | struct net_device *netdev; | |
930 | struct pci_dev *pdev; | |
931 | struct list_head mac_list; | |
932 | ||
933 | spinlock_t tx_clean_lock; | |
934 | ||
935 | u16 num_txd; | |
936 | u16 num_rxd; | |
937 | u16 num_jumbo_rxd; | |
af19b491 AKS |
938 | |
939 | u8 max_rds_rings; | |
940 | u8 max_sds_rings; | |
af19b491 AKS |
941 | u8 msix_supported; |
942 | u8 rx_csum; | |
af19b491 AKS |
943 | u8 portnum; |
944 | u8 physical_port; | |
68bf1c68 | 945 | u8 reset_context; |
af19b491 AKS |
946 | |
947 | u8 mc_enabled; | |
948 | u8 max_mc_count; | |
949 | u8 rss_supported; | |
af19b491 AKS |
950 | u8 fw_wait_cnt; |
951 | u8 fw_fail_cnt; | |
952 | u8 tx_timeo_cnt; | |
953 | u8 need_fw_reset; | |
954 | ||
955 | u8 has_link_events; | |
956 | u8 fw_type; | |
957 | u16 tx_context_id; | |
af19b491 AKS |
958 | u16 is_up; |
959 | ||
960 | u16 link_speed; | |
961 | u16 link_duplex; | |
962 | u16 link_autoneg; | |
963 | u16 module_type; | |
964 | ||
2e9d722d AC |
965 | u16 op_mode; |
966 | u16 switch_mode; | |
967 | u16 max_tx_ques; | |
968 | u16 max_rx_ques; | |
2e9d722d AC |
969 | u16 max_mtu; |
970 | ||
971 | u32 fw_hal_version; | |
af19b491 AKS |
972 | u32 capabilities; |
973 | u32 flags; | |
974 | u32 irq; | |
975 | u32 temp; | |
976 | ||
977 | u32 int_vec_bit; | |
978 | u32 heartbit; | |
979 | ||
2e9d722d | 980 | u8 max_mac_filters; |
af19b491 | 981 | u8 dev_state; |
7eb9855d AKS |
982 | u8 diag_test; |
983 | u8 diag_cnt; | |
aa5e18c0 SC |
984 | u8 reset_ack_timeo; |
985 | u8 dev_init_timeo; | |
65b5b420 | 986 | u16 msg_enable; |
af19b491 AKS |
987 | |
988 | u8 mac_addr[ETH_ALEN]; | |
989 | ||
6df900e9 SC |
990 | u64 dev_rst_time; |
991 | ||
346fe763 | 992 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
993 | struct qlcnic_eswitch *eswitch; |
994 | struct qlcnic_nic_template *nic_ops; | |
995 | ||
af19b491 AKS |
996 | struct qlcnic_adapter_stats stats; |
997 | ||
998 | struct qlcnic_recv_context recv_ctx; | |
999 | struct qlcnic_host_tx_ring *tx_ring; | |
1000 | ||
1001 | void __iomem *tgt_mask_reg; | |
1002 | void __iomem *tgt_status_reg; | |
1003 | void __iomem *crb_int_state_reg; | |
1004 | void __iomem *isr_int_vec; | |
1005 | ||
1006 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; | |
1007 | ||
1008 | struct delayed_work fw_work; | |
1009 | ||
af19b491 AKS |
1010 | struct qlcnic_nic_intr_coalesce coal; |
1011 | ||
1012 | unsigned long state; | |
1013 | __le32 file_prd_off; /*File fw product offset*/ | |
1014 | u32 fw_version; | |
1015 | const struct firmware *fw; | |
1016 | }; | |
1017 | ||
2e9d722d AC |
1018 | struct qlcnic_info { |
1019 | __le16 pci_func; | |
1020 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ | |
1021 | __le16 phys_port; | |
1022 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ | |
1023 | ||
1024 | __le32 capabilities; | |
1025 | u8 max_mac_filters; | |
1026 | u8 reserved1; | |
1027 | __le16 max_mtu; | |
1028 | ||
1029 | __le16 max_tx_ques; | |
1030 | __le16 max_rx_ques; | |
1031 | __le16 min_tx_bw; | |
1032 | __le16 max_tx_bw; | |
1033 | u8 reserved2[104]; | |
1034 | }; | |
1035 | ||
1036 | struct qlcnic_pci_info { | |
1037 | __le16 id; /* pci function id */ | |
1038 | __le16 active; /* 1 = Enabled */ | |
1039 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1040 | __le16 default_port; /* default port number */ | |
1041 | ||
1042 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
1043 | __le16 tx_max_bw; | |
1044 | __le16 reserved1[2]; | |
1045 | ||
1046 | u8 mac[ETH_ALEN]; | |
1047 | u8 reserved2[106]; | |
1048 | }; | |
1049 | ||
346fe763 | 1050 | struct qlcnic_npar_info { |
4e8acb01 | 1051 | u16 pvid; |
cea8975e AC |
1052 | u16 min_bw; |
1053 | u16 max_bw; | |
346fe763 RB |
1054 | u8 phy_port; |
1055 | u8 type; | |
1056 | u8 active; | |
1057 | u8 enable_pm; | |
1058 | u8 dest_npar; | |
346fe763 RB |
1059 | u8 discard_tagged; |
1060 | u8 mac_learning; | |
4e8acb01 RB |
1061 | u8 mac_anti_spoof; |
1062 | u8 promisc_mode; | |
1063 | u8 offload_flags; | |
346fe763 | 1064 | }; |
4e8acb01 | 1065 | |
2e9d722d AC |
1066 | struct qlcnic_eswitch { |
1067 | u8 port; | |
1068 | u8 active_vports; | |
1069 | u8 active_vlans; | |
1070 | u8 active_ucast_filters; | |
1071 | u8 max_ucast_filters; | |
1072 | u8 max_active_vlans; | |
1073 | ||
1074 | u32 flags; | |
1075 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1076 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1077 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1078 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1079 | }; | |
1080 | ||
346fe763 RB |
1081 | |
1082 | /* Return codes for Error handling */ | |
1083 | #define QL_STATUS_INVALID_PARAM -1 | |
1084 | ||
9963a8bd RB |
1085 | #define MAX_BW 100 |
1086 | #define MIN_BW 1 | |
346fe763 RB |
1087 | #define MAX_VLAN_ID 4095 |
1088 | #define MIN_VLAN_ID 2 | |
1089 | #define MAX_TX_QUEUES 1 | |
1090 | #define MAX_RX_QUEUES 4 | |
1091 | #define DEFAULT_MAC_LEARN 1 | |
1092 | ||
1093 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan <= MAX_VLAN_ID) | |
9963a8bd | 1094 | #define IS_VALID_BW(bw) (bw >= MIN_BW && bw <= MAX_BW) |
346fe763 RB |
1095 | #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES) |
1096 | #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES) | |
346fe763 RB |
1097 | |
1098 | struct qlcnic_pci_func_cfg { | |
1099 | u16 func_type; | |
1100 | u16 min_bw; | |
1101 | u16 max_bw; | |
1102 | u16 port_num; | |
1103 | u8 pci_func; | |
1104 | u8 func_state; | |
1105 | u8 def_mac_addr[6]; | |
1106 | }; | |
1107 | ||
1108 | struct qlcnic_npar_func_cfg { | |
1109 | u32 fw_capab; | |
1110 | u16 port_num; | |
1111 | u16 min_bw; | |
1112 | u16 max_bw; | |
1113 | u16 max_tx_queues; | |
1114 | u16 max_rx_queues; | |
1115 | u8 pci_func; | |
1116 | u8 op_mode; | |
1117 | }; | |
1118 | ||
1119 | struct qlcnic_pm_func_cfg { | |
1120 | u8 pci_func; | |
1121 | u8 action; | |
1122 | u8 dest_npar; | |
1123 | u8 reserved[5]; | |
1124 | }; | |
1125 | ||
1126 | struct qlcnic_esw_func_cfg { | |
1127 | u16 vlan_id; | |
4e8acb01 RB |
1128 | u8 op_mode; |
1129 | u8 op_type; | |
346fe763 RB |
1130 | u8 pci_func; |
1131 | u8 host_vlan_tag; | |
1132 | u8 promisc_mode; | |
1133 | u8 discard_tagged; | |
1134 | u8 mac_learning; | |
4e8acb01 RB |
1135 | u8 mac_anti_spoof; |
1136 | u8 offload_flags; | |
1137 | u8 reserved[5]; | |
346fe763 RB |
1138 | }; |
1139 | ||
b6021212 AKS |
1140 | #define QLCNIC_STATS_VERSION 1 |
1141 | #define QLCNIC_STATS_PORT 1 | |
1142 | #define QLCNIC_STATS_ESWITCH 2 | |
1143 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1144 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
1145 | struct __qlcnic_esw_statistics { | |
1146 | __le16 context_id; | |
1147 | __le16 version; | |
1148 | __le16 size; | |
1149 | __le16 unused; | |
1150 | __le64 unicast_frames; | |
1151 | __le64 multicast_frames; | |
1152 | __le64 broadcast_frames; | |
1153 | __le64 dropped_frames; | |
1154 | __le64 errors; | |
1155 | __le64 local_frames; | |
1156 | __le64 numbytes; | |
1157 | __le64 rsvd[3]; | |
1158 | }; | |
1159 | ||
1160 | struct qlcnic_esw_statistics { | |
1161 | struct __qlcnic_esw_statistics rx; | |
1162 | struct __qlcnic_esw_statistics tx; | |
1163 | }; | |
1164 | ||
af19b491 AKS |
1165 | int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val); |
1166 | int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val); | |
1167 | ||
1168 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); | |
1169 | int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); | |
1170 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); | |
1171 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1172 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1173 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1174 | ||
1175 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1176 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1177 | |
1178 | #define QLCRD32(adapter, off) \ | |
1179 | (qlcnic_hw_read_wx_2M(adapter, off)) | |
1180 | #define QLCWR32(adapter, off, val) \ | |
1181 | (qlcnic_hw_write_wx_2M(adapter, off, val)) | |
1182 | ||
1183 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1184 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1185 | ||
1186 | #define qlcnic_rom_lock(a) \ | |
1187 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1188 | #define qlcnic_rom_unlock(a) \ | |
1189 | qlcnic_pcie_sem_unlock((a), 2) | |
1190 | #define qlcnic_phy_lock(a) \ | |
1191 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1192 | #define qlcnic_phy_unlock(a) \ | |
1193 | qlcnic_pcie_sem_unlock((a), 3) | |
1194 | #define qlcnic_api_lock(a) \ | |
1195 | qlcnic_pcie_sem_lock((a), 5, 0) | |
1196 | #define qlcnic_api_unlock(a) \ | |
1197 | qlcnic_pcie_sem_unlock((a), 5) | |
1198 | #define qlcnic_sw_lock(a) \ | |
1199 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1200 | #define qlcnic_sw_unlock(a) \ | |
1201 | qlcnic_pcie_sem_unlock((a), 6) | |
1202 | #define crb_win_lock(a) \ | |
1203 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1204 | #define crb_win_unlock(a) \ | |
1205 | qlcnic_pcie_sem_unlock((a), 7) | |
1206 | ||
1207 | int qlcnic_get_board_info(struct qlcnic_adapter *adapter); | |
1208 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); | |
897d3596 | 1209 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); |
af19b491 AKS |
1210 | |
1211 | /* Functions from qlcnic_init.c */ | |
af19b491 AKS |
1212 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1213 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1214 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1215 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1216 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1217 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1218 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 AKS |
1219 | |
1220 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp); | |
1221 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, | |
1222 | u8 *bytes, size_t size); | |
1223 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1224 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1225 | ||
1226 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); | |
1227 | ||
1228 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1229 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1230 | ||
8a15ad1f AKS |
1231 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1232 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1233 | ||
1234 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1235 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1236 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1237 | ||
d4066833 | 1238 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 AKS |
1239 | void qlcnic_watchdog_task(struct work_struct *work); |
1240 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid, | |
1241 | struct qlcnic_host_rds_ring *rds_ring); | |
1242 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); | |
1243 | void qlcnic_set_multi(struct net_device *netdev); | |
1244 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
1245 | int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); | |
1246 | int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); | |
1247 | int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); | |
1248 | int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd); | |
1249 | int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); | |
1250 | void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); | |
1251 | ||
1252 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1253 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
1254 | int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); | |
2e9d722d | 1255 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 AKS |
1256 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
1257 | void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, | |
1258 | struct qlcnic_host_tx_ring *tx_ring); | |
2e9d722d | 1259 | int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u8 *mac); |
cdaff185 AKS |
1260 | void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter); |
1261 | int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter); | |
2e9d722d | 1262 | void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *); |
af19b491 AKS |
1263 | |
1264 | /* Functions from qlcnic_main.c */ | |
1265 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1266 | u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter, |
1267 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd); | |
1268 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); | |
1269 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 AKS |
1270 | int qlcnic_check_loopback_buff(unsigned char *data); |
1271 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); | |
1272 | void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); | |
af19b491 | 1273 | |
2e9d722d AC |
1274 | /* Management functions */ |
1275 | int qlcnic_set_mac_address(struct qlcnic_adapter *, u8*); | |
1276 | int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); | |
346fe763 | 1277 | int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); |
2e9d722d | 1278 | int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); |
346fe763 | 1279 | int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); |
2e9d722d AC |
1280 | int qlcnic_reset_partition(struct qlcnic_adapter *, u8); |
1281 | ||
1282 | /* eSwitch management functions */ | |
1283 | int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *, u8, | |
1284 | struct qlcnic_eswitch *); | |
1285 | int qlcnic_get_eswitch_status(struct qlcnic_adapter *, u8, | |
1286 | struct qlcnic_eswitch *); | |
1287 | int qlcnic_toggle_eswitch(struct qlcnic_adapter *, u8, u8); | |
4e8acb01 RB |
1288 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1289 | struct qlcnic_esw_func_cfg *); | |
1290 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, | |
1291 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1292 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1293 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1294 | struct __qlcnic_esw_statistics *); | |
1295 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1296 | struct __qlcnic_esw_statistics *); | |
1297 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
2e9d722d AC |
1298 | extern int qlcnic_config_tso; |
1299 | ||
af19b491 AKS |
1300 | /* |
1301 | * QLOGIC Board information | |
1302 | */ | |
1303 | ||
02420be6 | 1304 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
af19b491 AKS |
1305 | struct qlcnic_brdinfo { |
1306 | unsigned short vendor; | |
1307 | unsigned short device; | |
1308 | unsigned short sub_vendor; | |
1309 | unsigned short sub_device; | |
1310 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1311 | }; | |
1312 | ||
1313 | static const struct qlcnic_brdinfo qlcnic_boards[] = { | |
02420be6 | 1314 | {0x1077, 0x8020, 0x1077, 0x203, |
1515faf2 AKS |
1315 | "8200 Series Single Port 10GbE Converged Network Adapter " |
1316 | "(TCP/IP Networking)"}, | |
02420be6 | 1317 | {0x1077, 0x8020, 0x1077, 0x207, |
1515faf2 AKS |
1318 | "8200 Series Dual Port 10GbE Converged Network Adapter " |
1319 | "(TCP/IP Networking)"}, | |
af19b491 AKS |
1320 | {0x1077, 0x8020, 0x1077, 0x20b, |
1321 | "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, | |
1322 | {0x1077, 0x8020, 0x1077, 0x20c, | |
1323 | "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, | |
1324 | {0x1077, 0x8020, 0x1077, 0x20f, | |
1325 | "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, | |
1326 | {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, | |
1327 | }; | |
1328 | ||
1329 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) | |
1330 | ||
1331 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) | |
1332 | { | |
1333 | smp_mb(); | |
1334 | if (tx_ring->producer < tx_ring->sw_consumer) | |
1335 | return tx_ring->sw_consumer - tx_ring->producer; | |
1336 | else | |
1337 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1338 | tx_ring->producer; | |
1339 | } | |
1340 | ||
1341 | extern const struct ethtool_ops qlcnic_ethtool_ops; | |
1342 | ||
2e9d722d AC |
1343 | struct qlcnic_nic_template { |
1344 | int (*get_mac_addr) (struct qlcnic_adapter *, u8*); | |
1345 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1346 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
9f26f547 | 1347 | int (*start_firmware) (struct qlcnic_adapter *); |
2e9d722d AC |
1348 | }; |
1349 | ||
65b5b420 AKS |
1350 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
1351 | if (NETIF_MSG_##lvl & adapter->msg_enable) \ | |
1352 | printk(KERN_INFO "%s: %s: " _fmt, \ | |
1353 | dev_name(&adapter->pdev->dev), \ | |
1354 | __func__, ##_args); \ | |
1355 | } while (0) | |
1356 | ||
af19b491 | 1357 | #endif /* __QLCNIC_H_ */ |