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7a47dd7a SW |
1 | /* |
2 | * RDC R6040 Fast Ethernet MAC support | |
3 | * | |
4 | * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw> | |
5 | * Copyright (C) 2007 | |
6 | * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> | |
7 | * Florian Fainelli <florian@openwrt.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the | |
21 | * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
22 | * Boston, MA 02110-1301, USA. | |
23 | */ | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/version.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/mii.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/crc32.h> | |
44 | #include <linux/spinlock.h> | |
092427be JG |
45 | #include <linux/bitops.h> |
46 | #include <linux/io.h> | |
47 | #include <linux/irq.h> | |
48 | #include <linux/uaccess.h> | |
7a47dd7a SW |
49 | |
50 | #include <asm/processor.h> | |
7a47dd7a SW |
51 | |
52 | #define DRV_NAME "r6040" | |
53 | #define DRV_VERSION "0.16" | |
54 | #define DRV_RELDATE "10Nov2007" | |
55 | ||
56 | /* PHY CHIP Address */ | |
57 | #define PHY1_ADDR 1 /* For MAC1 */ | |
58 | #define PHY2_ADDR 2 /* For MAC2 */ | |
59 | #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */ | |
60 | #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */ | |
61 | ||
62 | /* Time in jiffies before concluding the transmitter is hung. */ | |
63 | #define TX_TIMEOUT (6000 * HZ / 1000) | |
64 | #define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ | |
65 | ||
66 | /* RDC MAC I/O Size */ | |
67 | #define R6040_IO_SIZE 256 | |
68 | ||
69 | /* MAX RDC MAC */ | |
70 | #define MAX_MAC 2 | |
71 | ||
72 | /* MAC registers */ | |
73 | #define MCR0 0x00 /* Control register 0 */ | |
74 | #define MCR1 0x04 /* Control register 1 */ | |
75 | #define MAC_RST 0x0001 /* Reset the MAC */ | |
76 | #define MBCR 0x08 /* Bus control */ | |
77 | #define MT_ICR 0x0C /* TX interrupt control */ | |
78 | #define MR_ICR 0x10 /* RX interrupt control */ | |
79 | #define MTPR 0x14 /* TX poll command register */ | |
80 | #define MR_BSR 0x18 /* RX buffer size */ | |
81 | #define MR_DCR 0x1A /* RX descriptor control */ | |
82 | #define MLSR 0x1C /* Last status */ | |
83 | #define MMDIO 0x20 /* MDIO control register */ | |
84 | #define MDIO_WRITE 0x4000 /* MDIO write */ | |
85 | #define MDIO_READ 0x2000 /* MDIO read */ | |
86 | #define MMRD 0x24 /* MDIO read data register */ | |
87 | #define MMWD 0x28 /* MDIO write data register */ | |
88 | #define MTD_SA0 0x2C /* TX descriptor start address 0 */ | |
89 | #define MTD_SA1 0x30 /* TX descriptor start address 1 */ | |
90 | #define MRD_SA0 0x34 /* RX descriptor start address 0 */ | |
91 | #define MRD_SA1 0x38 /* RX descriptor start address 1 */ | |
92 | #define MISR 0x3C /* Status register */ | |
93 | #define MIER 0x40 /* INT enable register */ | |
94 | #define MSK_INT 0x0000 /* Mask off interrupts */ | |
95 | #define ME_CISR 0x44 /* Event counter INT status */ | |
96 | #define ME_CIER 0x48 /* Event counter INT enable */ | |
97 | #define MR_CNT 0x50 /* Successfully received packet counter */ | |
98 | #define ME_CNT0 0x52 /* Event counter 0 */ | |
99 | #define ME_CNT1 0x54 /* Event counter 1 */ | |
100 | #define ME_CNT2 0x56 /* Event counter 2 */ | |
101 | #define ME_CNT3 0x58 /* Event counter 3 */ | |
102 | #define MT_CNT 0x5A /* Successfully transmit packet counter */ | |
103 | #define ME_CNT4 0x5C /* Event counter 4 */ | |
104 | #define MP_CNT 0x5E /* Pause frame counter register */ | |
105 | #define MAR0 0x60 /* Hash table 0 */ | |
106 | #define MAR1 0x62 /* Hash table 1 */ | |
107 | #define MAR2 0x64 /* Hash table 2 */ | |
108 | #define MAR3 0x66 /* Hash table 3 */ | |
109 | #define MID_0L 0x68 /* Multicast address MID0 Low */ | |
110 | #define MID_0M 0x6A /* Multicast address MID0 Medium */ | |
111 | #define MID_0H 0x6C /* Multicast address MID0 High */ | |
112 | #define MID_1L 0x70 /* MID1 Low */ | |
113 | #define MID_1M 0x72 /* MID1 Medium */ | |
114 | #define MID_1H 0x74 /* MID1 High */ | |
115 | #define MID_2L 0x78 /* MID2 Low */ | |
116 | #define MID_2M 0x7A /* MID2 Medium */ | |
117 | #define MID_2H 0x7C /* MID2 High */ | |
118 | #define MID_3L 0x80 /* MID3 Low */ | |
119 | #define MID_3M 0x82 /* MID3 Medium */ | |
120 | #define MID_3H 0x84 /* MID3 High */ | |
121 | #define PHY_CC 0x88 /* PHY status change configuration register */ | |
122 | #define PHY_ST 0x8A /* PHY status register */ | |
123 | #define MAC_SM 0xAC /* MAC status machine */ | |
124 | #define MAC_ID 0xBE /* Identifier register */ | |
125 | ||
126 | #define TX_DCNT 0x80 /* TX descriptor count */ | |
127 | #define RX_DCNT 0x80 /* RX descriptor count */ | |
128 | #define MAX_BUF_SIZE 0x600 | |
6c323103 FR |
129 | #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) |
130 | #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) | |
7a47dd7a SW |
131 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ |
132 | #define MCAST_MAX 4 /* Max number multicast addresses to filter */ | |
133 | ||
134 | /* PHY settings */ | |
135 | #define ICPLUS_PHY_ID 0x0243 | |
136 | ||
137 | MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>," | |
138 | "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>," | |
139 | "Florian Fainelli <florian@openwrt.org>"); | |
140 | MODULE_LICENSE("GPL"); | |
141 | MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver"); | |
142 | ||
143 | #define RX_INT 0x0001 | |
144 | #define TX_INT 0x0010 | |
145 | #define RX_NO_DESC_INT 0x0002 | |
146 | #define INT_MASK (RX_INT | TX_INT) | |
147 | ||
148 | struct r6040_descriptor { | |
149 | u16 status, len; /* 0-3 */ | |
150 | __le32 buf; /* 4-7 */ | |
151 | __le32 ndesc; /* 8-B */ | |
152 | u32 rev1; /* C-F */ | |
153 | char *vbufp; /* 10-13 */ | |
154 | struct r6040_descriptor *vndescp; /* 14-17 */ | |
155 | struct sk_buff *skb_ptr; /* 18-1B */ | |
156 | u32 rev2; /* 1C-1F */ | |
157 | } __attribute__((aligned(32))); | |
158 | ||
159 | struct r6040_private { | |
160 | spinlock_t lock; /* driver lock */ | |
161 | struct timer_list timer; | |
162 | struct pci_dev *pdev; | |
163 | struct r6040_descriptor *rx_insert_ptr; | |
164 | struct r6040_descriptor *rx_remove_ptr; | |
165 | struct r6040_descriptor *tx_insert_ptr; | |
166 | struct r6040_descriptor *tx_remove_ptr; | |
6c323103 FR |
167 | struct r6040_descriptor *rx_ring; |
168 | struct r6040_descriptor *tx_ring; | |
169 | dma_addr_t rx_ring_dma; | |
170 | dma_addr_t tx_ring_dma; | |
7a47dd7a SW |
171 | u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode; |
172 | u16 mcr0, mcr1; | |
7a47dd7a SW |
173 | u16 switch_sig; |
174 | struct net_device *dev; | |
175 | struct mii_if_info mii_if; | |
176 | struct napi_struct napi; | |
177 | struct net_device_stats stats; | |
178 | u16 napi_rx_running; | |
179 | void __iomem *base; | |
180 | }; | |
181 | ||
182 | static char version[] __devinitdata = KERN_INFO DRV_NAME | |
183 | ": RDC R6040 NAPI net driver," | |
184 | "version "DRV_VERSION " (" DRV_RELDATE ")\n"; | |
185 | ||
092427be | 186 | static int phy_table[] = { PHY1_ADDR, PHY2_ADDR }; |
7a47dd7a SW |
187 | |
188 | /* Read a word data from PHY Chip */ | |
189 | static int phy_read(void __iomem *ioaddr, int phy_addr, int reg) | |
190 | { | |
191 | int limit = 2048; | |
192 | u16 cmd; | |
193 | ||
194 | iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); | |
195 | /* Wait for the read bit to be cleared */ | |
196 | while (limit--) { | |
197 | cmd = ioread16(ioaddr + MMDIO); | |
198 | if (cmd & MDIO_READ) | |
199 | break; | |
200 | } | |
201 | ||
202 | return ioread16(ioaddr + MMRD); | |
203 | } | |
204 | ||
205 | /* Write a word data from PHY Chip */ | |
206 | static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val) | |
207 | { | |
208 | int limit = 2048; | |
209 | u16 cmd; | |
210 | ||
211 | iowrite16(val, ioaddr + MMWD); | |
212 | /* Write the command to the MDIO bus */ | |
213 | iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO); | |
214 | /* Wait for the write bit to be cleared */ | |
215 | while (limit--) { | |
216 | cmd = ioread16(ioaddr + MMDIO); | |
217 | if (cmd & MDIO_WRITE) | |
218 | break; | |
219 | } | |
220 | } | |
221 | ||
222 | static int mdio_read(struct net_device *dev, int mii_id, int reg) | |
223 | { | |
224 | struct r6040_private *lp = netdev_priv(dev); | |
225 | void __iomem *ioaddr = lp->base; | |
226 | ||
227 | return (phy_read(ioaddr, lp->phy_addr, reg)); | |
228 | } | |
229 | ||
230 | static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) | |
231 | { | |
232 | struct r6040_private *lp = netdev_priv(dev); | |
233 | void __iomem *ioaddr = lp->base; | |
234 | ||
235 | phy_write(ioaddr, lp->phy_addr, reg, val); | |
236 | } | |
237 | ||
238 | static void | |
239 | r6040_tx_timeout(struct net_device *dev) | |
240 | { | |
241 | struct r6040_private *priv = netdev_priv(dev); | |
242 | ||
243 | disable_irq(dev->irq); | |
244 | napi_disable(&priv->napi); | |
245 | spin_lock(&priv->lock); | |
246 | dev->stats.tx_errors++; | |
247 | spin_unlock(&priv->lock); | |
248 | ||
249 | netif_stop_queue(dev); | |
250 | } | |
251 | ||
252 | /* Allocate skb buffer for rx descriptor */ | |
253 | static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev) | |
254 | { | |
255 | struct r6040_descriptor *descptr; | |
256 | void __iomem *ioaddr = lp->base; | |
257 | ||
258 | descptr = lp->rx_insert_ptr; | |
259 | while (lp->rx_free_desc < RX_DCNT) { | |
260 | descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE); | |
261 | ||
262 | if (!descptr->skb_ptr) | |
263 | break; | |
264 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, | |
5125a786 | 265 | descptr->skb_ptr->data, |
7a47dd7a SW |
266 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); |
267 | descptr->status = 0x8000; | |
268 | descptr = descptr->vndescp; | |
269 | lp->rx_free_desc++; | |
270 | /* Trigger RX DMA */ | |
271 | iowrite16(lp->mcr0 | 0x0002, ioaddr); | |
272 | } | |
273 | lp->rx_insert_ptr = descptr; | |
274 | } | |
275 | ||
276 | ||
277 | static struct net_device_stats *r6040_get_stats(struct net_device *dev) | |
278 | { | |
279 | struct r6040_private *priv = netdev_priv(dev); | |
280 | void __iomem *ioaddr = priv->base; | |
281 | unsigned long flags; | |
282 | ||
283 | spin_lock_irqsave(&priv->lock, flags); | |
284 | priv->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1); | |
285 | priv->stats.multicast += ioread8(ioaddr + ME_CNT0); | |
286 | spin_unlock_irqrestore(&priv->lock, flags); | |
287 | ||
288 | return &priv->stats; | |
289 | } | |
290 | ||
291 | /* Stop RDC MAC and Free the allocated resource */ | |
292 | static void r6040_down(struct net_device *dev) | |
293 | { | |
294 | struct r6040_private *lp = netdev_priv(dev); | |
295 | void __iomem *ioaddr = lp->base; | |
6c323103 | 296 | struct pci_dev *pdev = lp->pdev; |
7a47dd7a SW |
297 | int i; |
298 | int limit = 2048; | |
299 | u16 *adrp; | |
300 | u16 cmd; | |
301 | ||
302 | /* Stop MAC */ | |
303 | iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */ | |
304 | iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */ | |
305 | while (limit--) { | |
306 | cmd = ioread16(ioaddr + MCR1); | |
307 | if (cmd & 0x1) | |
308 | break; | |
309 | } | |
310 | ||
311 | /* Restore MAC Address to MIDx */ | |
312 | adrp = (u16 *) dev->dev_addr; | |
313 | iowrite16(adrp[0], ioaddr + MID_0L); | |
314 | iowrite16(adrp[1], ioaddr + MID_0M); | |
315 | iowrite16(adrp[2], ioaddr + MID_0H); | |
316 | free_irq(dev->irq, dev); | |
317 | /* Free RX buffer */ | |
318 | for (i = 0; i < RX_DCNT; i++) { | |
319 | if (lp->rx_insert_ptr->skb_ptr) { | |
320 | pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf, | |
321 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
322 | dev_kfree_skb(lp->rx_insert_ptr->skb_ptr); | |
323 | lp->rx_insert_ptr->skb_ptr = NULL; | |
324 | } | |
325 | lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp; | |
326 | } | |
327 | ||
328 | /* Free TX buffer */ | |
329 | for (i = 0; i < TX_DCNT; i++) { | |
330 | if (lp->tx_insert_ptr->skb_ptr) { | |
331 | pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf, | |
332 | MAX_BUF_SIZE, PCI_DMA_TODEVICE); | |
333 | dev_kfree_skb(lp->tx_insert_ptr->skb_ptr); | |
334 | lp->rx_insert_ptr->skb_ptr = NULL; | |
335 | } | |
336 | lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp; | |
337 | } | |
338 | ||
339 | /* Free Descriptor memory */ | |
6c323103 FR |
340 | pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); |
341 | pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); | |
7a47dd7a SW |
342 | } |
343 | ||
344 | static int | |
345 | r6040_close(struct net_device *dev) | |
346 | { | |
347 | struct r6040_private *lp = netdev_priv(dev); | |
348 | ||
349 | /* deleted timer */ | |
350 | del_timer_sync(&lp->timer); | |
351 | ||
352 | spin_lock_irq(&lp->lock); | |
353 | netif_stop_queue(dev); | |
354 | r6040_down(dev); | |
355 | spin_unlock_irq(&lp->lock); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | /* Status of PHY CHIP */ | |
361 | static int phy_mode_chk(struct net_device *dev) | |
362 | { | |
363 | struct r6040_private *lp = netdev_priv(dev); | |
364 | void __iomem *ioaddr = lp->base; | |
365 | int phy_dat; | |
366 | ||
367 | /* PHY Link Status Check */ | |
368 | phy_dat = phy_read(ioaddr, lp->phy_addr, 1); | |
369 | if (!(phy_dat & 0x4)) | |
370 | phy_dat = 0x8000; /* Link Failed, full duplex */ | |
371 | ||
372 | /* PHY Chip Auto-Negotiation Status */ | |
373 | phy_dat = phy_read(ioaddr, lp->phy_addr, 1); | |
374 | if (phy_dat & 0x0020) { | |
375 | /* Auto Negotiation Mode */ | |
376 | phy_dat = phy_read(ioaddr, lp->phy_addr, 5); | |
377 | phy_dat &= phy_read(ioaddr, lp->phy_addr, 4); | |
378 | if (phy_dat & 0x140) | |
379 | /* Force full duplex */ | |
380 | phy_dat = 0x8000; | |
381 | else | |
382 | phy_dat = 0; | |
383 | } else { | |
384 | /* Force Mode */ | |
385 | phy_dat = phy_read(ioaddr, lp->phy_addr, 0); | |
386 | if (phy_dat & 0x100) | |
387 | phy_dat = 0x8000; | |
388 | else | |
389 | phy_dat = 0x0000; | |
390 | } | |
391 | ||
392 | return phy_dat; | |
393 | }; | |
394 | ||
395 | static void r6040_set_carrier(struct mii_if_info *mii) | |
396 | { | |
397 | if (phy_mode_chk(mii->dev)) { | |
398 | /* autoneg is off: Link is always assumed to be up */ | |
399 | if (!netif_carrier_ok(mii->dev)) | |
400 | netif_carrier_on(mii->dev); | |
401 | } else | |
402 | phy_mode_chk(mii->dev); | |
403 | } | |
404 | ||
405 | static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
406 | { | |
407 | struct r6040_private *lp = netdev_priv(dev); | |
408 | struct mii_ioctl_data *data = (struct mii_ioctl_data *) &rq->ifr_data; | |
409 | int rc; | |
410 | ||
411 | if (!netif_running(dev)) | |
412 | return -EINVAL; | |
413 | spin_lock_irq(&lp->lock); | |
414 | rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL); | |
415 | spin_unlock_irq(&lp->lock); | |
416 | r6040_set_carrier(&lp->mii_if); | |
417 | return rc; | |
418 | } | |
419 | ||
420 | static int r6040_rx(struct net_device *dev, int limit) | |
421 | { | |
422 | struct r6040_private *priv = netdev_priv(dev); | |
423 | int count; | |
424 | void __iomem *ioaddr = priv->base; | |
425 | u16 err; | |
426 | ||
427 | for (count = 0; count < limit; ++count) { | |
428 | struct r6040_descriptor *descptr = priv->rx_remove_ptr; | |
429 | struct sk_buff *skb_ptr; | |
430 | ||
431 | /* Disable RX interrupt */ | |
432 | iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER); | |
433 | descptr = priv->rx_remove_ptr; | |
434 | ||
435 | /* Check for errors */ | |
436 | err = ioread16(ioaddr + MLSR); | |
437 | if (err & 0x0400) priv->stats.rx_errors++; | |
438 | /* RX FIFO over-run */ | |
439 | if (err & 0x8000) priv->stats.rx_fifo_errors++; | |
440 | /* RX descriptor unavailable */ | |
441 | if (err & 0x0080) priv->stats.rx_frame_errors++; | |
442 | /* Received packet with length over buffer lenght */ | |
443 | if (err & 0x0020) priv->stats.rx_over_errors++; | |
444 | /* Received packet with too long or short */ | |
445 | if (err & (0x0010|0x0008)) priv->stats.rx_length_errors++; | |
446 | /* Received packet with CRC errors */ | |
447 | if (err & 0x0004) { | |
448 | spin_lock(&priv->lock); | |
449 | priv->stats.rx_crc_errors++; | |
450 | spin_unlock(&priv->lock); | |
451 | } | |
452 | ||
453 | while (priv->rx_free_desc) { | |
454 | /* No RX packet */ | |
455 | if (descptr->status & 0x8000) | |
456 | break; | |
457 | skb_ptr = descptr->skb_ptr; | |
458 | if (!skb_ptr) { | |
459 | printk(KERN_ERR "%s: Inconsistent RX" | |
460 | "descriptor chain\n", | |
461 | dev->name); | |
462 | break; | |
463 | } | |
464 | descptr->skb_ptr = NULL; | |
465 | skb_ptr->dev = priv->dev; | |
466 | /* Do not count the CRC */ | |
467 | skb_put(skb_ptr, descptr->len - 4); | |
468 | pci_unmap_single(priv->pdev, descptr->buf, | |
469 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); | |
470 | skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev); | |
471 | /* Send to upper layer */ | |
472 | netif_receive_skb(skb_ptr); | |
473 | dev->last_rx = jiffies; | |
474 | priv->dev->stats.rx_packets++; | |
475 | priv->dev->stats.rx_bytes += descptr->len; | |
476 | /* To next descriptor */ | |
477 | descptr = descptr->vndescp; | |
478 | priv->rx_free_desc--; | |
479 | } | |
480 | priv->rx_remove_ptr = descptr; | |
481 | } | |
482 | /* Allocate new RX buffer */ | |
483 | if (priv->rx_free_desc < RX_DCNT) | |
484 | rx_buf_alloc(priv, priv->dev); | |
485 | ||
486 | return count; | |
487 | } | |
488 | ||
489 | static void r6040_tx(struct net_device *dev) | |
490 | { | |
491 | struct r6040_private *priv = netdev_priv(dev); | |
492 | struct r6040_descriptor *descptr; | |
493 | void __iomem *ioaddr = priv->base; | |
494 | struct sk_buff *skb_ptr; | |
495 | u16 err; | |
496 | ||
497 | spin_lock(&priv->lock); | |
498 | descptr = priv->tx_remove_ptr; | |
499 | while (priv->tx_free_desc < TX_DCNT) { | |
500 | /* Check for errors */ | |
501 | err = ioread16(ioaddr + MLSR); | |
502 | ||
503 | if (err & 0x0200) priv->stats.rx_fifo_errors++; | |
504 | if (err & (0x2000 | 0x4000)) priv->stats.tx_carrier_errors++; | |
505 | ||
506 | if (descptr->status & 0x8000) | |
507 | break; /* Not complte */ | |
508 | skb_ptr = descptr->skb_ptr; | |
509 | pci_unmap_single(priv->pdev, descptr->buf, | |
510 | skb_ptr->len, PCI_DMA_TODEVICE); | |
511 | /* Free buffer */ | |
512 | dev_kfree_skb_irq(skb_ptr); | |
513 | descptr->skb_ptr = NULL; | |
514 | /* To next descriptor */ | |
515 | descptr = descptr->vndescp; | |
516 | priv->tx_free_desc++; | |
517 | } | |
518 | priv->tx_remove_ptr = descptr; | |
519 | ||
520 | if (priv->tx_free_desc) | |
521 | netif_wake_queue(dev); | |
522 | spin_unlock(&priv->lock); | |
523 | } | |
524 | ||
525 | static int r6040_poll(struct napi_struct *napi, int budget) | |
526 | { | |
527 | struct r6040_private *priv = | |
528 | container_of(napi, struct r6040_private, napi); | |
529 | struct net_device *dev = priv->dev; | |
530 | void __iomem *ioaddr = priv->base; | |
531 | int work_done; | |
532 | ||
533 | work_done = r6040_rx(dev, budget); | |
534 | ||
535 | if (work_done < budget) { | |
536 | netif_rx_complete(dev, napi); | |
537 | /* Enable RX interrupt */ | |
538 | iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER); | |
539 | } | |
540 | return work_done; | |
541 | } | |
542 | ||
543 | /* The RDC interrupt handler. */ | |
544 | static irqreturn_t r6040_interrupt(int irq, void *dev_id) | |
545 | { | |
546 | struct net_device *dev = dev_id; | |
547 | struct r6040_private *lp = netdev_priv(dev); | |
548 | void __iomem *ioaddr = lp->base; | |
549 | u16 status; | |
550 | int handled = 1; | |
551 | ||
552 | /* Mask off RDC MAC interrupt */ | |
553 | iowrite16(MSK_INT, ioaddr + MIER); | |
554 | /* Read MISR status and clear */ | |
555 | status = ioread16(ioaddr + MISR); | |
556 | ||
557 | if (status == 0x0000 || status == 0xffff) | |
558 | return IRQ_NONE; | |
559 | ||
560 | /* RX interrupt request */ | |
561 | if (status & 0x01) { | |
562 | netif_rx_schedule(dev, &lp->napi); | |
563 | iowrite16(TX_INT, ioaddr + MIER); | |
564 | } | |
565 | ||
566 | /* TX interrupt request */ | |
567 | if (status & 0x10) | |
568 | r6040_tx(dev); | |
569 | ||
570 | return IRQ_RETVAL(handled); | |
571 | } | |
572 | ||
573 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
574 | static void r6040_poll_controller(struct net_device *dev) | |
575 | { | |
576 | disable_irq(dev->irq); | |
577 | r6040_interrupt(dev->irq, (void *)dev); | |
578 | enable_irq(dev->irq); | |
579 | } | |
580 | #endif | |
581 | ||
582 | ||
6c323103 FR |
583 | static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring, |
584 | dma_addr_t desc_dma, int size) | |
585 | { | |
586 | struct r6040_descriptor *desc = desc_ring; | |
587 | dma_addr_t mapping = desc_dma; | |
588 | ||
589 | while (size-- > 0) { | |
590 | mapping += sizeof(sizeof(*desc)); | |
591 | desc->ndesc = cpu_to_le32(mapping); | |
592 | desc->vndescp = desc + 1; | |
593 | desc++; | |
594 | } | |
595 | desc--; | |
596 | desc->ndesc = cpu_to_le32(desc_dma); | |
597 | desc->vndescp = desc_ring; | |
598 | } | |
599 | ||
7a47dd7a SW |
600 | /* Init RDC MAC */ |
601 | static void r6040_up(struct net_device *dev) | |
602 | { | |
603 | struct r6040_private *lp = netdev_priv(dev); | |
7a47dd7a | 604 | void __iomem *ioaddr = lp->base; |
7a47dd7a SW |
605 | |
606 | /* Initialize */ | |
607 | lp->tx_free_desc = TX_DCNT; | |
608 | lp->rx_free_desc = 0; | |
609 | /* Init descriptor */ | |
6c323103 FR |
610 | lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring; |
611 | lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring; | |
7a47dd7a | 612 | /* Init TX descriptor */ |
6c323103 | 613 | r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT); |
7a47dd7a SW |
614 | |
615 | /* Init RX descriptor */ | |
6c323103 | 616 | r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT); |
7a47dd7a SW |
617 | |
618 | /* Allocate buffer for RX descriptor */ | |
619 | rx_buf_alloc(lp, dev); | |
620 | ||
6c323103 FR |
621 | /* |
622 | * TX and RX descriptor start registers. | |
623 | * Lower 16-bits to MxD_SA0. Higher 16-bits to MxD_SA1. | |
624 | */ | |
625 | iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0); | |
626 | iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1); | |
627 | ||
628 | iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0); | |
629 | iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1); | |
7a47dd7a SW |
630 | |
631 | /* Buffer Size Register */ | |
632 | iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR); | |
633 | /* Read the PHY ID */ | |
634 | lp->switch_sig = phy_read(ioaddr, 0, 2); | |
635 | ||
636 | if (lp->switch_sig == ICPLUS_PHY_ID) { | |
637 | phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */ | |
638 | lp->phy_mode = 0x8000; | |
639 | } else { | |
640 | /* PHY Mode Check */ | |
641 | phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP); | |
642 | phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE); | |
643 | ||
644 | if (PHY_MODE == 0x3100) | |
645 | lp->phy_mode = phy_mode_chk(dev); | |
646 | else | |
647 | lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; | |
648 | } | |
649 | /* MAC Bus Control Register */ | |
650 | iowrite16(MBCR_DEFAULT, ioaddr + MBCR); | |
651 | ||
652 | /* MAC TX/RX Enable */ | |
653 | lp->mcr0 |= lp->phy_mode; | |
654 | iowrite16(lp->mcr0, ioaddr); | |
655 | ||
656 | /* set interrupt waiting time and packet numbers */ | |
657 | iowrite16(0x0F06, ioaddr + MT_ICR); | |
658 | iowrite16(0x0F06, ioaddr + MR_ICR); | |
659 | ||
660 | /* improve performance (by RDC guys) */ | |
661 | phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000)); | |
662 | phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000)); | |
663 | phy_write(ioaddr, 0, 19, 0x0000); | |
664 | phy_write(ioaddr, 0, 30, 0x01F0); | |
665 | ||
666 | /* Interrupt Mask Register */ | |
667 | iowrite16(INT_MASK, ioaddr + MIER); | |
668 | } | |
669 | ||
670 | /* | |
671 | A periodic timer routine | |
672 | Polling PHY Chip Link Status | |
673 | */ | |
674 | static void r6040_timer(unsigned long data) | |
675 | { | |
676 | struct net_device *dev = (struct net_device *)data; | |
e6a9ea10 | 677 | struct r6040_private *lp = netdev_priv(dev); |
7a47dd7a SW |
678 | void __iomem *ioaddr = lp->base; |
679 | u16 phy_mode; | |
680 | ||
681 | /* Polling PHY Chip Status */ | |
682 | if (PHY_MODE == 0x3100) | |
683 | phy_mode = phy_mode_chk(dev); | |
684 | else | |
685 | phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; | |
686 | ||
687 | if (phy_mode != lp->phy_mode) { | |
688 | lp->phy_mode = phy_mode; | |
689 | lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode; | |
690 | iowrite16(lp->mcr0, ioaddr); | |
691 | printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr)); | |
692 | } | |
693 | ||
694 | /* Timer active again */ | |
695 | lp->timer.expires = TIMER_WUT; | |
696 | add_timer(&lp->timer); | |
697 | } | |
698 | ||
699 | /* Read/set MAC address routines */ | |
700 | static void r6040_mac_address(struct net_device *dev) | |
701 | { | |
702 | struct r6040_private *lp = netdev_priv(dev); | |
703 | void __iomem *ioaddr = lp->base; | |
704 | u16 *adrp; | |
705 | ||
706 | /* MAC operation register */ | |
707 | iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */ | |
708 | iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */ | |
709 | iowrite16(0, ioaddr + MAC_SM); | |
710 | udelay(5000); | |
711 | ||
712 | /* Restore MAC Address */ | |
713 | adrp = (u16 *) dev->dev_addr; | |
714 | iowrite16(adrp[0], ioaddr + MID_0L); | |
715 | iowrite16(adrp[1], ioaddr + MID_0M); | |
716 | iowrite16(adrp[2], ioaddr + MID_0H); | |
717 | } | |
718 | ||
719 | static int | |
720 | r6040_open(struct net_device *dev) | |
721 | { | |
722 | struct r6040_private *lp = dev->priv; | |
723 | int ret; | |
724 | ||
725 | /* Request IRQ and Register interrupt handler */ | |
726 | ret = request_irq(dev->irq, &r6040_interrupt, | |
727 | IRQF_SHARED, dev->name, dev); | |
728 | if (ret) | |
729 | return ret; | |
730 | ||
731 | /* Set MAC address */ | |
732 | r6040_mac_address(dev); | |
733 | ||
734 | /* Allocate Descriptor memory */ | |
6c323103 FR |
735 | lp->rx_ring = |
736 | pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma); | |
737 | if (!lp->rx_ring) | |
7a47dd7a SW |
738 | return -ENOMEM; |
739 | ||
6c323103 FR |
740 | lp->tx_ring = |
741 | pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma); | |
742 | if (!lp->tx_ring) { | |
743 | pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring, | |
744 | lp->rx_ring_dma); | |
745 | return -ENOMEM; | |
746 | } | |
747 | ||
7a47dd7a SW |
748 | r6040_up(dev); |
749 | ||
750 | napi_enable(&lp->napi); | |
751 | netif_start_queue(dev); | |
752 | ||
753 | if (lp->switch_sig != ICPLUS_PHY_ID) { | |
754 | /* set and active a timer process */ | |
755 | init_timer(&lp->timer); | |
756 | lp->timer.expires = TIMER_WUT; | |
757 | lp->timer.data = (unsigned long)dev; | |
758 | lp->timer.function = &r6040_timer; | |
759 | add_timer(&lp->timer); | |
760 | } | |
761 | return 0; | |
762 | } | |
763 | ||
764 | static int | |
765 | r6040_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
766 | { | |
767 | struct r6040_private *lp = netdev_priv(dev); | |
768 | struct r6040_descriptor *descptr; | |
769 | void __iomem *ioaddr = lp->base; | |
770 | unsigned long flags; | |
092427be | 771 | int ret = NETDEV_TX_OK; |
7a47dd7a SW |
772 | |
773 | /* Critical Section */ | |
774 | spin_lock_irqsave(&lp->lock, flags); | |
775 | ||
776 | /* TX resource check */ | |
777 | if (!lp->tx_free_desc) { | |
778 | spin_unlock_irqrestore(&lp->lock, flags); | |
092427be | 779 | netif_stop_queue(dev); |
7a47dd7a | 780 | printk(KERN_ERR DRV_NAME ": no tx descriptor\n"); |
092427be | 781 | ret = NETDEV_TX_BUSY; |
7a47dd7a SW |
782 | return ret; |
783 | } | |
784 | ||
785 | /* Statistic Counter */ | |
786 | dev->stats.tx_packets++; | |
787 | dev->stats.tx_bytes += skb->len; | |
788 | /* Set TX descriptor & Transmit it */ | |
789 | lp->tx_free_desc--; | |
790 | descptr = lp->tx_insert_ptr; | |
791 | if (skb->len < MISR) | |
792 | descptr->len = MISR; | |
793 | else | |
794 | descptr->len = skb->len; | |
795 | ||
796 | descptr->skb_ptr = skb; | |
797 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, | |
798 | skb->data, skb->len, PCI_DMA_TODEVICE)); | |
799 | descptr->status = 0x8000; | |
800 | /* Trigger the MAC to check the TX descriptor */ | |
801 | iowrite16(0x01, ioaddr + MTPR); | |
802 | lp->tx_insert_ptr = descptr->vndescp; | |
803 | ||
804 | /* If no tx resource, stop */ | |
805 | if (!lp->tx_free_desc) | |
806 | netif_stop_queue(dev); | |
807 | ||
808 | dev->trans_start = jiffies; | |
809 | spin_unlock_irqrestore(&lp->lock, flags); | |
810 | return ret; | |
811 | } | |
812 | ||
813 | static void | |
814 | r6040_multicast_list(struct net_device *dev) | |
815 | { | |
816 | struct r6040_private *lp = netdev_priv(dev); | |
817 | void __iomem *ioaddr = lp->base; | |
818 | u16 *adrp; | |
819 | u16 reg; | |
820 | unsigned long flags; | |
821 | struct dev_mc_list *dmi = dev->mc_list; | |
822 | int i; | |
823 | ||
824 | /* MAC Address */ | |
825 | adrp = (u16 *)dev->dev_addr; | |
826 | iowrite16(adrp[0], ioaddr + MID_0L); | |
827 | iowrite16(adrp[1], ioaddr + MID_0M); | |
828 | iowrite16(adrp[2], ioaddr + MID_0H); | |
829 | ||
830 | /* Promiscous Mode */ | |
831 | spin_lock_irqsave(&lp->lock, flags); | |
832 | ||
833 | /* Clear AMCP & PROM bits */ | |
834 | reg = ioread16(ioaddr) & ~0x0120; | |
835 | if (dev->flags & IFF_PROMISC) { | |
836 | reg |= 0x0020; | |
837 | lp->mcr0 |= 0x0020; | |
838 | } | |
839 | /* Too many multicast addresses | |
840 | * accept all traffic */ | |
841 | else if ((dev->mc_count > MCAST_MAX) | |
842 | || (dev->flags & IFF_ALLMULTI)) | |
843 | reg |= 0x0020; | |
844 | ||
845 | iowrite16(reg, ioaddr); | |
846 | spin_unlock_irqrestore(&lp->lock, flags); | |
847 | ||
848 | /* Build the hash table */ | |
849 | if (dev->mc_count > MCAST_MAX) { | |
850 | u16 hash_table[4]; | |
851 | u32 crc; | |
852 | ||
853 | for (i = 0; i < 4; i++) | |
854 | hash_table[i] = 0; | |
855 | ||
856 | for (i = 0; i < dev->mc_count; i++) { | |
857 | char *addrs = dmi->dmi_addr; | |
858 | ||
859 | dmi = dmi->next; | |
860 | ||
861 | if (!(*addrs & 1)) | |
862 | continue; | |
863 | ||
864 | crc = ether_crc_le(6, addrs); | |
865 | crc >>= 26; | |
866 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
867 | } | |
868 | /* Write the index of the hash table */ | |
869 | for (i = 0; i < 4; i++) | |
870 | iowrite16(hash_table[i] << 14, ioaddr + MCR1); | |
871 | /* Fill the MAC hash tables with their values */ | |
872 | iowrite16(hash_table[0], ioaddr + MAR0); | |
873 | iowrite16(hash_table[1], ioaddr + MAR1); | |
874 | iowrite16(hash_table[2], ioaddr + MAR2); | |
875 | iowrite16(hash_table[3], ioaddr + MAR3); | |
876 | } | |
877 | /* Multicast Address 1~4 case */ | |
878 | for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) { | |
879 | adrp = (u16 *)dmi->dmi_addr; | |
880 | iowrite16(adrp[0], ioaddr + MID_1L + 8*i); | |
881 | iowrite16(adrp[1], ioaddr + MID_1M + 8*i); | |
882 | iowrite16(adrp[2], ioaddr + MID_1H + 8*i); | |
883 | dmi = dmi->next; | |
884 | } | |
885 | for (i = dev->mc_count; i < MCAST_MAX; i++) { | |
886 | iowrite16(0xffff, ioaddr + MID_0L + 8*i); | |
887 | iowrite16(0xffff, ioaddr + MID_0M + 8*i); | |
888 | iowrite16(0xffff, ioaddr + MID_0H + 8*i); | |
889 | } | |
890 | } | |
891 | ||
892 | static void netdev_get_drvinfo(struct net_device *dev, | |
893 | struct ethtool_drvinfo *info) | |
894 | { | |
895 | struct r6040_private *rp = netdev_priv(dev); | |
896 | ||
897 | strcpy(info->driver, DRV_NAME); | |
898 | strcpy(info->version, DRV_VERSION); | |
899 | strcpy(info->bus_info, pci_name(rp->pdev)); | |
900 | } | |
901 | ||
902 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
903 | { | |
904 | struct r6040_private *rp = netdev_priv(dev); | |
905 | int rc; | |
906 | ||
907 | spin_lock_irq(&rp->lock); | |
908 | rc = mii_ethtool_gset(&rp->mii_if, cmd); | |
092427be | 909 | spin_unlock_irq(&rp->lock); |
7a47dd7a SW |
910 | |
911 | return rc; | |
912 | } | |
913 | ||
914 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
915 | { | |
916 | struct r6040_private *rp = netdev_priv(dev); | |
917 | int rc; | |
918 | ||
919 | spin_lock_irq(&rp->lock); | |
920 | rc = mii_ethtool_sset(&rp->mii_if, cmd); | |
921 | spin_unlock_irq(&rp->lock); | |
922 | r6040_set_carrier(&rp->mii_if); | |
923 | ||
924 | return rc; | |
925 | } | |
926 | ||
927 | static u32 netdev_get_link(struct net_device *dev) | |
928 | { | |
929 | struct r6040_private *rp = netdev_priv(dev); | |
930 | ||
931 | return mii_link_ok(&rp->mii_if); | |
932 | } | |
933 | ||
934 | static struct ethtool_ops netdev_ethtool_ops = { | |
935 | .get_drvinfo = netdev_get_drvinfo, | |
936 | .get_settings = netdev_get_settings, | |
937 | .set_settings = netdev_set_settings, | |
938 | .get_link = netdev_get_link, | |
939 | }; | |
940 | ||
941 | ||
942 | static int __devinit r6040_init_one(struct pci_dev *pdev, | |
943 | const struct pci_device_id *ent) | |
944 | { | |
945 | struct net_device *dev; | |
946 | struct r6040_private *lp; | |
947 | void __iomem *ioaddr; | |
948 | int err, io_size = R6040_IO_SIZE; | |
949 | static int card_idx = -1; | |
950 | int bar = 0; | |
951 | long pioaddr; | |
952 | u16 *adrp; | |
953 | ||
954 | printk(KERN_INFO "%s\n", version); | |
955 | ||
956 | err = pci_enable_device(pdev); | |
957 | if (err) | |
958 | return err; | |
959 | ||
960 | /* this should always be supported */ | |
961 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
962 | printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses" | |
963 | "not supported by the card\n"); | |
964 | return -ENODEV; | |
965 | } | |
092427be JG |
966 | if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { |
967 | printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses" | |
968 | "not supported by the card\n"); | |
969 | return -ENODEV; | |
970 | } | |
7a47dd7a SW |
971 | |
972 | /* IO Size check */ | |
973 | if (pci_resource_len(pdev, 0) < io_size) { | |
974 | printk(KERN_ERR "Insufficient PCI resources, aborting\n"); | |
975 | return -EIO; | |
976 | } | |
977 | ||
978 | pioaddr = pci_resource_start(pdev, 0); /* IO map base address */ | |
979 | pci_set_master(pdev); | |
980 | ||
981 | dev = alloc_etherdev(sizeof(struct r6040_private)); | |
982 | if (!dev) { | |
983 | printk(KERN_ERR "Failed to allocate etherdev\n"); | |
984 | return -ENOMEM; | |
985 | } | |
986 | SET_NETDEV_DEV(dev, &pdev->dev); | |
987 | lp = netdev_priv(dev); | |
988 | lp->pdev = pdev; | |
989 | ||
990 | if (pci_request_regions(pdev, DRV_NAME)) { | |
991 | printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n"); | |
992 | err = -ENODEV; | |
993 | goto err_out_disable; | |
994 | } | |
995 | ||
996 | ioaddr = pci_iomap(pdev, bar, io_size); | |
997 | if (!ioaddr) { | |
998 | printk(KERN_ERR "ioremap failed for device %s\n", | |
999 | pci_name(pdev)); | |
1000 | return -EIO; | |
1001 | } | |
1002 | ||
1003 | /* Init system & device */ | |
7a47dd7a SW |
1004 | lp->base = ioaddr; |
1005 | dev->irq = pdev->irq; | |
1006 | ||
1007 | spin_lock_init(&lp->lock); | |
1008 | pci_set_drvdata(pdev, dev); | |
1009 | ||
1010 | /* Set MAC address */ | |
1011 | card_idx++; | |
1012 | ||
1013 | adrp = (u16 *)dev->dev_addr; | |
1014 | adrp[0] = ioread16(ioaddr + MID_0L); | |
1015 | adrp[1] = ioread16(ioaddr + MID_0M); | |
1016 | adrp[2] = ioread16(ioaddr + MID_0H); | |
1017 | ||
1018 | /* Link new device into r6040_root_dev */ | |
1019 | lp->pdev = pdev; | |
1020 | ||
1021 | /* Init RDC private data */ | |
1022 | lp->mcr0 = 0x1002; | |
1023 | lp->phy_addr = phy_table[card_idx]; | |
1024 | lp->switch_sig = 0; | |
1025 | ||
1026 | /* The RDC-specific entries in the device structure. */ | |
1027 | dev->open = &r6040_open; | |
1028 | dev->hard_start_xmit = &r6040_start_xmit; | |
1029 | dev->stop = &r6040_close; | |
1030 | dev->get_stats = r6040_get_stats; | |
1031 | dev->set_multicast_list = &r6040_multicast_list; | |
1032 | dev->do_ioctl = &r6040_ioctl; | |
1033 | dev->ethtool_ops = &netdev_ethtool_ops; | |
1034 | dev->tx_timeout = &r6040_tx_timeout; | |
1035 | dev->watchdog_timeo = TX_TIMEOUT; | |
1036 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1037 | dev->poll_controller = r6040_poll_controller; | |
1038 | #endif | |
1039 | netif_napi_add(dev, &lp->napi, r6040_poll, 64); | |
1040 | lp->mii_if.dev = dev; | |
1041 | lp->mii_if.mdio_read = mdio_read; | |
1042 | lp->mii_if.mdio_write = mdio_write; | |
1043 | lp->mii_if.phy_id = lp->phy_addr; | |
1044 | lp->mii_if.phy_id_mask = 0x1f; | |
1045 | lp->mii_if.reg_num_mask = 0x1f; | |
1046 | ||
1047 | /* Register net device. After this dev->name assign */ | |
1048 | err = register_netdev(dev); | |
1049 | if (err) { | |
1050 | printk(KERN_ERR DRV_NAME ": Failed to register net device\n"); | |
1051 | goto err_out_res; | |
1052 | } | |
1053 | return 0; | |
1054 | ||
1055 | err_out_res: | |
1056 | pci_release_regions(pdev); | |
1057 | err_out_disable: | |
1058 | pci_disable_device(pdev); | |
1059 | pci_set_drvdata(pdev, NULL); | |
1060 | free_netdev(dev); | |
1061 | ||
1062 | return err; | |
1063 | } | |
1064 | ||
1065 | static void __devexit r6040_remove_one(struct pci_dev *pdev) | |
1066 | { | |
1067 | struct net_device *dev = pci_get_drvdata(pdev); | |
1068 | ||
1069 | unregister_netdev(dev); | |
1070 | pci_release_regions(pdev); | |
1071 | free_netdev(dev); | |
1072 | pci_disable_device(pdev); | |
1073 | pci_set_drvdata(pdev, NULL); | |
1074 | } | |
1075 | ||
1076 | ||
1077 | static struct pci_device_id r6040_pci_tbl[] = { | |
1078 | { PCI_DEVICE(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6040) }, | |
1079 | {0 } | |
1080 | }; | |
1081 | MODULE_DEVICE_TABLE(pci, r6040_pci_tbl); | |
1082 | ||
1083 | static struct pci_driver r6040_driver = { | |
1084 | .name = "r6040", | |
1085 | .id_table = r6040_pci_tbl, | |
1086 | .probe = r6040_init_one, | |
1087 | .remove = __devexit_p(r6040_remove_one), | |
1088 | }; | |
1089 | ||
1090 | ||
1091 | static int __init r6040_init(void) | |
1092 | { | |
1093 | return pci_register_driver(&r6040_driver); | |
1094 | } | |
1095 | ||
1096 | ||
1097 | static void __exit r6040_cleanup(void) | |
1098 | { | |
1099 | pci_unregister_driver(&r6040_driver); | |
1100 | } | |
1101 | ||
1102 | module_init(r6040_init); | |
1103 | module_exit(r6040_cleanup); |