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[PATCH] skge: get rid of Yukon2 defines
[deliverable/linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
2cd8e5d3 40#include <linux/mii.h>
baef58b1
SH		 41#include <asm/irq.h>
42
43#include "skge.h"
44
45#define DRV_NAME "skge"
d7eaee08 46#define DRV_VERSION "1.2"
baef58b1
SH		 47#define PFX DRV_NAME " "
48
49#define DEFAULT_TX_RING_SIZE 128
50#define DEFAULT_RX_RING_SIZE 512
51#define MAX_TX_RING_SIZE 1024
52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
baef58b1
SH		 60
61MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
62MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
63MODULE_LICENSE("GPL");
64MODULE_VERSION(DRV_VERSION);
65
66static const u32 default_msg
67 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
68 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
69
70static int debug = -1; /* defaults above */
71module_param(debug, int, 0);
72MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73
74static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 84 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 85 { 0 }
86};
87MODULE_DEVICE_TABLE(pci, skge_id_table);
88
89static int skge_up(struct net_device *dev);
90static int skge_down(struct net_device *dev);
ee294dcd 91static void skge_phy_reset(struct skge_port *skge);
baef58b1 92static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 93static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
94static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 95static void genesis_get_stats(struct skge_port *skge, u64 *data);
96static void yukon_get_stats(struct skge_port *skge, u64 *data);
97static void yukon_init(struct skge_hw *hw, int port);
baef58b1 98static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 99static void genesis_link_up(struct skge_port *skge);
baef58b1 100
7e676d91 101/* Avoid conditionals by using array */
baef58b1
SH		 102static const int txqaddr[] = { Q_XA1, Q_XA2 };
103static const int rxqaddr[] = { Q_R1, Q_R2 };
104static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 106static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 107
baef58b1
SH		 108static int skge_get_regs_len(struct net_device *dev)
109{
c3f8be96 110 return 0x4000;
baef58b1
SH		 111}
112
113/*
c3f8be96
SH		 114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
baef58b1
SH		 117 */
118static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120{
121 const struct skge_port *skge = netdev_priv(dev);
baef58b1 122 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 123
124 regs->version = 1;
c3f8be96
SH		 125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 127
c3f8be96
SH		 128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 130}
131
8f3f8193 132/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 133static int wol_supported(const struct skge_hw *hw)
134{
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 137}
138
139static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140{
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145}
146
147static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148{
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
95566065 152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170}
171
8f3f8193
SH		 172/* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 174 */
175static u32 skge_supported_modes(const struct skge_hw *hw)
176{
177 u32 supported;
178
5e1705dd 179 if (hw->copper) {
31b619c5
SH		 180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201}
baef58b1
SH		 202
203static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205{
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 210 ecmd->supported = skge_supported_modes(hw);
baef58b1 211
5e1705dd 212 if (hw->copper) {
baef58b1
SH		 213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
31b619c5 215 } else
baef58b1 216 ecmd->port = PORT_FIBRE;
baef58b1
SH		 217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223}
224
baef58b1
SH		 225static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226{
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
31b619c5 229 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
baef58b1 235 } else {
31b619c5
SH		 236 u32 setting;
237
2c668514 238 switch (ecmd->speed) {
baef58b1 239 case SPEED_1000:
31b619c5
SH		 240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
baef58b1
SH		 246 break;
247 case SPEED_100:
31b619c5
SH		 248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
baef58b1 256 case SPEED_10:
31b619c5
SH		 257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
baef58b1
SH		 262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
31b619c5
SH		 267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
baef58b1
SH		 273 }
274
275 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 276 skge->advertising = ecmd->advertising;
277
ee294dcd
SH		 278 if (netif_running(dev))
279 skge_phy_reset(skge);
280
baef58b1
SH		 281 return (0);
282}
283
284static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286{
287 struct skge_port *skge = netdev_priv(dev);
288
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
293}
294
295static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
297 u16 xmac_offset;
298 u16 gma_offset;
299} skge_stats[] = {
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
302
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
311
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
318
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
324};
325
326static int skge_get_stats_count(struct net_device *dev)
327{
328 return ARRAY_SIZE(skge_stats);
329}
330
331static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
333{
334 struct skge_port *skge = netdev_priv(dev);
335
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
338 else
339 yukon_get_stats(skge, data);
340}
341
342/* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
345 */
346static struct net_device_stats *skge_get_stats(struct net_device *dev)
347{
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
350
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
353 else
354 yukon_get_stats(skge, data);
355
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
363
364 return &skge->net_stats;
365}
366
367static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
368{
369 int i;
370
95566065 371 switch (stringset) {
baef58b1
SH		 372 case ETH_SS_STATS:
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
376 break;
377 }
378}
379
380static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
382{
383 struct skge_port *skge = netdev_priv(dev);
384
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
389
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
394}
395
396static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
398{
399 struct skge_port *skge = netdev_priv(dev);
400
401 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
402 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
403 return -EINVAL;
404
405 skge->rx_ring.count = p->rx_pending;
406 skge->tx_ring.count = p->tx_pending;
407
408 if (netif_running(dev)) {
409 skge_down(dev);
410 skge_up(dev);
411 }
412
413 return 0;
414}
415
416static u32 skge_get_msglevel(struct net_device *netdev)
417{
418 struct skge_port *skge = netdev_priv(netdev);
419 return skge->msg_enable;
420}
421
422static void skge_set_msglevel(struct net_device *netdev, u32 value)
423{
424 struct skge_port *skge = netdev_priv(netdev);
425 skge->msg_enable = value;
426}
427
428static int skge_nway_reset(struct net_device *dev)
429{
430 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 431
432 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
433 return -EINVAL;
434
ee294dcd 435 skge_phy_reset(skge);
baef58b1
SH		 436 return 0;
437}
438
439static int skge_set_sg(struct net_device *dev, u32 data)
440{
441 struct skge_port *skge = netdev_priv(dev);
442 struct skge_hw *hw = skge->hw;
443
444 if (hw->chip_id == CHIP_ID_GENESIS && data)
445 return -EOPNOTSUPP;
446 return ethtool_op_set_sg(dev, data);
447}
448
449static int skge_set_tx_csum(struct net_device *dev, u32 data)
450{
451 struct skge_port *skge = netdev_priv(dev);
452 struct skge_hw *hw = skge->hw;
453
454 if (hw->chip_id == CHIP_ID_GENESIS && data)
455 return -EOPNOTSUPP;
456
457 return ethtool_op_set_tx_csum(dev, data);
458}
459
460static u32 skge_get_rx_csum(struct net_device *dev)
461{
462 struct skge_port *skge = netdev_priv(dev);
463
464 return skge->rx_csum;
465}
466
467/* Only Yukon supports checksum offload. */
468static int skge_set_rx_csum(struct net_device *dev, u32 data)
469{
470 struct skge_port *skge = netdev_priv(dev);
471
472 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
473 return -EOPNOTSUPP;
474
475 skge->rx_csum = data;
476 return 0;
477}
478
baef58b1
SH		 479static void skge_get_pauseparam(struct net_device *dev,
480 struct ethtool_pauseparam *ecmd)
481{
482 struct skge_port *skge = netdev_priv(dev);
483
484 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
485 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
486 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
487 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
488
489 ecmd->autoneg = skge->autoneg;
490}
491
492static int skge_set_pauseparam(struct net_device *dev,
493 struct ethtool_pauseparam *ecmd)
494{
495 struct skge_port *skge = netdev_priv(dev);
496
497 skge->autoneg = ecmd->autoneg;
498 if (ecmd->rx_pause && ecmd->tx_pause)
499 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 500 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 501 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 502 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 503 skge->flow_control = FLOW_MODE_LOC_SEND;
504 else
505 skge->flow_control = FLOW_MODE_NONE;
506
e8df8554
SH		 507 if (netif_running(dev))
508 skge_phy_reset(skge);
baef58b1
SH		 509 return 0;
510}
511
512/* Chip internal frequency for clock calculations */
513static inline u32 hwkhz(const struct skge_hw *hw)
514{
515 if (hw->chip_id == CHIP_ID_GENESIS)
516 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 517 else
518 return 78215; /* or: 78.125 MHz */
519}
520
8f3f8193 521/* Chip HZ to microseconds */
baef58b1
SH		 522static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
523{
524 return (ticks * 1000) / hwkhz(hw);
525}
526
8f3f8193 527/* Microseconds to chip HZ */
baef58b1
SH		 528static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
529{
530 return hwkhz(hw) * usec / 1000;
531}
532
533static int skge_get_coalesce(struct net_device *dev,
534 struct ethtool_coalesce *ecmd)
535{
536 struct skge_port *skge = netdev_priv(dev);
537 struct skge_hw *hw = skge->hw;
538 int port = skge->port;
539
540 ecmd->rx_coalesce_usecs = 0;
541 ecmd->tx_coalesce_usecs = 0;
542
543 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
544 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
545 u32 msk = skge_read32(hw, B2_IRQM_MSK);
546
547 if (msk & rxirqmask[port])
548 ecmd->rx_coalesce_usecs = delay;
549 if (msk & txirqmask[port])
550 ecmd->tx_coalesce_usecs = delay;
551 }
552
553 return 0;
554}
555
556/* Note: interrupt timer is per board, but can turn on/off per port */
557static int skge_set_coalesce(struct net_device *dev,
558 struct ethtool_coalesce *ecmd)
559{
560 struct skge_port *skge = netdev_priv(dev);
561 struct skge_hw *hw = skge->hw;
562 int port = skge->port;
563 u32 msk = skge_read32(hw, B2_IRQM_MSK);
564 u32 delay = 25;
565
566 if (ecmd->rx_coalesce_usecs == 0)
567 msk &= ~rxirqmask[port];
568 else if (ecmd->rx_coalesce_usecs < 25 ||
569 ecmd->rx_coalesce_usecs > 33333)
570 return -EINVAL;
571 else {
572 msk |= rxirqmask[port];
573 delay = ecmd->rx_coalesce_usecs;
574 }
575
576 if (ecmd->tx_coalesce_usecs == 0)
577 msk &= ~txirqmask[port];
578 else if (ecmd->tx_coalesce_usecs < 25 ||
579 ecmd->tx_coalesce_usecs > 33333)
580 return -EINVAL;
581 else {
582 msk |= txirqmask[port];
583 delay = min(delay, ecmd->rx_coalesce_usecs);
584 }
585
586 skge_write32(hw, B2_IRQM_MSK, msk);
587 if (msk == 0)
588 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
589 else {
590 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
591 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
592 }
593 return 0;
594}
595
6abebb53
SH		 596enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
597static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 598{
6abebb53
SH		 599 struct skge_hw *hw = skge->hw;
600 int port = skge->port;
601
602 spin_lock_bh(&hw->phy_lock);
baef58b1 603 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 604 switch (mode) {
605 case LED_MODE_OFF:
606 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
607 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
608 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
609 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
610 break;
baef58b1 611
6abebb53
SH		 612 case LED_MODE_ON:
613 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
614 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 615
6abebb53
SH		 616 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
617 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 618
6abebb53 619 break;
baef58b1 620
6abebb53
SH		 621 case LED_MODE_TST:
622 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
623 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
624 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 625
6abebb53
SH		 626 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
627 break;
628 }
baef58b1 629 } else {
6abebb53
SH		 630 switch (mode) {
631 case LED_MODE_OFF:
632 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
633 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
634 PHY_M_LED_MO_DUP(MO_LED_OFF) |
635 PHY_M_LED_MO_10(MO_LED_OFF) |
636 PHY_M_LED_MO_100(MO_LED_OFF) |
637 PHY_M_LED_MO_1000(MO_LED_OFF) |
638 PHY_M_LED_MO_RX(MO_LED_OFF));
639 break;
640 case LED_MODE_ON:
641 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
642 PHY_M_LED_PULS_DUR(PULS_170MS) |
643 PHY_M_LED_BLINK_RT(BLINK_84MS) |
644 PHY_M_LEDC_TX_CTRL |
645 PHY_M_LEDC_DP_CTRL);
46a60f2d 646
6abebb53
SH		 647 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
648 PHY_M_LED_MO_RX(MO_LED_OFF) |
649 (skge->speed == SPEED_100 ?
650 PHY_M_LED_MO_100(MO_LED_ON) : 0));
651 break;
652 case LED_MODE_TST:
653 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
654 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
655 PHY_M_LED_MO_DUP(MO_LED_ON) |
656 PHY_M_LED_MO_10(MO_LED_ON) |
657 PHY_M_LED_MO_100(MO_LED_ON) |
658 PHY_M_LED_MO_1000(MO_LED_ON) |
659 PHY_M_LED_MO_RX(MO_LED_ON));
660 }
baef58b1 661 }
4ff6ac05 662 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 663}
664
665/* blink LED's for finding board */
666static int skge_phys_id(struct net_device *dev, u32 data)
667{
668 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 669 unsigned long ms;
670 enum led_mode mode = LED_MODE_TST;
baef58b1 671
95566065 672 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 673 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
674 else
675 ms = data * 1000;
baef58b1 676
6abebb53
SH		 677 while (ms > 0) {
678 skge_led(skge, mode);
679 mode ^= LED_MODE_TST;
baef58b1 680
6abebb53
SH		 681 if (msleep_interruptible(BLINK_MS))
682 break;
683 ms -= BLINK_MS;
684 }
baef58b1 685
6abebb53
SH		 686 /* back to regular LED state */
687 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 688
689 return 0;
690}
691
692static struct ethtool_ops skge_ethtool_ops = {
693 .get_settings = skge_get_settings,
694 .set_settings = skge_set_settings,
695 .get_drvinfo = skge_get_drvinfo,
696 .get_regs_len = skge_get_regs_len,
697 .get_regs = skge_get_regs,
698 .get_wol = skge_get_wol,
699 .set_wol = skge_set_wol,
700 .get_msglevel = skge_get_msglevel,
701 .set_msglevel = skge_set_msglevel,
702 .nway_reset = skge_nway_reset,
703 .get_link = ethtool_op_get_link,
704 .get_ringparam = skge_get_ring_param,
705 .set_ringparam = skge_set_ring_param,
706 .get_pauseparam = skge_get_pauseparam,
707 .set_pauseparam = skge_set_pauseparam,
708 .get_coalesce = skge_get_coalesce,
709 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 710 .get_sg = ethtool_op_get_sg,
711 .set_sg = skge_set_sg,
712 .get_tx_csum = ethtool_op_get_tx_csum,
713 .set_tx_csum = skge_set_tx_csum,
714 .get_rx_csum = skge_get_rx_csum,
715 .set_rx_csum = skge_set_rx_csum,
716 .get_strings = skge_get_strings,
717 .phys_id = skge_phys_id,
718 .get_stats_count = skge_get_stats_count,
719 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 720 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 721};
722
723/*
724 * Allocate ring elements and chain them together
725 * One-to-one association of board descriptors with ring elements
726 */
727static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
728{
729 struct skge_tx_desc *d;
730 struct skge_element *e;
731 int i;
732
733 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
734 if (!ring->start)
735 return -ENOMEM;
736
737 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
738 e->desc = d;
19a33d4e 739 e->skb = NULL;
baef58b1
SH		 740 if (i == ring->count - 1) {
741 e->next = ring->start;
742 d->next_offset = base;
743 } else {
744 e->next = e + 1;
745 d->next_offset = base + (i+1) * sizeof(*d);
746 }
747 }
748 ring->to_use = ring->to_clean = ring->start;
749
750 return 0;
751}
752
19a33d4e
SH		 753/* Allocate and setup a new buffer for receiving */
754static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
755 struct sk_buff *skb, unsigned int bufsize)
756{
757 struct skge_rx_desc *rd = e->desc;
758 u64 map;
baef58b1
SH		 759
760 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
761 PCI_DMA_FROMDEVICE);
762
763 rd->dma_lo = map;
764 rd->dma_hi = map >> 32;
765 e->skb = skb;
766 rd->csum1_start = ETH_HLEN;
767 rd->csum2_start = ETH_HLEN;
768 rd->csum1 = 0;
769 rd->csum2 = 0;
770
771 wmb();
772
773 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
774 pci_unmap_addr_set(e, mapaddr, map);
775 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 776}
777
19a33d4e
SH		 778/* Resume receiving using existing skb,
779 * Note: DMA address is not changed by chip.
780 * MTU not changed while receiver active.
781 */
782static void skge_rx_reuse(struct skge_element *e, unsigned int size)
783{
784 struct skge_rx_desc *rd = e->desc;
785
786 rd->csum2 = 0;
787 rd->csum2_start = ETH_HLEN;
788
789 wmb();
790
791 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
792}
793
794
795/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 796static void skge_rx_clean(struct skge_port *skge)
797{
798 struct skge_hw *hw = skge->hw;
799 struct skge_ring *ring = &skge->rx_ring;
800 struct skge_element *e;
801
19a33d4e
SH		 802 e = ring->start;
803 do {
baef58b1
SH		 804 struct skge_rx_desc *rd = e->desc;
805 rd->control = 0;
19a33d4e
SH		 806 if (e->skb) {
807 pci_unmap_single(hw->pdev,
808 pci_unmap_addr(e, mapaddr),
809 pci_unmap_len(e, maplen),
810 PCI_DMA_FROMDEVICE);
811 dev_kfree_skb(e->skb);
812 e->skb = NULL;
813 }
814 } while ((e = e->next) != ring->start);
baef58b1
SH		 815}
816
19a33d4e 817
baef58b1 818/* Allocate buffers for receive ring
19a33d4e 819 * For receive: to_clean is next received frame.
baef58b1
SH		 820 */
821static int skge_rx_fill(struct skge_port *skge)
822{
823 struct skge_ring *ring = &skge->rx_ring;
824 struct skge_element *e;
baef58b1 825
19a33d4e
SH		 826 e = ring->start;
827 do {
383181ac 828 struct sk_buff *skb;
baef58b1 829
383181ac 830 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
19a33d4e
SH		 831 if (!skb)
832 return -ENOMEM;
833
383181ac
SH		 834 skb_reserve(skb, NET_IP_ALIGN);
835 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 836 } while ( (e = e->next) != ring->start);
baef58b1 837
19a33d4e
SH		 838 ring->to_clean = ring->start;
839 return 0;
baef58b1
SH		 840}
841
842static void skge_link_up(struct skge_port *skge)
843{
46a60f2d 844 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 845 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
846
baef58b1
SH		 847 netif_carrier_on(skge->netdev);
848 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
849 netif_wake_queue(skge->netdev);
850
851 if (netif_msg_link(skge))
852 printk(KERN_INFO PFX
853 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
854 skge->netdev->name, skge->speed,
855 skge->duplex == DUPLEX_FULL ? "full" : "half",
856 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
857 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
858 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
859 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
860 "unknown");
861}
862
863static void skge_link_down(struct skge_port *skge)
864{
54cfb5aa 865 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 866 netif_carrier_off(skge->netdev);
867 netif_stop_queue(skge->netdev);
868
869 if (netif_msg_link(skge))
870 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
871}
872
2cd8e5d3 873static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 874{
875 int i;
baef58b1 876
6b0c1480 877 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
2cd8e5d3 878 xm_read16(hw, port, XM_PHY_DATA);
baef58b1 879
89bf5f23
SH		 880 /* Need to wait for external PHY */
881 for (i = 0; i < PHY_RETRIES; i++) {
882 udelay(1);
2cd8e5d3 883 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 884 goto ready;
baef58b1
SH		 885 }
886
2cd8e5d3 887 return -ETIMEDOUT;
89bf5f23 888 ready:
2cd8e5d3 889 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 890
2cd8e5d3
SH		 891 return 0;
892}
893
894static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
895{
896 u16 v = 0;
897 if (__xm_phy_read(hw, port, reg, &v))
898 printk(KERN_WARNING PFX "%s: phy read timed out\n",
899 hw->dev[port]->name);
baef58b1
SH		 900 return v;
901}
902
2cd8e5d3 903static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 904{
905 int i;
906
6b0c1480 907 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 908 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 909 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 910 goto ready;
89bf5f23 911 udelay(1);
baef58b1 912 }
2cd8e5d3 913 return -EIO;
baef58b1
SH		 914
915 ready:
6b0c1480 916 xm_write16(hw, port, XM_PHY_DATA, val);
2cd8e5d3 917 return 0;
baef58b1
SH		 918}
919
920static void genesis_init(struct skge_hw *hw)
921{
922 /* set blink source counter */
923 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
924 skge_write8(hw, B2_BSC_CTRL, BSC_START);
925
926 /* configure mac arbiter */
927 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
928
929 /* configure mac arbiter timeout values */
930 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
931 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
932 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
933 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
934
935 skge_write8(hw, B3_MA_RCINI_RX1, 0);
936 skge_write8(hw, B3_MA_RCINI_RX2, 0);
937 skge_write8(hw, B3_MA_RCINI_TX1, 0);
938 skge_write8(hw, B3_MA_RCINI_TX2, 0);
939
940 /* configure packet arbiter timeout */
941 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
942 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
943 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
944 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
945 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
946}
947
948static void genesis_reset(struct skge_hw *hw, int port)
949{
45bada65 950 const u8 zero[8] = { 0 };
baef58b1 951
46a60f2d
SH		 952 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
953
baef58b1 954 /* reset the statistics module */
6b0c1480
SH		 955 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
956 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
957 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
958 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
959 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 960
89bf5f23
SH		 961 /* disable Broadcom PHY IRQ */
962 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 963
45bada65 964 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 965}
966
967
45bada65
SH		 968/* Convert mode to MII values */
969static const u16 phy_pause_map[] = {
970 [FLOW_MODE_NONE] = 0,
971 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
972 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
973 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
974};
975
976
977/* Check status of Broadcom phy link */
978static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 979{
45bada65
SH		 980 struct net_device *dev = hw->dev[port];
981 struct skge_port *skge = netdev_priv(dev);
982 u16 status;
983
984 /* read twice because of latch */
985 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
986 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
987
45bada65
SH		 988 if ((status & PHY_ST_LSYNC) == 0) {
989 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
990 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
991 xm_write16(hw, port, XM_MMU_CMD, cmd);
992 /* dummy read to ensure writing */
993 (void) xm_read16(hw, port, XM_MMU_CMD);
994
995 if (netif_carrier_ok(dev))
996 skge_link_down(skge);
997 } else {
998 if (skge->autoneg == AUTONEG_ENABLE &&
999 (status & PHY_ST_AN_OVER)) {
1000 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1001 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1002
1003 if (lpa & PHY_B_AN_RF) {
1004 printk(KERN_NOTICE PFX "%s: remote fault\n",
1005 dev->name);
1006 return;
1007 }
1008
1009 /* Check Duplex mismatch */
2c668514 1010 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1011 case PHY_B_RES_1000FD:
1012 skge->duplex = DUPLEX_FULL;
1013 break;
1014 case PHY_B_RES_1000HD:
1015 skge->duplex = DUPLEX_HALF;
1016 break;
1017 default:
1018 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1019 dev->name);
1020 return;
1021 }
1022
1023
1024 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1025 switch (aux & PHY_B_AS_PAUSE_MSK) {
1026 case PHY_B_AS_PAUSE_MSK:
1027 skge->flow_control = FLOW_MODE_SYMMETRIC;
1028 break;
1029 case PHY_B_AS_PRR:
1030 skge->flow_control = FLOW_MODE_REM_SEND;
1031 break;
1032 case PHY_B_AS_PRT:
1033 skge->flow_control = FLOW_MODE_LOC_SEND;
1034 break;
1035 default:
1036 skge->flow_control = FLOW_MODE_NONE;
1037 }
1038
1039 skge->speed = SPEED_1000;
1040 }
1041
1042 if (!netif_carrier_ok(dev))
1043 genesis_link_up(skge);
1044 }
1045}
1046
1047/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1048 * Phy on for 100 or 10Mbit operation
1049 */
1050static void bcom_phy_init(struct skge_port *skge, int jumbo)
1051{
1052 struct skge_hw *hw = skge->hw;
1053 int port = skge->port;
baef58b1 1054 int i;
45bada65 1055 u16 id1, r, ext, ctl;
baef58b1
SH		 1056
1057 /* magic workaround patterns for Broadcom */
1058 static const struct {
1059 u16 reg;
1060 u16 val;
1061 } A1hack[] = {
1062 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1063 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1064 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1065 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1066 }, C0hack[] = {
1067 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1068 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1069 };
1070
45bada65
SH		 1071 /* read Id from external PHY (all have the same address) */
1072 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1073
1074 /* Optimize MDIO transfer by suppressing preamble. */
1075 r = xm_read16(hw, port, XM_MMU_CMD);
1076 r |= XM_MMU_NO_PRE;
1077 xm_write16(hw, port, XM_MMU_CMD,r);
1078
2c668514 1079 switch (id1) {
45bada65
SH		 1080 case PHY_BCOM_ID1_C0:
1081 /*
1082 * Workaround BCOM Errata for the C0 type.
1083 * Write magic patterns to reserved registers.
1084 */
1085 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1086 xm_phy_write(hw, port,
1087 C0hack[i].reg, C0hack[i].val);
1088
1089 break;
1090 case PHY_BCOM_ID1_A1:
1091 /*
1092 * Workaround BCOM Errata for the A1 type.
1093 * Write magic patterns to reserved registers.
1094 */
1095 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1096 xm_phy_write(hw, port,
1097 A1hack[i].reg, A1hack[i].val);
1098 break;
1099 }
1100
1101 /*
1102 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1103 * Disable Power Management after reset.
1104 */
1105 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1106 r |= PHY_B_AC_DIS_PM;
1107 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1108
1109 /* Dummy read */
1110 xm_read16(hw, port, XM_ISRC);
1111
1112 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1113 ctl = PHY_CT_SP1000; /* always 1000mbit */
1114
1115 if (skge->autoneg == AUTONEG_ENABLE) {
1116 /*
1117 * Workaround BCOM Errata #1 for the C5 type.
1118 * 1000Base-T Link Acquisition Failure in Slave Mode
1119 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1120 */
1121 u16 adv = PHY_B_1000C_RD;
1122 if (skge->advertising & ADVERTISED_1000baseT_Half)
1123 adv |= PHY_B_1000C_AHD;
1124 if (skge->advertising & ADVERTISED_1000baseT_Full)
1125 adv |= PHY_B_1000C_AFD;
1126 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1127
1128 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1129 } else {
1130 if (skge->duplex == DUPLEX_FULL)
1131 ctl |= PHY_CT_DUP_MD;
1132 /* Force to slave */
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1134 }
1135
1136 /* Set autonegotiation pause parameters */
1137 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1138 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1139
1140 /* Handle Jumbo frames */
1141 if (jumbo) {
1142 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1143 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1144
1145 ext |= PHY_B_PEC_HIGH_LA;
1146
1147 }
1148
1149 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1150 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1151
8f3f8193 1152 /* Use link status change interrupt */
45bada65
SH		 1153 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1154
1155 bcom_check_link(hw, port);
1156}
1157
1158static void genesis_mac_init(struct skge_hw *hw, int port)
1159{
1160 struct net_device *dev = hw->dev[port];
1161 struct skge_port *skge = netdev_priv(dev);
1162 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1163 int i;
1164 u32 r;
1165 const u8 zero[6] = { 0 };
1166
1167 /* Clear MIB counters */
1168 xm_write16(hw, port, XM_STAT_CMD,
1169 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1170 /* Clear two times according to Errata #3 */
1171 xm_write16(hw, port, XM_STAT_CMD,
1172 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1 1173
baef58b1 1174 /* Unreset the XMAC. */
6b0c1480 1175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1176
1177 /*
1178 * Perform additional initialization for external PHYs,
1179 * namely for the 1000baseTX cards that use the XMAC's
1180 * GMII mode.
1181 */
45bada65 1182 /* Take external Phy out of reset */
89bf5f23
SH		 1183 r = skge_read32(hw, B2_GP_IO);
1184 if (port == 0)
1185 r |= GP_DIR_0|GP_IO_0;
1186 else
1187 r |= GP_DIR_2|GP_IO_2;
1188
1189 skge_write32(hw, B2_GP_IO, r);
1190 skge_read32(hw, B2_GP_IO);
1191
8f3f8193 1192 /* Enable GMII interface */
89bf5f23
SH		 1193 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1194
45bada65 1195 bcom_phy_init(skge, jumbo);
89bf5f23 1196
45bada65
SH		 1197 /* Set Station Address */
1198 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1199
45bada65
SH		 1200 /* We don't use match addresses so clear */
1201 for (i = 1; i < 16; i++)
1202 xm_outaddr(hw, port, XM_EXM(i), zero);
1203
1204 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1205 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1206
1207 /* We don't need the FCS appended to the packet. */
1208 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1209 if (jumbo)
1210 r |= XM_RX_BIG_PK_OK;
89bf5f23 1211
45bada65 1212 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1213 /*
45bada65
SH		 1214 * If in manual half duplex mode the other side might be in
1215 * full duplex mode, so ignore if a carrier extension is not seen
1216 * on frames received
89bf5f23 1217 */
45bada65 1218 r |= XM_RX_DIS_CEXT;
baef58b1 1219 }
45bada65 1220 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1221
baef58b1
SH		 1222
1223 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1224 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1225
1226 /*
1227 * Bump up the transmit threshold. This helps hold off transmit
1228 * underruns when we're blasting traffic from both ports at once.
1229 */
1230 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1231
1232 /*
1233 * Enable the reception of all error frames. This is is
1234 * a necessary evil due to the design of the XMAC. The
1235 * XMAC's receive FIFO is only 8K in size, however jumbo
1236 * frames can be up to 9000 bytes in length. When bad
1237 * frame filtering is enabled, the XMAC's RX FIFO operates
1238 * in 'store and forward' mode. For this to work, the
1239 * entire frame has to fit into the FIFO, but that means
1240 * that jumbo frames larger than 8192 bytes will be
1241 * truncated. Disabling all bad frame filtering causes
1242 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1243 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1244 * RX FIFO as soon as the FIFO threshold is reached.
1245 */
45bada65 1246 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1247
baef58b1
SH		 1248
1249 /*
45bada65
SH		 1250 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1251 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1252 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1253 */
45bada65
SH		 1254 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1255
1256 /*
1257 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1258 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1259 * and 'Octets Tx OK Hi Cnt Ov'.
1260 */
1261 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1262
1263 /* Configure MAC arbiter */
1264 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1265
1266 /* configure timeout values */
1267 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1268 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1269 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1270 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1271
1272 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1273 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1274 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1275 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1276
1277 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1278 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1279 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1280 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1281
1282 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1283 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1284 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1285 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1286
45bada65 1287 if (jumbo) {
baef58b1 1288 /* Enable frame flushing if jumbo frames used */
6b0c1480 1289 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1290 } else {
1291 /* enable timeout timers if normal frames */
1292 skge_write16(hw, B3_PA_CTRL,
45bada65 1293 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1294 }
baef58b1
SH		 1295}
1296
1297static void genesis_stop(struct skge_port *skge)
1298{
1299 struct skge_hw *hw = skge->hw;
1300 int port = skge->port;
89bf5f23 1301 u32 reg;
baef58b1 1302
46a60f2d
SH		 1303 genesis_reset(hw, port);
1304
baef58b1
SH		 1305 /* Clear Tx packet arbiter timeout IRQ */
1306 skge_write16(hw, B3_PA_CTRL,
1307 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1308
1309 /*
8f3f8193 1310 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1311 * terminate if we don't flush the XMAC's transmit FIFO !
1312 */
6b0c1480
SH		 1313 xm_write32(hw, port, XM_MODE,
1314 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1315
1316
1317 /* Reset the MAC */
6b0c1480 1318 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1319
1320 /* For external PHYs there must be special handling */
89bf5f23
SH		 1321 reg = skge_read32(hw, B2_GP_IO);
1322 if (port == 0) {
1323 reg |= GP_DIR_0;
1324 reg &= ~GP_IO_0;
1325 } else {
1326 reg |= GP_DIR_2;
1327 reg &= ~GP_IO_2;
baef58b1 1328 }
89bf5f23
SH		 1329 skge_write32(hw, B2_GP_IO, reg);
1330 skge_read32(hw, B2_GP_IO);
baef58b1 1331
6b0c1480
SH		 1332 xm_write16(hw, port, XM_MMU_CMD,
1333 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1334 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1335
6b0c1480 1336 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1337}
1338
1339
1340static void genesis_get_stats(struct skge_port *skge, u64 *data)
1341{
1342 struct skge_hw *hw = skge->hw;
1343 int port = skge->port;
1344 int i;
1345 unsigned long timeout = jiffies + HZ;
1346
6b0c1480 1347 xm_write16(hw, port,
baef58b1
SH		 1348 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1349
1350 /* wait for update to complete */
6b0c1480 1351 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1352 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1353 if (time_after(jiffies, timeout))
1354 break;
1355 udelay(10);
1356 }
1357
1358 /* special case for 64 bit octet counter */
6b0c1480
SH		 1359 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1360 | xm_read32(hw, port, XM_TXO_OK_LO);
1361 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1362 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1363
1364 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1365 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1366}
1367
1368static void genesis_mac_intr(struct skge_hw *hw, int port)
1369{
1370 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1371 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1372
7e676d91
SH		 1373 if (netif_msg_intr(skge))
1374 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1375 skge->netdev->name, status);
baef58b1
SH		 1376
1377 if (status & XM_IS_TXF_UR) {
6b0c1480 1378 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1379 ++skge->net_stats.tx_fifo_errors;
1380 }
1381 if (status & XM_IS_RXF_OV) {
6b0c1480 1382 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1383 ++skge->net_stats.rx_fifo_errors;
1384 }
1385}
1386
baef58b1
SH		 1387static void genesis_link_up(struct skge_port *skge)
1388{
1389 struct skge_hw *hw = skge->hw;
1390 int port = skge->port;
1391 u16 cmd;
1392 u32 mode, msk;
1393
6b0c1480 1394 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1395
1396 /*
1397 * enabling pause frame reception is required for 1000BT
1398 * because the XMAC is not reset if the link is going down
1399 */
1400 if (skge->flow_control == FLOW_MODE_NONE ||
1401 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1402 /* Disable Pause Frame Reception */
baef58b1
SH		 1403 cmd |= XM_MMU_IGN_PF;
1404 else
1405 /* Enable Pause Frame Reception */
1406 cmd &= ~XM_MMU_IGN_PF;
1407
6b0c1480 1408 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1409
6b0c1480 1410 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1411 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1412 skge->flow_control == FLOW_MODE_LOC_SEND) {
1413 /*
1414 * Configure Pause Frame Generation
1415 * Use internal and external Pause Frame Generation.
1416 * Sending pause frames is edge triggered.
1417 * Send a Pause frame with the maximum pause time if
1418 * internal oder external FIFO full condition occurs.
1419 * Send a zero pause time frame to re-start transmission.
1420 */
1421 /* XM_PAUSE_DA = '010000C28001' (default) */
1422 /* XM_MAC_PTIME = 0xffff (maximum) */
1423 /* remember this value is defined in big endian (!) */
6b0c1480 1424 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1425
1426 mode |= XM_PAUSE_MODE;
6b0c1480 1427 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1428 } else {
1429 /*
1430 * disable pause frame generation is required for 1000BT
1431 * because the XMAC is not reset if the link is going down
1432 */
1433 /* Disable Pause Mode in Mode Register */
1434 mode &= ~XM_PAUSE_MODE;
1435
6b0c1480 1436 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1437 }
1438
6b0c1480 1439 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1440
1441 msk = XM_DEF_MSK;
89bf5f23
SH		 1442 /* disable GP0 interrupt bit for external Phy */
1443 msk |= XM_IS_INP_ASS;
baef58b1 1444
6b0c1480
SH		 1445 xm_write16(hw, port, XM_IMSK, msk);
1446 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1447
1448 /* get MMU Command Reg. */
6b0c1480 1449 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1450 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1451 cmd |= XM_MMU_GMII_FD;
1452
89bf5f23
SH		 1453 /*
1454 * Workaround BCOM Errata (#10523) for all BCom Phys
1455 * Enable Power Management after link up
1456 */
1457 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1458 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1459 & ~PHY_B_AC_DIS_PM);
1460 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1461
1462 /* enable Rx/Tx */
6b0c1480 1463 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1464 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1465 skge_link_up(skge);
1466}
1467
1468
45bada65 1469static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1470{
1471 struct skge_hw *hw = skge->hw;
1472 int port = skge->port;
45bada65
SH		 1473 u16 isrc;
1474
1475 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1476 if (netif_msg_intr(skge))
1477 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1478 skge->netdev->name, isrc);
baef58b1 1479
45bada65
SH		 1480 if (isrc & PHY_B_IS_PSE)
1481 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1482 hw->dev[port]->name);
baef58b1
SH		 1483
1484 /* Workaround BCom Errata:
1485 * enable and disable loopback mode if "NO HCD" occurs.
1486 */
45bada65 1487 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1488 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1489 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1490 ctrl | PHY_CT_LOOP);
6b0c1480 1491 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1492 ctrl & ~PHY_CT_LOOP);
1493 }
1494
45bada65
SH		 1495 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1496 bcom_check_link(hw, port);
baef58b1 1497
baef58b1
SH		 1498}
1499
2cd8e5d3
SH		 1500static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1501{
1502 int i;
1503
1504 gma_write16(hw, port, GM_SMI_DATA, val);
1505 gma_write16(hw, port, GM_SMI_CTRL,
1506 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1507 for (i = 0; i < PHY_RETRIES; i++) {
1508 udelay(1);
1509
1510 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1511 return 0;
1512 }
1513
1514 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1515 hw->dev[port]->name);
1516 return -EIO;
1517}
1518
1519static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1520{
1521 int i;
1522
1523 gma_write16(hw, port, GM_SMI_CTRL,
1524 GM_SMI_CT_PHY_AD(hw->phy_addr)
1525 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1526
1527 for (i = 0; i < PHY_RETRIES; i++) {
1528 udelay(1);
1529 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1530 goto ready;
1531 }
1532
1533 return -ETIMEDOUT;
1534 ready:
1535 *val = gma_read16(hw, port, GM_SMI_DATA);
1536 return 0;
1537}
1538
1539static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1540{
1541 u16 v = 0;
1542 if (__gm_phy_read(hw, port, reg, &v))
1543 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1544 hw->dev[port]->name);
1545 return v;
1546}
1547
8f3f8193 1548/* Marvell Phy Initialization */
baef58b1
SH		 1549static void yukon_init(struct skge_hw *hw, int port)
1550{
1551 struct skge_port *skge = netdev_priv(hw->dev[port]);
1552 u16 ctrl, ct1000, adv;
baef58b1 1553
baef58b1 1554 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1555 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1556
1557 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1558 PHY_M_EC_MAC_S_MSK);
1559 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1560
c506a509 1561 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1562
6b0c1480 1563 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1564 }
1565
6b0c1480 1566 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1567 if (skge->autoneg == AUTONEG_DISABLE)
1568 ctrl &= ~PHY_CT_ANE;
1569
1570 ctrl |= PHY_CT_RESET;
6b0c1480 1571 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1572
1573 ctrl = 0;
1574 ct1000 = 0;
b18f2091 1575 adv = PHY_AN_CSMA;
baef58b1
SH		 1576
1577 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1578 if (hw->copper) {
baef58b1
SH		 1579 if (skge->advertising & ADVERTISED_1000baseT_Full)
1580 ct1000 |= PHY_M_1000C_AFD;
1581 if (skge->advertising & ADVERTISED_1000baseT_Half)
1582 ct1000 |= PHY_M_1000C_AHD;
1583 if (skge->advertising & ADVERTISED_100baseT_Full)
1584 adv |= PHY_M_AN_100_FD;
1585 if (skge->advertising & ADVERTISED_100baseT_Half)
1586 adv |= PHY_M_AN_100_HD;
1587 if (skge->advertising & ADVERTISED_10baseT_Full)
1588 adv |= PHY_M_AN_10_FD;
1589 if (skge->advertising & ADVERTISED_10baseT_Half)
1590 adv |= PHY_M_AN_10_HD;
45bada65 1591 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1592 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1593
45bada65
SH		 1594 /* Set Flow-control capabilities */
1595 adv |= phy_pause_map[skge->flow_control];
1596
baef58b1
SH		 1597 /* Restart Auto-negotiation */
1598 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1599 } else {
1600 /* forced speed/duplex settings */
1601 ct1000 = PHY_M_1000C_MSE;
1602
1603 if (skge->duplex == DUPLEX_FULL)
1604 ctrl |= PHY_CT_DUP_MD;
1605
1606 switch (skge->speed) {
1607 case SPEED_1000:
1608 ctrl |= PHY_CT_SP1000;
1609 break;
1610 case SPEED_100:
1611 ctrl |= PHY_CT_SP100;
1612 break;
1613 }
1614
1615 ctrl |= PHY_CT_RESET;
1616 }
1617
c506a509 1618 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1619
6b0c1480
SH		 1620 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1621 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1622
baef58b1
SH		 1623 /* Enable phy interrupt on autonegotiation complete (or link up) */
1624 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1625 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1626 else
4cde06ed 1627 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1628}
1629
1630static void yukon_reset(struct skge_hw *hw, int port)
1631{
6b0c1480
SH		 1632 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1633 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1634 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1635 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1636 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1637
6b0c1480
SH		 1638 gma_write16(hw, port, GM_RX_CTRL,
1639 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1640 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1641}
1642
c8868611
SH		 1643/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1644static int is_yukon_lite_a0(struct skge_hw *hw)
1645{
1646 u32 reg;
1647 int ret;
1648
1649 if (hw->chip_id != CHIP_ID_YUKON)
1650 return 0;
1651
1652 reg = skge_read32(hw, B2_FAR);
1653 skge_write8(hw, B2_FAR + 3, 0xff);
1654 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1655 skge_write32(hw, B2_FAR, reg);
1656 return ret;
1657}
1658
baef58b1
SH		 1659static void yukon_mac_init(struct skge_hw *hw, int port)
1660{
1661 struct skge_port *skge = netdev_priv(hw->dev[port]);
1662 int i;
1663 u32 reg;
1664 const u8 *addr = hw->dev[port]->dev_addr;
1665
1666 /* WA code for COMA mode -- set PHY reset */
1667 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1668 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1669 reg = skge_read32(hw, B2_GP_IO);
1670 reg |= GP_DIR_9 | GP_IO_9;
1671 skge_write32(hw, B2_GP_IO, reg);
1672 }
baef58b1
SH		 1673
1674 /* hard reset */
6b0c1480
SH		 1675 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1676 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1677
1678 /* WA code for COMA mode -- clear PHY reset */
1679 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1680 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1681 reg = skge_read32(hw, B2_GP_IO);
1682 reg |= GP_DIR_9;
1683 reg &= ~GP_IO_9;
1684 skge_write32(hw, B2_GP_IO, reg);
1685 }
baef58b1
SH		 1686
1687 /* Set hardware config mode */
1688 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1689 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1690 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1691
1692 /* Clear GMC reset */
6b0c1480
SH		 1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1694 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1695 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1696 if (skge->autoneg == AUTONEG_DISABLE) {
1697 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1698 gma_write16(hw, port, GM_GP_CTRL,
1699 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1700
1701 switch (skge->speed) {
1702 case SPEED_1000:
1703 reg |= GM_GPCR_SPEED_1000;
1704 /* fallthru */
1705 case SPEED_100:
1706 reg |= GM_GPCR_SPEED_100;
1707 }
1708
1709 if (skge->duplex == DUPLEX_FULL)
1710 reg |= GM_GPCR_DUP_FULL;
1711 } else
1712 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1713 switch (skge->flow_control) {
1714 case FLOW_MODE_NONE:
6b0c1480 1715 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1716 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1717 break;
1718 case FLOW_MODE_LOC_SEND:
1719 /* disable Rx flow-control */
1720 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 }
1722
6b0c1480 1723 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1724 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1725
baef58b1 1726 yukon_init(hw, port);
baef58b1
SH		 1727
1728 /* MIB clear */
6b0c1480
SH		 1729 reg = gma_read16(hw, port, GM_PHY_ADDR);
1730 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1731
1732 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1733 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1734 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1735
1736 /* transmit control */
6b0c1480 1737 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1738
1739 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1740 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1741 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1742
1743 /* transmit flow control */
6b0c1480 1744 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1745
1746 /* transmit parameter */
6b0c1480 1747 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1748 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1749 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1750 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1751
1752 /* serial mode register */
1753 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1754 if (hw->dev[port]->mtu > 1500)
1755 reg |= GM_SMOD_JUMBO_ENA;
1756
6b0c1480 1757 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1758
1759 /* physical address: used for pause frames */
6b0c1480 1760 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1761 /* virtual address for data */
6b0c1480 1762 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1763
1764 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1765 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1766 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1767 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1768
1769 /* Initialize Mac Fifo */
1770
1771 /* Configure Rx MAC FIFO */
6b0c1480 1772 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1773 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1774
1775 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1776 if (is_yukon_lite_a0(hw))
baef58b1 1777 reg &= ~GMF_RX_F_FL_ON;
c8868611 1778
6b0c1480
SH		 1779 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1780 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1781 /*
1782 * because Pause Packet Truncation in GMAC is not working
1783 * we have to increase the Flush Threshold to 64 bytes
1784 * in order to flush pause packets in Rx FIFO on Yukon-1
1785 */
1786 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1787
1788 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1789 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1790 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1791}
1792
355ec572
SH		 1793/* Go into power down mode */
1794static void yukon_suspend(struct skge_hw *hw, int port)
1795{
1796 u16 ctrl;
1797
1798 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1799 ctrl |= PHY_M_PC_POL_R_DIS;
1800 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1801
1802 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1803 ctrl |= PHY_CT_RESET;
1804 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1805
1806 /* switch IEEE compatible power down mode on */
1807 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1808 ctrl |= PHY_CT_PDOWN;
1809 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1810}
1811
baef58b1
SH		 1812static void yukon_stop(struct skge_port *skge)
1813{
1814 struct skge_hw *hw = skge->hw;
1815 int port = skge->port;
1816
46a60f2d
SH		 1817 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1818 yukon_reset(hw, port);
baef58b1 1819
6b0c1480
SH		 1820 gma_write16(hw, port, GM_GP_CTRL,
1821 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1822 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1823 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1824
355ec572 1825 yukon_suspend(hw, port);
46a60f2d 1826
baef58b1 1827 /* set GPHY Control reset */
46a60f2d
SH		 1828 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1829 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1830}
1831
1832static void yukon_get_stats(struct skge_port *skge, u64 *data)
1833{
1834 struct skge_hw *hw = skge->hw;
1835 int port = skge->port;
1836 int i;
1837
6b0c1480
SH		 1838 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1839 | gma_read32(hw, port, GM_TXO_OK_LO);
1840 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1841 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1842
1843 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1844 data[i] = gma_read32(hw, port,
baef58b1
SH		 1845 skge_stats[i].gma_offset);
1846}
1847
1848static void yukon_mac_intr(struct skge_hw *hw, int port)
1849{
7e676d91
SH		 1850 struct net_device *dev = hw->dev[port];
1851 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1852 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1853
7e676d91
SH		 1854 if (netif_msg_intr(skge))
1855 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1856 dev->name, status);
1857
baef58b1
SH		 1858 if (status & GM_IS_RX_FF_OR) {
1859 ++skge->net_stats.rx_fifo_errors;
d8a09943 1860 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1861 }
d8a09943 1862
baef58b1
SH		 1863 if (status & GM_IS_TX_FF_UR) {
1864 ++skge->net_stats.tx_fifo_errors;
d8a09943 1865 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1866 }
1867
1868}
1869
1870static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1871{
95566065 1872 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1873 case PHY_M_PS_SPEED_1000:
1874 return SPEED_1000;
1875 case PHY_M_PS_SPEED_100:
1876 return SPEED_100;
1877 default:
1878 return SPEED_10;
1879 }
1880}
1881
1882static void yukon_link_up(struct skge_port *skge)
1883{
1884 struct skge_hw *hw = skge->hw;
1885 int port = skge->port;
1886 u16 reg;
1887
baef58b1 1888 /* Enable Transmit FIFO Underrun */
46a60f2d 1889 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1890
6b0c1480 1891 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1892 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1893 reg |= GM_GPCR_DUP_FULL;
1894
1895 /* enable Rx/Tx */
1896 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1897 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1898
4cde06ed 1899 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1900 skge_link_up(skge);
1901}
1902
1903static void yukon_link_down(struct skge_port *skge)
1904{
1905 struct skge_hw *hw = skge->hw;
1906 int port = skge->port;
d8a09943 1907 u16 ctrl;
baef58b1 1908
6b0c1480 1909 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1910
1911 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1912 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1913 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1914
c506a509 1915 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1916 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1917 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1918 gm_phy_read(hw, port,
baef58b1
SH		 1919 PHY_MARV_AUNE_ADV)
1920 | PHY_M_AN_ASP);
1921
1922 }
1923
1924 yukon_reset(hw, port);
1925 skge_link_down(skge);
1926
1927 yukon_init(hw, port);
1928}
1929
1930static void yukon_phy_intr(struct skge_port *skge)
1931{
1932 struct skge_hw *hw = skge->hw;
1933 int port = skge->port;
1934 const char *reason = NULL;
1935 u16 istatus, phystat;
1936
6b0c1480
SH		 1937 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1938 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1939
1940 if (netif_msg_intr(skge))
1941 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1942 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1943
1944 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1945 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1946 & PHY_M_AN_RF) {
1947 reason = "remote fault";
1948 goto failed;
1949 }
1950
c506a509 1951 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1952 reason = "master/slave fault";
1953 goto failed;
1954 }
1955
1956 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1957 reason = "speed/duplex";
1958 goto failed;
1959 }
1960
1961 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1962 ? DUPLEX_FULL : DUPLEX_HALF;
1963 skge->speed = yukon_speed(hw, phystat);
1964
baef58b1
SH		 1965 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1966 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1967 case PHY_M_PS_PAUSE_MSK:
1968 skge->flow_control = FLOW_MODE_SYMMETRIC;
1969 break;
1970 case PHY_M_PS_RX_P_EN:
1971 skge->flow_control = FLOW_MODE_REM_SEND;
1972 break;
1973 case PHY_M_PS_TX_P_EN:
1974 skge->flow_control = FLOW_MODE_LOC_SEND;
1975 break;
1976 default:
1977 skge->flow_control = FLOW_MODE_NONE;
1978 }
1979
1980 if (skge->flow_control == FLOW_MODE_NONE ||
1981 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1982 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1983 else
6b0c1480 1984 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1985 yukon_link_up(skge);
1986 return;
1987 }
1988
1989 if (istatus & PHY_M_IS_LSP_CHANGE)
1990 skge->speed = yukon_speed(hw, phystat);
1991
1992 if (istatus & PHY_M_IS_DUP_CHANGE)
1993 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1994 if (istatus & PHY_M_IS_LST_CHANGE) {
1995 if (phystat & PHY_M_PS_LINK_UP)
1996 yukon_link_up(skge);
1997 else
1998 yukon_link_down(skge);
1999 }
2000 return;
2001 failed:
2002 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2003 skge->netdev->name, reason);
2004
2005 /* XXX restart autonegotiation? */
2006}
2007
ee294dcd
SH		 2008static void skge_phy_reset(struct skge_port *skge)
2009{
2010 struct skge_hw *hw = skge->hw;
2011 int port = skge->port;
2012
2013 netif_stop_queue(skge->netdev);
2014 netif_carrier_off(skge->netdev);
2015
2016 spin_lock_bh(&hw->phy_lock);
2017 if (hw->chip_id == CHIP_ID_GENESIS) {
2018 genesis_reset(hw, port);
2019 genesis_mac_init(hw, port);
2020 } else {
2021 yukon_reset(hw, port);
2022 yukon_init(hw, port);
2023 }
2024 spin_unlock_bh(&hw->phy_lock);
2025}
2026
2cd8e5d3
SH		 2027/* Basic MII support */
2028static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2029{
2030 struct mii_ioctl_data *data = if_mii(ifr);
2031 struct skge_port *skge = netdev_priv(dev);
2032 struct skge_hw *hw = skge->hw;
2033 int err = -EOPNOTSUPP;
2034
2035 if (!netif_running(dev))
2036 return -ENODEV; /* Phy still in reset */
2037
2038 switch(cmd) {
2039 case SIOCGMIIPHY:
2040 data->phy_id = hw->phy_addr;
2041
2042 /* fallthru */
2043 case SIOCGMIIREG: {
2044 u16 val = 0;
2045 spin_lock_bh(&hw->phy_lock);
2046 if (hw->chip_id == CHIP_ID_GENESIS)
2047 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2048 else
2049 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2050 spin_unlock_bh(&hw->phy_lock);
2051 data->val_out = val;
2052 break;
2053 }
2054
2055 case SIOCSMIIREG:
2056 if (!capable(CAP_NET_ADMIN))
2057 return -EPERM;
2058
2059 spin_lock_bh(&hw->phy_lock);
2060 if (hw->chip_id == CHIP_ID_GENESIS)
2061 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2062 data->val_in);
2063 else
2064 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2065 data->val_in);
2066 spin_unlock_bh(&hw->phy_lock);
2067 break;
2068 }
2069 return err;
2070}
2071
baef58b1
SH		 2072static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2073{
2074 u32 end;
2075
2076 start /= 8;
2077 len /= 8;
2078 end = start + len - 1;
2079
2080 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2081 skge_write32(hw, RB_ADDR(q, RB_START), start);
2082 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2083 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2084 skge_write32(hw, RB_ADDR(q, RB_END), end);
2085
2086 if (q == Q_R1 || q == Q_R2) {
2087 /* Set thresholds on receive queue's */
2088 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2089 start + (2*len)/3);
2090 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2091 start + (len/3));
2092 } else {
2093 /* Enable store & forward on Tx queue's because
2094 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2095 */
2096 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2097 }
2098
2099 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2100}
2101
2102/* Setup Bus Memory Interface */
2103static void skge_qset(struct skge_port *skge, u16 q,
2104 const struct skge_element *e)
2105{
2106 struct skge_hw *hw = skge->hw;
2107 u32 watermark = 0x600;
2108 u64 base = skge->dma + (e->desc - skge->mem);
2109
2110 /* optimization to reduce window on 32bit/33mhz */
2111 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2112 watermark /= 2;
2113
2114 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2115 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2116 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2117 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2118}
2119
2120static int skge_up(struct net_device *dev)
2121{
2122 struct skge_port *skge = netdev_priv(dev);
2123 struct skge_hw *hw = skge->hw;
2124 int port = skge->port;
2125 u32 chunk, ram_addr;
2126 size_t rx_size, tx_size;
2127 int err;
2128
2129 if (netif_msg_ifup(skge))
2130 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2131
19a33d4e
SH		 2132 if (dev->mtu > RX_BUF_SIZE)
2133 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2134 else
2135 skge->rx_buf_size = RX_BUF_SIZE;
2136
2137
baef58b1
SH		 2138 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2139 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2140 skge->mem_size = tx_size + rx_size;
2141 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2142 if (!skge->mem)
2143 return -ENOMEM;
2144
2145 memset(skge->mem, 0, skge->mem_size);
2146
2147 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2148 goto free_pci_mem;
2149
19a33d4e
SH		 2150 err = skge_rx_fill(skge);
2151 if (err)
baef58b1
SH		 2152 goto free_rx_ring;
2153
2154 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2155 skge->dma + rx_size)))
2156 goto free_rx_ring;
2157
2158 skge->tx_avail = skge->tx_ring.count - 1;
2159
7e676d91
SH		 2160 /* Enable IRQ from port */
2161 hw->intr_mask |= portirqmask[port];
2162 skge_write32(hw, B0_IMSK, hw->intr_mask);
2163
8f3f8193 2164 /* Initialize MAC */
4ff6ac05 2165 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2166 if (hw->chip_id == CHIP_ID_GENESIS)
2167 genesis_mac_init(hw, port);
2168 else
2169 yukon_mac_init(hw, port);
4ff6ac05 2170 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2171
2172 /* Configure RAMbuffers */
981d0377 2173 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2174 ram_addr = hw->ram_offset + 2 * chunk * port;
2175
2176 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2177 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2178
2179 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2180 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2181 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2182
2183 /* Start receiver BMU */
2184 wmb();
2185 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2186 skge_led(skge, LED_MODE_ON);
baef58b1 2187
baef58b1
SH		 2188 return 0;
2189
2190 free_rx_ring:
2191 skge_rx_clean(skge);
2192 kfree(skge->rx_ring.start);
2193 free_pci_mem:
2194 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2195 skge->mem = NULL;
baef58b1
SH		 2196
2197 return err;
2198}
2199
2200static int skge_down(struct net_device *dev)
2201{
2202 struct skge_port *skge = netdev_priv(dev);
2203 struct skge_hw *hw = skge->hw;
2204 int port = skge->port;
2205
7731a4ea
SH		 2206 if (skge->mem == NULL)
2207 return 0;
2208
baef58b1
SH		 2209 if (netif_msg_ifdown(skge))
2210 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2211
2212 netif_stop_queue(dev);
2213
46a60f2d
SH		 2214 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2215 if (hw->chip_id == CHIP_ID_GENESIS)
2216 genesis_stop(skge);
2217 else
2218 yukon_stop(skge);
2219
2220 hw->intr_mask &= ~portirqmask[skge->port];
2221 skge_write32(hw, B0_IMSK, hw->intr_mask);
2222
baef58b1
SH		 2223 /* Stop transmitter */
2224 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2225 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2226 RB_RST_SET|RB_DIS_OP_MD);
2227
baef58b1
SH		 2228
2229 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2230 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2231 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2232
2233 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2234 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2235 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2236
2237 /* Reset PCI FIFO */
2238 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2239 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2240
2241 /* Reset the RAM Buffer async Tx queue */
2242 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2243 /* stop receiver */
2244 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2245 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2246 RB_RST_SET|RB_DIS_OP_MD);
2247 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2248
2249 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2250 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2251 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2252 } else {
6b0c1480
SH		 2253 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2254 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2255 }
2256
6abebb53 2257 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2258
2259 skge_tx_clean(skge);
2260 skge_rx_clean(skge);
2261
2262 kfree(skge->rx_ring.start);
2263 kfree(skge->tx_ring.start);
2264 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2265 skge->mem = NULL;
baef58b1
SH		 2266 return 0;
2267}
2268
2269static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2270{
2271 struct skge_port *skge = netdev_priv(dev);
2272 struct skge_hw *hw = skge->hw;
2273 struct skge_ring *ring = &skge->tx_ring;
2274 struct skge_element *e;
2275 struct skge_tx_desc *td;
2276 int i;
2277 u32 control, len;
2278 u64 map;
2279 unsigned long flags;
2280
2281 skb = skb_padto(skb, ETH_ZLEN);
2282 if (!skb)
2283 return NETDEV_TX_OK;
2284
2285 local_irq_save(flags);
2286 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2287 /* Collision - tell upper layer to requeue */
2288 local_irq_restore(flags);
2289 return NETDEV_TX_LOCKED;
2290 }
baef58b1
SH		 2291
2292 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
98684a9d 2293 if (!netif_queue_stopped(dev)) {
ee1c8191 2294 netif_stop_queue(dev);
baef58b1 2295
ee1c8191
SH		 2296 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2297 dev->name);
2298 }
2299 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1
SH		 2300 return NETDEV_TX_BUSY;
2301 }
2302
2303 e = ring->to_use;
2304 td = e->desc;
2305 e->skb = skb;
2306 len = skb_headlen(skb);
2307 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2308 pci_unmap_addr_set(e, mapaddr, map);
2309 pci_unmap_len_set(e, maplen, len);
2310
2311 td->dma_lo = map;
2312 td->dma_hi = map >> 32;
2313
2314 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2315 int offset = skb->h.raw - skb->data;
2316
2317 /* This seems backwards, but it is what the sk98lin
2318 * does. Looks like hardware is wrong?
2319 */
ea182d4a 2320 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2321 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2322 control = BMU_TCP_CHECK;
2323 else
2324 control = BMU_UDP_CHECK;
2325
2326 td->csum_offs = 0;
2327 td->csum_start = offset;
2328 td->csum_write = offset + skb->csum;
2329 } else
2330 control = BMU_CHECK;
2331
2332 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2333 control |= BMU_EOF| BMU_IRQ_EOF;
2334 else {
2335 struct skge_tx_desc *tf = td;
2336
2337 control |= BMU_STFWD;
2338 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2339 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2340
2341 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2342 frag->size, PCI_DMA_TODEVICE);
2343
2344 e = e->next;
2345 e->skb = NULL;
2346 tf = e->desc;
2347 tf->dma_lo = map;
2348 tf->dma_hi = (u64) map >> 32;
2349 pci_unmap_addr_set(e, mapaddr, map);
2350 pci_unmap_len_set(e, maplen, frag->size);
2351
2352 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2353 }
2354 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2355 }
2356 /* Make sure all the descriptors written */
2357 wmb();
2358 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2359 wmb();
2360
2361 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2362
2363 if (netif_msg_tx_queued(skge))
0b2d7fea 2364 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2365 dev->name, e - ring->start, skb->len);
2366
2367 ring->to_use = e->next;
2368 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2369 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2370 pr_debug("%s: transmit queue full\n", dev->name);
2371 netif_stop_queue(dev);
2372 }
2373
2374 dev->trans_start = jiffies;
2375 spin_unlock_irqrestore(&skge->tx_lock, flags);
2376
2377 return NETDEV_TX_OK;
2378}
2379
2380static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2381{
19a33d4e 2382 /* This ring element can be skb or fragment */
baef58b1
SH		 2383 if (e->skb) {
2384 pci_unmap_single(hw->pdev,
2385 pci_unmap_addr(e, mapaddr),
2386 pci_unmap_len(e, maplen),
2387 PCI_DMA_TODEVICE);
2388 dev_kfree_skb_any(e->skb);
2389 e->skb = NULL;
2390 } else {
2391 pci_unmap_page(hw->pdev,
2392 pci_unmap_addr(e, mapaddr),
2393 pci_unmap_len(e, maplen),
2394 PCI_DMA_TODEVICE);
2395 }
2396}
2397
2398static void skge_tx_clean(struct skge_port *skge)
2399{
2400 struct skge_ring *ring = &skge->tx_ring;
2401 struct skge_element *e;
2402 unsigned long flags;
2403
2404 spin_lock_irqsave(&skge->tx_lock, flags);
2405 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2406 ++skge->tx_avail;
2407 skge_tx_free(skge->hw, e);
2408 }
2409 ring->to_clean = e;
2410 spin_unlock_irqrestore(&skge->tx_lock, flags);
2411}
2412
2413static void skge_tx_timeout(struct net_device *dev)
2414{
2415 struct skge_port *skge = netdev_priv(dev);
2416
2417 if (netif_msg_timer(skge))
2418 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2419
2420 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2421 skge_tx_clean(skge);
2422}
2423
2424static int skge_change_mtu(struct net_device *dev, int new_mtu)
2425{
7731a4ea 2426 int err;
baef58b1 2427
95566065 2428 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2429 return -EINVAL;
2430
7731a4ea
SH		 2431 if (!netif_running(dev)) {
2432 dev->mtu = new_mtu;
2433 return 0;
2434 }
2435
2436 skge_down(dev);
baef58b1 2437
19a33d4e 2438 dev->mtu = new_mtu;
7731a4ea
SH		 2439
2440 err = skge_up(dev);
2441 if (err)
2442 dev_close(dev);
baef58b1
SH		 2443
2444 return err;
2445}
2446
2447static void genesis_set_multicast(struct net_device *dev)
2448{
2449 struct skge_port *skge = netdev_priv(dev);
2450 struct skge_hw *hw = skge->hw;
2451 int port = skge->port;
2452 int i, count = dev->mc_count;
2453 struct dev_mc_list *list = dev->mc_list;
2454 u32 mode;
2455 u8 filter[8];
2456
6b0c1480 2457 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2458 mode |= XM_MD_ENA_HASH;
2459 if (dev->flags & IFF_PROMISC)
2460 mode |= XM_MD_ENA_PROM;
2461 else
2462 mode &= ~XM_MD_ENA_PROM;
2463
2464 if (dev->flags & IFF_ALLMULTI)
2465 memset(filter, 0xff, sizeof(filter));
2466 else {
2467 memset(filter, 0, sizeof(filter));
95566065 2468 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2469 u32 crc, bit;
2470 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2471 bit = ~crc & 0x3f;
baef58b1
SH		 2472 filter[bit/8] |= 1 << (bit%8);
2473 }
2474 }
2475
6b0c1480 2476 xm_write32(hw, port, XM_MODE, mode);
45bada65 2477 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2478}
2479
2480static void yukon_set_multicast(struct net_device *dev)
2481{
2482 struct skge_port *skge = netdev_priv(dev);
2483 struct skge_hw *hw = skge->hw;
2484 int port = skge->port;
2485 struct dev_mc_list *list = dev->mc_list;
2486 u16 reg;
2487 u8 filter[8];
2488
2489 memset(filter, 0, sizeof(filter));
2490
6b0c1480 2491 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2492 reg |= GM_RXCR_UCF_ENA;
2493
8f3f8193 2494 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2495 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2496 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2497 memset(filter, 0xff, sizeof(filter));
2498 else if (dev->mc_count == 0) /* no multicast */
2499 reg &= ~GM_RXCR_MCF_ENA;
2500 else {
2501 int i;
2502 reg |= GM_RXCR_MCF_ENA;
2503
95566065 2504 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2505 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2506 filter[bit/8] |= 1 << (bit%8);
2507 }
2508 }
2509
2510
6b0c1480 2511 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2512 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2513 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2514 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2515 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2516 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2517 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2518 (u16)filter[6] | ((u16)filter[7] << 8));
2519
6b0c1480 2520 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2521}
2522
383181ac
SH		 2523static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2524{
2525 if (hw->chip_id == CHIP_ID_GENESIS)
2526 return status >> XMR_FS_LEN_SHIFT;
2527 else
2528 return status >> GMR_FS_LEN_SHIFT;
2529}
2530
baef58b1
SH		 2531static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2532{
2533 if (hw->chip_id == CHIP_ID_GENESIS)
2534 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2535 else
2536 return (status & GMR_FS_ANY_ERR) ||
2537 (status & GMR_FS_RX_OK) == 0;
2538}
2539
19a33d4e
SH		 2540
2541/* Get receive buffer from descriptor.
2542 * Handles copy of small buffers and reallocation failures
2543 */
2544static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2545 struct skge_element *e,
383181ac 2546 u32 control, u32 status, u16 csum)
19a33d4e 2547{
383181ac
SH		 2548 struct sk_buff *skb;
2549 u16 len = control & BMU_BBC;
2550
2551 if (unlikely(netif_msg_rx_status(skge)))
2552 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2553 skge->netdev->name, e - skge->rx_ring.start,
2554 status, len);
2555
2556 if (len > skge->rx_buf_size)
2557 goto error;
2558
2559 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2560 goto error;
2561
2562 if (bad_phy_status(skge->hw, status))
2563 goto error;
2564
2565 if (phy_length(skge->hw, status) != len)
2566 goto error;
19a33d4e
SH		 2567
2568 if (len < RX_COPY_THRESHOLD) {
383181ac
SH		 2569 skb = dev_alloc_skb(len + 2);
2570 if (!skb)
2571 goto resubmit;
19a33d4e 2572
383181ac 2573 skb_reserve(skb, 2);
19a33d4e
SH		 2574 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2575 pci_unmap_addr(e, mapaddr),
2576 len, PCI_DMA_FROMDEVICE);
383181ac 2577 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2578 pci_dma_sync_single_for_device(skge->hw->pdev,
2579 pci_unmap_addr(e, mapaddr),
2580 len, PCI_DMA_FROMDEVICE);
19a33d4e 2581 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2582 } else {
383181ac
SH		 2583 struct sk_buff *nskb;
2584 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2585 if (!nskb)
2586 goto resubmit;
19a33d4e
SH		 2587
2588 pci_unmap_single(skge->hw->pdev,
2589 pci_unmap_addr(e, mapaddr),
2590 pci_unmap_len(e, maplen),
2591 PCI_DMA_FROMDEVICE);
2592 skb = e->skb;
383181ac 2593 prefetch(skb->data);
19a33d4e 2594 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2595 }
383181ac
SH		 2596
2597 skb_put(skb, len);
2598 skb->dev = skge->netdev;
2599 if (skge->rx_csum) {
2600 skb->csum = csum;
2601 skb->ip_summed = CHECKSUM_HW;
2602 }
2603
2604 skb->protocol = eth_type_trans(skb, skge->netdev);
2605
2606 return skb;
2607error:
2608
2609 if (netif_msg_rx_err(skge))
2610 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2611 skge->netdev->name, e - skge->rx_ring.start,
2612 control, status);
2613
2614 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2615 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2616 skge->net_stats.rx_length_errors++;
2617 if (status & XMR_FS_FRA_ERR)
2618 skge->net_stats.rx_frame_errors++;
2619 if (status & XMR_FS_FCS_ERR)
2620 skge->net_stats.rx_crc_errors++;
2621 } else {
2622 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2623 skge->net_stats.rx_length_errors++;
2624 if (status & GMR_FS_FRAGMENT)
2625 skge->net_stats.rx_frame_errors++;
2626 if (status & GMR_FS_CRC_ERR)
2627 skge->net_stats.rx_crc_errors++;
2628 }
2629
2630resubmit:
2631 skge_rx_reuse(e, skge->rx_buf_size);
2632 return NULL;
baef58b1
SH		 2633}
2634
19a33d4e 2635
baef58b1
SH		 2636static int skge_poll(struct net_device *dev, int *budget)
2637{
2638 struct skge_port *skge = netdev_priv(dev);
2639 struct skge_hw *hw = skge->hw;
2640 struct skge_ring *ring = &skge->rx_ring;
2641 struct skge_element *e;
2642 unsigned int to_do = min(dev->quota, *budget);
2643 unsigned int work_done = 0;
7e676d91 2644
1631aef1 2645 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2646 struct skge_rx_desc *rd = e->desc;
19a33d4e 2647 struct sk_buff *skb;
383181ac 2648 u32 control;
baef58b1
SH		 2649
2650 rmb();
2651 control = rd->control;
2652 if (control & BMU_OWN)
2653 break;
2654
383181ac
SH		 2655 skb = skge_rx_get(skge, e, control, rd->status,
2656 le16_to_cpu(rd->csum2));
19a33d4e 2657 if (likely(skb)) {
19a33d4e
SH		 2658 dev->last_rx = jiffies;
2659 netif_receive_skb(skb);
baef58b1 2660
19a33d4e
SH		 2661 ++work_done;
2662 } else
2663 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2664 }
2665 ring->to_clean = e;
2666
baef58b1
SH		 2667 /* restart receiver */
2668 wmb();
2669 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2670 CSR_START | CSR_IRQ_CL_F);
2671
19a33d4e
SH		 2672 *budget -= work_done;
2673 dev->quota -= work_done;
2674
2675 if (work_done >= to_do)
2676 return 1; /* not done */
baef58b1 2677
1631aef1 2678 netif_rx_complete(dev);
19a33d4e
SH		 2679 hw->intr_mask |= portirqmask[skge->port];
2680 skge_write32(hw, B0_IMSK, hw->intr_mask);
1631aef1
SH		 2681 skge_read32(hw, B0_IMSK);
2682
19a33d4e 2683 return 0;
baef58b1
SH		 2684}
2685
2686static inline void skge_tx_intr(struct net_device *dev)
2687{
2688 struct skge_port *skge = netdev_priv(dev);
2689 struct skge_hw *hw = skge->hw;
2690 struct skge_ring *ring = &skge->tx_ring;
2691 struct skge_element *e;
2692
2693 spin_lock(&skge->tx_lock);
1631aef1 2694 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
baef58b1
SH		 2695 struct skge_tx_desc *td = e->desc;
2696 u32 control;
2697
2698 rmb();
2699 control = td->control;
2700 if (control & BMU_OWN)
2701 break;
2702
2703 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2704 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2705 dev->name, e - ring->start, td->status);
2706
2707 skge_tx_free(hw, e);
2708 e->skb = NULL;
2709 ++skge->tx_avail;
2710 }
2711 ring->to_clean = e;
2712 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2713
2714 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2715 netif_wake_queue(dev);
2716
2717 spin_unlock(&skge->tx_lock);
2718}
2719
f6620cab
SH		 2720/* Parity errors seem to happen when Genesis is connected to a switch
2721 * with no other ports present. Heartbeat error??
2722 */
baef58b1
SH		 2723static void skge_mac_parity(struct skge_hw *hw, int port)
2724{
f6620cab
SH		 2725 struct net_device *dev = hw->dev[port];
2726
2727 if (dev) {
2728 struct skge_port *skge = netdev_priv(dev);
2729 ++skge->net_stats.tx_heartbeat_errors;
2730 }
baef58b1
SH		 2731
2732 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2733 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2734 MFF_CLR_PERR);
2735 else
2736 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2737 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2738 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2739 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2740}
2741
2742static void skge_pci_clear(struct skge_hw *hw)
2743{
2744 u16 status;
2745
467b3417 2746 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2747 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2748 pci_write_config_word(hw->pdev, PCI_STATUS,
2749 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2750 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2751}
2752
2753static void skge_mac_intr(struct skge_hw *hw, int port)
2754{
95566065 2755 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2756 genesis_mac_intr(hw, port);
2757 else
2758 yukon_mac_intr(hw, port);
2759}
2760
2761/* Handle device specific framing and timeout interrupts */
2762static void skge_error_irq(struct skge_hw *hw)
2763{
2764 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2765
2766 if (hw->chip_id == CHIP_ID_GENESIS) {
2767 /* clear xmac errors */
2768 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2769 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2770 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2771 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2772 } else {
2773 /* Timestamp (unused) overflow */
2774 if (hwstatus & IS_IRQ_TIST_OV)
2775 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2776 }
2777
2778 if (hwstatus & IS_RAM_RD_PAR) {
2779 printk(KERN_ERR PFX "Ram read data parity error\n");
2780 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2781 }
2782
2783 if (hwstatus & IS_RAM_WR_PAR) {
2784 printk(KERN_ERR PFX "Ram write data parity error\n");
2785 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2786 }
2787
2788 if (hwstatus & IS_M1_PAR_ERR)
2789 skge_mac_parity(hw, 0);
2790
2791 if (hwstatus & IS_M2_PAR_ERR)
2792 skge_mac_parity(hw, 1);
2793
2794 if (hwstatus & IS_R1_PAR_ERR)
2795 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2796
2797 if (hwstatus & IS_R2_PAR_ERR)
2798 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2799
2800 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2801 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2802 hwstatus);
2803
2804 skge_pci_clear(hw);
2805
050ec18a 2806 /* if error still set then just ignore it */
baef58b1
SH		 2807 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2808 if (hwstatus & IS_IRQ_STAT) {
050ec18a 2809 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
baef58b1
SH		 2810 hwstatus);
2811 hw->intr_mask &= ~IS_HW_ERR;
2812 }
2813 }
2814}
2815
2816/*
8f3f8193 2817 * Interrupt from PHY are handled in tasklet (soft irq)
baef58b1
SH		 2818 * because accessing phy registers requires spin wait which might
2819 * cause excess interrupt latency.
2820 */
2821static void skge_extirq(unsigned long data)
2822{
2823 struct skge_hw *hw = (struct skge_hw *) data;
2824 int port;
2825
2826 spin_lock(&hw->phy_lock);
2827 for (port = 0; port < 2; port++) {
2828 struct net_device *dev = hw->dev[port];
2829
2830 if (dev && netif_running(dev)) {
2831 struct skge_port *skge = netdev_priv(dev);
2832
2833 if (hw->chip_id != CHIP_ID_GENESIS)
2834 yukon_phy_intr(skge);
89bf5f23 2835 else
45bada65 2836 bcom_phy_intr(skge);
baef58b1
SH		 2837 }
2838 }
2839 spin_unlock(&hw->phy_lock);
2840
2841 local_irq_disable();
2842 hw->intr_mask |= IS_EXT_REG;
2843 skge_write32(hw, B0_IMSK, hw->intr_mask);
2844 local_irq_enable();
2845}
2846
1631aef1
SH		 2847static inline void skge_wakeup(struct net_device *dev)
2848{
2849 struct skge_port *skge = netdev_priv(dev);
2850
2851 prefetch(skge->rx_ring.to_clean);
2852 netif_rx_schedule(dev);
2853}
2854
baef58b1
SH		 2855static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2856{
2857 struct skge_hw *hw = dev_id;
2858 u32 status = skge_read32(hw, B0_SP_ISRC);
2859
2860 if (status == 0 || status == ~0) /* hotplug or shared irq */
2861 return IRQ_NONE;
2862
2863 status &= hw->intr_mask;
7e676d91 2864 if (status & IS_R1_F) {
baef58b1 2865 hw->intr_mask &= ~IS_R1_F;
1631aef1 2866 skge_wakeup(hw->dev[0]);
baef58b1
SH		 2867 }
2868
7e676d91 2869 if (status & IS_R2_F) {
baef58b1 2870 hw->intr_mask &= ~IS_R2_F;
1631aef1 2871 skge_wakeup(hw->dev[1]);
baef58b1
SH		 2872 }
2873
2874 if (status & IS_XA1_F)
2875 skge_tx_intr(hw->dev[0]);
2876
2877 if (status & IS_XA2_F)
2878 skge_tx_intr(hw->dev[1]);
2879
d25f5a67
SH		 2880 if (status & IS_PA_TO_RX1) {
2881 struct skge_port *skge = netdev_priv(hw->dev[0]);
2882 ++skge->net_stats.rx_over_errors;
2883 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2884 }
2885
2886 if (status & IS_PA_TO_RX2) {
2887 struct skge_port *skge = netdev_priv(hw->dev[1]);
2888 ++skge->net_stats.rx_over_errors;
2889 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2890 }
2891
2892 if (status & IS_PA_TO_TX1)
2893 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2894
2895 if (status & IS_PA_TO_TX2)
2896 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2897
baef58b1
SH		 2898 if (status & IS_MAC1)
2899 skge_mac_intr(hw, 0);
95566065 2900
baef58b1
SH		 2901 if (status & IS_MAC2)
2902 skge_mac_intr(hw, 1);
2903
2904 if (status & IS_HW_ERR)
2905 skge_error_irq(hw);
2906
2907 if (status & IS_EXT_REG) {
2908 hw->intr_mask &= ~IS_EXT_REG;
2909 tasklet_schedule(&hw->ext_tasklet);
2910 }
2911
7e676d91 2912 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2913
2914 return IRQ_HANDLED;
2915}
2916
2917#ifdef CONFIG_NET_POLL_CONTROLLER
2918static void skge_netpoll(struct net_device *dev)
2919{
2920 struct skge_port *skge = netdev_priv(dev);
2921
2922 disable_irq(dev->irq);
2923 skge_intr(dev->irq, skge->hw, NULL);
2924 enable_irq(dev->irq);
2925}
2926#endif
2927
2928static int skge_set_mac_address(struct net_device *dev, void *p)
2929{
2930 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2931 struct skge_hw *hw = skge->hw;
2932 unsigned port = skge->port;
2933 const struct sockaddr *addr = p;
baef58b1
SH		 2934
2935 if (!is_valid_ether_addr(addr->sa_data))
2936 return -EADDRNOTAVAIL;
2937
c2681dd8 2938 spin_lock_bh(&hw->phy_lock);
baef58b1 2939 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2940 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2941 dev->dev_addr, ETH_ALEN);
c2681dd8 2942 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2943 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2944
2945 if (hw->chip_id == CHIP_ID_GENESIS)
2946 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2947 else {
2948 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2949 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2950 }
2951 spin_unlock_bh(&hw->phy_lock);
2952
2953 return 0;
baef58b1
SH		 2954}
2955
2956static const struct {
2957 u8 id;
2958 const char *name;
2959} skge_chips[] = {
2960 { CHIP_ID_GENESIS, "Genesis" },
2961 { CHIP_ID_YUKON, "Yukon" },
2962 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2963 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2964};
2965
2966static const char *skge_board_name(const struct skge_hw *hw)
2967{
2968 int i;
2969 static char buf[16];
2970
2971 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2972 if (skge_chips[i].id == hw->chip_id)
2973 return skge_chips[i].name;
2974
2975 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2976 return buf;
2977}
2978
2979
2980/*
2981 * Setup the board data structure, but don't bring up
2982 * the port(s)
2983 */
2984static int skge_reset(struct skge_hw *hw)
2985{
adba9e23 2986 u32 reg;
baef58b1 2987 u16 ctst;
5e1705dd 2988 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 2989 int i;
baef58b1
SH		 2990
2991 ctst = skge_read16(hw, B0_CTST);
2992
2993 /* do a SW reset */
2994 skge_write8(hw, B0_CTST, CS_RST_SET);
2995 skge_write8(hw, B0_CTST, CS_RST_CLR);
2996
2997 /* clear PCI errors, if any */
2998 skge_pci_clear(hw);
2999
3000 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3001
3002 /* restore CLK_RUN bits (for Yukon-Lite) */
3003 skge_write16(hw, B0_CTST,
3004 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3005
3006 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 3007 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3008 pmd_type = skge_read8(hw, B2_PMD_TYP);
3009 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3010
95566065 3011 switch (hw->chip_id) {
baef58b1 3012 case CHIP_ID_GENESIS:
5e1705dd 3013 switch (phy_type) {
baef58b1
SH		 3014 case SK_PHY_BCOM:
3015 hw->phy_addr = PHY_ADDR_BCOM;
3016 break;
3017 default:
3018 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3019 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3020 return -EOPNOTSUPP;
3021 }
3022 break;
3023
3024 case CHIP_ID_YUKON:
3025 case CHIP_ID_YUKON_LITE:
3026 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3027 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3028 hw->copper = 1;
baef58b1
SH		 3029
3030 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3031 break;
3032
3033 default:
3034 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3035 pci_name(hw->pdev), hw->chip_id);
3036 return -EOPNOTSUPP;
3037 }
3038
981d0377
SH		 3039 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3040 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3041 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3042
3043 /* read the adapters RAM size */
3044 t8 = skge_read8(hw, B2_E_0);
3045 if (hw->chip_id == CHIP_ID_GENESIS) {
3046 if (t8 == 3) {
3047 /* special case: 4 x 64k x 36, offset = 0x80000 */
3048 hw->ram_size = 0x100000;
3049 hw->ram_offset = 0x80000;
3050 } else
3051 hw->ram_size = t8 * 512;
3052 }
3053 else if (t8 == 0)
3054 hw->ram_size = 0x20000;
3055 else
3056 hw->ram_size = t8 * 4096;
3057
050ec18a 3058 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3059 if (hw->chip_id == CHIP_ID_GENESIS)
3060 genesis_init(hw);
3061 else {
3062 /* switch power to VCC (WA for VAUX problem) */
3063 skge_write8(hw, B0_POWER_CTRL,
3064 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3065
050ec18a
SH		 3066 /* avoid boards with stuck Hardware error bits */
3067 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3068 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3069 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3070 hw->intr_mask &= ~IS_HW_ERR;
3071 }
3072
adba9e23
SH		 3073 /* Clear PHY COMA */
3074 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3075 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3076 reg &= ~PCI_PHY_COMA;
3077 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3078 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3079
3080
981d0377 3081 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3082 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3083 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3084 }
3085 }
3086
3087 /* turn off hardware timer (unused) */
3088 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3089 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3090 skge_write8(hw, B0_LED, LED_STAT_ON);
3091
3092 /* enable the Tx Arbiters */
981d0377 3093 for (i = 0; i < hw->ports; i++)
6b0c1480 3094 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3095
3096 /* Initialize ram interface */
3097 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3098
3099 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3100 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3101 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3102 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3103 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3104 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3105 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3106 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3107 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3108 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3109 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3110 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3111
3112 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3113
3114 /* Set interrupt moderation for Transmit only
3115 * Receive interrupts avoided by NAPI
3116 */
3117 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3118 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3119 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3120
baef58b1
SH		 3121 skge_write32(hw, B0_IMSK, hw->intr_mask);
3122
baef58b1 3123 spin_lock_bh(&hw->phy_lock);
981d0377 3124 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3125 if (hw->chip_id == CHIP_ID_GENESIS)
3126 genesis_reset(hw, i);
3127 else
3128 yukon_reset(hw, i);
3129 }
3130 spin_unlock_bh(&hw->phy_lock);
3131
3132 return 0;
3133}
3134
3135/* Initialize network device */
981d0377
SH		 3136static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3137 int highmem)
baef58b1
SH		 3138{
3139 struct skge_port *skge;
3140 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3141
3142 if (!dev) {
3143 printk(KERN_ERR "skge etherdev alloc failed");
3144 return NULL;
3145 }
3146
3147 SET_MODULE_OWNER(dev);
3148 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3149 dev->open = skge_up;
3150 dev->stop = skge_down;
2cd8e5d3 3151 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3152 dev->hard_start_xmit = skge_xmit_frame;
3153 dev->get_stats = skge_get_stats;
3154 if (hw->chip_id == CHIP_ID_GENESIS)
3155 dev->set_multicast_list = genesis_set_multicast;
3156 else
3157 dev->set_multicast_list = yukon_set_multicast;
3158
3159 dev->set_mac_address = skge_set_mac_address;
3160 dev->change_mtu = skge_change_mtu;
3161 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3162 dev->tx_timeout = skge_tx_timeout;
3163 dev->watchdog_timeo = TX_WATCHDOG;
3164 dev->poll = skge_poll;
3165 dev->weight = NAPI_WEIGHT;
3166#ifdef CONFIG_NET_POLL_CONTROLLER
3167 dev->poll_controller = skge_netpoll;
3168#endif
3169 dev->irq = hw->pdev->irq;
3170 dev->features = NETIF_F_LLTX;
981d0377
SH		 3171 if (highmem)
3172 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3173
3174 skge = netdev_priv(dev);
3175 skge->netdev = dev;
3176 skge->hw = hw;
3177 skge->msg_enable = netif_msg_init(debug, default_msg);
3178 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3179 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3180
3181 /* Auto speed and flow control */
3182 skge->autoneg = AUTONEG_ENABLE;
3183 skge->flow_control = FLOW_MODE_SYMMETRIC;
3184 skge->duplex = -1;
3185 skge->speed = -1;
31b619c5 3186 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3187
3188 hw->dev[port] = dev;
3189
3190 skge->port = port;
3191
3192 spin_lock_init(&skge->tx_lock);
3193
baef58b1
SH		 3194 if (hw->chip_id != CHIP_ID_GENESIS) {
3195 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3196 skge->rx_csum = 1;
3197 }
3198
3199 /* read the mac address */
3200 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3201 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3202
3203 /* device is off until link detection */
3204 netif_carrier_off(dev);
3205 netif_stop_queue(dev);
3206
3207 return dev;
3208}
3209
3210static void __devinit skge_show_addr(struct net_device *dev)
3211{
3212 const struct skge_port *skge = netdev_priv(dev);
3213
3214 if (netif_msg_probe(skge))
3215 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3216 dev->name,
3217 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3218 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3219}
3220
3221static int __devinit skge_probe(struct pci_dev *pdev,
3222 const struct pci_device_id *ent)
3223{
3224 struct net_device *dev, *dev1;
3225 struct skge_hw *hw;
3226 int err, using_dac = 0;
3227
3228 if ((err = pci_enable_device(pdev))) {
3229 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3230 pci_name(pdev));
3231 goto err_out;
3232 }
3233
3234 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3235 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3236 pci_name(pdev));
3237 goto err_out_disable_pdev;
3238 }
3239
3240 pci_set_master(pdev);
3241
3242 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3243 using_dac = 1;
3244 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3245 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3246 pci_name(pdev));
3247 goto err_out_free_regions;
3248 }
3249
3250#ifdef __BIG_ENDIAN
8f3f8193 3251 /* byte swap descriptors in hardware */
baef58b1
SH		 3252 {
3253 u32 reg;
3254
3255 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3256 reg |= PCI_REV_DESC;
3257 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3258 }
3259#endif
3260
3261 err = -ENOMEM;
7e863061 3262 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3263 if (!hw) {
3264 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3265 pci_name(pdev));
3266 goto err_out_free_regions;
3267 }
3268
baef58b1
SH		 3269 hw->pdev = pdev;
3270 spin_lock_init(&hw->phy_lock);
3271 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3272
3273 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3274 if (!hw->regs) {
3275 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3276 pci_name(pdev));
3277 goto err_out_free_hw;
3278 }
3279
3280 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3281 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3282 pci_name(pdev), pdev->irq);
3283 goto err_out_iounmap;
3284 }
3285 pci_set_drvdata(pdev, hw);
3286
3287 err = skge_reset(hw);
3288 if (err)
3289 goto err_out_free_irq;
3290
d7eaee08 3291 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3292 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3293 skge_board_name(hw), hw->chip_rev);
baef58b1 3294
981d0377 3295 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3296 goto err_out_led_off;
3297
baef58b1
SH		 3298 if ((err = register_netdev(dev))) {
3299 printk(KERN_ERR PFX "%s: cannot register net device\n",
3300 pci_name(pdev));
3301 goto err_out_free_netdev;
3302 }
3303
3304 skge_show_addr(dev);
3305
981d0377 3306 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3307 if (register_netdev(dev1) == 0)
3308 skge_show_addr(dev1);
3309 else {
3310 /* Failure to register second port need not be fatal */
3311 printk(KERN_WARNING PFX "register of second port failed\n");
3312 hw->dev[1] = NULL;
3313 free_netdev(dev1);
3314 }
3315 }
3316
3317 return 0;
3318
3319err_out_free_netdev:
3320 free_netdev(dev);
3321err_out_led_off:
3322 skge_write16(hw, B0_LED, LED_STAT_OFF);
3323err_out_free_irq:
3324 free_irq(pdev->irq, hw);
3325err_out_iounmap:
3326 iounmap(hw->regs);
3327err_out_free_hw:
3328 kfree(hw);
3329err_out_free_regions:
3330 pci_release_regions(pdev);
3331err_out_disable_pdev:
3332 pci_disable_device(pdev);
3333 pci_set_drvdata(pdev, NULL);
3334err_out:
3335 return err;
3336}
3337
3338static void __devexit skge_remove(struct pci_dev *pdev)
3339{
3340 struct skge_hw *hw = pci_get_drvdata(pdev);
3341 struct net_device *dev0, *dev1;
3342
95566065 3343 if (!hw)
baef58b1
SH		 3344 return;
3345
3346 if ((dev1 = hw->dev[1]))
3347 unregister_netdev(dev1);
3348 dev0 = hw->dev[0];
3349 unregister_netdev(dev0);
3350
46a60f2d
SH		 3351 skge_write32(hw, B0_IMSK, 0);
3352 skge_write16(hw, B0_LED, LED_STAT_OFF);
3353 skge_pci_clear(hw);
3354 skge_write8(hw, B0_CTST, CS_RST_SET);
3355
baef58b1
SH		 3356 tasklet_kill(&hw->ext_tasklet);
3357
3358 free_irq(pdev->irq, hw);
3359 pci_release_regions(pdev);
3360 pci_disable_device(pdev);
3361 if (dev1)
3362 free_netdev(dev1);
3363 free_netdev(dev0);
46a60f2d 3364
baef58b1
SH		 3365 iounmap(hw->regs);
3366 kfree(hw);
3367 pci_set_drvdata(pdev, NULL);
3368}
3369
3370#ifdef CONFIG_PM
2a569579 3371static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3372{
3373 struct skge_hw *hw = pci_get_drvdata(pdev);
3374 int i, wol = 0;
3375
95566065 3376 for (i = 0; i < 2; i++) {
baef58b1
SH		 3377 struct net_device *dev = hw->dev[i];
3378
3379 if (dev) {
3380 struct skge_port *skge = netdev_priv(dev);
3381 if (netif_running(dev)) {
3382 netif_carrier_off(dev);
46a60f2d
SH		 3383 if (skge->wol)
3384 netif_stop_queue(dev);
3385 else
3386 skge_down(dev);
baef58b1
SH		 3387 }
3388 netif_device_detach(dev);
3389 wol |= skge->wol;
3390 }
3391 }
3392
3393 pci_save_state(pdev);
2a569579 3394 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3395 pci_disable_device(pdev);
3396 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3397
3398 return 0;
3399}
3400
3401static int skge_resume(struct pci_dev *pdev)
3402{
3403 struct skge_hw *hw = pci_get_drvdata(pdev);
3404 int i;
3405
3406 pci_set_power_state(pdev, PCI_D0);
3407 pci_restore_state(pdev);
3408 pci_enable_wake(pdev, PCI_D0, 0);
3409
3410 skge_reset(hw);
3411
95566065 3412 for (i = 0; i < 2; i++) {
baef58b1
SH		 3413 struct net_device *dev = hw->dev[i];
3414 if (dev) {
3415 netif_device_attach(dev);
95566065 3416 if (netif_running(dev))
baef58b1
SH		 3417 skge_up(dev);
3418 }
3419 }
3420 return 0;
3421}
3422#endif
3423
3424static struct pci_driver skge_driver = {
3425 .name = DRV_NAME,
3426 .id_table = skge_id_table,
3427 .probe = skge_probe,
3428 .remove = __devexit_p(skge_remove),
3429#ifdef CONFIG_PM
3430 .suspend = skge_suspend,
3431 .resume = skge_resume,
3432#endif
3433};
3434
3435static int __init skge_init_module(void)
3436{
3437 return pci_module_init(&skge_driver);
3438}
3439
3440static void __exit skge_cleanup_module(void)
3441{
3442 pci_unregister_driver(&skge_driver);
3443}
3444
3445module_init(skge_init_module);
3446module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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