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[PATCH] skge: use pci_read_config_word
[deliverable/linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6"
46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
52#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4)
57#define LINK_POLL_HZ (HZ/10)
58
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(DRV_VERSION);
63
64static const u32 default_msg
65 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
66 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
67
68static int debug = -1; /* defaults above */
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
75 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 84 { 0 }
85};
86MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port);
96static void yukon_reset(struct skge_hw *hw, int port);
97static void genesis_mac_init(struct skge_hw *hw, int port);
98static void genesis_reset(struct skge_hw *hw, int port);
99
100static const int txqaddr[] = { Q_XA1, Q_XA2 };
101static const int rxqaddr[] = { Q_R1, Q_R2 };
102static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
103static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
104
105/* Don't need to look at whole 16K.
106 * last interesting register is descriptor poll timer.
107 */
108#define SKGE_REGS_LEN (29*128)
109
110static int skge_get_regs_len(struct net_device *dev)
111{
112 return SKGE_REGS_LEN;
113}
114
115/*
116 * Returns copy of control register region
117 * I/O region is divided into banks and certain regions are unreadable
118 */
119static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121{
122 const struct skge_port *skge = netdev_priv(dev);
123 unsigned long offs;
124 const void __iomem *io = skge->hw->regs;
125 static const unsigned long bankmap
126 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
127 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
128 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
129 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
130
131 regs->version = 1;
132 for (offs = 0; offs < regs->len; offs += 128) {
133 u32 len = min_t(u32, 128, regs->len - offs);
134
135 if (bankmap & (1<<(offs/128)))
136 memcpy_fromio(p + offs, io + offs, len);
137 else
138 memset(p + offs, 0, len);
139 }
140}
141
142/* Wake on Lan only supported on Yukon chps with rev 1 or above */
143static int wol_supported(const struct skge_hw *hw)
144{
145 return !((hw->chip_id == CHIP_ID_GENESIS ||
146 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)));
147}
148
149static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152
153 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
154 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
155}
156
157static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
158{
159 struct skge_port *skge = netdev_priv(dev);
160 struct skge_hw *hw = skge->hw;
161
95566065 162 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 163 return -EOPNOTSUPP;
164
165 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
166 return -EOPNOTSUPP;
167
168 skge->wol = wol->wolopts == WAKE_MAGIC;
169
170 if (skge->wol) {
171 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
172
173 skge_write16(hw, WOL_CTRL_STAT,
174 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
175 WOL_CTL_ENA_MAGIC_PKT_UNIT);
176 } else
177 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
178
179 return 0;
180}
181
182
183static int skge_get_settings(struct net_device *dev,
184 struct ethtool_cmd *ecmd)
185{
186 struct skge_port *skge = netdev_priv(dev);
187 struct skge_hw *hw = skge->hw;
188
189 ecmd->transceiver = XCVR_INTERNAL;
190
191 if (iscopper(hw)) {
192 if (hw->chip_id == CHIP_ID_GENESIS)
193 ecmd->supported = SUPPORTED_1000baseT_Full
194 | SUPPORTED_1000baseT_Half
195 | SUPPORTED_Autoneg | SUPPORTED_TP;
196 else {
197 ecmd->supported = SUPPORTED_10baseT_Half
198 | SUPPORTED_10baseT_Full
199 | SUPPORTED_100baseT_Half
200 | SUPPORTED_100baseT_Full
201 | SUPPORTED_1000baseT_Half
202 | SUPPORTED_1000baseT_Full
203 | SUPPORTED_Autoneg| SUPPORTED_TP;
204
205 if (hw->chip_id == CHIP_ID_YUKON)
206 ecmd->supported &= ~SUPPORTED_1000baseT_Half;
207
208 else if (hw->chip_id == CHIP_ID_YUKON_FE)
209 ecmd->supported &= ~(SUPPORTED_1000baseT_Half
210 | SUPPORTED_1000baseT_Full);
211 }
212
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
215 } else {
216 ecmd->supported = SUPPORTED_1000baseT_Full
217 | SUPPORTED_FIBRE
218 | SUPPORTED_Autoneg;
219
220 ecmd->port = PORT_FIBRE;
221 }
222
223 ecmd->advertising = skge->advertising;
224 ecmd->autoneg = skge->autoneg;
225 ecmd->speed = skge->speed;
226 ecmd->duplex = skge->duplex;
227 return 0;
228}
229
230static u32 skge_modes(const struct skge_hw *hw)
231{
232 u32 modes = ADVERTISED_Autoneg
233 | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
234 | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
235 | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
236
237 if (iscopper(hw)) {
238 modes |= ADVERTISED_TP;
95566065 239 switch (hw->chip_id) {
baef58b1
SH		 240 case CHIP_ID_GENESIS:
241 modes &= ~(ADVERTISED_100baseT_Full
242 | ADVERTISED_100baseT_Half
243 | ADVERTISED_10baseT_Full
244 | ADVERTISED_10baseT_Half);
245 break;
246
247 case CHIP_ID_YUKON:
248 modes &= ~ADVERTISED_1000baseT_Half;
249 break;
250
251 case CHIP_ID_YUKON_FE:
252 modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
253 break;
254 }
255 } else {
256 modes |= ADVERTISED_FIBRE;
257 modes &= ~ADVERTISED_1000baseT_Half;
258 }
259 return modes;
260}
261
262static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
263{
264 struct skge_port *skge = netdev_priv(dev);
265 const struct skge_hw *hw = skge->hw;
266
267 if (ecmd->autoneg == AUTONEG_ENABLE) {
268 if (ecmd->advertising & skge_modes(hw))
269 return -EINVAL;
270 } else {
95566065 271 switch (ecmd->speed) {
baef58b1
SH		 272 case SPEED_1000:
273 if (hw->chip_id == CHIP_ID_YUKON_FE)
274 return -EINVAL;
275 break;
276 case SPEED_100:
277 case SPEED_10:
278 if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS)
279 return -EINVAL;
280 break;
281 default:
282 return -EINVAL;
283 }
284 }
285
286 skge->autoneg = ecmd->autoneg;
287 skge->speed = ecmd->speed;
288 skge->duplex = ecmd->duplex;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296}
297
298static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300{
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307}
308
309static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313} skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338};
339
340static int skge_get_stats_count(struct net_device *dev)
341{
342 return ARRAY_SIZE(skge_stats);
343}
344
345static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347{
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354}
355
356/* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360static struct net_device_stats *skge_get_stats(struct net_device *dev)
361{
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379}
380
381static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382{
383 int i;
384
95566065 385 switch (stringset) {
baef58b1
SH		 386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392}
393
394static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396{
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408}
409
410static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412{
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428}
429
430static u32 skge_get_msglevel(struct net_device *netdev)
431{
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434}
435
436static void skge_set_msglevel(struct net_device *netdev, u32 value)
437{
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440}
441
442static int skge_nway_reset(struct net_device *dev)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461}
462
463static int skge_set_sg(struct net_device *dev, u32 data)
464{
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471}
472
473static int skge_set_tx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482}
483
484static u32 skge_get_rx_csum(struct net_device *dev)
485{
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489}
490
491/* Only Yukon supports checksum offload. */
492static int skge_set_rx_csum(struct net_device *dev, u32 data)
493{
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501}
502
503/* Only Yukon II supports TSO (not implemented yet) */
504static int skge_set_tso(struct net_device *dev, u32 data)
505{
506 if (data)
507 return -EOPNOTSUPP;
508 return 0;
509}
510
511static void skge_get_pauseparam(struct net_device *dev,
512 struct ethtool_pauseparam *ecmd)
513{
514 struct skge_port *skge = netdev_priv(dev);
515
516 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
517 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
518 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
519 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
520
521 ecmd->autoneg = skge->autoneg;
522}
523
524static int skge_set_pauseparam(struct net_device *dev,
525 struct ethtool_pauseparam *ecmd)
526{
527 struct skge_port *skge = netdev_priv(dev);
528
529 skge->autoneg = ecmd->autoneg;
530 if (ecmd->rx_pause && ecmd->tx_pause)
531 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 532 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 533 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 534 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 535 skge->flow_control = FLOW_MODE_LOC_SEND;
536 else
537 skge->flow_control = FLOW_MODE_NONE;
538
539 if (netif_running(dev)) {
540 skge_down(dev);
541 skge_up(dev);
542 }
543 return 0;
544}
545
546/* Chip internal frequency for clock calculations */
547static inline u32 hwkhz(const struct skge_hw *hw)
548{
549 if (hw->chip_id == CHIP_ID_GENESIS)
550 return 53215; /* or: 53.125 MHz */
551 else if (hw->chip_id == CHIP_ID_YUKON_EC)
552 return 125000; /* or: 125.000 MHz */
553 else
554 return 78215; /* or: 78.125 MHz */
555}
556
557/* Chip hz to microseconds */
558static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
559{
560 return (ticks * 1000) / hwkhz(hw);
561}
562
563/* Microseconds to chip hz */
564static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
565{
566 return hwkhz(hw) * usec / 1000;
567}
568
569static int skge_get_coalesce(struct net_device *dev,
570 struct ethtool_coalesce *ecmd)
571{
572 struct skge_port *skge = netdev_priv(dev);
573 struct skge_hw *hw = skge->hw;
574 int port = skge->port;
575
576 ecmd->rx_coalesce_usecs = 0;
577 ecmd->tx_coalesce_usecs = 0;
578
579 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
580 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
581 u32 msk = skge_read32(hw, B2_IRQM_MSK);
582
583 if (msk & rxirqmask[port])
584 ecmd->rx_coalesce_usecs = delay;
585 if (msk & txirqmask[port])
586 ecmd->tx_coalesce_usecs = delay;
587 }
588
589 return 0;
590}
591
592/* Note: interrupt timer is per board, but can turn on/off per port */
593static int skge_set_coalesce(struct net_device *dev,
594 struct ethtool_coalesce *ecmd)
595{
596 struct skge_port *skge = netdev_priv(dev);
597 struct skge_hw *hw = skge->hw;
598 int port = skge->port;
599 u32 msk = skge_read32(hw, B2_IRQM_MSK);
600 u32 delay = 25;
601
602 if (ecmd->rx_coalesce_usecs == 0)
603 msk &= ~rxirqmask[port];
604 else if (ecmd->rx_coalesce_usecs < 25 ||
605 ecmd->rx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= rxirqmask[port];
609 delay = ecmd->rx_coalesce_usecs;
610 }
611
612 if (ecmd->tx_coalesce_usecs == 0)
613 msk &= ~txirqmask[port];
614 else if (ecmd->tx_coalesce_usecs < 25 ||
615 ecmd->tx_coalesce_usecs > 33333)
616 return -EINVAL;
617 else {
618 msk |= txirqmask[port];
619 delay = min(delay, ecmd->rx_coalesce_usecs);
620 }
621
622 skge_write32(hw, B2_IRQM_MSK, msk);
623 if (msk == 0)
624 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
625 else {
626 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
627 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
628 }
629 return 0;
630}
631
632static void skge_led_on(struct skge_hw *hw, int port)
633{
634 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 635 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 636 skge_write8(hw, B0_LED, LED_STAT_ON);
637
6b0c1480
SH		 638 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
639 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
640 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1
SH		 641
642 switch (hw->phy_type) {
643 case SK_PHY_BCOM:
6b0c1480 644 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
baef58b1
SH		 645 PHY_B_PEC_LED_ON);
646 break;
647 case SK_PHY_LONE:
6b0c1480 648 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
baef58b1
SH		 649 0x0800);
650 break;
651 default:
6b0c1480
SH		 652 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
653 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
654 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 655 }
656 } else {
6b0c1480
SH		 657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 659 PHY_M_LED_MO_DUP(MO_LED_ON) |
660 PHY_M_LED_MO_10(MO_LED_ON) |
661 PHY_M_LED_MO_100(MO_LED_ON) |
662 PHY_M_LED_MO_1000(MO_LED_ON) |
663 PHY_M_LED_MO_RX(MO_LED_ON));
664 }
665}
666
667static void skge_led_off(struct skge_hw *hw, int port)
668{
669 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 670 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 671 skge_write8(hw, B0_LED, LED_STAT_OFF);
672
6b0c1480
SH		 673 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
674 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1
SH		 675
676 switch (hw->phy_type) {
677 case SK_PHY_BCOM:
6b0c1480 678 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
baef58b1
SH		 679 PHY_B_PEC_LED_OFF);
680 break;
681 case SK_PHY_LONE:
6b0c1480 682 xm_phy_write(hw, port, PHY_LONE_LED_CFG,
baef58b1
SH		 683 PHY_L_LC_LEDT);
684 break;
685 default:
6b0c1480
SH		 686 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
687 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
baef58b1
SH		 688 }
689 } else {
6b0c1480
SH		 690 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
691 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 692 PHY_M_LED_MO_DUP(MO_LED_OFF) |
693 PHY_M_LED_MO_10(MO_LED_OFF) |
694 PHY_M_LED_MO_100(MO_LED_OFF) |
695 PHY_M_LED_MO_1000(MO_LED_OFF) |
696 PHY_M_LED_MO_RX(MO_LED_OFF));
697 }
698}
699
700static void skge_blink_timer(unsigned long data)
701{
702 struct skge_port *skge = (struct skge_port *) data;
703 struct skge_hw *hw = skge->hw;
704 unsigned long flags;
705
706 spin_lock_irqsave(&hw->phy_lock, flags);
707 if (skge->blink_on)
708 skge_led_on(hw, skge->port);
709 else
710 skge_led_off(hw, skge->port);
711 spin_unlock_irqrestore(&hw->phy_lock, flags);
712
713 skge->blink_on = !skge->blink_on;
714 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
715}
716
717/* blink LED's for finding board */
718static int skge_phys_id(struct net_device *dev, u32 data)
719{
720 struct skge_port *skge = netdev_priv(dev);
721
95566065 722 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 723 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
724
725 /* start blinking */
726 skge->blink_on = 1;
727 mod_timer(&skge->led_blink, jiffies+1);
728
729 msleep_interruptible(data * 1000);
730 del_timer_sync(&skge->led_blink);
731
732 skge_led_off(skge->hw, skge->port);
733
734 return 0;
735}
736
737static struct ethtool_ops skge_ethtool_ops = {
738 .get_settings = skge_get_settings,
739 .set_settings = skge_set_settings,
740 .get_drvinfo = skge_get_drvinfo,
741 .get_regs_len = skge_get_regs_len,
742 .get_regs = skge_get_regs,
743 .get_wol = skge_get_wol,
744 .set_wol = skge_set_wol,
745 .get_msglevel = skge_get_msglevel,
746 .set_msglevel = skge_set_msglevel,
747 .nway_reset = skge_nway_reset,
748 .get_link = ethtool_op_get_link,
749 .get_ringparam = skge_get_ring_param,
750 .set_ringparam = skge_set_ring_param,
751 .get_pauseparam = skge_get_pauseparam,
752 .set_pauseparam = skge_set_pauseparam,
753 .get_coalesce = skge_get_coalesce,
754 .set_coalesce = skge_set_coalesce,
755 .get_tso = ethtool_op_get_tso,
756 .set_tso = skge_set_tso,
757 .get_sg = ethtool_op_get_sg,
758 .set_sg = skge_set_sg,
759 .get_tx_csum = ethtool_op_get_tx_csum,
760 .set_tx_csum = skge_set_tx_csum,
761 .get_rx_csum = skge_get_rx_csum,
762 .set_rx_csum = skge_set_rx_csum,
763 .get_strings = skge_get_strings,
764 .phys_id = skge_phys_id,
765 .get_stats_count = skge_get_stats_count,
766 .get_ethtool_stats = skge_get_ethtool_stats,
767};
768
769/*
770 * Allocate ring elements and chain them together
771 * One-to-one association of board descriptors with ring elements
772 */
773static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
774{
775 struct skge_tx_desc *d;
776 struct skge_element *e;
777 int i;
778
779 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
780 if (!ring->start)
781 return -ENOMEM;
782
783 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
784 e->desc = d;
785 if (i == ring->count - 1) {
786 e->next = ring->start;
787 d->next_offset = base;
788 } else {
789 e->next = e + 1;
790 d->next_offset = base + (i+1) * sizeof(*d);
791 }
792 }
793 ring->to_use = ring->to_clean = ring->start;
794
795 return 0;
796}
797
798/* Setup buffer for receiving */
799static inline int skge_rx_alloc(struct skge_port *skge,
800 struct skge_element *e)
801{
802 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
803 struct skge_rx_desc *rd = e->desc;
804 struct sk_buff *skb;
805 u64 map;
806
807 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
808 if (unlikely(!skb)) {
809 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
810 skge->netdev->name);
811 return -ENOMEM;
812 }
813
814 skb->dev = skge->netdev;
815 skb_reserve(skb, NET_IP_ALIGN);
816
817 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
818 PCI_DMA_FROMDEVICE);
819
820 rd->dma_lo = map;
821 rd->dma_hi = map >> 32;
822 e->skb = skb;
823 rd->csum1_start = ETH_HLEN;
824 rd->csum2_start = ETH_HLEN;
825 rd->csum1 = 0;
826 rd->csum2 = 0;
827
828 wmb();
829
830 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
831 pci_unmap_addr_set(e, mapaddr, map);
832 pci_unmap_len_set(e, maplen, bufsize);
833 return 0;
834}
835
836/* Free all unused buffers in receive ring, assumes receiver stopped */
837static void skge_rx_clean(struct skge_port *skge)
838{
839 struct skge_hw *hw = skge->hw;
840 struct skge_ring *ring = &skge->rx_ring;
841 struct skge_element *e;
842
843 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
844 struct skge_rx_desc *rd = e->desc;
845 rd->control = 0;
846
847 pci_unmap_single(hw->pdev,
848 pci_unmap_addr(e, mapaddr),
849 pci_unmap_len(e, maplen),
850 PCI_DMA_FROMDEVICE);
851 dev_kfree_skb(e->skb);
852 e->skb = NULL;
853 }
854 ring->to_clean = e;
855}
856
857/* Allocate buffers for receive ring
858 * For receive: to_use is refill location
859 * to_clean is next received frame.
860 *
861 * if (to_use == to_clean)
862 * then ring all frames in ring need buffers
863 * if (to_use->next == to_clean)
864 * then ring all frames in ring have buffers
865 */
866static int skge_rx_fill(struct skge_port *skge)
867{
868 struct skge_ring *ring = &skge->rx_ring;
869 struct skge_element *e;
870 int ret = 0;
871
872 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
873 if (skge_rx_alloc(skge, e)) {
874 ret = 1;
875 break;
876 }
877
878 }
879 ring->to_use = e;
880
881 return ret;
882}
883
884static void skge_link_up(struct skge_port *skge)
885{
886 netif_carrier_on(skge->netdev);
887 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
888 netif_wake_queue(skge->netdev);
889
890 if (netif_msg_link(skge))
891 printk(KERN_INFO PFX
892 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
893 skge->netdev->name, skge->speed,
894 skge->duplex == DUPLEX_FULL ? "full" : "half",
895 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
896 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
897 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
898 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
899 "unknown");
900}
901
902static void skge_link_down(struct skge_port *skge)
903{
904 netif_carrier_off(skge->netdev);
905 netif_stop_queue(skge->netdev);
906
907 if (netif_msg_link(skge))
908 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
909}
910
6b0c1480 911static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 912{
913 int i;
914 u16 v;
915
6b0c1480
SH		 916 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
917 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1
SH		 918 if (hw->phy_type != SK_PHY_XMAC) {
919 for (i = 0; i < PHY_RETRIES; i++) {
920 udelay(1);
6b0c1480 921 if (xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 922 & XM_MMU_PHY_RDY)
923 goto ready;
924 }
925
926 printk(KERN_WARNING PFX "%s: phy read timed out\n",
927 hw->dev[port]->name);
928 return 0;
929 ready:
6b0c1480 930 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1
SH		 931 }
932
933 return v;
934}
935
6b0c1480 936static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 937{
938 int i;
939
6b0c1480 940 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 941 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 942 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 943 goto ready;
944 cpu_relax();
945 }
946 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
947 hw->dev[port]->name);
948
949
950 ready:
6b0c1480 951 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 952 for (i = 0; i < PHY_RETRIES; i++) {
953 udelay(1);
6b0c1480 954 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 955 return;
956 }
957 printk(KERN_WARNING PFX "%s: phy write timed out\n",
958 hw->dev[port]->name);
959}
960
961static void genesis_init(struct skge_hw *hw)
962{
963 /* set blink source counter */
964 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
965 skge_write8(hw, B2_BSC_CTRL, BSC_START);
966
967 /* configure mac arbiter */
968 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
969
970 /* configure mac arbiter timeout values */
971 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
972 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
973 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
974 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
975
976 skge_write8(hw, B3_MA_RCINI_RX1, 0);
977 skge_write8(hw, B3_MA_RCINI_RX2, 0);
978 skge_write8(hw, B3_MA_RCINI_TX1, 0);
979 skge_write8(hw, B3_MA_RCINI_TX2, 0);
980
981 /* configure packet arbiter timeout */
982 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
983 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
984 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
985 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
986 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
987}
988
989static void genesis_reset(struct skge_hw *hw, int port)
990{
991 int i;
992 u64 zero = 0;
993
994 /* reset the statistics module */
6b0c1480
SH		 995 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
996 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
997 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
998 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
999 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1
SH		 1000
1001 /* disable all PHY IRQs */
1002 if (hw->phy_type == SK_PHY_BCOM)
6b0c1480 1003 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1004
6b0c1480 1005 xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
baef58b1 1006 for (i = 0; i < 15; i++)
6b0c1480
SH		 1007 xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
1008 xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
baef58b1
SH		 1009}
1010
1011
1012static void genesis_mac_init(struct skge_hw *hw, int port)
1013{
1014 struct skge_port *skge = netdev_priv(hw->dev[port]);
1015 int i;
1016 u32 r;
1017 u16 id1;
1018 u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
1019
1020 /* magic workaround patterns for Broadcom */
1021 static const struct {
1022 u16 reg;
1023 u16 val;
1024 } A1hack[] = {
1025 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1026 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1027 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1028 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1029 }, C0hack[] = {
1030 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1031 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1032 };
1033
1034
1035 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1036 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1037 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1038
6b0c1480
SH		 1039 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1040 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1041
1042 /* Unreset the XMAC. */
6b0c1480 1043 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1044
1045 /*
1046 * Perform additional initialization for external PHYs,
1047 * namely for the 1000baseTX cards that use the XMAC's
1048 * GMII mode.
1049 */
1050 spin_lock_bh(&hw->phy_lock);
1051 if (hw->phy_type != SK_PHY_XMAC) {
1052 /* Take PHY out of reset. */
1053 r = skge_read32(hw, B2_GP_IO);
1054 if (port == 0)
1055 r |= GP_DIR_0|GP_IO_0;
1056 else
1057 r |= GP_DIR_2|GP_IO_2;
1058
1059 skge_write32(hw, B2_GP_IO, r);
1060 skge_read32(hw, B2_GP_IO);
1061
1062 /* Enable GMII mode on the XMAC. */
6b0c1480 1063 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
baef58b1 1064
6b0c1480 1065 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
baef58b1
SH		 1066
1067 /* Optimize MDIO transfer by suppressing preamble. */
6b0c1480
SH		 1068 xm_write16(hw, port, XM_MMU_CMD,
1069 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1070 | XM_MMU_NO_PRE);
1071
1072 if (id1 == PHY_BCOM_ID1_C0) {
1073 /*
1074 * Workaround BCOM Errata for the C0 type.
1075 * Write magic patterns to reserved registers.
1076 */
1077 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
6b0c1480 1078 xm_phy_write(hw, port,
baef58b1
SH		 1079 C0hack[i].reg, C0hack[i].val);
1080
1081 } else if (id1 == PHY_BCOM_ID1_A1) {
1082 /*
1083 * Workaround BCOM Errata for the A1 type.
1084 * Write magic patterns to reserved registers.
1085 */
1086 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
6b0c1480 1087 xm_phy_write(hw, port,
baef58b1
SH		 1088 A1hack[i].reg, A1hack[i].val);
1089 }
1090
1091 /*
1092 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1093 * Disable Power Management after reset.
1094 */
6b0c1480
SH		 1095 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1096 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
baef58b1
SH		 1097 }
1098
1099 /* Dummy read */
6b0c1480 1100 xm_read16(hw, port, XM_ISRC);
baef58b1 1101
6b0c1480
SH		 1102 r = xm_read32(hw, port, XM_MODE);
1103 xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
baef58b1
SH		 1104
1105 /* We don't need the FCS appended to the packet. */
6b0c1480
SH		 1106 r = xm_read16(hw, port, XM_RX_CMD);
1107 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
baef58b1
SH		 1108
1109 /* We want short frames padded to 60 bytes. */
6b0c1480
SH		 1110 r = xm_read16(hw, port, XM_TX_CMD);
1111 xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
baef58b1
SH		 1112
1113 /*
1114 * Enable the reception of all error frames. This is is
1115 * a necessary evil due to the design of the XMAC. The
1116 * XMAC's receive FIFO is only 8K in size, however jumbo
1117 * frames can be up to 9000 bytes in length. When bad
1118 * frame filtering is enabled, the XMAC's RX FIFO operates
1119 * in 'store and forward' mode. For this to work, the
1120 * entire frame has to fit into the FIFO, but that means
1121 * that jumbo frames larger than 8192 bytes will be
1122 * truncated. Disabling all bad frame filtering causes
1123 * the RX FIFO to operate in streaming mode, in which
1124 * case the XMAC will start transfering frames out of the
1125 * RX FIFO as soon as the FIFO threshold is reached.
1126 */
6b0c1480
SH		 1127 r = xm_read32(hw, port, XM_MODE);
1128 xm_write32(hw, port, XM_MODE,
baef58b1
SH		 1129 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1130 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1131
6b0c1480
SH		 1132 xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1133 xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
baef58b1
SH		 1134
1135 /*
1136 * Bump up the transmit threshold. This helps hold off transmit
1137 * underruns when we're blasting traffic from both ports at once.
1138 */
6b0c1480 1139 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1140
1141 /* Configure MAC arbiter */
1142 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1143
1144 /* configure timeout values */
1145 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1146 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1147 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1148 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1149
1150 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1151 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1152 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1153 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1154
1155 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1156 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1157 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1158 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1159
1160 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1161 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1162 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1163 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1164
1165 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1166 /* Enable frame flushing if jumbo frames used */
6b0c1480 1167 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1168 } else {
1169 /* enable timeout timers if normal frames */
1170 skge_write16(hw, B3_PA_CTRL,
1171 port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1172 }
1173
1174
6b0c1480 1175 r = xm_read16(hw, port, XM_RX_CMD);
baef58b1 1176 if (hw->dev[port]->mtu > ETH_DATA_LEN)
6b0c1480 1177 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
baef58b1 1178 else
6b0c1480 1179 xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
baef58b1
SH		 1180
1181 switch (hw->phy_type) {
1182 case SK_PHY_XMAC:
1183 if (skge->autoneg == AUTONEG_ENABLE) {
1184 ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
1185
1186 switch (skge->flow_control) {
1187 case FLOW_MODE_NONE:
1188 ctrl1 |= PHY_X_P_NO_PAUSE;
1189 break;
1190 case FLOW_MODE_LOC_SEND:
1191 ctrl1 |= PHY_X_P_ASYM_MD;
1192 break;
1193 case FLOW_MODE_SYMMETRIC:
1194 ctrl1 |= PHY_X_P_SYM_MD;
1195 break;
1196 case FLOW_MODE_REM_SEND:
1197 ctrl1 |= PHY_X_P_BOTH_MD;
1198 break;
1199 }
1200
6b0c1480 1201 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
baef58b1
SH		 1202 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1203 } else {
1204 ctrl2 = 0;
1205 if (skge->duplex == DUPLEX_FULL)
1206 ctrl2 |= PHY_CT_DUP_MD;
1207 }
1208
6b0c1480 1209 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
baef58b1
SH		 1210 break;
1211
1212 case SK_PHY_BCOM:
1213 ctrl1 = PHY_CT_SP1000;
1214 ctrl2 = 0;
1215 ctrl3 = PHY_SEL_TYPE;
1216 ctrl4 = PHY_B_PEC_EN_LTR;
1217 ctrl5 = PHY_B_AC_TX_TST;
1218
1219 if (skge->autoneg == AUTONEG_ENABLE) {
1220 /*
1221 * Workaround BCOM Errata #1 for the C5 type.
1222 * 1000Base-T Link Acquisition Failure in Slave Mode
1223 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1224 */
1225 ctrl2 |= PHY_B_1000C_RD;
1226 if (skge->advertising & ADVERTISED_1000baseT_Half)
1227 ctrl2 |= PHY_B_1000C_AHD;
1228 if (skge->advertising & ADVERTISED_1000baseT_Full)
1229 ctrl2 |= PHY_B_1000C_AFD;
1230
1231 /* Set Flow-control capabilities */
1232 switch (skge->flow_control) {
1233 case FLOW_MODE_NONE:
1234 ctrl3 |= PHY_B_P_NO_PAUSE;
1235 break;
1236 case FLOW_MODE_LOC_SEND:
1237 ctrl3 |= PHY_B_P_ASYM_MD;
1238 break;
1239 case FLOW_MODE_SYMMETRIC:
1240 ctrl3 |= PHY_B_P_SYM_MD;
1241 break;
1242 case FLOW_MODE_REM_SEND:
1243 ctrl3 |= PHY_B_P_BOTH_MD;
1244 break;
1245 }
1246
1247 /* Restart Auto-negotiation */
1248 ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1249 } else {
1250 if (skge->duplex == DUPLEX_FULL)
1251 ctrl1 |= PHY_CT_DUP_MD;
1252
1253 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1254 }
1255
6b0c1480
SH		 1256 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1257 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
baef58b1
SH		 1258
1259 if (skge->netdev->mtu > ETH_DATA_LEN) {
1260 ctrl4 |= PHY_B_PEC_HIGH_LA;
1261 ctrl5 |= PHY_B_AC_LONG_PACK;
1262
6b0c1480 1263 xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
baef58b1
SH		 1264 }
1265
6b0c1480
SH		 1266 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1267 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
baef58b1
SH		 1268 break;
1269 }
1270 spin_unlock_bh(&hw->phy_lock);
1271
1272 /* Clear MIB counters */
6b0c1480 1273 xm_write16(hw, port, XM_STAT_CMD,
baef58b1
SH		 1274 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1275 /* Clear two times according to Errata #3 */
6b0c1480 1276 xm_write16(hw, port, XM_STAT_CMD,
baef58b1
SH		 1277 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1278
1279 /* Start polling for link status */
1280 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1281}
1282
1283static void genesis_stop(struct skge_port *skge)
1284{
1285 struct skge_hw *hw = skge->hw;
1286 int port = skge->port;
1287
1288 /* Clear Tx packet arbiter timeout IRQ */
1289 skge_write16(hw, B3_PA_CTRL,
1290 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1291
1292 /*
1293 * If the transfer stucks at the MAC the STOP command will not
1294 * terminate if we don't flush the XMAC's transmit FIFO !
1295 */
6b0c1480
SH		 1296 xm_write32(hw, port, XM_MODE,
1297 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1298
1299
1300 /* Reset the MAC */
6b0c1480 1301 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1302
1303 /* For external PHYs there must be special handling */
1304 if (hw->phy_type != SK_PHY_XMAC) {
1305 u32 reg = skge_read32(hw, B2_GP_IO);
1306
1307 if (port == 0) {
1308 reg |= GP_DIR_0;
1309 reg &= ~GP_IO_0;
1310 } else {
1311 reg |= GP_DIR_2;
1312 reg &= ~GP_IO_2;
1313 }
1314 skge_write32(hw, B2_GP_IO, reg);
1315 skge_read32(hw, B2_GP_IO);
1316 }
1317
6b0c1480
SH		 1318 xm_write16(hw, port, XM_MMU_CMD,
1319 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1320 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1321
6b0c1480 1322 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1323}
1324
1325
1326static void genesis_get_stats(struct skge_port *skge, u64 *data)
1327{
1328 struct skge_hw *hw = skge->hw;
1329 int port = skge->port;
1330 int i;
1331 unsigned long timeout = jiffies + HZ;
1332
6b0c1480 1333 xm_write16(hw, port,
baef58b1
SH		 1334 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1335
1336 /* wait for update to complete */
6b0c1480 1337 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1338 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1339 if (time_after(jiffies, timeout))
1340 break;
1341 udelay(10);
1342 }
1343
1344 /* special case for 64 bit octet counter */
6b0c1480
SH		 1345 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1346 | xm_read32(hw, port, XM_TXO_OK_LO);
1347 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1348 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1349
1350 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1351 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1352}
1353
1354static void genesis_mac_intr(struct skge_hw *hw, int port)
1355{
1356 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1357 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1358
1359 pr_debug("genesis_intr status %x\n", status);
1360 if (hw->phy_type == SK_PHY_XMAC) {
1361 /* LInk down, start polling for state change */
1362 if (status & XM_IS_INP_ASS) {
6b0c1480
SH		 1363 xm_write16(hw, port, XM_IMSK,
1364 xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
baef58b1
SH		 1365 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1366 }
1367 else if (status & XM_IS_AND)
1368 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1369 }
1370
1371 if (status & XM_IS_TXF_UR) {
6b0c1480 1372 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1373 ++skge->net_stats.tx_fifo_errors;
1374 }
1375 if (status & XM_IS_RXF_OV) {
6b0c1480 1376 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1377 ++skge->net_stats.rx_fifo_errors;
1378 }
1379}
1380
6b0c1480 1381static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1382{
1383 int i;
1384
6b0c1480
SH		 1385 gma_write16(hw, port, GM_SMI_DATA, val);
1386 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1387 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1388 for (i = 0; i < PHY_RETRIES; i++) {
1389 udelay(1);
1390
6b0c1480 1391 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1392 break;
1393 }
1394}
1395
6b0c1480 1396static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1397{
1398 int i;
1399
6b0c1480 1400 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1401 GM_SMI_CT_PHY_AD(hw->phy_addr)
1402 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1403
1404 for (i = 0; i < PHY_RETRIES; i++) {
1405 udelay(1);
6b0c1480 1406 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1407 goto ready;
1408 }
1409
1410 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1411 hw->dev[port]->name);
1412 return 0;
1413 ready:
6b0c1480 1414 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1415}
1416
1417static void genesis_link_down(struct skge_port *skge)
1418{
1419 struct skge_hw *hw = skge->hw;
1420 int port = skge->port;
1421
1422 pr_debug("genesis_link_down\n");
1423
6b0c1480
SH		 1424 xm_write16(hw, port, XM_MMU_CMD,
1425 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1426 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1427
1428 /* dummy read to ensure writing */
6b0c1480 1429 (void) xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1430
1431 skge_link_down(skge);
1432}
1433
1434static void genesis_link_up(struct skge_port *skge)
1435{
1436 struct skge_hw *hw = skge->hw;
1437 int port = skge->port;
1438 u16 cmd;
1439 u32 mode, msk;
1440
1441 pr_debug("genesis_link_up\n");
6b0c1480 1442 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1443
1444 /*
1445 * enabling pause frame reception is required for 1000BT
1446 * because the XMAC is not reset if the link is going down
1447 */
1448 if (skge->flow_control == FLOW_MODE_NONE ||
1449 skge->flow_control == FLOW_MODE_LOC_SEND)
1450 cmd |= XM_MMU_IGN_PF;
1451 else
1452 /* Enable Pause Frame Reception */
1453 cmd &= ~XM_MMU_IGN_PF;
1454
6b0c1480 1455 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1456
6b0c1480 1457 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1458 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1459 skge->flow_control == FLOW_MODE_LOC_SEND) {
1460 /*
1461 * Configure Pause Frame Generation
1462 * Use internal and external Pause Frame Generation.
1463 * Sending pause frames is edge triggered.
1464 * Send a Pause frame with the maximum pause time if
1465 * internal oder external FIFO full condition occurs.
1466 * Send a zero pause time frame to re-start transmission.
1467 */
1468 /* XM_PAUSE_DA = '010000C28001' (default) */
1469 /* XM_MAC_PTIME = 0xffff (maximum) */
1470 /* remember this value is defined in big endian (!) */
6b0c1480 1471 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1472
1473 mode |= XM_PAUSE_MODE;
6b0c1480 1474 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1475 } else {
1476 /*
1477 * disable pause frame generation is required for 1000BT
1478 * because the XMAC is not reset if the link is going down
1479 */
1480 /* Disable Pause Mode in Mode Register */
1481 mode &= ~XM_PAUSE_MODE;
1482
6b0c1480 1483 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1484 }
1485
6b0c1480 1486 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1487
1488 msk = XM_DEF_MSK;
1489 if (hw->phy_type != SK_PHY_XMAC)
1490 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1491
6b0c1480
SH		 1492 xm_write16(hw, port, XM_IMSK, msk);
1493 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1494
1495 /* get MMU Command Reg. */
6b0c1480 1496 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1497 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1498 cmd |= XM_MMU_GMII_FD;
1499
1500 if (hw->phy_type == SK_PHY_BCOM) {
1501 /*
1502 * Workaround BCOM Errata (#10523) for all BCom Phys
1503 * Enable Power Management after link up
1504 */
6b0c1480
SH		 1505 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1506 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
baef58b1 1507 & ~PHY_B_AC_DIS_PM);
6b0c1480 1508 xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
baef58b1
SH		 1509 PHY_B_DEF_MSK);
1510 }
1511
1512 /* enable Rx/Tx */
6b0c1480 1513 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1514 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1515 skge_link_up(skge);
1516}
1517
1518
1519static void genesis_bcom_intr(struct skge_port *skge)
1520{
1521 struct skge_hw *hw = skge->hw;
1522 int port = skge->port;
6b0c1480 1523 u16 stat = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
baef58b1
SH		 1524
1525 pr_debug("genesis_bcom intr stat=%x\n", stat);
1526
1527 /* Workaround BCom Errata:
1528 * enable and disable loopback mode if "NO HCD" occurs.
1529 */
1530 if (stat & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1531 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1532 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1533 ctrl | PHY_CT_LOOP);
6b0c1480 1534 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1535 ctrl & ~PHY_CT_LOOP);
1536 }
1537
6b0c1480 1538 stat = xm_phy_read(hw, port, PHY_BCOM_STAT);
baef58b1 1539 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
6b0c1480 1540 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
baef58b1
SH		 1541 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1542 genesis_link_down(skge);
1543
1544 else if (stat & PHY_B_IS_LST_CHANGE) {
1545 if (aux & PHY_B_AS_AN_C) {
1546 switch (aux & PHY_B_AS_AN_RES_MSK) {
1547 case PHY_B_RES_1000FD:
1548 skge->duplex = DUPLEX_FULL;
1549 break;
1550 case PHY_B_RES_1000HD:
1551 skge->duplex = DUPLEX_HALF;
1552 break;
1553 }
1554
1555 switch (aux & PHY_B_AS_PAUSE_MSK) {
1556 case PHY_B_AS_PAUSE_MSK:
1557 skge->flow_control = FLOW_MODE_SYMMETRIC;
1558 break;
1559 case PHY_B_AS_PRR:
1560 skge->flow_control = FLOW_MODE_REM_SEND;
1561 break;
1562 case PHY_B_AS_PRT:
1563 skge->flow_control = FLOW_MODE_LOC_SEND;
1564 break;
1565 default:
1566 skge->flow_control = FLOW_MODE_NONE;
1567 }
1568 skge->speed = SPEED_1000;
1569 }
1570 genesis_link_up(skge);
1571 }
1572 else
1573 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1574 }
1575}
1576
1577/* Perodic poll of phy status to check for link transistion */
1578static void skge_link_timer(unsigned long __arg)
1579{
1580 struct skge_port *skge = (struct skge_port *) __arg;
1581 struct skge_hw *hw = skge->hw;
1582 int port = skge->port;
1583
1584 if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1585 return;
1586
1587 spin_lock_bh(&hw->phy_lock);
1588 if (hw->phy_type == SK_PHY_BCOM)
1589 genesis_bcom_intr(skge);
1590 else {
1591 int i;
1592 for (i = 0; i < 3; i++)
6b0c1480 1593 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
baef58b1
SH		 1594 break;
1595
1596 if (i == 3)
1597 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1598 else
1599 genesis_link_up(skge);
1600 }
1601 spin_unlock_bh(&hw->phy_lock);
1602}
1603
1604/* Marvell Phy Initailization */
1605static void yukon_init(struct skge_hw *hw, int port)
1606{
1607 struct skge_port *skge = netdev_priv(hw->dev[port]);
1608 u16 ctrl, ct1000, adv;
1609 u16 ledctrl, ledover;
1610
1611 pr_debug("yukon_init\n");
1612 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1613 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1614
1615 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1616 PHY_M_EC_MAC_S_MSK);
1617 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1618
1619 /* on PHY 88E1111 there is a change for downshift control */
1620 if (hw->chip_id == CHIP_ID_YUKON_EC)
1621 ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
1622 else
1623 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1624
6b0c1480 1625 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1626 }
1627
6b0c1480 1628 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1629 if (skge->autoneg == AUTONEG_DISABLE)
1630 ctrl &= ~PHY_CT_ANE;
1631
1632 ctrl |= PHY_CT_RESET;
6b0c1480 1633 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1634
1635 ctrl = 0;
1636 ct1000 = 0;
1637 adv = PHY_SEL_TYPE;
1638
1639 if (skge->autoneg == AUTONEG_ENABLE) {
1640 if (iscopper(hw)) {
1641 if (skge->advertising & ADVERTISED_1000baseT_Full)
1642 ct1000 |= PHY_M_1000C_AFD;
1643 if (skge->advertising & ADVERTISED_1000baseT_Half)
1644 ct1000 |= PHY_M_1000C_AHD;
1645 if (skge->advertising & ADVERTISED_100baseT_Full)
1646 adv |= PHY_M_AN_100_FD;
1647 if (skge->advertising & ADVERTISED_100baseT_Half)
1648 adv |= PHY_M_AN_100_HD;
1649 if (skge->advertising & ADVERTISED_10baseT_Full)
1650 adv |= PHY_M_AN_10_FD;
1651 if (skge->advertising & ADVERTISED_10baseT_Half)
1652 adv |= PHY_M_AN_10_HD;
1653
1654 /* Set Flow-control capabilities */
1655 switch (skge->flow_control) {
1656 case FLOW_MODE_NONE:
1657 adv |= PHY_B_P_NO_PAUSE;
1658 break;
1659 case FLOW_MODE_LOC_SEND:
1660 adv |= PHY_B_P_ASYM_MD;
1661 break;
1662 case FLOW_MODE_SYMMETRIC:
1663 adv |= PHY_B_P_SYM_MD;
1664 break;
1665 case FLOW_MODE_REM_SEND:
1666 adv |= PHY_B_P_BOTH_MD;
1667 break;
1668 }
1669 } else { /* special defines for FIBER (88E1011S only) */
1670 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1671
1672 /* Set Flow-control capabilities */
1673 switch (skge->flow_control) {
1674 case FLOW_MODE_NONE:
1675 adv |= PHY_M_P_NO_PAUSE_X;
1676 break;
1677 case FLOW_MODE_LOC_SEND:
1678 adv |= PHY_M_P_ASYM_MD_X;
1679 break;
1680 case FLOW_MODE_SYMMETRIC:
1681 adv |= PHY_M_P_SYM_MD_X;
1682 break;
1683 case FLOW_MODE_REM_SEND:
1684 adv |= PHY_M_P_BOTH_MD_X;
1685 break;
1686 }
1687 }
1688 /* Restart Auto-negotiation */
1689 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1690 } else {
1691 /* forced speed/duplex settings */
1692 ct1000 = PHY_M_1000C_MSE;
1693
1694 if (skge->duplex == DUPLEX_FULL)
1695 ctrl |= PHY_CT_DUP_MD;
1696
1697 switch (skge->speed) {
1698 case SPEED_1000:
1699 ctrl |= PHY_CT_SP1000;
1700 break;
1701 case SPEED_100:
1702 ctrl |= PHY_CT_SP100;
1703 break;
1704 }
1705
1706 ctrl |= PHY_CT_RESET;
1707 }
1708
1709 if (hw->chip_id != CHIP_ID_YUKON_FE)
6b0c1480 1710 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1711
6b0c1480
SH		 1712 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1713 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1714
1715 /* Setup Phy LED's */
1716 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1717 ledover = 0;
1718
1719 if (hw->chip_id == CHIP_ID_YUKON_FE) {
1720 /* on 88E3082 these bits are at 11..9 (shifted left) */
1721 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1722
6b0c1480
SH		 1723 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1724 ((gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
baef58b1
SH		 1725
1726 & ~PHY_M_FELP_LED1_MSK)
1727 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
1728 } else {
1729 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
1730 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1731
1732 /* turn off the Rx LED (LED_RX) */
1733 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1734 }
1735
1736 /* disable blink mode (LED_DUPLEX) on collisions */
1737 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1738 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1739
1740 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1741 /* turn on 100 Mbps LED (LED_LINK100) */
1742 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1743 }
1744
1745 if (ledover)
6b0c1480 1746 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1747
1748 /* Enable phy interrupt on autonegotiation complete (or link up) */
1749 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1750 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1751 else
6b0c1480 1752 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1753}
1754
1755static void yukon_reset(struct skge_hw *hw, int port)
1756{
6b0c1480
SH		 1757 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1758 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1759 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1760 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1761 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1762
6b0c1480
SH		 1763 gma_write16(hw, port, GM_RX_CTRL,
1764 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1765 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1766}
1767
1768static void yukon_mac_init(struct skge_hw *hw, int port)
1769{
1770 struct skge_port *skge = netdev_priv(hw->dev[port]);
1771 int i;
1772 u32 reg;
1773 const u8 *addr = hw->dev[port]->dev_addr;
1774
1775 /* WA code for COMA mode -- set PHY reset */
1776 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1777 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1778 skge_write32(hw, B2_GP_IO,
1779 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1780
1781 /* hard reset */
6b0c1480
SH		 1782 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1783 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1784
1785 /* WA code for COMA mode -- clear PHY reset */
1786 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1787 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1788 skge_write32(hw, B2_GP_IO,
1789 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1790 & ~GP_IO_9);
1791
1792 /* Set hardware config mode */
1793 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1794 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1795 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1796
1797 /* Clear GMC reset */
6b0c1480
SH		 1798 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1799 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1800 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1801 if (skge->autoneg == AUTONEG_DISABLE) {
1802 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1803 gma_write16(hw, port, GM_GP_CTRL,
1804 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1805
1806 switch (skge->speed) {
1807 case SPEED_1000:
1808 reg |= GM_GPCR_SPEED_1000;
1809 /* fallthru */
1810 case SPEED_100:
1811 reg |= GM_GPCR_SPEED_100;
1812 }
1813
1814 if (skge->duplex == DUPLEX_FULL)
1815 reg |= GM_GPCR_DUP_FULL;
1816 } else
1817 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1818 switch (skge->flow_control) {
1819 case FLOW_MODE_NONE:
6b0c1480 1820 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1821 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1822 break;
1823 case FLOW_MODE_LOC_SEND:
1824 /* disable Rx flow-control */
1825 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1826 }
1827
6b0c1480 1828 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1829 skge_read16(hw, GMAC_IRQ_SRC);
1830
1831 spin_lock_bh(&hw->phy_lock);
1832 yukon_init(hw, port);
1833 spin_unlock_bh(&hw->phy_lock);
1834
1835 /* MIB clear */
6b0c1480
SH		 1836 reg = gma_read16(hw, port, GM_PHY_ADDR);
1837 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1838
1839 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1840 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1841 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1842
1843 /* transmit control */
6b0c1480 1844 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1845
1846 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1847 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1848 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1849
1850 /* transmit flow control */
6b0c1480 1851 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1852
1853 /* transmit parameter */
6b0c1480 1854 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1855 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1856 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1857 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1858
1859 /* serial mode register */
1860 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1861 if (hw->dev[port]->mtu > 1500)
1862 reg |= GM_SMOD_JUMBO_ENA;
1863
6b0c1480 1864 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1865
1866 /* physical address: used for pause frames */
6b0c1480 1867 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1868 /* virtual address for data */
6b0c1480 1869 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1870
1871 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1872 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1873 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1874 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1875
1876 /* Initialize Mac Fifo */
1877
1878 /* Configure Rx MAC FIFO */
6b0c1480 1879 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1880 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1881 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1882 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1883 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1884 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1885 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1886 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1887
1888 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1889 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1890 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1891}
1892
1893static void yukon_stop(struct skge_port *skge)
1894{
1895 struct skge_hw *hw = skge->hw;
1896 int port = skge->port;
1897
1898 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1899 chip_rev(hw) == CHIP_REV_YU_LITE_A3) {
1900 skge_write32(hw, B2_GP_IO,
1901 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1902 }
1903
6b0c1480
SH		 1904 gma_write16(hw, port, GM_GP_CTRL,
1905 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1906 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1907 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1908
1909 /* set GPHY Control reset */
6b0c1480
SH		 1910 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1911 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1912}
1913
1914static void yukon_get_stats(struct skge_port *skge, u64 *data)
1915{
1916 struct skge_hw *hw = skge->hw;
1917 int port = skge->port;
1918 int i;
1919
6b0c1480
SH		 1920 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1921 | gma_read32(hw, port, GM_TXO_OK_LO);
1922 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1923 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1924
1925 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1926 data[i] = gma_read32(hw, port,
baef58b1
SH		 1927 skge_stats[i].gma_offset);
1928}
1929
1930static void yukon_mac_intr(struct skge_hw *hw, int port)
1931{
1932 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1933 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1
SH		 1934
1935 pr_debug("yukon_intr status %x\n", status);
1936 if (status & GM_IS_RX_FF_OR) {
1937 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1938 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1939 }
1940 if (status & GM_IS_TX_FF_UR) {
1941 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1942 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1943 }
1944
1945}
1946
1947static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1948{
1949 if (hw->chip_id == CHIP_ID_YUKON_FE)
1950 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1951
95566065 1952 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1953 case PHY_M_PS_SPEED_1000:
1954 return SPEED_1000;
1955 case PHY_M_PS_SPEED_100:
1956 return SPEED_100;
1957 default:
1958 return SPEED_10;
1959 }
1960}
1961
1962static void yukon_link_up(struct skge_port *skge)
1963{
1964 struct skge_hw *hw = skge->hw;
1965 int port = skge->port;
1966 u16 reg;
1967
1968 pr_debug("yukon_link_up\n");
1969
1970 /* Enable Transmit FIFO Underrun */
1971 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1972
6b0c1480 1973 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1974 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1975 reg |= GM_GPCR_DUP_FULL;
1976
1977 /* enable Rx/Tx */
1978 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1979 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1980
6b0c1480 1981 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1982 skge_link_up(skge);
1983}
1984
1985static void yukon_link_down(struct skge_port *skge)
1986{
1987 struct skge_hw *hw = skge->hw;
1988 int port = skge->port;
1989
1990 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1991 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1992 gm_phy_write(hw, port, GM_GP_CTRL,
1993 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1994 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1995
1996 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1997 skge->flow_control == FLOW_MODE_REM_SEND) {
1998 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1999 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2000 gm_phy_read(hw, port,
baef58b1
SH		 2001 PHY_MARV_AUNE_ADV)
2002 | PHY_M_AN_ASP);
2003
2004 }
2005
2006 yukon_reset(hw, port);
2007 skge_link_down(skge);
2008
2009 yukon_init(hw, port);
2010}
2011
2012static void yukon_phy_intr(struct skge_port *skge)
2013{
2014 struct skge_hw *hw = skge->hw;
2015 int port = skge->port;
2016 const char *reason = NULL;
2017 u16 istatus, phystat;
2018
6b0c1480
SH		 2019 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2020 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
baef58b1
SH		 2021 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
2022
2023 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2024 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2025 & PHY_M_AN_RF) {
2026 reason = "remote fault";
2027 goto failed;
2028 }
2029
2030 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
6b0c1480 2031 && (gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
baef58b1
SH		 2032 & PHY_B_1000S_MSF)) {
2033 reason = "master/slave fault";
2034 goto failed;
2035 }
2036
2037 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2038 reason = "speed/duplex";
2039 goto failed;
2040 }
2041
2042 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2043 ? DUPLEX_FULL : DUPLEX_HALF;
2044 skge->speed = yukon_speed(hw, phystat);
2045
2046 /* Tx & Rx Pause Enabled bits are at 9..8 */
2047 if (hw->chip_id == CHIP_ID_YUKON_XL)
2048 phystat >>= 6;
2049
2050 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2051 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2052 case PHY_M_PS_PAUSE_MSK:
2053 skge->flow_control = FLOW_MODE_SYMMETRIC;
2054 break;
2055 case PHY_M_PS_RX_P_EN:
2056 skge->flow_control = FLOW_MODE_REM_SEND;
2057 break;
2058 case PHY_M_PS_TX_P_EN:
2059 skge->flow_control = FLOW_MODE_LOC_SEND;
2060 break;
2061 default:
2062 skge->flow_control = FLOW_MODE_NONE;
2063 }
2064
2065 if (skge->flow_control == FLOW_MODE_NONE ||
2066 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2067 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2068 else
6b0c1480 2069 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2070 yukon_link_up(skge);
2071 return;
2072 }
2073
2074 if (istatus & PHY_M_IS_LSP_CHANGE)
2075 skge->speed = yukon_speed(hw, phystat);
2076
2077 if (istatus & PHY_M_IS_DUP_CHANGE)
2078 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2079 if (istatus & PHY_M_IS_LST_CHANGE) {
2080 if (phystat & PHY_M_PS_LINK_UP)
2081 yukon_link_up(skge);
2082 else
2083 yukon_link_down(skge);
2084 }
2085 return;
2086 failed:
2087 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2088 skge->netdev->name, reason);
2089
2090 /* XXX restart autonegotiation? */
2091}
2092
2093static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2094{
2095 u32 end;
2096
2097 start /= 8;
2098 len /= 8;
2099 end = start + len - 1;
2100
2101 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2102 skge_write32(hw, RB_ADDR(q, RB_START), start);
2103 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2104 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2105 skge_write32(hw, RB_ADDR(q, RB_END), end);
2106
2107 if (q == Q_R1 || q == Q_R2) {
2108 /* Set thresholds on receive queue's */
2109 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2110 start + (2*len)/3);
2111 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2112 start + (len/3));
2113 } else {
2114 /* Enable store & forward on Tx queue's because
2115 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2116 */
2117 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2118 }
2119
2120 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2121}
2122
2123/* Setup Bus Memory Interface */
2124static void skge_qset(struct skge_port *skge, u16 q,
2125 const struct skge_element *e)
2126{
2127 struct skge_hw *hw = skge->hw;
2128 u32 watermark = 0x600;
2129 u64 base = skge->dma + (e->desc - skge->mem);
2130
2131 /* optimization to reduce window on 32bit/33mhz */
2132 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2133 watermark /= 2;
2134
2135 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2136 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2137 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2138 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2139}
2140
2141static int skge_up(struct net_device *dev)
2142{
2143 struct skge_port *skge = netdev_priv(dev);
2144 struct skge_hw *hw = skge->hw;
2145 int port = skge->port;
2146 u32 chunk, ram_addr;
2147 size_t rx_size, tx_size;
2148 int err;
2149
2150 if (netif_msg_ifup(skge))
2151 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2152
2153 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2154 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2155 skge->mem_size = tx_size + rx_size;
2156 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2157 if (!skge->mem)
2158 return -ENOMEM;
2159
2160 memset(skge->mem, 0, skge->mem_size);
2161
2162 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2163 goto free_pci_mem;
2164
2165 if (skge_rx_fill(skge))
2166 goto free_rx_ring;
2167
2168 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2169 skge->dma + rx_size)))
2170 goto free_rx_ring;
2171
2172 skge->tx_avail = skge->tx_ring.count - 1;
2173
2174 /* Initialze MAC */
2175 if (hw->chip_id == CHIP_ID_GENESIS)
2176 genesis_mac_init(hw, port);
2177 else
2178 yukon_mac_init(hw, port);
2179
2180 /* Configure RAMbuffers */
2181 chunk = hw->ram_size / (isdualport(hw) ? 4 : 2);
2182 ram_addr = hw->ram_offset + 2 * chunk * port;
2183
2184 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2185 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2186
2187 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2188 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2189 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2190
2191 /* Start receiver BMU */
2192 wmb();
2193 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2194
2195 pr_debug("skge_up completed\n");
2196 return 0;
2197
2198 free_rx_ring:
2199 skge_rx_clean(skge);
2200 kfree(skge->rx_ring.start);
2201 free_pci_mem:
2202 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2203
2204 return err;
2205}
2206
2207static int skge_down(struct net_device *dev)
2208{
2209 struct skge_port *skge = netdev_priv(dev);
2210 struct skge_hw *hw = skge->hw;
2211 int port = skge->port;
2212
2213 if (netif_msg_ifdown(skge))
2214 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2215
2216 netif_stop_queue(dev);
2217
2218 del_timer_sync(&skge->led_blink);
2219 del_timer_sync(&skge->link_check);
2220
2221 /* Stop transmitter */
2222 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2223 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2224 RB_RST_SET|RB_DIS_OP_MD);
2225
2226 if (hw->chip_id == CHIP_ID_GENESIS)
2227 genesis_stop(skge);
2228 else
2229 yukon_stop(skge);
2230
2231 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2232 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2233 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2234
2235 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2236 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2237 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2238
2239 /* Reset PCI FIFO */
2240 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2241 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2242
2243 /* Reset the RAM Buffer async Tx queue */
2244 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2245 /* stop receiver */
2246 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2247 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2248 RB_RST_SET|RB_DIS_OP_MD);
2249 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2250
2251 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2252 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2253 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2254 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2255 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2256 } else {
6b0c1480
SH		 2257 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2258 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2259 }
2260
2261 /* turn off led's */
2262 skge_write16(hw, B0_LED, LED_STAT_OFF);
2263
2264 skge_tx_clean(skge);
2265 skge_rx_clean(skge);
2266
2267 kfree(skge->rx_ring.start);
2268 kfree(skge->tx_ring.start);
2269 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2270 return 0;
2271}
2272
2273static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2274{
2275 struct skge_port *skge = netdev_priv(dev);
2276 struct skge_hw *hw = skge->hw;
2277 struct skge_ring *ring = &skge->tx_ring;
2278 struct skge_element *e;
2279 struct skge_tx_desc *td;
2280 int i;
2281 u32 control, len;
2282 u64 map;
2283 unsigned long flags;
2284
2285 skb = skb_padto(skb, ETH_ZLEN);
2286 if (!skb)
2287 return NETDEV_TX_OK;
2288
2289 local_irq_save(flags);
2290 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2291 /* Collision - tell upper layer to requeue */
2292 local_irq_restore(flags);
2293 return NETDEV_TX_LOCKED;
2294 }
baef58b1
SH		 2295
2296 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2297 netif_stop_queue(dev);
2298 spin_unlock_irqrestore(&skge->tx_lock, flags);
2299
2300 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2301 dev->name);
2302 return NETDEV_TX_BUSY;
2303 }
2304
2305 e = ring->to_use;
2306 td = e->desc;
2307 e->skb = skb;
2308 len = skb_headlen(skb);
2309 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2310 pci_unmap_addr_set(e, mapaddr, map);
2311 pci_unmap_len_set(e, maplen, len);
2312
2313 td->dma_lo = map;
2314 td->dma_hi = map >> 32;
2315
2316 if (skb->ip_summed == CHECKSUM_HW) {
2317 const struct iphdr *ip
2318 = (const struct iphdr *) (skb->data + ETH_HLEN);
2319 int offset = skb->h.raw - skb->data;
2320
2321 /* This seems backwards, but it is what the sk98lin
2322 * does. Looks like hardware is wrong?
2323 */
2324 if (ip->protocol == IPPROTO_UDP
2325 && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON)
2326 control = BMU_TCP_CHECK;
2327 else
2328 control = BMU_UDP_CHECK;
2329
2330 td->csum_offs = 0;
2331 td->csum_start = offset;
2332 td->csum_write = offset + skb->csum;
2333 } else
2334 control = BMU_CHECK;
2335
2336 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2337 control |= BMU_EOF| BMU_IRQ_EOF;
2338 else {
2339 struct skge_tx_desc *tf = td;
2340
2341 control |= BMU_STFWD;
2342 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2343 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2344
2345 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2346 frag->size, PCI_DMA_TODEVICE);
2347
2348 e = e->next;
2349 e->skb = NULL;
2350 tf = e->desc;
2351 tf->dma_lo = map;
2352 tf->dma_hi = (u64) map >> 32;
2353 pci_unmap_addr_set(e, mapaddr, map);
2354 pci_unmap_len_set(e, maplen, frag->size);
2355
2356 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2357 }
2358 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2359 }
2360 /* Make sure all the descriptors written */
2361 wmb();
2362 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2363 wmb();
2364
2365 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2366
2367 if (netif_msg_tx_queued(skge))
0b2d7fea 2368 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2369 dev->name, e - ring->start, skb->len);
2370
2371 ring->to_use = e->next;
2372 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2373 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2374 pr_debug("%s: transmit queue full\n", dev->name);
2375 netif_stop_queue(dev);
2376 }
2377
2378 dev->trans_start = jiffies;
2379 spin_unlock_irqrestore(&skge->tx_lock, flags);
2380
2381 return NETDEV_TX_OK;
2382}
2383
2384static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2385{
2386 if (e->skb) {
2387 pci_unmap_single(hw->pdev,
2388 pci_unmap_addr(e, mapaddr),
2389 pci_unmap_len(e, maplen),
2390 PCI_DMA_TODEVICE);
2391 dev_kfree_skb_any(e->skb);
2392 e->skb = NULL;
2393 } else {
2394 pci_unmap_page(hw->pdev,
2395 pci_unmap_addr(e, mapaddr),
2396 pci_unmap_len(e, maplen),
2397 PCI_DMA_TODEVICE);
2398 }
2399}
2400
2401static void skge_tx_clean(struct skge_port *skge)
2402{
2403 struct skge_ring *ring = &skge->tx_ring;
2404 struct skge_element *e;
2405 unsigned long flags;
2406
2407 spin_lock_irqsave(&skge->tx_lock, flags);
2408 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2409 ++skge->tx_avail;
2410 skge_tx_free(skge->hw, e);
2411 }
2412 ring->to_clean = e;
2413 spin_unlock_irqrestore(&skge->tx_lock, flags);
2414}
2415
2416static void skge_tx_timeout(struct net_device *dev)
2417{
2418 struct skge_port *skge = netdev_priv(dev);
2419
2420 if (netif_msg_timer(skge))
2421 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2422
2423 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2424 skge_tx_clean(skge);
2425}
2426
2427static int skge_change_mtu(struct net_device *dev, int new_mtu)
2428{
2429 int err = 0;
2430
95566065 2431 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2432 return -EINVAL;
2433
2434 dev->mtu = new_mtu;
2435
2436 if (netif_running(dev)) {
2437 skge_down(dev);
2438 skge_up(dev);
2439 }
2440
2441 return err;
2442}
2443
2444static void genesis_set_multicast(struct net_device *dev)
2445{
2446 struct skge_port *skge = netdev_priv(dev);
2447 struct skge_hw *hw = skge->hw;
2448 int port = skge->port;
2449 int i, count = dev->mc_count;
2450 struct dev_mc_list *list = dev->mc_list;
2451 u32 mode;
2452 u8 filter[8];
2453
6b0c1480 2454 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2455 mode |= XM_MD_ENA_HASH;
2456 if (dev->flags & IFF_PROMISC)
2457 mode |= XM_MD_ENA_PROM;
2458 else
2459 mode &= ~XM_MD_ENA_PROM;
2460
2461 if (dev->flags & IFF_ALLMULTI)
2462 memset(filter, 0xff, sizeof(filter));
2463 else {
2464 memset(filter, 0, sizeof(filter));
95566065 2465 for (i = 0; list && i < count; i++, list = list->next) {
baef58b1
SH		 2466 u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
2467 u8 bit = 63 - (crc & 63);
2468
2469 filter[bit/8] |= 1 << (bit%8);
2470 }
2471 }
2472
6b0c1480 2473 xm_outhash(hw, port, XM_HSM, filter);
baef58b1 2474
6b0c1480 2475 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 2476}
2477
2478static void yukon_set_multicast(struct net_device *dev)
2479{
2480 struct skge_port *skge = netdev_priv(dev);
2481 struct skge_hw *hw = skge->hw;
2482 int port = skge->port;
2483 struct dev_mc_list *list = dev->mc_list;
2484 u16 reg;
2485 u8 filter[8];
2486
2487 memset(filter, 0, sizeof(filter));
2488
6b0c1480 2489 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2490 reg |= GM_RXCR_UCF_ENA;
2491
2492 if (dev->flags & IFF_PROMISC) /* promiscious */
2493 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2494 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2495 memset(filter, 0xff, sizeof(filter));
2496 else if (dev->mc_count == 0) /* no multicast */
2497 reg &= ~GM_RXCR_MCF_ENA;
2498 else {
2499 int i;
2500 reg |= GM_RXCR_MCF_ENA;
2501
95566065 2502 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2503 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2504 filter[bit/8] |= 1 << (bit%8);
2505 }
2506 }
2507
2508
6b0c1480 2509 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2510 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2511 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2512 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2513 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2514 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2515 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2516 (u16)filter[6] | ((u16)filter[7] << 8));
2517
6b0c1480 2518 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2519}
2520
2521static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2522{
2523 if (hw->chip_id == CHIP_ID_GENESIS)
2524 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2525 else
2526 return (status & GMR_FS_ANY_ERR) ||
2527 (status & GMR_FS_RX_OK) == 0;
2528}
2529
2530static void skge_rx_error(struct skge_port *skge, int slot,
2531 u32 control, u32 status)
2532{
2533 if (netif_msg_rx_err(skge))
2534 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2535 skge->netdev->name, slot, control, status);
2536
2537 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2538 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2539 skge->net_stats.rx_length_errors++;
2540 else {
2541 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2542 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2543 skge->net_stats.rx_length_errors++;
2544 if (status & XMR_FS_FRA_ERR)
2545 skge->net_stats.rx_frame_errors++;
2546 if (status & XMR_FS_FCS_ERR)
2547 skge->net_stats.rx_crc_errors++;
2548 } else {
2549 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2550 skge->net_stats.rx_length_errors++;
2551 if (status & GMR_FS_FRAGMENT)
2552 skge->net_stats.rx_frame_errors++;
2553 if (status & GMR_FS_CRC_ERR)
2554 skge->net_stats.rx_crc_errors++;
2555 }
2556 }
2557}
2558
2559static int skge_poll(struct net_device *dev, int *budget)
2560{
2561 struct skge_port *skge = netdev_priv(dev);
2562 struct skge_hw *hw = skge->hw;
2563 struct skge_ring *ring = &skge->rx_ring;
2564 struct skge_element *e;
2565 unsigned int to_do = min(dev->quota, *budget);
2566 unsigned int work_done = 0;
2567 int done;
2568 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2569
2570 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2571 e = e->next) {
2572 struct skge_rx_desc *rd = e->desc;
2573 struct sk_buff *skb = e->skb;
2574 u32 control, len, status;
2575
2576 rmb();
2577 control = rd->control;
2578 if (control & BMU_OWN)
2579 break;
2580
2581 len = control & BMU_BBC;
2582 e->skb = NULL;
2583
2584 pci_unmap_single(hw->pdev,
2585 pci_unmap_addr(e, mapaddr),
2586 pci_unmap_len(e, maplen),
2587 PCI_DMA_FROMDEVICE);
2588
2589 status = rd->status;
2590 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2591 || len > dev->mtu + VLAN_ETH_HLEN
2592 || bad_phy_status(hw, status)) {
2593 skge_rx_error(skge, e - ring->start, control, status);
2594 dev_kfree_skb(skb);
2595 continue;
2596 }
2597
2598 if (netif_msg_rx_status(skge))
0b2d7fea 2599 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2600 dev->name, e - ring->start, rd->status, len);
2601
2602 skb_put(skb, len);
2603 skb->protocol = eth_type_trans(skb, dev);
2604
2605 if (skge->rx_csum) {
2606 skb->csum = le16_to_cpu(rd->csum2);
2607 skb->ip_summed = CHECKSUM_HW;
2608 }
2609
2610 dev->last_rx = jiffies;
2611 netif_receive_skb(skb);
2612
2613 ++work_done;
2614 }
2615 ring->to_clean = e;
2616
2617 *budget -= work_done;
2618 dev->quota -= work_done;
2619 done = work_done < to_do;
2620
2621 if (skge_rx_fill(skge))
2622 done = 0;
2623
2624 /* restart receiver */
2625 wmb();
2626 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2627 CSR_START | CSR_IRQ_CL_F);
2628
2629 if (done) {
2630 local_irq_disable();
2631 hw->intr_mask |= irqmask[skge->port];
2632 /* Order is important since data can get interrupted */
2633 skge_write32(hw, B0_IMSK, hw->intr_mask);
2634 __netif_rx_complete(dev);
2635 local_irq_enable();
2636 }
2637
2638 return !done;
2639}
2640
2641static inline void skge_tx_intr(struct net_device *dev)
2642{
2643 struct skge_port *skge = netdev_priv(dev);
2644 struct skge_hw *hw = skge->hw;
2645 struct skge_ring *ring = &skge->tx_ring;
2646 struct skge_element *e;
2647
2648 spin_lock(&skge->tx_lock);
95566065 2649 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2650 struct skge_tx_desc *td = e->desc;
2651 u32 control;
2652
2653 rmb();
2654 control = td->control;
2655 if (control & BMU_OWN)
2656 break;
2657
2658 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2659 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2660 dev->name, e - ring->start, td->status);
2661
2662 skge_tx_free(hw, e);
2663 e->skb = NULL;
2664 ++skge->tx_avail;
2665 }
2666 ring->to_clean = e;
2667 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2668
2669 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2670 netif_wake_queue(dev);
2671
2672 spin_unlock(&skge->tx_lock);
2673}
2674
2675static void skge_mac_parity(struct skge_hw *hw, int port)
2676{
2677 printk(KERN_ERR PFX "%s: mac data parity error\n",
2678 hw->dev[port] ? hw->dev[port]->name
2679 : (port == 0 ? "(port A)": "(port B"));
2680
2681 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2682 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2683 MFF_CLR_PERR);
2684 else
2685 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2686 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
baef58b1
SH		 2687 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)
2688 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2689}
2690
2691static void skge_pci_clear(struct skge_hw *hw)
2692{
2693 u16 status;
2694
467b3417 2695 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2696 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2697 pci_write_config_word(hw->pdev, PCI_STATUS,
2698 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2699 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2700}
2701
2702static void skge_mac_intr(struct skge_hw *hw, int port)
2703{
95566065 2704 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2705 genesis_mac_intr(hw, port);
2706 else
2707 yukon_mac_intr(hw, port);
2708}
2709
2710/* Handle device specific framing and timeout interrupts */
2711static void skge_error_irq(struct skge_hw *hw)
2712{
2713 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2714
2715 if (hw->chip_id == CHIP_ID_GENESIS) {
2716 /* clear xmac errors */
2717 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2718 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2719 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2720 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2721 } else {
2722 /* Timestamp (unused) overflow */
2723 if (hwstatus & IS_IRQ_TIST_OV)
2724 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2725
2726 if (hwstatus & IS_IRQ_SENSOR) {
2727 /* no sensors on 32-bit Yukon */
2728 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2729 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2730 skge_write32(hw, B0_HWE_IMSK,
2731 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2732 } else
2733 printk(KERN_WARNING PFX "sensor interrupt\n");
2734 }
2735
2736
2737 }
2738
2739 if (hwstatus & IS_RAM_RD_PAR) {
2740 printk(KERN_ERR PFX "Ram read data parity error\n");
2741 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2742 }
2743
2744 if (hwstatus & IS_RAM_WR_PAR) {
2745 printk(KERN_ERR PFX "Ram write data parity error\n");
2746 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2747 }
2748
2749 if (hwstatus & IS_M1_PAR_ERR)
2750 skge_mac_parity(hw, 0);
2751
2752 if (hwstatus & IS_M2_PAR_ERR)
2753 skge_mac_parity(hw, 1);
2754
2755 if (hwstatus & IS_R1_PAR_ERR)
2756 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2757
2758 if (hwstatus & IS_R2_PAR_ERR)
2759 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2760
2761 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2762 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2763 hwstatus);
2764
2765 skge_pci_clear(hw);
2766
2767 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2768 if (hwstatus & IS_IRQ_STAT) {
2769 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2770 hwstatus);
2771 hw->intr_mask &= ~IS_HW_ERR;
2772 }
2773 }
2774}
2775
2776/*
2777 * Interrrupt from PHY are handled in tasklet (soft irq)
2778 * because accessing phy registers requires spin wait which might
2779 * cause excess interrupt latency.
2780 */
2781static void skge_extirq(unsigned long data)
2782{
2783 struct skge_hw *hw = (struct skge_hw *) data;
2784 int port;
2785
2786 spin_lock(&hw->phy_lock);
2787 for (port = 0; port < 2; port++) {
2788 struct net_device *dev = hw->dev[port];
2789
2790 if (dev && netif_running(dev)) {
2791 struct skge_port *skge = netdev_priv(dev);
2792
2793 if (hw->chip_id != CHIP_ID_GENESIS)
2794 yukon_phy_intr(skge);
2795 else if (hw->phy_type == SK_PHY_BCOM)
2796 genesis_bcom_intr(skge);
2797 }
2798 }
2799 spin_unlock(&hw->phy_lock);
2800
2801 local_irq_disable();
2802 hw->intr_mask |= IS_EXT_REG;
2803 skge_write32(hw, B0_IMSK, hw->intr_mask);
2804 local_irq_enable();
2805}
2806
2807static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2808{
2809 struct skge_hw *hw = dev_id;
2810 u32 status = skge_read32(hw, B0_SP_ISRC);
2811
2812 if (status == 0 || status == ~0) /* hotplug or shared irq */
2813 return IRQ_NONE;
2814
2815 status &= hw->intr_mask;
2816
2817 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2818 status &= ~IS_R1_F;
2819 hw->intr_mask &= ~IS_R1_F;
2820 skge_write32(hw, B0_IMSK, hw->intr_mask);
2821 __netif_rx_schedule(hw->dev[0]);
2822 }
2823
2824 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2825 status &= ~IS_R2_F;
2826 hw->intr_mask &= ~IS_R2_F;
2827 skge_write32(hw, B0_IMSK, hw->intr_mask);
2828 __netif_rx_schedule(hw->dev[1]);
2829 }
2830
2831 if (status & IS_XA1_F)
2832 skge_tx_intr(hw->dev[0]);
2833
2834 if (status & IS_XA2_F)
2835 skge_tx_intr(hw->dev[1]);
2836
2837 if (status & IS_MAC1)
2838 skge_mac_intr(hw, 0);
95566065 2839
baef58b1
SH		 2840 if (status & IS_MAC2)
2841 skge_mac_intr(hw, 1);
2842
2843 if (status & IS_HW_ERR)
2844 skge_error_irq(hw);
2845
2846 if (status & IS_EXT_REG) {
2847 hw->intr_mask &= ~IS_EXT_REG;
2848 tasklet_schedule(&hw->ext_tasklet);
2849 }
2850
2851 if (status)
2852 skge_write32(hw, B0_IMSK, hw->intr_mask);
2853
2854 return IRQ_HANDLED;
2855}
2856
2857#ifdef CONFIG_NET_POLL_CONTROLLER
2858static void skge_netpoll(struct net_device *dev)
2859{
2860 struct skge_port *skge = netdev_priv(dev);
2861
2862 disable_irq(dev->irq);
2863 skge_intr(dev->irq, skge->hw, NULL);
2864 enable_irq(dev->irq);
2865}
2866#endif
2867
2868static int skge_set_mac_address(struct net_device *dev, void *p)
2869{
2870 struct skge_port *skge = netdev_priv(dev);
2871 struct sockaddr *addr = p;
2872 int err = 0;
2873
2874 if (!is_valid_ether_addr(addr->sa_data))
2875 return -EADDRNOTAVAIL;
2876
2877 skge_down(dev);
2878 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2879 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2880 dev->dev_addr, ETH_ALEN);
2881 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2882 dev->dev_addr, ETH_ALEN);
2883 if (dev->flags & IFF_UP)
2884 err = skge_up(dev);
2885 return err;
2886}
2887
2888static const struct {
2889 u8 id;
2890 const char *name;
2891} skge_chips[] = {
2892 { CHIP_ID_GENESIS, "Genesis" },
2893 { CHIP_ID_YUKON, "Yukon" },
2894 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2895 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2896 { CHIP_ID_YUKON_XL, "Yukon-2 XL"},
2897 { CHIP_ID_YUKON_EC, "YUKON-2 EC"},
2898 { CHIP_ID_YUKON_FE, "YUKON-2 FE"},
2899};
2900
2901static const char *skge_board_name(const struct skge_hw *hw)
2902{
2903 int i;
2904 static char buf[16];
2905
2906 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2907 if (skge_chips[i].id == hw->chip_id)
2908 return skge_chips[i].name;
2909
2910 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2911 return buf;
2912}
2913
2914
2915/*
2916 * Setup the board data structure, but don't bring up
2917 * the port(s)
2918 */
2919static int skge_reset(struct skge_hw *hw)
2920{
2921 u16 ctst;
2922 u8 t8;
2923 int i, ports;
2924
2925 ctst = skge_read16(hw, B0_CTST);
2926
2927 /* do a SW reset */
2928 skge_write8(hw, B0_CTST, CS_RST_SET);
2929 skge_write8(hw, B0_CTST, CS_RST_CLR);
2930
2931 /* clear PCI errors, if any */
2932 skge_pci_clear(hw);
2933
2934 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2935
2936 /* restore CLK_RUN bits (for Yukon-Lite) */
2937 skge_write16(hw, B0_CTST,
2938 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2939
2940 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2941 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2942 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2943
95566065 2944 switch (hw->chip_id) {
baef58b1
SH		 2945 case CHIP_ID_GENESIS:
2946 switch (hw->phy_type) {
2947 case SK_PHY_XMAC:
2948 hw->phy_addr = PHY_ADDR_XMAC;
2949 break;
2950 case SK_PHY_BCOM:
2951 hw->phy_addr = PHY_ADDR_BCOM;
2952 break;
2953 default:
2954 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2955 pci_name(hw->pdev), hw->phy_type);
2956 return -EOPNOTSUPP;
2957 }
2958 break;
2959
2960 case CHIP_ID_YUKON:
2961 case CHIP_ID_YUKON_LITE:
2962 case CHIP_ID_YUKON_LP:
2963 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2964 hw->phy_type = SK_PHY_MARV_COPPER;
2965
2966 hw->phy_addr = PHY_ADDR_MARV;
2967 if (!iscopper(hw))
2968 hw->phy_type = SK_PHY_MARV_FIBER;
2969
2970 break;
2971
2972 default:
2973 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2974 pci_name(hw->pdev), hw->chip_id);
2975 return -EOPNOTSUPP;
2976 }
2977
2978 hw->mac_cfg = skge_read8(hw, B2_MAC_CFG);
2979 ports = isdualport(hw) ? 2 : 1;
2980
2981 /* read the adapters RAM size */
2982 t8 = skge_read8(hw, B2_E_0);
2983 if (hw->chip_id == CHIP_ID_GENESIS) {
2984 if (t8 == 3) {
2985 /* special case: 4 x 64k x 36, offset = 0x80000 */
2986 hw->ram_size = 0x100000;
2987 hw->ram_offset = 0x80000;
2988 } else
2989 hw->ram_size = t8 * 512;
2990 }
2991 else if (t8 == 0)
2992 hw->ram_size = 0x20000;
2993 else
2994 hw->ram_size = t8 * 4096;
2995
2996 if (hw->chip_id == CHIP_ID_GENESIS)
2997 genesis_init(hw);
2998 else {
2999 /* switch power to VCC (WA for VAUX problem) */
3000 skge_write8(hw, B0_POWER_CTRL,
3001 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3002 for (i = 0; i < ports; i++) {
6b0c1480
SH		 3003 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3004 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3005 }
3006 }
3007
3008 /* turn off hardware timer (unused) */
3009 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3010 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3011 skge_write8(hw, B0_LED, LED_STAT_ON);
3012
3013 /* enable the Tx Arbiters */
3014 for (i = 0; i < ports; i++)
6b0c1480 3015 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3016
3017 /* Initialize ram interface */
3018 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3019
3020 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3021 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3022 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3023 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3024 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3025 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3026 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3027 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3028 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3029 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3030 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3031 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3032
3033 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3034
3035 /* Set interrupt moderation for Transmit only
3036 * Receive interrupts avoided by NAPI
3037 */
3038 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3039 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3040 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3041
3042 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3043 if (isdualport(hw))
3044 hw->intr_mask |= IS_PORT_2;
3045 skge_write32(hw, B0_IMSK, hw->intr_mask);
3046
3047 if (hw->chip_id != CHIP_ID_GENESIS)
3048 skge_write8(hw, GMAC_IRQ_MSK, 0);
3049
3050 spin_lock_bh(&hw->phy_lock);
3051 for (i = 0; i < ports; i++) {
3052 if (hw->chip_id == CHIP_ID_GENESIS)
3053 genesis_reset(hw, i);
3054 else
3055 yukon_reset(hw, i);
3056 }
3057 spin_unlock_bh(&hw->phy_lock);
3058
3059 return 0;
3060}
3061
3062/* Initialize network device */
3063static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3064{
3065 struct skge_port *skge;
3066 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3067
3068 if (!dev) {
3069 printk(KERN_ERR "skge etherdev alloc failed");
3070 return NULL;
3071 }
3072
3073 SET_MODULE_OWNER(dev);
3074 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3075 dev->open = skge_up;
3076 dev->stop = skge_down;
3077 dev->hard_start_xmit = skge_xmit_frame;
3078 dev->get_stats = skge_get_stats;
3079 if (hw->chip_id == CHIP_ID_GENESIS)
3080 dev->set_multicast_list = genesis_set_multicast;
3081 else
3082 dev->set_multicast_list = yukon_set_multicast;
3083
3084 dev->set_mac_address = skge_set_mac_address;
3085 dev->change_mtu = skge_change_mtu;
3086 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3087 dev->tx_timeout = skge_tx_timeout;
3088 dev->watchdog_timeo = TX_WATCHDOG;
3089 dev->poll = skge_poll;
3090 dev->weight = NAPI_WEIGHT;
3091#ifdef CONFIG_NET_POLL_CONTROLLER
3092 dev->poll_controller = skge_netpoll;
3093#endif
3094 dev->irq = hw->pdev->irq;
3095 dev->features = NETIF_F_LLTX;
3096
3097 skge = netdev_priv(dev);
3098 skge->netdev = dev;
3099 skge->hw = hw;
3100 skge->msg_enable = netif_msg_init(debug, default_msg);
3101 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3102 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3103
3104 /* Auto speed and flow control */
3105 skge->autoneg = AUTONEG_ENABLE;
3106 skge->flow_control = FLOW_MODE_SYMMETRIC;
3107 skge->duplex = -1;
3108 skge->speed = -1;
3109 skge->advertising = skge_modes(hw);
3110
3111 hw->dev[port] = dev;
3112
3113 skge->port = port;
3114
3115 spin_lock_init(&skge->tx_lock);
3116
3117 init_timer(&skge->link_check);
3118 skge->link_check.function = skge_link_timer;
3119 skge->link_check.data = (unsigned long) skge;
3120
3121 init_timer(&skge->led_blink);
3122 skge->led_blink.function = skge_blink_timer;
3123 skge->led_blink.data = (unsigned long) skge;
3124
3125 if (hw->chip_id != CHIP_ID_GENESIS) {
3126 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3127 skge->rx_csum = 1;
3128 }
3129
3130 /* read the mac address */
3131 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3132
3133 /* device is off until link detection */
3134 netif_carrier_off(dev);
3135 netif_stop_queue(dev);
3136
3137 return dev;
3138}
3139
3140static void __devinit skge_show_addr(struct net_device *dev)
3141{
3142 const struct skge_port *skge = netdev_priv(dev);
3143
3144 if (netif_msg_probe(skge))
3145 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3146 dev->name,
3147 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3148 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3149}
3150
3151static int __devinit skge_probe(struct pci_dev *pdev,
3152 const struct pci_device_id *ent)
3153{
3154 struct net_device *dev, *dev1;
3155 struct skge_hw *hw;
3156 int err, using_dac = 0;
3157
3158 if ((err = pci_enable_device(pdev))) {
3159 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3160 pci_name(pdev));
3161 goto err_out;
3162 }
3163
3164 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3165 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3166 pci_name(pdev));
3167 goto err_out_disable_pdev;
3168 }
3169
3170 pci_set_master(pdev);
3171
3172 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3173 using_dac = 1;
3174 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3175 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3176 pci_name(pdev));
3177 goto err_out_free_regions;
3178 }
3179
3180#ifdef __BIG_ENDIAN
3181 /* byte swap decriptors in hardware */
3182 {
3183 u32 reg;
3184
3185 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3186 reg |= PCI_REV_DESC;
3187 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3188 }
3189#endif
3190
3191 err = -ENOMEM;
3192 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3193 if (!hw) {
3194 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3195 pci_name(pdev));
3196 goto err_out_free_regions;
3197 }
3198
3199 memset(hw, 0, sizeof(*hw));
3200 hw->pdev = pdev;
3201 spin_lock_init(&hw->phy_lock);
3202 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3203
3204 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3205 if (!hw->regs) {
3206 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3207 pci_name(pdev));
3208 goto err_out_free_hw;
3209 }
3210
3211 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3212 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3213 pci_name(pdev), pdev->irq);
3214 goto err_out_iounmap;
3215 }
3216 pci_set_drvdata(pdev, hw);
3217
3218 err = skge_reset(hw);
3219 if (err)
3220 goto err_out_free_irq;
3221
3222 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3223 pci_resource_start(pdev, 0), pdev->irq,
3224 skge_board_name(hw), chip_rev(hw));
3225
3226 if ((dev = skge_devinit(hw, 0)) == NULL)
3227 goto err_out_led_off;
3228
3229 if (using_dac)
3230 dev->features |= NETIF_F_HIGHDMA;
3231
3232 if ((err = register_netdev(dev))) {
3233 printk(KERN_ERR PFX "%s: cannot register net device\n",
3234 pci_name(pdev));
3235 goto err_out_free_netdev;
3236 }
3237
3238 skge_show_addr(dev);
3239
3240 if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) {
3241 if (using_dac)
3242 dev1->features |= NETIF_F_HIGHDMA;
3243
3244 if (register_netdev(dev1) == 0)
3245 skge_show_addr(dev1);
3246 else {
3247 /* Failure to register second port need not be fatal */
3248 printk(KERN_WARNING PFX "register of second port failed\n");
3249 hw->dev[1] = NULL;
3250 free_netdev(dev1);
3251 }
3252 }
3253
3254 return 0;
3255
3256err_out_free_netdev:
3257 free_netdev(dev);
3258err_out_led_off:
3259 skge_write16(hw, B0_LED, LED_STAT_OFF);
3260err_out_free_irq:
3261 free_irq(pdev->irq, hw);
3262err_out_iounmap:
3263 iounmap(hw->regs);
3264err_out_free_hw:
3265 kfree(hw);
3266err_out_free_regions:
3267 pci_release_regions(pdev);
3268err_out_disable_pdev:
3269 pci_disable_device(pdev);
3270 pci_set_drvdata(pdev, NULL);
3271err_out:
3272 return err;
3273}
3274
3275static void __devexit skge_remove(struct pci_dev *pdev)
3276{
3277 struct skge_hw *hw = pci_get_drvdata(pdev);
3278 struct net_device *dev0, *dev1;
3279
95566065 3280 if (!hw)
baef58b1
SH		 3281 return;
3282
3283 if ((dev1 = hw->dev[1]))
3284 unregister_netdev(dev1);
3285 dev0 = hw->dev[0];
3286 unregister_netdev(dev0);
3287
3288 tasklet_kill(&hw->ext_tasklet);
3289
3290 free_irq(pdev->irq, hw);
3291 pci_release_regions(pdev);
3292 pci_disable_device(pdev);
3293 if (dev1)
3294 free_netdev(dev1);
3295 free_netdev(dev0);
3296 skge_write16(hw, B0_LED, LED_STAT_OFF);
3297 iounmap(hw->regs);
3298 kfree(hw);
3299 pci_set_drvdata(pdev, NULL);
3300}
3301
3302#ifdef CONFIG_PM
3303static int skge_suspend(struct pci_dev *pdev, u32 state)
3304{
3305 struct skge_hw *hw = pci_get_drvdata(pdev);
3306 int i, wol = 0;
3307
95566065 3308 for (i = 0; i < 2; i++) {
baef58b1
SH		 3309 struct net_device *dev = hw->dev[i];
3310
3311 if (dev) {
3312 struct skge_port *skge = netdev_priv(dev);
3313 if (netif_running(dev)) {
3314 netif_carrier_off(dev);
3315 skge_down(dev);
3316 }
3317 netif_device_detach(dev);
3318 wol |= skge->wol;
3319 }
3320 }
3321
3322 pci_save_state(pdev);
3323 pci_enable_wake(pdev, state, wol);
3324 pci_disable_device(pdev);
3325 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3326
3327 return 0;
3328}
3329
3330static int skge_resume(struct pci_dev *pdev)
3331{
3332 struct skge_hw *hw = pci_get_drvdata(pdev);
3333 int i;
3334
3335 pci_set_power_state(pdev, PCI_D0);
3336 pci_restore_state(pdev);
3337 pci_enable_wake(pdev, PCI_D0, 0);
3338
3339 skge_reset(hw);
3340
95566065 3341 for (i = 0; i < 2; i++) {
baef58b1
SH		 3342 struct net_device *dev = hw->dev[i];
3343 if (dev) {
3344 netif_device_attach(dev);
95566065 3345 if (netif_running(dev))
baef58b1
SH		 3346 skge_up(dev);
3347 }
3348 }
3349 return 0;
3350}
3351#endif
3352
3353static struct pci_driver skge_driver = {
3354 .name = DRV_NAME,
3355 .id_table = skge_id_table,
3356 .probe = skge_probe,
3357 .remove = __devexit_p(skge_remove),
3358#ifdef CONFIG_PM
3359 .suspend = skge_suspend,
3360 .resume = skge_resume,
3361#endif
3362};
3363
3364static int __init skge_init_module(void)
3365{
3366 return pci_module_init(&skge_driver);
3367}
3368
3369static void __exit skge_cleanup_module(void)
3370{
3371 pci_unregister_driver(&skge_driver);
3372}
3373
3374module_init(skge_init_module);
3375module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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