Commit | Line | Data |
---|---|---|
baef58b1 SH |
1 | /* |
2 | * New driver for Marvell Yukon chipset and SysKonnect Gigabit | |
3 | * Ethernet adapters. Based on earlier sk98lin, e100 and | |
4 | * FreeBSD if_sk drivers. | |
5 | * | |
6 | * This driver intentionally does not support all the features | |
7 | * of the original driver such as link fail-over and link management because | |
8 | * those should be done at higher levels. | |
9 | * | |
747802ab | 10 | * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> |
baef58b1 SH |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 14 | * the Free Software Foundation; either version 2 of the License. |
baef58b1 SH |
15 | * |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
14c85021 | 26 | #include <linux/in.h> |
baef58b1 SH |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
29 | #include <linux/moduleparam.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/if_vlan.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/crc32.h> | |
4075400b | 38 | #include <linux/dma-mapping.h> |
2cd8e5d3 | 39 | #include <linux/mii.h> |
baef58b1 SH |
40 | #include <asm/irq.h> |
41 | ||
42 | #include "skge.h" | |
43 | ||
44 | #define DRV_NAME "skge" | |
a5f8f3b6 | 45 | #define DRV_VERSION "1.11" |
baef58b1 SH |
46 | #define PFX DRV_NAME " " |
47 | ||
48 | #define DEFAULT_TX_RING_SIZE 128 | |
49 | #define DEFAULT_RX_RING_SIZE 512 | |
50 | #define MAX_TX_RING_SIZE 1024 | |
9db96479 | 51 | #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) |
baef58b1 | 52 | #define MAX_RX_RING_SIZE 4096 |
19a33d4e SH |
53 | #define RX_COPY_THRESHOLD 128 |
54 | #define RX_BUF_SIZE 1536 | |
baef58b1 SH |
55 | #define PHY_RETRIES 1000 |
56 | #define ETH_JUMBO_MTU 9000 | |
57 | #define TX_WATCHDOG (5 * HZ) | |
58 | #define NAPI_WEIGHT 64 | |
6abebb53 | 59 | #define BLINK_MS 250 |
64f6b64d | 60 | #define LINK_HZ (HZ/2) |
baef58b1 SH |
61 | |
62 | MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); | |
65ebe634 | 63 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
baef58b1 SH |
64 | MODULE_LICENSE("GPL"); |
65 | MODULE_VERSION(DRV_VERSION); | |
66 | ||
67 | static const u32 default_msg | |
68 | = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK | |
69 | | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN; | |
70 | ||
71 | static int debug = -1; /* defaults above */ | |
72 | module_param(debug, int, 0); | |
73 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
74 | ||
75 | static const struct pci_device_id skge_id_table[] = { | |
275834d1 SH |
76 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) }, |
77 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) }, | |
78 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, | |
79 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, | |
f19841f5 | 80 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) }, |
2d2a3871 | 81 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */ |
275834d1 SH |
82 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, |
83 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ | |
84 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, | |
275834d1 | 85 | { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) }, |
f19841f5 | 86 | { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, |
baef58b1 SH |
87 | { 0 } |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, skge_id_table); | |
90 | ||
91 | static int skge_up(struct net_device *dev); | |
92 | static int skge_down(struct net_device *dev); | |
ee294dcd | 93 | static void skge_phy_reset(struct skge_port *skge); |
513f533e | 94 | static void skge_tx_clean(struct net_device *dev); |
2cd8e5d3 SH |
95 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); |
96 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
baef58b1 SH |
97 | static void genesis_get_stats(struct skge_port *skge, u64 *data); |
98 | static void yukon_get_stats(struct skge_port *skge, u64 *data); | |
99 | static void yukon_init(struct skge_hw *hw, int port); | |
baef58b1 | 100 | static void genesis_mac_init(struct skge_hw *hw, int port); |
45bada65 | 101 | static void genesis_link_up(struct skge_port *skge); |
baef58b1 | 102 | |
7e676d91 | 103 | /* Avoid conditionals by using array */ |
baef58b1 SH |
104 | static const int txqaddr[] = { Q_XA1, Q_XA2 }; |
105 | static const int rxqaddr[] = { Q_R1, Q_R2 }; | |
106 | static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; | |
107 | static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; | |
4ebabfcb SH |
108 | static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; |
109 | static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; | |
baef58b1 | 110 | |
baef58b1 SH |
111 | static int skge_get_regs_len(struct net_device *dev) |
112 | { | |
c3f8be96 | 113 | return 0x4000; |
baef58b1 SH |
114 | } |
115 | ||
116 | /* | |
c3f8be96 SH |
117 | * Returns copy of whole control register region |
118 | * Note: skip RAM address register because accessing it will | |
119 | * cause bus hangs! | |
baef58b1 SH |
120 | */ |
121 | static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
122 | void *p) | |
123 | { | |
124 | const struct skge_port *skge = netdev_priv(dev); | |
baef58b1 | 125 | const void __iomem *io = skge->hw->regs; |
baef58b1 SH |
126 | |
127 | regs->version = 1; | |
c3f8be96 SH |
128 | memset(p, 0, regs->len); |
129 | memcpy_fromio(p, io, B3_RAM_ADDR); | |
baef58b1 | 130 | |
c3f8be96 SH |
131 | memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, |
132 | regs->len - B3_RI_WTO_R1); | |
baef58b1 SH |
133 | } |
134 | ||
8f3f8193 | 135 | /* Wake on Lan only supported on Yukon chips with rev 1 or above */ |
a504e64a | 136 | static u32 wol_supported(const struct skge_hw *hw) |
baef58b1 | 137 | { |
d17ecb23 | 138 | if (hw->chip_id == CHIP_ID_GENESIS) |
a504e64a | 139 | return 0; |
d17ecb23 SH |
140 | |
141 | if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) | |
142 | return 0; | |
143 | ||
144 | return WAKE_MAGIC | WAKE_PHY; | |
a504e64a SH |
145 | } |
146 | ||
147 | static u32 pci_wake_enabled(struct pci_dev *dev) | |
148 | { | |
149 | int pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
150 | u16 value; | |
151 | ||
152 | /* If device doesn't support PM Capabilities, but request is to disable | |
153 | * wake events, it's a nop; otherwise fail */ | |
154 | if (!pm) | |
155 | return 0; | |
156 | ||
157 | pci_read_config_word(dev, pm + PCI_PM_PMC, &value); | |
158 | ||
159 | value &= PCI_PM_CAP_PME_MASK; | |
160 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
161 | ||
162 | return value != 0; | |
163 | } | |
164 | ||
165 | static void skge_wol_init(struct skge_port *skge) | |
166 | { | |
167 | struct skge_hw *hw = skge->hw; | |
168 | int port = skge->port; | |
692412b3 | 169 | u16 ctrl; |
a504e64a | 170 | |
a504e64a SH |
171 | skge_write16(hw, B0_CTST, CS_RST_CLR); |
172 | skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
173 | ||
692412b3 SH |
174 | /* Turn on Vaux */ |
175 | skge_write8(hw, B0_POWER_CTRL, | |
176 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); | |
a504e64a | 177 | |
692412b3 SH |
178 | /* WA code for COMA mode -- clear PHY reset */ |
179 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
180 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | |
181 | u32 reg = skge_read32(hw, B2_GP_IO); | |
182 | reg |= GP_DIR_9; | |
183 | reg &= ~GP_IO_9; | |
184 | skge_write32(hw, B2_GP_IO, reg); | |
185 | } | |
a504e64a | 186 | |
692412b3 SH |
187 | skge_write32(hw, SK_REG(port, GPHY_CTRL), |
188 | GPC_DIS_SLEEP | | |
189 | GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | | |
190 | GPC_ANEG_1 | GPC_RST_SET); | |
a504e64a | 191 | |
692412b3 SH |
192 | skge_write32(hw, SK_REG(port, GPHY_CTRL), |
193 | GPC_DIS_SLEEP | | |
194 | GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | | |
195 | GPC_ANEG_1 | GPC_RST_CLR); | |
196 | ||
197 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
198 | ||
199 | /* Force to 10/100 skge_reset will re-enable on resume */ | |
200 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
201 | PHY_AN_100FULL | PHY_AN_100HALF | | |
202 | PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA); | |
203 | /* no 1000 HD/FD */ | |
204 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); | |
205 | gm_phy_write(hw, port, PHY_MARV_CTRL, | |
206 | PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE | | |
207 | PHY_CT_RE_CFG | PHY_CT_DUP_MD); | |
a504e64a | 208 | |
a504e64a SH |
209 | |
210 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
211 | gma_write16(hw, port, GM_GP_CTRL, | |
212 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
213 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
214 | ||
215 | /* Set WOL address */ | |
216 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
217 | skge->netdev->dev_addr, ETH_ALEN); | |
218 | ||
219 | /* Turn on appropriate WOL control bits */ | |
220 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
221 | ctrl = 0; | |
222 | if (skge->wol & WAKE_PHY) | |
223 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
224 | else | |
225 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
226 | ||
227 | if (skge->wol & WAKE_MAGIC) | |
228 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
229 | else | |
230 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;; | |
231 | ||
232 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
233 | skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
234 | ||
235 | /* block receiver */ | |
236 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
237 | } |
238 | ||
239 | static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
240 | { | |
241 | struct skge_port *skge = netdev_priv(dev); | |
242 | ||
a504e64a SH |
243 | wol->supported = wol_supported(skge->hw); |
244 | wol->wolopts = skge->wol; | |
baef58b1 SH |
245 | } |
246 | ||
247 | static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
248 | { | |
249 | struct skge_port *skge = netdev_priv(dev); | |
250 | struct skge_hw *hw = skge->hw; | |
251 | ||
692412b3 | 252 | if (wol->wolopts & ~wol_supported(hw)) |
baef58b1 SH |
253 | return -EOPNOTSUPP; |
254 | ||
a504e64a | 255 | skge->wol = wol->wolopts; |
baef58b1 SH |
256 | return 0; |
257 | } | |
258 | ||
8f3f8193 SH |
259 | /* Determine supported/advertised modes based on hardware. |
260 | * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx | |
31b619c5 SH |
261 | */ |
262 | static u32 skge_supported_modes(const struct skge_hw *hw) | |
263 | { | |
264 | u32 supported; | |
265 | ||
5e1705dd | 266 | if (hw->copper) { |
31b619c5 SH |
267 | supported = SUPPORTED_10baseT_Half |
268 | | SUPPORTED_10baseT_Full | |
269 | | SUPPORTED_100baseT_Half | |
270 | | SUPPORTED_100baseT_Full | |
271 | | SUPPORTED_1000baseT_Half | |
272 | | SUPPORTED_1000baseT_Full | |
273 | | SUPPORTED_Autoneg| SUPPORTED_TP; | |
274 | ||
275 | if (hw->chip_id == CHIP_ID_GENESIS) | |
276 | supported &= ~(SUPPORTED_10baseT_Half | |
277 | | SUPPORTED_10baseT_Full | |
278 | | SUPPORTED_100baseT_Half | |
279 | | SUPPORTED_100baseT_Full); | |
280 | ||
281 | else if (hw->chip_id == CHIP_ID_YUKON) | |
282 | supported &= ~SUPPORTED_1000baseT_Half; | |
283 | } else | |
4b67be99 SH |
284 | supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half |
285 | | SUPPORTED_FIBRE | SUPPORTED_Autoneg; | |
31b619c5 SH |
286 | |
287 | return supported; | |
288 | } | |
baef58b1 SH |
289 | |
290 | static int skge_get_settings(struct net_device *dev, | |
291 | struct ethtool_cmd *ecmd) | |
292 | { | |
293 | struct skge_port *skge = netdev_priv(dev); | |
294 | struct skge_hw *hw = skge->hw; | |
295 | ||
296 | ecmd->transceiver = XCVR_INTERNAL; | |
31b619c5 | 297 | ecmd->supported = skge_supported_modes(hw); |
baef58b1 | 298 | |
5e1705dd | 299 | if (hw->copper) { |
baef58b1 SH |
300 | ecmd->port = PORT_TP; |
301 | ecmd->phy_address = hw->phy_addr; | |
31b619c5 | 302 | } else |
baef58b1 | 303 | ecmd->port = PORT_FIBRE; |
baef58b1 SH |
304 | |
305 | ecmd->advertising = skge->advertising; | |
306 | ecmd->autoneg = skge->autoneg; | |
307 | ecmd->speed = skge->speed; | |
308 | ecmd->duplex = skge->duplex; | |
309 | return 0; | |
310 | } | |
311 | ||
baef58b1 SH |
312 | static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
313 | { | |
314 | struct skge_port *skge = netdev_priv(dev); | |
315 | const struct skge_hw *hw = skge->hw; | |
31b619c5 | 316 | u32 supported = skge_supported_modes(hw); |
baef58b1 SH |
317 | |
318 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
31b619c5 SH |
319 | ecmd->advertising = supported; |
320 | skge->duplex = -1; | |
321 | skge->speed = -1; | |
baef58b1 | 322 | } else { |
31b619c5 SH |
323 | u32 setting; |
324 | ||
2c668514 | 325 | switch (ecmd->speed) { |
baef58b1 | 326 | case SPEED_1000: |
31b619c5 SH |
327 | if (ecmd->duplex == DUPLEX_FULL) |
328 | setting = SUPPORTED_1000baseT_Full; | |
329 | else if (ecmd->duplex == DUPLEX_HALF) | |
330 | setting = SUPPORTED_1000baseT_Half; | |
331 | else | |
332 | return -EINVAL; | |
baef58b1 SH |
333 | break; |
334 | case SPEED_100: | |
31b619c5 SH |
335 | if (ecmd->duplex == DUPLEX_FULL) |
336 | setting = SUPPORTED_100baseT_Full; | |
337 | else if (ecmd->duplex == DUPLEX_HALF) | |
338 | setting = SUPPORTED_100baseT_Half; | |
339 | else | |
340 | return -EINVAL; | |
341 | break; | |
342 | ||
baef58b1 | 343 | case SPEED_10: |
31b619c5 SH |
344 | if (ecmd->duplex == DUPLEX_FULL) |
345 | setting = SUPPORTED_10baseT_Full; | |
346 | else if (ecmd->duplex == DUPLEX_HALF) | |
347 | setting = SUPPORTED_10baseT_Half; | |
348 | else | |
baef58b1 SH |
349 | return -EINVAL; |
350 | break; | |
351 | default: | |
352 | return -EINVAL; | |
353 | } | |
31b619c5 SH |
354 | |
355 | if ((setting & supported) == 0) | |
356 | return -EINVAL; | |
357 | ||
358 | skge->speed = ecmd->speed; | |
359 | skge->duplex = ecmd->duplex; | |
baef58b1 SH |
360 | } |
361 | ||
362 | skge->autoneg = ecmd->autoneg; | |
baef58b1 SH |
363 | skge->advertising = ecmd->advertising; |
364 | ||
ee294dcd SH |
365 | if (netif_running(dev)) |
366 | skge_phy_reset(skge); | |
367 | ||
baef58b1 SH |
368 | return (0); |
369 | } | |
370 | ||
371 | static void skge_get_drvinfo(struct net_device *dev, | |
372 | struct ethtool_drvinfo *info) | |
373 | { | |
374 | struct skge_port *skge = netdev_priv(dev); | |
375 | ||
376 | strcpy(info->driver, DRV_NAME); | |
377 | strcpy(info->version, DRV_VERSION); | |
378 | strcpy(info->fw_version, "N/A"); | |
379 | strcpy(info->bus_info, pci_name(skge->hw->pdev)); | |
380 | } | |
381 | ||
382 | static const struct skge_stat { | |
383 | char name[ETH_GSTRING_LEN]; | |
384 | u16 xmac_offset; | |
385 | u16 gma_offset; | |
386 | } skge_stats[] = { | |
387 | { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, | |
388 | { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, | |
389 | ||
390 | { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, | |
391 | { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, | |
392 | { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, | |
393 | { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, | |
394 | { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, | |
395 | { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, | |
396 | { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, | |
397 | { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, | |
398 | ||
399 | { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, | |
400 | { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, | |
401 | { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, | |
402 | { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, | |
403 | { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, | |
404 | { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, | |
405 | ||
406 | { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
407 | { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, | |
408 | { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, | |
409 | { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
410 | { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, | |
411 | }; | |
412 | ||
413 | static int skge_get_stats_count(struct net_device *dev) | |
414 | { | |
415 | return ARRAY_SIZE(skge_stats); | |
416 | } | |
417 | ||
418 | static void skge_get_ethtool_stats(struct net_device *dev, | |
419 | struct ethtool_stats *stats, u64 *data) | |
420 | { | |
421 | struct skge_port *skge = netdev_priv(dev); | |
422 | ||
423 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
424 | genesis_get_stats(skge, data); | |
425 | else | |
426 | yukon_get_stats(skge, data); | |
427 | } | |
428 | ||
429 | /* Use hardware MIB variables for critical path statistics and | |
430 | * transmit feedback not reported at interrupt. | |
431 | * Other errors are accounted for in interrupt handler. | |
432 | */ | |
433 | static struct net_device_stats *skge_get_stats(struct net_device *dev) | |
434 | { | |
435 | struct skge_port *skge = netdev_priv(dev); | |
436 | u64 data[ARRAY_SIZE(skge_stats)]; | |
437 | ||
438 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
439 | genesis_get_stats(skge, data); | |
440 | else | |
441 | yukon_get_stats(skge, data); | |
442 | ||
443 | skge->net_stats.tx_bytes = data[0]; | |
444 | skge->net_stats.rx_bytes = data[1]; | |
445 | skge->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
446 | skge->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
4c180fc4 | 447 | skge->net_stats.multicast = data[3] + data[5]; |
baef58b1 SH |
448 | skge->net_stats.collisions = data[10]; |
449 | skge->net_stats.tx_aborted_errors = data[12]; | |
450 | ||
451 | return &skge->net_stats; | |
452 | } | |
453 | ||
454 | static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
455 | { | |
456 | int i; | |
457 | ||
95566065 | 458 | switch (stringset) { |
baef58b1 SH |
459 | case ETH_SS_STATS: |
460 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | |
461 | memcpy(data + i * ETH_GSTRING_LEN, | |
462 | skge_stats[i].name, ETH_GSTRING_LEN); | |
463 | break; | |
464 | } | |
465 | } | |
466 | ||
467 | static void skge_get_ring_param(struct net_device *dev, | |
468 | struct ethtool_ringparam *p) | |
469 | { | |
470 | struct skge_port *skge = netdev_priv(dev); | |
471 | ||
472 | p->rx_max_pending = MAX_RX_RING_SIZE; | |
473 | p->tx_max_pending = MAX_TX_RING_SIZE; | |
474 | p->rx_mini_max_pending = 0; | |
475 | p->rx_jumbo_max_pending = 0; | |
476 | ||
477 | p->rx_pending = skge->rx_ring.count; | |
478 | p->tx_pending = skge->tx_ring.count; | |
479 | p->rx_mini_pending = 0; | |
480 | p->rx_jumbo_pending = 0; | |
481 | } | |
482 | ||
483 | static int skge_set_ring_param(struct net_device *dev, | |
484 | struct ethtool_ringparam *p) | |
485 | { | |
486 | struct skge_port *skge = netdev_priv(dev); | |
3b8bb472 | 487 | int err; |
baef58b1 SH |
488 | |
489 | if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || | |
9db96479 | 490 | p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) |
baef58b1 SH |
491 | return -EINVAL; |
492 | ||
493 | skge->rx_ring.count = p->rx_pending; | |
494 | skge->tx_ring.count = p->tx_pending; | |
495 | ||
496 | if (netif_running(dev)) { | |
497 | skge_down(dev); | |
3b8bb472 SH |
498 | err = skge_up(dev); |
499 | if (err) | |
500 | dev_close(dev); | |
baef58b1 SH |
501 | } |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static u32 skge_get_msglevel(struct net_device *netdev) | |
507 | { | |
508 | struct skge_port *skge = netdev_priv(netdev); | |
509 | return skge->msg_enable; | |
510 | } | |
511 | ||
512 | static void skge_set_msglevel(struct net_device *netdev, u32 value) | |
513 | { | |
514 | struct skge_port *skge = netdev_priv(netdev); | |
515 | skge->msg_enable = value; | |
516 | } | |
517 | ||
518 | static int skge_nway_reset(struct net_device *dev) | |
519 | { | |
520 | struct skge_port *skge = netdev_priv(dev); | |
baef58b1 SH |
521 | |
522 | if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) | |
523 | return -EINVAL; | |
524 | ||
ee294dcd | 525 | skge_phy_reset(skge); |
baef58b1 SH |
526 | return 0; |
527 | } | |
528 | ||
529 | static int skge_set_sg(struct net_device *dev, u32 data) | |
530 | { | |
531 | struct skge_port *skge = netdev_priv(dev); | |
532 | struct skge_hw *hw = skge->hw; | |
533 | ||
534 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
535 | return -EOPNOTSUPP; | |
536 | return ethtool_op_set_sg(dev, data); | |
537 | } | |
538 | ||
539 | static int skge_set_tx_csum(struct net_device *dev, u32 data) | |
540 | { | |
541 | struct skge_port *skge = netdev_priv(dev); | |
542 | struct skge_hw *hw = skge->hw; | |
543 | ||
544 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
545 | return -EOPNOTSUPP; | |
546 | ||
547 | return ethtool_op_set_tx_csum(dev, data); | |
548 | } | |
549 | ||
550 | static u32 skge_get_rx_csum(struct net_device *dev) | |
551 | { | |
552 | struct skge_port *skge = netdev_priv(dev); | |
553 | ||
554 | return skge->rx_csum; | |
555 | } | |
556 | ||
557 | /* Only Yukon supports checksum offload. */ | |
558 | static int skge_set_rx_csum(struct net_device *dev, u32 data) | |
559 | { | |
560 | struct skge_port *skge = netdev_priv(dev); | |
561 | ||
562 | if (skge->hw->chip_id == CHIP_ID_GENESIS && data) | |
563 | return -EOPNOTSUPP; | |
564 | ||
565 | skge->rx_csum = data; | |
566 | return 0; | |
567 | } | |
568 | ||
baef58b1 SH |
569 | static void skge_get_pauseparam(struct net_device *dev, |
570 | struct ethtool_pauseparam *ecmd) | |
571 | { | |
572 | struct skge_port *skge = netdev_priv(dev); | |
573 | ||
5d5c8e03 SH |
574 | ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC) |
575 | || (skge->flow_control == FLOW_MODE_SYM_OR_REM); | |
576 | ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND); | |
baef58b1 | 577 | |
5d5c8e03 | 578 | ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; |
baef58b1 SH |
579 | } |
580 | ||
581 | static int skge_set_pauseparam(struct net_device *dev, | |
582 | struct ethtool_pauseparam *ecmd) | |
583 | { | |
584 | struct skge_port *skge = netdev_priv(dev); | |
5d5c8e03 | 585 | struct ethtool_pauseparam old; |
baef58b1 | 586 | |
5d5c8e03 SH |
587 | skge_get_pauseparam(dev, &old); |
588 | ||
589 | if (ecmd->autoneg != old.autoneg) | |
590 | skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; | |
591 | else { | |
592 | if (ecmd->rx_pause && ecmd->tx_pause) | |
593 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
594 | else if (ecmd->rx_pause && !ecmd->tx_pause) | |
595 | skge->flow_control = FLOW_MODE_SYM_OR_REM; | |
596 | else if (!ecmd->rx_pause && ecmd->tx_pause) | |
597 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
598 | else | |
599 | skge->flow_control = FLOW_MODE_NONE; | |
600 | } | |
baef58b1 | 601 | |
e8df8554 SH |
602 | if (netif_running(dev)) |
603 | skge_phy_reset(skge); | |
5d5c8e03 | 604 | |
baef58b1 SH |
605 | return 0; |
606 | } | |
607 | ||
608 | /* Chip internal frequency for clock calculations */ | |
609 | static inline u32 hwkhz(const struct skge_hw *hw) | |
610 | { | |
187ff3b8 | 611 | return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; |
baef58b1 SH |
612 | } |
613 | ||
8f3f8193 | 614 | /* Chip HZ to microseconds */ |
baef58b1 SH |
615 | static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) |
616 | { | |
617 | return (ticks * 1000) / hwkhz(hw); | |
618 | } | |
619 | ||
8f3f8193 | 620 | /* Microseconds to chip HZ */ |
baef58b1 SH |
621 | static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) |
622 | { | |
623 | return hwkhz(hw) * usec / 1000; | |
624 | } | |
625 | ||
626 | static int skge_get_coalesce(struct net_device *dev, | |
627 | struct ethtool_coalesce *ecmd) | |
628 | { | |
629 | struct skge_port *skge = netdev_priv(dev); | |
630 | struct skge_hw *hw = skge->hw; | |
631 | int port = skge->port; | |
632 | ||
633 | ecmd->rx_coalesce_usecs = 0; | |
634 | ecmd->tx_coalesce_usecs = 0; | |
635 | ||
636 | if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { | |
637 | u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); | |
638 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
639 | ||
640 | if (msk & rxirqmask[port]) | |
641 | ecmd->rx_coalesce_usecs = delay; | |
642 | if (msk & txirqmask[port]) | |
643 | ecmd->tx_coalesce_usecs = delay; | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | /* Note: interrupt timer is per board, but can turn on/off per port */ | |
650 | static int skge_set_coalesce(struct net_device *dev, | |
651 | struct ethtool_coalesce *ecmd) | |
652 | { | |
653 | struct skge_port *skge = netdev_priv(dev); | |
654 | struct skge_hw *hw = skge->hw; | |
655 | int port = skge->port; | |
656 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
657 | u32 delay = 25; | |
658 | ||
659 | if (ecmd->rx_coalesce_usecs == 0) | |
660 | msk &= ~rxirqmask[port]; | |
661 | else if (ecmd->rx_coalesce_usecs < 25 || | |
662 | ecmd->rx_coalesce_usecs > 33333) | |
663 | return -EINVAL; | |
664 | else { | |
665 | msk |= rxirqmask[port]; | |
666 | delay = ecmd->rx_coalesce_usecs; | |
667 | } | |
668 | ||
669 | if (ecmd->tx_coalesce_usecs == 0) | |
670 | msk &= ~txirqmask[port]; | |
671 | else if (ecmd->tx_coalesce_usecs < 25 || | |
672 | ecmd->tx_coalesce_usecs > 33333) | |
673 | return -EINVAL; | |
674 | else { | |
675 | msk |= txirqmask[port]; | |
676 | delay = min(delay, ecmd->rx_coalesce_usecs); | |
677 | } | |
678 | ||
679 | skge_write32(hw, B2_IRQM_MSK, msk); | |
680 | if (msk == 0) | |
681 | skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); | |
682 | else { | |
683 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); | |
684 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
685 | } | |
686 | return 0; | |
687 | } | |
688 | ||
6abebb53 SH |
689 | enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; |
690 | static void skge_led(struct skge_port *skge, enum led_mode mode) | |
baef58b1 | 691 | { |
6abebb53 SH |
692 | struct skge_hw *hw = skge->hw; |
693 | int port = skge->port; | |
694 | ||
9cbe330f | 695 | spin_lock_bh(&hw->phy_lock); |
baef58b1 | 696 | if (hw->chip_id == CHIP_ID_GENESIS) { |
6abebb53 SH |
697 | switch (mode) { |
698 | case LED_MODE_OFF: | |
64f6b64d SH |
699 | if (hw->phy_type == SK_PHY_BCOM) |
700 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); | |
701 | else { | |
702 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); | |
703 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); | |
704 | } | |
6abebb53 SH |
705 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
706 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); | |
707 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); | |
708 | break; | |
baef58b1 | 709 | |
6abebb53 SH |
710 | case LED_MODE_ON: |
711 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); | |
712 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); | |
baef58b1 | 713 | |
6abebb53 SH |
714 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); |
715 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
baef58b1 | 716 | |
6abebb53 | 717 | break; |
baef58b1 | 718 | |
6abebb53 SH |
719 | case LED_MODE_TST: |
720 | skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); | |
721 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); | |
722 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); | |
baef58b1 | 723 | |
64f6b64d SH |
724 | if (hw->phy_type == SK_PHY_BCOM) |
725 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); | |
726 | else { | |
727 | skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); | |
728 | skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); | |
729 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
730 | } | |
731 | ||
6abebb53 | 732 | } |
baef58b1 | 733 | } else { |
6abebb53 SH |
734 | switch (mode) { |
735 | case LED_MODE_OFF: | |
736 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
737 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
738 | PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
739 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
740 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
741 | PHY_M_LED_MO_1000(MO_LED_OFF) | | |
742 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
743 | break; | |
744 | case LED_MODE_ON: | |
745 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, | |
746 | PHY_M_LED_PULS_DUR(PULS_170MS) | | |
747 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | |
748 | PHY_M_LEDC_TX_CTRL | | |
749 | PHY_M_LEDC_DP_CTRL); | |
46a60f2d | 750 | |
6abebb53 SH |
751 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
752 | PHY_M_LED_MO_RX(MO_LED_OFF) | | |
753 | (skge->speed == SPEED_100 ? | |
754 | PHY_M_LED_MO_100(MO_LED_ON) : 0)); | |
755 | break; | |
756 | case LED_MODE_TST: | |
757 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
758 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
759 | PHY_M_LED_MO_DUP(MO_LED_ON) | | |
760 | PHY_M_LED_MO_10(MO_LED_ON) | | |
761 | PHY_M_LED_MO_100(MO_LED_ON) | | |
762 | PHY_M_LED_MO_1000(MO_LED_ON) | | |
763 | PHY_M_LED_MO_RX(MO_LED_ON)); | |
764 | } | |
baef58b1 | 765 | } |
9cbe330f | 766 | spin_unlock_bh(&hw->phy_lock); |
baef58b1 SH |
767 | } |
768 | ||
769 | /* blink LED's for finding board */ | |
770 | static int skge_phys_id(struct net_device *dev, u32 data) | |
771 | { | |
772 | struct skge_port *skge = netdev_priv(dev); | |
6abebb53 SH |
773 | unsigned long ms; |
774 | enum led_mode mode = LED_MODE_TST; | |
baef58b1 | 775 | |
95566065 | 776 | if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) |
6abebb53 SH |
777 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000; |
778 | else | |
779 | ms = data * 1000; | |
baef58b1 | 780 | |
6abebb53 SH |
781 | while (ms > 0) { |
782 | skge_led(skge, mode); | |
783 | mode ^= LED_MODE_TST; | |
baef58b1 | 784 | |
6abebb53 SH |
785 | if (msleep_interruptible(BLINK_MS)) |
786 | break; | |
787 | ms -= BLINK_MS; | |
788 | } | |
baef58b1 | 789 | |
6abebb53 SH |
790 | /* back to regular LED state */ |
791 | skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); | |
baef58b1 SH |
792 | |
793 | return 0; | |
794 | } | |
795 | ||
7282d491 | 796 | static const struct ethtool_ops skge_ethtool_ops = { |
baef58b1 SH |
797 | .get_settings = skge_get_settings, |
798 | .set_settings = skge_set_settings, | |
799 | .get_drvinfo = skge_get_drvinfo, | |
800 | .get_regs_len = skge_get_regs_len, | |
801 | .get_regs = skge_get_regs, | |
802 | .get_wol = skge_get_wol, | |
803 | .set_wol = skge_set_wol, | |
804 | .get_msglevel = skge_get_msglevel, | |
805 | .set_msglevel = skge_set_msglevel, | |
806 | .nway_reset = skge_nway_reset, | |
807 | .get_link = ethtool_op_get_link, | |
808 | .get_ringparam = skge_get_ring_param, | |
809 | .set_ringparam = skge_set_ring_param, | |
810 | .get_pauseparam = skge_get_pauseparam, | |
811 | .set_pauseparam = skge_set_pauseparam, | |
812 | .get_coalesce = skge_get_coalesce, | |
813 | .set_coalesce = skge_set_coalesce, | |
baef58b1 | 814 | .set_sg = skge_set_sg, |
baef58b1 SH |
815 | .set_tx_csum = skge_set_tx_csum, |
816 | .get_rx_csum = skge_get_rx_csum, | |
817 | .set_rx_csum = skge_set_rx_csum, | |
818 | .get_strings = skge_get_strings, | |
819 | .phys_id = skge_phys_id, | |
820 | .get_stats_count = skge_get_stats_count, | |
821 | .get_ethtool_stats = skge_get_ethtool_stats, | |
822 | }; | |
823 | ||
824 | /* | |
825 | * Allocate ring elements and chain them together | |
826 | * One-to-one association of board descriptors with ring elements | |
827 | */ | |
c3da1447 | 828 | static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) |
baef58b1 SH |
829 | { |
830 | struct skge_tx_desc *d; | |
831 | struct skge_element *e; | |
832 | int i; | |
833 | ||
cd861280 | 834 | ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); |
baef58b1 SH |
835 | if (!ring->start) |
836 | return -ENOMEM; | |
837 | ||
838 | for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { | |
839 | e->desc = d; | |
840 | if (i == ring->count - 1) { | |
841 | e->next = ring->start; | |
842 | d->next_offset = base; | |
843 | } else { | |
844 | e->next = e + 1; | |
845 | d->next_offset = base + (i+1) * sizeof(*d); | |
846 | } | |
847 | } | |
848 | ring->to_use = ring->to_clean = ring->start; | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
19a33d4e SH |
853 | /* Allocate and setup a new buffer for receiving */ |
854 | static void skge_rx_setup(struct skge_port *skge, struct skge_element *e, | |
855 | struct sk_buff *skb, unsigned int bufsize) | |
856 | { | |
857 | struct skge_rx_desc *rd = e->desc; | |
858 | u64 map; | |
baef58b1 SH |
859 | |
860 | map = pci_map_single(skge->hw->pdev, skb->data, bufsize, | |
861 | PCI_DMA_FROMDEVICE); | |
862 | ||
863 | rd->dma_lo = map; | |
864 | rd->dma_hi = map >> 32; | |
865 | e->skb = skb; | |
866 | rd->csum1_start = ETH_HLEN; | |
867 | rd->csum2_start = ETH_HLEN; | |
868 | rd->csum1 = 0; | |
869 | rd->csum2 = 0; | |
870 | ||
871 | wmb(); | |
872 | ||
873 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; | |
874 | pci_unmap_addr_set(e, mapaddr, map); | |
875 | pci_unmap_len_set(e, maplen, bufsize); | |
baef58b1 SH |
876 | } |
877 | ||
19a33d4e SH |
878 | /* Resume receiving using existing skb, |
879 | * Note: DMA address is not changed by chip. | |
880 | * MTU not changed while receiver active. | |
881 | */ | |
5a011447 | 882 | static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) |
19a33d4e SH |
883 | { |
884 | struct skge_rx_desc *rd = e->desc; | |
885 | ||
886 | rd->csum2 = 0; | |
887 | rd->csum2_start = ETH_HLEN; | |
888 | ||
889 | wmb(); | |
890 | ||
891 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; | |
892 | } | |
893 | ||
894 | ||
895 | /* Free all buffers in receive ring, assumes receiver stopped */ | |
baef58b1 SH |
896 | static void skge_rx_clean(struct skge_port *skge) |
897 | { | |
898 | struct skge_hw *hw = skge->hw; | |
899 | struct skge_ring *ring = &skge->rx_ring; | |
900 | struct skge_element *e; | |
901 | ||
19a33d4e SH |
902 | e = ring->start; |
903 | do { | |
baef58b1 SH |
904 | struct skge_rx_desc *rd = e->desc; |
905 | rd->control = 0; | |
19a33d4e SH |
906 | if (e->skb) { |
907 | pci_unmap_single(hw->pdev, | |
908 | pci_unmap_addr(e, mapaddr), | |
909 | pci_unmap_len(e, maplen), | |
910 | PCI_DMA_FROMDEVICE); | |
911 | dev_kfree_skb(e->skb); | |
912 | e->skb = NULL; | |
913 | } | |
914 | } while ((e = e->next) != ring->start); | |
baef58b1 SH |
915 | } |
916 | ||
19a33d4e | 917 | |
baef58b1 | 918 | /* Allocate buffers for receive ring |
19a33d4e | 919 | * For receive: to_clean is next received frame. |
baef58b1 | 920 | */ |
c54f9765 | 921 | static int skge_rx_fill(struct net_device *dev) |
baef58b1 | 922 | { |
c54f9765 | 923 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 SH |
924 | struct skge_ring *ring = &skge->rx_ring; |
925 | struct skge_element *e; | |
baef58b1 | 926 | |
19a33d4e SH |
927 | e = ring->start; |
928 | do { | |
383181ac | 929 | struct sk_buff *skb; |
baef58b1 | 930 | |
c54f9765 SH |
931 | skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, |
932 | GFP_KERNEL); | |
19a33d4e SH |
933 | if (!skb) |
934 | return -ENOMEM; | |
935 | ||
383181ac SH |
936 | skb_reserve(skb, NET_IP_ALIGN); |
937 | skge_rx_setup(skge, e, skb, skge->rx_buf_size); | |
19a33d4e | 938 | } while ( (e = e->next) != ring->start); |
baef58b1 | 939 | |
19a33d4e SH |
940 | ring->to_clean = ring->start; |
941 | return 0; | |
baef58b1 SH |
942 | } |
943 | ||
5d5c8e03 SH |
944 | static const char *skge_pause(enum pause_status status) |
945 | { | |
946 | switch(status) { | |
947 | case FLOW_STAT_NONE: | |
948 | return "none"; | |
949 | case FLOW_STAT_REM_SEND: | |
950 | return "rx only"; | |
951 | case FLOW_STAT_LOC_SEND: | |
952 | return "tx_only"; | |
953 | case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ | |
954 | return "both"; | |
955 | default: | |
956 | return "indeterminated"; | |
957 | } | |
958 | } | |
959 | ||
960 | ||
baef58b1 SH |
961 | static void skge_link_up(struct skge_port *skge) |
962 | { | |
46a60f2d | 963 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
54cfb5aa SH |
964 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
965 | ||
baef58b1 | 966 | netif_carrier_on(skge->netdev); |
29b4e886 | 967 | netif_wake_queue(skge->netdev); |
baef58b1 | 968 | |
5d5c8e03 | 969 | if (netif_msg_link(skge)) { |
baef58b1 SH |
970 | printk(KERN_INFO PFX |
971 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", | |
972 | skge->netdev->name, skge->speed, | |
973 | skge->duplex == DUPLEX_FULL ? "full" : "half", | |
5d5c8e03 SH |
974 | skge_pause(skge->flow_status)); |
975 | } | |
baef58b1 SH |
976 | } |
977 | ||
978 | static void skge_link_down(struct skge_port *skge) | |
979 | { | |
54cfb5aa | 980 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
baef58b1 SH |
981 | netif_carrier_off(skge->netdev); |
982 | netif_stop_queue(skge->netdev); | |
983 | ||
984 | if (netif_msg_link(skge)) | |
985 | printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); | |
986 | } | |
987 | ||
a1bc9b87 SH |
988 | |
989 | static void xm_link_down(struct skge_hw *hw, int port) | |
990 | { | |
991 | struct net_device *dev = hw->dev[port]; | |
992 | struct skge_port *skge = netdev_priv(dev); | |
993 | u16 cmd, msk; | |
994 | ||
995 | if (hw->phy_type == SK_PHY_XMAC) { | |
996 | msk = xm_read16(hw, port, XM_IMSK); | |
997 | msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND; | |
998 | xm_write16(hw, port, XM_IMSK, msk); | |
999 | } | |
1000 | ||
1001 | cmd = xm_read16(hw, port, XM_MMU_CMD); | |
1002 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | |
1003 | xm_write16(hw, port, XM_MMU_CMD, cmd); | |
1004 | /* dummy read to ensure writing */ | |
1005 | (void) xm_read16(hw, port, XM_MMU_CMD); | |
1006 | ||
1007 | if (netif_carrier_ok(dev)) | |
1008 | skge_link_down(skge); | |
1009 | } | |
1010 | ||
2cd8e5d3 | 1011 | static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) |
baef58b1 SH |
1012 | { |
1013 | int i; | |
baef58b1 | 1014 | |
6b0c1480 | 1015 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
0781191c | 1016 | *val = xm_read16(hw, port, XM_PHY_DATA); |
baef58b1 | 1017 | |
64f6b64d SH |
1018 | if (hw->phy_type == SK_PHY_XMAC) |
1019 | goto ready; | |
1020 | ||
89bf5f23 | 1021 | for (i = 0; i < PHY_RETRIES; i++) { |
2cd8e5d3 | 1022 | if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) |
89bf5f23 | 1023 | goto ready; |
0781191c | 1024 | udelay(1); |
baef58b1 SH |
1025 | } |
1026 | ||
2cd8e5d3 | 1027 | return -ETIMEDOUT; |
89bf5f23 | 1028 | ready: |
2cd8e5d3 | 1029 | *val = xm_read16(hw, port, XM_PHY_DATA); |
89bf5f23 | 1030 | |
2cd8e5d3 SH |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1035 | { | |
1036 | u16 v = 0; | |
1037 | if (__xm_phy_read(hw, port, reg, &v)) | |
1038 | printk(KERN_WARNING PFX "%s: phy read timed out\n", | |
1039 | hw->dev[port]->name); | |
baef58b1 SH |
1040 | return v; |
1041 | } | |
1042 | ||
2cd8e5d3 | 1043 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
baef58b1 SH |
1044 | { |
1045 | int i; | |
1046 | ||
6b0c1480 | 1047 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
baef58b1 | 1048 | for (i = 0; i < PHY_RETRIES; i++) { |
6b0c1480 | 1049 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) |
baef58b1 | 1050 | goto ready; |
89bf5f23 | 1051 | udelay(1); |
baef58b1 | 1052 | } |
2cd8e5d3 | 1053 | return -EIO; |
baef58b1 SH |
1054 | |
1055 | ready: | |
6b0c1480 | 1056 | xm_write16(hw, port, XM_PHY_DATA, val); |
0781191c SH |
1057 | for (i = 0; i < PHY_RETRIES; i++) { |
1058 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
1059 | return 0; | |
1060 | udelay(1); | |
1061 | } | |
1062 | return -ETIMEDOUT; | |
baef58b1 SH |
1063 | } |
1064 | ||
1065 | static void genesis_init(struct skge_hw *hw) | |
1066 | { | |
1067 | /* set blink source counter */ | |
1068 | skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); | |
1069 | skge_write8(hw, B2_BSC_CTRL, BSC_START); | |
1070 | ||
1071 | /* configure mac arbiter */ | |
1072 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1073 | ||
1074 | /* configure mac arbiter timeout values */ | |
1075 | skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); | |
1076 | skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); | |
1077 | skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); | |
1078 | skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); | |
1079 | ||
1080 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1081 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1082 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1083 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1084 | ||
1085 | /* configure packet arbiter timeout */ | |
1086 | skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); | |
1087 | skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); | |
1088 | skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); | |
1089 | skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); | |
1090 | skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); | |
1091 | } | |
1092 | ||
1093 | static void genesis_reset(struct skge_hw *hw, int port) | |
1094 | { | |
45bada65 | 1095 | const u8 zero[8] = { 0 }; |
baef58b1 | 1096 | |
46a60f2d SH |
1097 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1098 | ||
baef58b1 | 1099 | /* reset the statistics module */ |
6b0c1480 SH |
1100 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
1101 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | |
1102 | xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ | |
1103 | xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ | |
1104 | xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ | |
baef58b1 | 1105 | |
89bf5f23 | 1106 | /* disable Broadcom PHY IRQ */ |
64f6b64d SH |
1107 | if (hw->phy_type == SK_PHY_BCOM) |
1108 | xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); | |
baef58b1 | 1109 | |
45bada65 | 1110 | xm_outhash(hw, port, XM_HSM, zero); |
baef58b1 SH |
1111 | } |
1112 | ||
1113 | ||
45bada65 SH |
1114 | /* Convert mode to MII values */ |
1115 | static const u16 phy_pause_map[] = { | |
1116 | [FLOW_MODE_NONE] = 0, | |
1117 | [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, | |
1118 | [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, | |
5d5c8e03 | 1119 | [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, |
45bada65 SH |
1120 | }; |
1121 | ||
4b67be99 SH |
1122 | /* special defines for FIBER (88E1011S only) */ |
1123 | static const u16 fiber_pause_map[] = { | |
1124 | [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, | |
1125 | [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, | |
1126 | [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, | |
5d5c8e03 | 1127 | [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, |
4b67be99 SH |
1128 | }; |
1129 | ||
45bada65 SH |
1130 | |
1131 | /* Check status of Broadcom phy link */ | |
1132 | static void bcom_check_link(struct skge_hw *hw, int port) | |
baef58b1 | 1133 | { |
45bada65 SH |
1134 | struct net_device *dev = hw->dev[port]; |
1135 | struct skge_port *skge = netdev_priv(dev); | |
1136 | u16 status; | |
1137 | ||
1138 | /* read twice because of latch */ | |
1139 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); | |
1140 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); | |
1141 | ||
45bada65 | 1142 | if ((status & PHY_ST_LSYNC) == 0) { |
a1bc9b87 | 1143 | xm_link_down(hw, port); |
64f6b64d SH |
1144 | return; |
1145 | } | |
45bada65 | 1146 | |
64f6b64d SH |
1147 | if (skge->autoneg == AUTONEG_ENABLE) { |
1148 | u16 lpa, aux; | |
45bada65 | 1149 | |
64f6b64d SH |
1150 | if (!(status & PHY_ST_AN_OVER)) |
1151 | return; | |
45bada65 | 1152 | |
64f6b64d SH |
1153 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); |
1154 | if (lpa & PHY_B_AN_RF) { | |
1155 | printk(KERN_NOTICE PFX "%s: remote fault\n", | |
1156 | dev->name); | |
1157 | return; | |
1158 | } | |
45bada65 | 1159 | |
64f6b64d SH |
1160 | aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); |
1161 | ||
1162 | /* Check Duplex mismatch */ | |
1163 | switch (aux & PHY_B_AS_AN_RES_MSK) { | |
1164 | case PHY_B_RES_1000FD: | |
1165 | skge->duplex = DUPLEX_FULL; | |
1166 | break; | |
1167 | case PHY_B_RES_1000HD: | |
1168 | skge->duplex = DUPLEX_HALF; | |
1169 | break; | |
1170 | default: | |
1171 | printk(KERN_NOTICE PFX "%s: duplex mismatch\n", | |
1172 | dev->name); | |
1173 | return; | |
45bada65 SH |
1174 | } |
1175 | ||
64f6b64d SH |
1176 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
1177 | switch (aux & PHY_B_AS_PAUSE_MSK) { | |
1178 | case PHY_B_AS_PAUSE_MSK: | |
5d5c8e03 | 1179 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
64f6b64d SH |
1180 | break; |
1181 | case PHY_B_AS_PRR: | |
5d5c8e03 | 1182 | skge->flow_status = FLOW_STAT_REM_SEND; |
64f6b64d SH |
1183 | break; |
1184 | case PHY_B_AS_PRT: | |
5d5c8e03 | 1185 | skge->flow_status = FLOW_STAT_LOC_SEND; |
64f6b64d SH |
1186 | break; |
1187 | default: | |
5d5c8e03 | 1188 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1189 | } |
1190 | skge->speed = SPEED_1000; | |
45bada65 | 1191 | } |
64f6b64d SH |
1192 | |
1193 | if (!netif_carrier_ok(dev)) | |
1194 | genesis_link_up(skge); | |
45bada65 SH |
1195 | } |
1196 | ||
1197 | /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional | |
1198 | * Phy on for 100 or 10Mbit operation | |
1199 | */ | |
64f6b64d | 1200 | static void bcom_phy_init(struct skge_port *skge) |
45bada65 SH |
1201 | { |
1202 | struct skge_hw *hw = skge->hw; | |
1203 | int port = skge->port; | |
baef58b1 | 1204 | int i; |
45bada65 | 1205 | u16 id1, r, ext, ctl; |
baef58b1 SH |
1206 | |
1207 | /* magic workaround patterns for Broadcom */ | |
1208 | static const struct { | |
1209 | u16 reg; | |
1210 | u16 val; | |
1211 | } A1hack[] = { | |
1212 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, | |
1213 | { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, | |
1214 | { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, | |
1215 | { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, | |
1216 | }, C0hack[] = { | |
1217 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, | |
1218 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | |
1219 | }; | |
1220 | ||
45bada65 SH |
1221 | /* read Id from external PHY (all have the same address) */ |
1222 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | |
1223 | ||
1224 | /* Optimize MDIO transfer by suppressing preamble. */ | |
1225 | r = xm_read16(hw, port, XM_MMU_CMD); | |
1226 | r |= XM_MMU_NO_PRE; | |
1227 | xm_write16(hw, port, XM_MMU_CMD,r); | |
1228 | ||
2c668514 | 1229 | switch (id1) { |
45bada65 SH |
1230 | case PHY_BCOM_ID1_C0: |
1231 | /* | |
1232 | * Workaround BCOM Errata for the C0 type. | |
1233 | * Write magic patterns to reserved registers. | |
1234 | */ | |
1235 | for (i = 0; i < ARRAY_SIZE(C0hack); i++) | |
1236 | xm_phy_write(hw, port, | |
1237 | C0hack[i].reg, C0hack[i].val); | |
1238 | ||
1239 | break; | |
1240 | case PHY_BCOM_ID1_A1: | |
1241 | /* | |
1242 | * Workaround BCOM Errata for the A1 type. | |
1243 | * Write magic patterns to reserved registers. | |
1244 | */ | |
1245 | for (i = 0; i < ARRAY_SIZE(A1hack); i++) | |
1246 | xm_phy_write(hw, port, | |
1247 | A1hack[i].reg, A1hack[i].val); | |
1248 | break; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * Workaround BCOM Errata (#10523) for all BCom PHYs. | |
1253 | * Disable Power Management after reset. | |
1254 | */ | |
1255 | r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); | |
1256 | r |= PHY_B_AC_DIS_PM; | |
1257 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); | |
1258 | ||
1259 | /* Dummy read */ | |
1260 | xm_read16(hw, port, XM_ISRC); | |
1261 | ||
1262 | ext = PHY_B_PEC_EN_LTR; /* enable tx led */ | |
1263 | ctl = PHY_CT_SP1000; /* always 1000mbit */ | |
1264 | ||
1265 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1266 | /* | |
1267 | * Workaround BCOM Errata #1 for the C5 type. | |
1268 | * 1000Base-T Link Acquisition Failure in Slave Mode | |
1269 | * Set Repeater/DTE bit 10 of the 1000Base-T Control Register | |
1270 | */ | |
1271 | u16 adv = PHY_B_1000C_RD; | |
1272 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1273 | adv |= PHY_B_1000C_AHD; | |
1274 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1275 | adv |= PHY_B_1000C_AFD; | |
1276 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); | |
1277 | ||
1278 | ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1279 | } else { | |
1280 | if (skge->duplex == DUPLEX_FULL) | |
1281 | ctl |= PHY_CT_DUP_MD; | |
1282 | /* Force to slave */ | |
1283 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); | |
1284 | } | |
1285 | ||
1286 | /* Set autonegotiation pause parameters */ | |
1287 | xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, | |
1288 | phy_pause_map[skge->flow_control] | PHY_AN_CSMA); | |
1289 | ||
1290 | /* Handle Jumbo frames */ | |
64f6b64d | 1291 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { |
45bada65 SH |
1292 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, |
1293 | PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); | |
1294 | ||
1295 | ext |= PHY_B_PEC_HIGH_LA; | |
1296 | ||
1297 | } | |
1298 | ||
1299 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); | |
1300 | xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); | |
1301 | ||
8f3f8193 | 1302 | /* Use link status change interrupt */ |
45bada65 | 1303 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); |
64f6b64d | 1304 | } |
45bada65 | 1305 | |
64f6b64d SH |
1306 | static void xm_phy_init(struct skge_port *skge) |
1307 | { | |
1308 | struct skge_hw *hw = skge->hw; | |
1309 | int port = skge->port; | |
1310 | u16 ctrl = 0; | |
1311 | ||
1312 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1313 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1314 | ctrl |= PHY_X_AN_HD; | |
1315 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1316 | ctrl |= PHY_X_AN_FD; | |
1317 | ||
4b67be99 | 1318 | ctrl |= fiber_pause_map[skge->flow_control]; |
64f6b64d SH |
1319 | |
1320 | xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); | |
1321 | ||
1322 | /* Restart Auto-negotiation */ | |
1323 | ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; | |
1324 | } else { | |
1325 | /* Set DuplexMode in Config register */ | |
1326 | if (skge->duplex == DUPLEX_FULL) | |
1327 | ctrl |= PHY_CT_DUP_MD; | |
1328 | /* | |
1329 | * Do NOT enable Auto-negotiation here. This would hold | |
1330 | * the link down because no IDLEs are transmitted | |
1331 | */ | |
1332 | } | |
1333 | ||
1334 | xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); | |
1335 | ||
1336 | /* Poll PHY for status changes */ | |
9cbe330f | 1337 | mod_timer(&skge->link_timer, jiffies + LINK_HZ); |
64f6b64d SH |
1338 | } |
1339 | ||
1340 | static void xm_check_link(struct net_device *dev) | |
1341 | { | |
1342 | struct skge_port *skge = netdev_priv(dev); | |
1343 | struct skge_hw *hw = skge->hw; | |
1344 | int port = skge->port; | |
1345 | u16 status; | |
1346 | ||
1347 | /* read twice because of latch */ | |
1348 | (void) xm_phy_read(hw, port, PHY_XMAC_STAT); | |
1349 | status = xm_phy_read(hw, port, PHY_XMAC_STAT); | |
1350 | ||
1351 | if ((status & PHY_ST_LSYNC) == 0) { | |
a1bc9b87 | 1352 | xm_link_down(hw, port); |
64f6b64d SH |
1353 | return; |
1354 | } | |
1355 | ||
1356 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1357 | u16 lpa, res; | |
1358 | ||
1359 | if (!(status & PHY_ST_AN_OVER)) | |
1360 | return; | |
1361 | ||
1362 | lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); | |
1363 | if (lpa & PHY_B_AN_RF) { | |
1364 | printk(KERN_NOTICE PFX "%s: remote fault\n", | |
1365 | dev->name); | |
1366 | return; | |
1367 | } | |
1368 | ||
1369 | res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); | |
1370 | ||
1371 | /* Check Duplex mismatch */ | |
1372 | switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { | |
1373 | case PHY_X_RS_FD: | |
1374 | skge->duplex = DUPLEX_FULL; | |
1375 | break; | |
1376 | case PHY_X_RS_HD: | |
1377 | skge->duplex = DUPLEX_HALF; | |
1378 | break; | |
1379 | default: | |
1380 | printk(KERN_NOTICE PFX "%s: duplex mismatch\n", | |
1381 | dev->name); | |
1382 | return; | |
1383 | } | |
1384 | ||
1385 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ | |
5d5c8e03 SH |
1386 | if ((skge->flow_control == FLOW_MODE_SYMMETRIC || |
1387 | skge->flow_control == FLOW_MODE_SYM_OR_REM) && | |
1388 | (lpa & PHY_X_P_SYM_MD)) | |
1389 | skge->flow_status = FLOW_STAT_SYMMETRIC; | |
1390 | else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && | |
1391 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) | |
1392 | /* Enable PAUSE receive, disable PAUSE transmit */ | |
1393 | skge->flow_status = FLOW_STAT_REM_SEND; | |
1394 | else if (skge->flow_control == FLOW_MODE_LOC_SEND && | |
1395 | (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) | |
1396 | /* Disable PAUSE receive, enable PAUSE transmit */ | |
1397 | skge->flow_status = FLOW_STAT_LOC_SEND; | |
64f6b64d | 1398 | else |
5d5c8e03 | 1399 | skge->flow_status = FLOW_STAT_NONE; |
64f6b64d SH |
1400 | |
1401 | skge->speed = SPEED_1000; | |
1402 | } | |
1403 | ||
1404 | if (!netif_carrier_ok(dev)) | |
1405 | genesis_link_up(skge); | |
1406 | } | |
1407 | ||
1408 | /* Poll to check for link coming up. | |
1409 | * Since internal PHY is wired to a level triggered pin, can't | |
1410 | * get an interrupt when carrier is detected. | |
1411 | */ | |
9cbe330f | 1412 | static void xm_link_timer(unsigned long arg) |
64f6b64d | 1413 | { |
9cbe330f | 1414 | struct skge_port *skge = (struct skge_port *) arg; |
c4028958 | 1415 | struct net_device *dev = skge->netdev; |
64f6b64d SH |
1416 | struct skge_hw *hw = skge->hw; |
1417 | int port = skge->port; | |
1418 | ||
1419 | if (!netif_running(dev)) | |
1420 | return; | |
1421 | ||
1422 | if (netif_carrier_ok(dev)) { | |
1423 | xm_read16(hw, port, XM_ISRC); | |
1424 | if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)) | |
1425 | goto nochange; | |
1426 | } else { | |
1427 | if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) | |
1428 | goto nochange; | |
1429 | xm_read16(hw, port, XM_ISRC); | |
1430 | if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS) | |
1431 | goto nochange; | |
1432 | } | |
1433 | ||
9cbe330f | 1434 | spin_lock(&hw->phy_lock); |
64f6b64d | 1435 | xm_check_link(dev); |
9cbe330f | 1436 | spin_unlock(&hw->phy_lock); |
64f6b64d SH |
1437 | |
1438 | nochange: | |
208491d8 | 1439 | if (netif_running(dev)) |
9cbe330f | 1440 | mod_timer(&skge->link_timer, jiffies + LINK_HZ); |
45bada65 SH |
1441 | } |
1442 | ||
1443 | static void genesis_mac_init(struct skge_hw *hw, int port) | |
1444 | { | |
1445 | struct net_device *dev = hw->dev[port]; | |
1446 | struct skge_port *skge = netdev_priv(dev); | |
1447 | int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; | |
1448 | int i; | |
1449 | u32 r; | |
1450 | const u8 zero[6] = { 0 }; | |
1451 | ||
0781191c SH |
1452 | for (i = 0; i < 10; i++) { |
1453 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), | |
1454 | MFF_SET_MAC_RST); | |
1455 | if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) | |
1456 | goto reset_ok; | |
1457 | udelay(1); | |
1458 | } | |
baef58b1 | 1459 | |
0781191c SH |
1460 | printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name); |
1461 | ||
1462 | reset_ok: | |
baef58b1 | 1463 | /* Unreset the XMAC. */ |
6b0c1480 | 1464 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); |
baef58b1 SH |
1465 | |
1466 | /* | |
1467 | * Perform additional initialization for external PHYs, | |
1468 | * namely for the 1000baseTX cards that use the XMAC's | |
1469 | * GMII mode. | |
1470 | */ | |
64f6b64d SH |
1471 | if (hw->phy_type != SK_PHY_XMAC) { |
1472 | /* Take external Phy out of reset */ | |
1473 | r = skge_read32(hw, B2_GP_IO); | |
1474 | if (port == 0) | |
1475 | r |= GP_DIR_0|GP_IO_0; | |
1476 | else | |
1477 | r |= GP_DIR_2|GP_IO_2; | |
89bf5f23 | 1478 | |
64f6b64d | 1479 | skge_write32(hw, B2_GP_IO, r); |
0781191c | 1480 | |
64f6b64d SH |
1481 | /* Enable GMII interface */ |
1482 | xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); | |
1483 | } | |
89bf5f23 | 1484 | |
89bf5f23 | 1485 | |
64f6b64d SH |
1486 | switch(hw->phy_type) { |
1487 | case SK_PHY_XMAC: | |
1488 | xm_phy_init(skge); | |
1489 | break; | |
1490 | case SK_PHY_BCOM: | |
1491 | bcom_phy_init(skge); | |
1492 | bcom_check_link(hw, port); | |
1493 | } | |
89bf5f23 | 1494 | |
45bada65 SH |
1495 | /* Set Station Address */ |
1496 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
89bf5f23 | 1497 | |
45bada65 SH |
1498 | /* We don't use match addresses so clear */ |
1499 | for (i = 1; i < 16; i++) | |
1500 | xm_outaddr(hw, port, XM_EXM(i), zero); | |
1501 | ||
0781191c SH |
1502 | /* Clear MIB counters */ |
1503 | xm_write16(hw, port, XM_STAT_CMD, | |
1504 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1505 | /* Clear two times according to Errata #3 */ | |
1506 | xm_write16(hw, port, XM_STAT_CMD, | |
1507 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1508 | ||
45bada65 SH |
1509 | /* configure Rx High Water Mark (XM_RX_HI_WM) */ |
1510 | xm_write16(hw, port, XM_RX_HI_WM, 1450); | |
1511 | ||
1512 | /* We don't need the FCS appended to the packet. */ | |
1513 | r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; | |
1514 | if (jumbo) | |
1515 | r |= XM_RX_BIG_PK_OK; | |
89bf5f23 | 1516 | |
45bada65 | 1517 | if (skge->duplex == DUPLEX_HALF) { |
89bf5f23 | 1518 | /* |
45bada65 SH |
1519 | * If in manual half duplex mode the other side might be in |
1520 | * full duplex mode, so ignore if a carrier extension is not seen | |
1521 | * on frames received | |
89bf5f23 | 1522 | */ |
45bada65 | 1523 | r |= XM_RX_DIS_CEXT; |
baef58b1 | 1524 | } |
45bada65 | 1525 | xm_write16(hw, port, XM_RX_CMD, r); |
baef58b1 | 1526 | |
baef58b1 SH |
1527 | |
1528 | /* We want short frames padded to 60 bytes. */ | |
45bada65 SH |
1529 | xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); |
1530 | ||
1531 | /* | |
1532 | * Bump up the transmit threshold. This helps hold off transmit | |
1533 | * underruns when we're blasting traffic from both ports at once. | |
1534 | */ | |
1535 | xm_write16(hw, port, XM_TX_THR, 512); | |
baef58b1 SH |
1536 | |
1537 | /* | |
1538 | * Enable the reception of all error frames. This is is | |
1539 | * a necessary evil due to the design of the XMAC. The | |
1540 | * XMAC's receive FIFO is only 8K in size, however jumbo | |
1541 | * frames can be up to 9000 bytes in length. When bad | |
1542 | * frame filtering is enabled, the XMAC's RX FIFO operates | |
1543 | * in 'store and forward' mode. For this to work, the | |
1544 | * entire frame has to fit into the FIFO, but that means | |
1545 | * that jumbo frames larger than 8192 bytes will be | |
1546 | * truncated. Disabling all bad frame filtering causes | |
1547 | * the RX FIFO to operate in streaming mode, in which | |
8f3f8193 | 1548 | * case the XMAC will start transferring frames out of the |
baef58b1 SH |
1549 | * RX FIFO as soon as the FIFO threshold is reached. |
1550 | */ | |
45bada65 | 1551 | xm_write32(hw, port, XM_MODE, XM_DEF_MODE); |
baef58b1 | 1552 | |
baef58b1 SH |
1553 | |
1554 | /* | |
45bada65 SH |
1555 | * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) |
1556 | * - Enable all bits excepting 'Octets Rx OK Low CntOv' | |
1557 | * and 'Octets Rx OK Hi Cnt Ov'. | |
baef58b1 | 1558 | */ |
45bada65 SH |
1559 | xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); |
1560 | ||
1561 | /* | |
1562 | * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) | |
1563 | * - Enable all bits excepting 'Octets Tx OK Low CntOv' | |
1564 | * and 'Octets Tx OK Hi Cnt Ov'. | |
1565 | */ | |
1566 | xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); | |
baef58b1 SH |
1567 | |
1568 | /* Configure MAC arbiter */ | |
1569 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1570 | ||
1571 | /* configure timeout values */ | |
1572 | skge_write8(hw, B3_MA_TOINI_RX1, 72); | |
1573 | skge_write8(hw, B3_MA_TOINI_RX2, 72); | |
1574 | skge_write8(hw, B3_MA_TOINI_TX1, 72); | |
1575 | skge_write8(hw, B3_MA_TOINI_TX2, 72); | |
1576 | ||
1577 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1578 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1579 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1580 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1581 | ||
1582 | /* Configure Rx MAC FIFO */ | |
6b0c1480 SH |
1583 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); |
1584 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); | |
1585 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 SH |
1586 | |
1587 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
1588 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); |
1589 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); | |
1590 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 | 1591 | |
45bada65 | 1592 | if (jumbo) { |
baef58b1 | 1593 | /* Enable frame flushing if jumbo frames used */ |
6b0c1480 | 1594 | skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); |
baef58b1 SH |
1595 | } else { |
1596 | /* enable timeout timers if normal frames */ | |
1597 | skge_write16(hw, B3_PA_CTRL, | |
45bada65 | 1598 | (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); |
baef58b1 | 1599 | } |
baef58b1 SH |
1600 | } |
1601 | ||
1602 | static void genesis_stop(struct skge_port *skge) | |
1603 | { | |
1604 | struct skge_hw *hw = skge->hw; | |
1605 | int port = skge->port; | |
89bf5f23 | 1606 | u32 reg; |
baef58b1 | 1607 | |
46a60f2d SH |
1608 | genesis_reset(hw, port); |
1609 | ||
baef58b1 SH |
1610 | /* Clear Tx packet arbiter timeout IRQ */ |
1611 | skge_write16(hw, B3_PA_CTRL, | |
1612 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | |
1613 | ||
1614 | /* | |
8f3f8193 | 1615 | * If the transfer sticks at the MAC the STOP command will not |
baef58b1 SH |
1616 | * terminate if we don't flush the XMAC's transmit FIFO ! |
1617 | */ | |
6b0c1480 SH |
1618 | xm_write32(hw, port, XM_MODE, |
1619 | xm_read32(hw, port, XM_MODE)|XM_MD_FTF); | |
baef58b1 SH |
1620 | |
1621 | ||
1622 | /* Reset the MAC */ | |
6b0c1480 | 1623 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); |
baef58b1 SH |
1624 | |
1625 | /* For external PHYs there must be special handling */ | |
64f6b64d SH |
1626 | if (hw->phy_type != SK_PHY_XMAC) { |
1627 | reg = skge_read32(hw, B2_GP_IO); | |
1628 | if (port == 0) { | |
1629 | reg |= GP_DIR_0; | |
1630 | reg &= ~GP_IO_0; | |
1631 | } else { | |
1632 | reg |= GP_DIR_2; | |
1633 | reg &= ~GP_IO_2; | |
1634 | } | |
1635 | skge_write32(hw, B2_GP_IO, reg); | |
1636 | skge_read32(hw, B2_GP_IO); | |
baef58b1 SH |
1637 | } |
1638 | ||
6b0c1480 SH |
1639 | xm_write16(hw, port, XM_MMU_CMD, |
1640 | xm_read16(hw, port, XM_MMU_CMD) | |
baef58b1 SH |
1641 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); |
1642 | ||
6b0c1480 | 1643 | xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1644 | } |
1645 | ||
1646 | ||
1647 | static void genesis_get_stats(struct skge_port *skge, u64 *data) | |
1648 | { | |
1649 | struct skge_hw *hw = skge->hw; | |
1650 | int port = skge->port; | |
1651 | int i; | |
1652 | unsigned long timeout = jiffies + HZ; | |
1653 | ||
6b0c1480 | 1654 | xm_write16(hw, port, |
baef58b1 SH |
1655 | XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); |
1656 | ||
1657 | /* wait for update to complete */ | |
6b0c1480 | 1658 | while (xm_read16(hw, port, XM_STAT_CMD) |
baef58b1 SH |
1659 | & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { |
1660 | if (time_after(jiffies, timeout)) | |
1661 | break; | |
1662 | udelay(10); | |
1663 | } | |
1664 | ||
1665 | /* special case for 64 bit octet counter */ | |
6b0c1480 SH |
1666 | data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 |
1667 | | xm_read32(hw, port, XM_TXO_OK_LO); | |
1668 | data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 | |
1669 | | xm_read32(hw, port, XM_RXO_OK_LO); | |
baef58b1 SH |
1670 | |
1671 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 1672 | data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); |
baef58b1 SH |
1673 | } |
1674 | ||
1675 | static void genesis_mac_intr(struct skge_hw *hw, int port) | |
1676 | { | |
1677 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
6b0c1480 | 1678 | u16 status = xm_read16(hw, port, XM_ISRC); |
baef58b1 | 1679 | |
7e676d91 SH |
1680 | if (netif_msg_intr(skge)) |
1681 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
1682 | skge->netdev->name, status); | |
baef58b1 | 1683 | |
a1bc9b87 SH |
1684 | if (hw->phy_type == SK_PHY_XMAC && |
1685 | (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC))) | |
1686 | xm_link_down(hw, port); | |
1687 | ||
baef58b1 | 1688 | if (status & XM_IS_TXF_UR) { |
6b0c1480 | 1689 | xm_write32(hw, port, XM_MODE, XM_MD_FTF); |
baef58b1 SH |
1690 | ++skge->net_stats.tx_fifo_errors; |
1691 | } | |
1692 | if (status & XM_IS_RXF_OV) { | |
6b0c1480 | 1693 | xm_write32(hw, port, XM_MODE, XM_MD_FRF); |
baef58b1 SH |
1694 | ++skge->net_stats.rx_fifo_errors; |
1695 | } | |
1696 | } | |
1697 | ||
baef58b1 SH |
1698 | static void genesis_link_up(struct skge_port *skge) |
1699 | { | |
1700 | struct skge_hw *hw = skge->hw; | |
1701 | int port = skge->port; | |
a1bc9b87 | 1702 | u16 cmd, msk; |
64f6b64d | 1703 | u32 mode; |
baef58b1 | 1704 | |
6b0c1480 | 1705 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1706 | |
1707 | /* | |
1708 | * enabling pause frame reception is required for 1000BT | |
1709 | * because the XMAC is not reset if the link is going down | |
1710 | */ | |
5d5c8e03 SH |
1711 | if (skge->flow_status == FLOW_STAT_NONE || |
1712 | skge->flow_status == FLOW_STAT_LOC_SEND) | |
7e676d91 | 1713 | /* Disable Pause Frame Reception */ |
baef58b1 SH |
1714 | cmd |= XM_MMU_IGN_PF; |
1715 | else | |
1716 | /* Enable Pause Frame Reception */ | |
1717 | cmd &= ~XM_MMU_IGN_PF; | |
1718 | ||
6b0c1480 | 1719 | xm_write16(hw, port, XM_MMU_CMD, cmd); |
baef58b1 | 1720 | |
6b0c1480 | 1721 | mode = xm_read32(hw, port, XM_MODE); |
5d5c8e03 SH |
1722 | if (skge->flow_status== FLOW_STAT_SYMMETRIC || |
1723 | skge->flow_status == FLOW_STAT_LOC_SEND) { | |
baef58b1 SH |
1724 | /* |
1725 | * Configure Pause Frame Generation | |
1726 | * Use internal and external Pause Frame Generation. | |
1727 | * Sending pause frames is edge triggered. | |
1728 | * Send a Pause frame with the maximum pause time if | |
1729 | * internal oder external FIFO full condition occurs. | |
1730 | * Send a zero pause time frame to re-start transmission. | |
1731 | */ | |
1732 | /* XM_PAUSE_DA = '010000C28001' (default) */ | |
1733 | /* XM_MAC_PTIME = 0xffff (maximum) */ | |
1734 | /* remember this value is defined in big endian (!) */ | |
6b0c1480 | 1735 | xm_write16(hw, port, XM_MAC_PTIME, 0xffff); |
baef58b1 SH |
1736 | |
1737 | mode |= XM_PAUSE_MODE; | |
6b0c1480 | 1738 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); |
baef58b1 SH |
1739 | } else { |
1740 | /* | |
1741 | * disable pause frame generation is required for 1000BT | |
1742 | * because the XMAC is not reset if the link is going down | |
1743 | */ | |
1744 | /* Disable Pause Mode in Mode Register */ | |
1745 | mode &= ~XM_PAUSE_MODE; | |
1746 | ||
6b0c1480 | 1747 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); |
baef58b1 SH |
1748 | } |
1749 | ||
6b0c1480 | 1750 | xm_write32(hw, port, XM_MODE, mode); |
a1bc9b87 SH |
1751 | msk = XM_DEF_MSK; |
1752 | if (hw->phy_type != SK_PHY_XMAC) | |
1753 | msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */ | |
1754 | ||
1755 | xm_write16(hw, port, XM_IMSK, msk); | |
6b0c1480 | 1756 | xm_read16(hw, port, XM_ISRC); |
baef58b1 SH |
1757 | |
1758 | /* get MMU Command Reg. */ | |
6b0c1480 | 1759 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
64f6b64d | 1760 | if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) |
baef58b1 SH |
1761 | cmd |= XM_MMU_GMII_FD; |
1762 | ||
89bf5f23 SH |
1763 | /* |
1764 | * Workaround BCOM Errata (#10523) for all BCom Phys | |
1765 | * Enable Power Management after link up | |
1766 | */ | |
64f6b64d SH |
1767 | if (hw->phy_type == SK_PHY_BCOM) { |
1768 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1769 | xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) | |
1770 | & ~PHY_B_AC_DIS_PM); | |
1771 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); | |
1772 | } | |
baef58b1 SH |
1773 | |
1774 | /* enable Rx/Tx */ | |
6b0c1480 | 1775 | xm_write16(hw, port, XM_MMU_CMD, |
baef58b1 SH |
1776 | cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
1777 | skge_link_up(skge); | |
1778 | } | |
1779 | ||
1780 | ||
45bada65 | 1781 | static inline void bcom_phy_intr(struct skge_port *skge) |
baef58b1 SH |
1782 | { |
1783 | struct skge_hw *hw = skge->hw; | |
1784 | int port = skge->port; | |
45bada65 SH |
1785 | u16 isrc; |
1786 | ||
1787 | isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); | |
7e676d91 SH |
1788 | if (netif_msg_intr(skge)) |
1789 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n", | |
1790 | skge->netdev->name, isrc); | |
baef58b1 | 1791 | |
45bada65 SH |
1792 | if (isrc & PHY_B_IS_PSE) |
1793 | printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n", | |
1794 | hw->dev[port]->name); | |
baef58b1 SH |
1795 | |
1796 | /* Workaround BCom Errata: | |
1797 | * enable and disable loopback mode if "NO HCD" occurs. | |
1798 | */ | |
45bada65 | 1799 | if (isrc & PHY_B_IS_NO_HDCL) { |
6b0c1480 SH |
1800 | u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); |
1801 | xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
baef58b1 | 1802 | ctrl | PHY_CT_LOOP); |
6b0c1480 | 1803 | xm_phy_write(hw, port, PHY_BCOM_CTRL, |
baef58b1 SH |
1804 | ctrl & ~PHY_CT_LOOP); |
1805 | } | |
1806 | ||
45bada65 SH |
1807 | if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) |
1808 | bcom_check_link(hw, port); | |
baef58b1 | 1809 | |
baef58b1 SH |
1810 | } |
1811 | ||
2cd8e5d3 SH |
1812 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
1813 | { | |
1814 | int i; | |
1815 | ||
1816 | gma_write16(hw, port, GM_SMI_DATA, val); | |
1817 | gma_write16(hw, port, GM_SMI_CTRL, | |
1818 | GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); | |
1819 | for (i = 0; i < PHY_RETRIES; i++) { | |
1820 | udelay(1); | |
1821 | ||
1822 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) | |
1823 | return 0; | |
1824 | } | |
1825 | ||
1826 | printk(KERN_WARNING PFX "%s: phy write timeout\n", | |
1827 | hw->dev[port]->name); | |
1828 | return -EIO; | |
1829 | } | |
1830 | ||
1831 | static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) | |
1832 | { | |
1833 | int i; | |
1834 | ||
1835 | gma_write16(hw, port, GM_SMI_CTRL, | |
1836 | GM_SMI_CT_PHY_AD(hw->phy_addr) | |
1837 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); | |
1838 | ||
1839 | for (i = 0; i < PHY_RETRIES; i++) { | |
1840 | udelay(1); | |
1841 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) | |
1842 | goto ready; | |
1843 | } | |
1844 | ||
1845 | return -ETIMEDOUT; | |
1846 | ready: | |
1847 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
1848 | return 0; | |
1849 | } | |
1850 | ||
1851 | static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1852 | { | |
1853 | u16 v = 0; | |
1854 | if (__gm_phy_read(hw, port, reg, &v)) | |
1855 | printk(KERN_WARNING PFX "%s: phy read timeout\n", | |
1856 | hw->dev[port]->name); | |
1857 | return v; | |
1858 | } | |
1859 | ||
8f3f8193 | 1860 | /* Marvell Phy Initialization */ |
baef58b1 SH |
1861 | static void yukon_init(struct skge_hw *hw, int port) |
1862 | { | |
1863 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1864 | u16 ctrl, ct1000, adv; | |
baef58b1 | 1865 | |
baef58b1 | 1866 | if (skge->autoneg == AUTONEG_ENABLE) { |
6b0c1480 | 1867 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
baef58b1 SH |
1868 | |
1869 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
1870 | PHY_M_EC_MAC_S_MSK); | |
1871 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); | |
1872 | ||
c506a509 | 1873 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); |
baef58b1 | 1874 | |
6b0c1480 | 1875 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); |
baef58b1 SH |
1876 | } |
1877 | ||
6b0c1480 | 1878 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); |
baef58b1 SH |
1879 | if (skge->autoneg == AUTONEG_DISABLE) |
1880 | ctrl &= ~PHY_CT_ANE; | |
1881 | ||
1882 | ctrl |= PHY_CT_RESET; | |
6b0c1480 | 1883 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); |
baef58b1 SH |
1884 | |
1885 | ctrl = 0; | |
1886 | ct1000 = 0; | |
b18f2091 | 1887 | adv = PHY_AN_CSMA; |
baef58b1 SH |
1888 | |
1889 | if (skge->autoneg == AUTONEG_ENABLE) { | |
5e1705dd | 1890 | if (hw->copper) { |
baef58b1 SH |
1891 | if (skge->advertising & ADVERTISED_1000baseT_Full) |
1892 | ct1000 |= PHY_M_1000C_AFD; | |
1893 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1894 | ct1000 |= PHY_M_1000C_AHD; | |
1895 | if (skge->advertising & ADVERTISED_100baseT_Full) | |
1896 | adv |= PHY_M_AN_100_FD; | |
1897 | if (skge->advertising & ADVERTISED_100baseT_Half) | |
1898 | adv |= PHY_M_AN_100_HD; | |
1899 | if (skge->advertising & ADVERTISED_10baseT_Full) | |
1900 | adv |= PHY_M_AN_10_FD; | |
1901 | if (skge->advertising & ADVERTISED_10baseT_Half) | |
1902 | adv |= PHY_M_AN_10_HD; | |
baef58b1 | 1903 | |
4b67be99 SH |
1904 | /* Set Flow-control capabilities */ |
1905 | adv |= phy_pause_map[skge->flow_control]; | |
1906 | } else { | |
1907 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1908 | adv |= PHY_M_AN_1000X_AFD; | |
1909 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1910 | adv |= PHY_M_AN_1000X_AHD; | |
1911 | ||
1912 | adv |= fiber_pause_map[skge->flow_control]; | |
1913 | } | |
45bada65 | 1914 | |
baef58b1 SH |
1915 | /* Restart Auto-negotiation */ |
1916 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1917 | } else { | |
1918 | /* forced speed/duplex settings */ | |
1919 | ct1000 = PHY_M_1000C_MSE; | |
1920 | ||
1921 | if (skge->duplex == DUPLEX_FULL) | |
1922 | ctrl |= PHY_CT_DUP_MD; | |
1923 | ||
1924 | switch (skge->speed) { | |
1925 | case SPEED_1000: | |
1926 | ctrl |= PHY_CT_SP1000; | |
1927 | break; | |
1928 | case SPEED_100: | |
1929 | ctrl |= PHY_CT_SP100; | |
1930 | break; | |
1931 | } | |
1932 | ||
1933 | ctrl |= PHY_CT_RESET; | |
1934 | } | |
1935 | ||
c506a509 | 1936 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
baef58b1 | 1937 | |
6b0c1480 SH |
1938 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); |
1939 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
baef58b1 | 1940 | |
baef58b1 SH |
1941 | /* Enable phy interrupt on autonegotiation complete (or link up) */ |
1942 | if (skge->autoneg == AUTONEG_ENABLE) | |
4cde06ed | 1943 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); |
baef58b1 | 1944 | else |
4cde06ed | 1945 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
1946 | } |
1947 | ||
1948 | static void yukon_reset(struct skge_hw *hw, int port) | |
1949 | { | |
6b0c1480 SH |
1950 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ |
1951 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ | |
1952 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
1953 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
1954 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
baef58b1 | 1955 | |
6b0c1480 SH |
1956 | gma_write16(hw, port, GM_RX_CTRL, |
1957 | gma_read16(hw, port, GM_RX_CTRL) | |
baef58b1 SH |
1958 | | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
1959 | } | |
1960 | ||
c8868611 SH |
1961 | /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ |
1962 | static int is_yukon_lite_a0(struct skge_hw *hw) | |
1963 | { | |
1964 | u32 reg; | |
1965 | int ret; | |
1966 | ||
1967 | if (hw->chip_id != CHIP_ID_YUKON) | |
1968 | return 0; | |
1969 | ||
1970 | reg = skge_read32(hw, B2_FAR); | |
1971 | skge_write8(hw, B2_FAR + 3, 0xff); | |
1972 | ret = (skge_read8(hw, B2_FAR + 3) != 0); | |
1973 | skge_write32(hw, B2_FAR, reg); | |
1974 | return ret; | |
1975 | } | |
1976 | ||
baef58b1 SH |
1977 | static void yukon_mac_init(struct skge_hw *hw, int port) |
1978 | { | |
1979 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1980 | int i; | |
1981 | u32 reg; | |
1982 | const u8 *addr = hw->dev[port]->dev_addr; | |
1983 | ||
1984 | /* WA code for COMA mode -- set PHY reset */ | |
1985 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1986 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1987 | reg = skge_read32(hw, B2_GP_IO); | |
1988 | reg |= GP_DIR_9 | GP_IO_9; | |
1989 | skge_write32(hw, B2_GP_IO, reg); | |
1990 | } | |
baef58b1 SH |
1991 | |
1992 | /* hard reset */ | |
6b0c1480 SH |
1993 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1994 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
1995 | |
1996 | /* WA code for COMA mode -- clear PHY reset */ | |
1997 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1998 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1999 | reg = skge_read32(hw, B2_GP_IO); | |
2000 | reg |= GP_DIR_9; | |
2001 | reg &= ~GP_IO_9; | |
2002 | skge_write32(hw, B2_GP_IO, reg); | |
2003 | } | |
baef58b1 SH |
2004 | |
2005 | /* Set hardware config mode */ | |
2006 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | |
2007 | GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; | |
5e1705dd | 2008 | reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; |
baef58b1 SH |
2009 | |
2010 | /* Clear GMC reset */ | |
6b0c1480 SH |
2011 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); |
2012 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); | |
2013 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); | |
564f9abb | 2014 | |
baef58b1 SH |
2015 | if (skge->autoneg == AUTONEG_DISABLE) { |
2016 | reg = GM_GPCR_AU_ALL_DIS; | |
6b0c1480 SH |
2017 | gma_write16(hw, port, GM_GP_CTRL, |
2018 | gma_read16(hw, port, GM_GP_CTRL) | reg); | |
baef58b1 SH |
2019 | |
2020 | switch (skge->speed) { | |
2021 | case SPEED_1000: | |
564f9abb | 2022 | reg &= ~GM_GPCR_SPEED_100; |
baef58b1 | 2023 | reg |= GM_GPCR_SPEED_1000; |
564f9abb | 2024 | break; |
baef58b1 | 2025 | case SPEED_100: |
564f9abb | 2026 | reg &= ~GM_GPCR_SPEED_1000; |
baef58b1 | 2027 | reg |= GM_GPCR_SPEED_100; |
564f9abb SH |
2028 | break; |
2029 | case SPEED_10: | |
2030 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
2031 | break; | |
baef58b1 SH |
2032 | } |
2033 | ||
2034 | if (skge->duplex == DUPLEX_FULL) | |
2035 | reg |= GM_GPCR_DUP_FULL; | |
2036 | } else | |
2037 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
564f9abb | 2038 | |
baef58b1 SH |
2039 | switch (skge->flow_control) { |
2040 | case FLOW_MODE_NONE: | |
6b0c1480 | 2041 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 SH |
2042 | reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; |
2043 | break; | |
2044 | case FLOW_MODE_LOC_SEND: | |
2045 | /* disable Rx flow-control */ | |
2046 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
5d5c8e03 SH |
2047 | break; |
2048 | case FLOW_MODE_SYMMETRIC: | |
2049 | case FLOW_MODE_SYM_OR_REM: | |
2050 | /* enable Tx & Rx flow-control */ | |
2051 | break; | |
baef58b1 SH |
2052 | } |
2053 | ||
6b0c1480 | 2054 | gma_write16(hw, port, GM_GP_CTRL, reg); |
46a60f2d | 2055 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2056 | |
baef58b1 | 2057 | yukon_init(hw, port); |
baef58b1 SH |
2058 | |
2059 | /* MIB clear */ | |
6b0c1480 SH |
2060 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
2061 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
baef58b1 SH |
2062 | |
2063 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
6b0c1480 SH |
2064 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); |
2065 | gma_write16(hw, port, GM_PHY_ADDR, reg); | |
baef58b1 SH |
2066 | |
2067 | /* transmit control */ | |
6b0c1480 | 2068 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); |
baef58b1 SH |
2069 | |
2070 | /* receive control reg: unicast + multicast + no FCS */ | |
6b0c1480 | 2071 | gma_write16(hw, port, GM_RX_CTRL, |
baef58b1 SH |
2072 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
2073 | ||
2074 | /* transmit flow control */ | |
6b0c1480 | 2075 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); |
baef58b1 SH |
2076 | |
2077 | /* transmit parameter */ | |
6b0c1480 | 2078 | gma_write16(hw, port, GM_TX_PARAM, |
baef58b1 SH |
2079 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | |
2080 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
2081 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); | |
2082 | ||
2083 | /* serial mode register */ | |
2084 | reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
2085 | if (hw->dev[port]->mtu > 1500) | |
2086 | reg |= GM_SMOD_JUMBO_ENA; | |
2087 | ||
6b0c1480 | 2088 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
baef58b1 SH |
2089 | |
2090 | /* physical address: used for pause frames */ | |
6b0c1480 | 2091 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); |
baef58b1 | 2092 | /* virtual address for data */ |
6b0c1480 | 2093 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); |
baef58b1 SH |
2094 | |
2095 | /* enable interrupt mask for counter overflows */ | |
6b0c1480 SH |
2096 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
2097 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
2098 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
baef58b1 SH |
2099 | |
2100 | /* Initialize Mac Fifo */ | |
2101 | ||
2102 | /* Configure Rx MAC FIFO */ | |
6b0c1480 | 2103 | skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); |
baef58b1 | 2104 | reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
c8868611 SH |
2105 | |
2106 | /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ | |
2107 | if (is_yukon_lite_a0(hw)) | |
baef58b1 | 2108 | reg &= ~GMF_RX_F_FL_ON; |
c8868611 | 2109 | |
6b0c1480 SH |
2110 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); |
2111 | skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); | |
c5923081 SH |
2112 | /* |
2113 | * because Pause Packet Truncation in GMAC is not working | |
2114 | * we have to increase the Flush Threshold to 64 bytes | |
2115 | * in order to flush pause packets in Rx FIFO on Yukon-1 | |
2116 | */ | |
2117 | skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); | |
baef58b1 SH |
2118 | |
2119 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
2120 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
2121 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
baef58b1 SH |
2122 | } |
2123 | ||
355ec572 SH |
2124 | /* Go into power down mode */ |
2125 | static void yukon_suspend(struct skge_hw *hw, int port) | |
2126 | { | |
2127 | u16 ctrl; | |
2128 | ||
2129 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2130 | ctrl |= PHY_M_PC_POL_R_DIS; | |
2131 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
2132 | ||
2133 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2134 | ctrl |= PHY_CT_RESET; | |
2135 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2136 | ||
2137 | /* switch IEEE compatible power down mode on */ | |
2138 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
2139 | ctrl |= PHY_CT_PDOWN; | |
2140 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
2141 | } | |
2142 | ||
baef58b1 SH |
2143 | static void yukon_stop(struct skge_port *skge) |
2144 | { | |
2145 | struct skge_hw *hw = skge->hw; | |
2146 | int port = skge->port; | |
2147 | ||
46a60f2d SH |
2148 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
2149 | yukon_reset(hw, port); | |
baef58b1 | 2150 | |
6b0c1480 SH |
2151 | gma_write16(hw, port, GM_GP_CTRL, |
2152 | gma_read16(hw, port, GM_GP_CTRL) | |
0eedf4ac | 2153 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
6b0c1480 | 2154 | gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 | 2155 | |
355ec572 | 2156 | yukon_suspend(hw, port); |
46a60f2d | 2157 | |
baef58b1 | 2158 | /* set GPHY Control reset */ |
46a60f2d SH |
2159 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
2160 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
2161 | } |
2162 | ||
2163 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | |
2164 | { | |
2165 | struct skge_hw *hw = skge->hw; | |
2166 | int port = skge->port; | |
2167 | int i; | |
2168 | ||
6b0c1480 SH |
2169 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 |
2170 | | gma_read32(hw, port, GM_TXO_OK_LO); | |
2171 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 | |
2172 | | gma_read32(hw, port, GM_RXO_OK_LO); | |
baef58b1 SH |
2173 | |
2174 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 2175 | data[i] = gma_read32(hw, port, |
baef58b1 SH |
2176 | skge_stats[i].gma_offset); |
2177 | } | |
2178 | ||
2179 | static void yukon_mac_intr(struct skge_hw *hw, int port) | |
2180 | { | |
7e676d91 SH |
2181 | struct net_device *dev = hw->dev[port]; |
2182 | struct skge_port *skge = netdev_priv(dev); | |
6b0c1480 | 2183 | u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 2184 | |
7e676d91 SH |
2185 | if (netif_msg_intr(skge)) |
2186 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
2187 | dev->name, status); | |
2188 | ||
baef58b1 SH |
2189 | if (status & GM_IS_RX_FF_OR) { |
2190 | ++skge->net_stats.rx_fifo_errors; | |
d8a09943 | 2191 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
baef58b1 | 2192 | } |
d8a09943 | 2193 | |
baef58b1 SH |
2194 | if (status & GM_IS_TX_FF_UR) { |
2195 | ++skge->net_stats.tx_fifo_errors; | |
d8a09943 | 2196 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
baef58b1 SH |
2197 | } |
2198 | ||
2199 | } | |
2200 | ||
2201 | static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |
2202 | { | |
95566065 | 2203 | switch (aux & PHY_M_PS_SPEED_MSK) { |
baef58b1 SH |
2204 | case PHY_M_PS_SPEED_1000: |
2205 | return SPEED_1000; | |
2206 | case PHY_M_PS_SPEED_100: | |
2207 | return SPEED_100; | |
2208 | default: | |
2209 | return SPEED_10; | |
2210 | } | |
2211 | } | |
2212 | ||
2213 | static void yukon_link_up(struct skge_port *skge) | |
2214 | { | |
2215 | struct skge_hw *hw = skge->hw; | |
2216 | int port = skge->port; | |
2217 | u16 reg; | |
2218 | ||
baef58b1 | 2219 | /* Enable Transmit FIFO Underrun */ |
46a60f2d | 2220 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
baef58b1 | 2221 | |
6b0c1480 | 2222 | reg = gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 SH |
2223 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
2224 | reg |= GM_GPCR_DUP_FULL; | |
2225 | ||
2226 | /* enable Rx/Tx */ | |
2227 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
6b0c1480 | 2228 | gma_write16(hw, port, GM_GP_CTRL, reg); |
baef58b1 | 2229 | |
4cde06ed | 2230 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
2231 | skge_link_up(skge); |
2232 | } | |
2233 | ||
2234 | static void yukon_link_down(struct skge_port *skge) | |
2235 | { | |
2236 | struct skge_hw *hw = skge->hw; | |
2237 | int port = skge->port; | |
d8a09943 | 2238 | u16 ctrl; |
baef58b1 | 2239 | |
d8a09943 SH |
2240 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
2241 | ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2242 | gma_write16(hw, port, GM_GP_CTRL, ctrl); | |
baef58b1 | 2243 | |
5d5c8e03 SH |
2244 | if (skge->flow_status == FLOW_STAT_REM_SEND) { |
2245 | ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); | |
2246 | ctrl |= PHY_M_AN_ASP; | |
baef58b1 | 2247 | /* restore Asymmetric Pause bit */ |
5d5c8e03 | 2248 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); |
baef58b1 SH |
2249 | } |
2250 | ||
baef58b1 SH |
2251 | skge_link_down(skge); |
2252 | ||
2253 | yukon_init(hw, port); | |
2254 | } | |
2255 | ||
2256 | static void yukon_phy_intr(struct skge_port *skge) | |
2257 | { | |
2258 | struct skge_hw *hw = skge->hw; | |
2259 | int port = skge->port; | |
2260 | const char *reason = NULL; | |
2261 | u16 istatus, phystat; | |
2262 | ||
6b0c1480 SH |
2263 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); |
2264 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
7e676d91 SH |
2265 | |
2266 | if (netif_msg_intr(skge)) | |
2267 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
2268 | skge->netdev->name, istatus, phystat); | |
baef58b1 SH |
2269 | |
2270 | if (istatus & PHY_M_IS_AN_COMPL) { | |
6b0c1480 | 2271 | if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) |
baef58b1 SH |
2272 | & PHY_M_AN_RF) { |
2273 | reason = "remote fault"; | |
2274 | goto failed; | |
2275 | } | |
2276 | ||
c506a509 | 2277 | if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { |
baef58b1 SH |
2278 | reason = "master/slave fault"; |
2279 | goto failed; | |
2280 | } | |
2281 | ||
2282 | if (!(phystat & PHY_M_PS_SPDUP_RES)) { | |
2283 | reason = "speed/duplex"; | |
2284 | goto failed; | |
2285 | } | |
2286 | ||
2287 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) | |
2288 | ? DUPLEX_FULL : DUPLEX_HALF; | |
2289 | skge->speed = yukon_speed(hw, phystat); | |
2290 | ||
baef58b1 SH |
2291 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
2292 | switch (phystat & PHY_M_PS_PAUSE_MSK) { | |
2293 | case PHY_M_PS_PAUSE_MSK: | |
5d5c8e03 | 2294 | skge->flow_status = FLOW_STAT_SYMMETRIC; |
baef58b1 SH |
2295 | break; |
2296 | case PHY_M_PS_RX_P_EN: | |
5d5c8e03 | 2297 | skge->flow_status = FLOW_STAT_REM_SEND; |
baef58b1 SH |
2298 | break; |
2299 | case PHY_M_PS_TX_P_EN: | |
5d5c8e03 | 2300 | skge->flow_status = FLOW_STAT_LOC_SEND; |
baef58b1 SH |
2301 | break; |
2302 | default: | |
5d5c8e03 | 2303 | skge->flow_status = FLOW_STAT_NONE; |
baef58b1 SH |
2304 | } |
2305 | ||
5d5c8e03 | 2306 | if (skge->flow_status == FLOW_STAT_NONE || |
baef58b1 | 2307 | (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) |
6b0c1480 | 2308 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 | 2309 | else |
6b0c1480 | 2310 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
baef58b1 SH |
2311 | yukon_link_up(skge); |
2312 | return; | |
2313 | } | |
2314 | ||
2315 | if (istatus & PHY_M_IS_LSP_CHANGE) | |
2316 | skge->speed = yukon_speed(hw, phystat); | |
2317 | ||
2318 | if (istatus & PHY_M_IS_DUP_CHANGE) | |
2319 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
2320 | if (istatus & PHY_M_IS_LST_CHANGE) { | |
2321 | if (phystat & PHY_M_PS_LINK_UP) | |
2322 | yukon_link_up(skge); | |
2323 | else | |
2324 | yukon_link_down(skge); | |
2325 | } | |
2326 | return; | |
2327 | failed: | |
2328 | printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n", | |
2329 | skge->netdev->name, reason); | |
2330 | ||
2331 | /* XXX restart autonegotiation? */ | |
2332 | } | |
2333 | ||
ee294dcd SH |
2334 | static void skge_phy_reset(struct skge_port *skge) |
2335 | { | |
2336 | struct skge_hw *hw = skge->hw; | |
2337 | int port = skge->port; | |
aae343d4 | 2338 | struct net_device *dev = hw->dev[port]; |
ee294dcd SH |
2339 | |
2340 | netif_stop_queue(skge->netdev); | |
2341 | netif_carrier_off(skge->netdev); | |
2342 | ||
9cbe330f | 2343 | spin_lock_bh(&hw->phy_lock); |
ee294dcd SH |
2344 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2345 | genesis_reset(hw, port); | |
2346 | genesis_mac_init(hw, port); | |
2347 | } else { | |
2348 | yukon_reset(hw, port); | |
2349 | yukon_init(hw, port); | |
2350 | } | |
9cbe330f | 2351 | spin_unlock_bh(&hw->phy_lock); |
75814090 SH |
2352 | |
2353 | dev->set_multicast_list(dev); | |
ee294dcd SH |
2354 | } |
2355 | ||
2cd8e5d3 SH |
2356 | /* Basic MII support */ |
2357 | static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2358 | { | |
2359 | struct mii_ioctl_data *data = if_mii(ifr); | |
2360 | struct skge_port *skge = netdev_priv(dev); | |
2361 | struct skge_hw *hw = skge->hw; | |
2362 | int err = -EOPNOTSUPP; | |
2363 | ||
2364 | if (!netif_running(dev)) | |
2365 | return -ENODEV; /* Phy still in reset */ | |
2366 | ||
2367 | switch(cmd) { | |
2368 | case SIOCGMIIPHY: | |
2369 | data->phy_id = hw->phy_addr; | |
2370 | ||
2371 | /* fallthru */ | |
2372 | case SIOCGMIIREG: { | |
2373 | u16 val = 0; | |
9cbe330f | 2374 | spin_lock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2375 | if (hw->chip_id == CHIP_ID_GENESIS) |
2376 | err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
2377 | else | |
2378 | err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
9cbe330f | 2379 | spin_unlock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2380 | data->val_out = val; |
2381 | break; | |
2382 | } | |
2383 | ||
2384 | case SIOCSMIIREG: | |
2385 | if (!capable(CAP_NET_ADMIN)) | |
2386 | return -EPERM; | |
2387 | ||
9cbe330f | 2388 | spin_lock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2389 | if (hw->chip_id == CHIP_ID_GENESIS) |
2390 | err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2391 | data->val_in); | |
2392 | else | |
2393 | err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2394 | data->val_in); | |
9cbe330f | 2395 | spin_unlock_bh(&hw->phy_lock); |
2cd8e5d3 SH |
2396 | break; |
2397 | } | |
2398 | return err; | |
2399 | } | |
2400 | ||
baef58b1 SH |
2401 | static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) |
2402 | { | |
2403 | u32 end; | |
2404 | ||
2405 | start /= 8; | |
2406 | len /= 8; | |
2407 | end = start + len - 1; | |
2408 | ||
2409 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); | |
2410 | skge_write32(hw, RB_ADDR(q, RB_START), start); | |
2411 | skge_write32(hw, RB_ADDR(q, RB_WP), start); | |
2412 | skge_write32(hw, RB_ADDR(q, RB_RP), start); | |
2413 | skge_write32(hw, RB_ADDR(q, RB_END), end); | |
2414 | ||
2415 | if (q == Q_R1 || q == Q_R2) { | |
2416 | /* Set thresholds on receive queue's */ | |
2417 | skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), | |
2418 | start + (2*len)/3); | |
2419 | skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), | |
2420 | start + (len/3)); | |
2421 | } else { | |
2422 | /* Enable store & forward on Tx queue's because | |
2423 | * Tx FIFO is only 4K on Genesis and 1K on Yukon | |
2424 | */ | |
2425 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
2426 | } | |
2427 | ||
2428 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
2429 | } | |
2430 | ||
2431 | /* Setup Bus Memory Interface */ | |
2432 | static void skge_qset(struct skge_port *skge, u16 q, | |
2433 | const struct skge_element *e) | |
2434 | { | |
2435 | struct skge_hw *hw = skge->hw; | |
2436 | u32 watermark = 0x600; | |
2437 | u64 base = skge->dma + (e->desc - skge->mem); | |
2438 | ||
2439 | /* optimization to reduce window on 32bit/33mhz */ | |
2440 | if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) | |
2441 | watermark /= 2; | |
2442 | ||
2443 | skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); | |
2444 | skge_write32(hw, Q_ADDR(q, Q_F), watermark); | |
2445 | skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); | |
2446 | skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); | |
2447 | } | |
2448 | ||
2449 | static int skge_up(struct net_device *dev) | |
2450 | { | |
2451 | struct skge_port *skge = netdev_priv(dev); | |
2452 | struct skge_hw *hw = skge->hw; | |
2453 | int port = skge->port; | |
2454 | u32 chunk, ram_addr; | |
2455 | size_t rx_size, tx_size; | |
2456 | int err; | |
2457 | ||
fae87592 SH |
2458 | if (!is_valid_ether_addr(dev->dev_addr)) |
2459 | return -EINVAL; | |
2460 | ||
baef58b1 SH |
2461 | if (netif_msg_ifup(skge)) |
2462 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
2463 | ||
19a33d4e | 2464 | if (dev->mtu > RX_BUF_SIZE) |
901ccefb | 2465 | skge->rx_buf_size = dev->mtu + ETH_HLEN; |
19a33d4e SH |
2466 | else |
2467 | skge->rx_buf_size = RX_BUF_SIZE; | |
2468 | ||
2469 | ||
baef58b1 SH |
2470 | rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); |
2471 | tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); | |
2472 | skge->mem_size = tx_size + rx_size; | |
2473 | skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); | |
2474 | if (!skge->mem) | |
2475 | return -ENOMEM; | |
2476 | ||
c3da1447 SH |
2477 | BUG_ON(skge->dma & 7); |
2478 | ||
2479 | if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) { | |
1479d13c | 2480 | dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); |
c3da1447 SH |
2481 | err = -EINVAL; |
2482 | goto free_pci_mem; | |
2483 | } | |
2484 | ||
baef58b1 SH |
2485 | memset(skge->mem, 0, skge->mem_size); |
2486 | ||
203babb6 SH |
2487 | err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); |
2488 | if (err) | |
baef58b1 SH |
2489 | goto free_pci_mem; |
2490 | ||
c54f9765 | 2491 | err = skge_rx_fill(dev); |
19a33d4e | 2492 | if (err) |
baef58b1 SH |
2493 | goto free_rx_ring; |
2494 | ||
203babb6 SH |
2495 | err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, |
2496 | skge->dma + rx_size); | |
2497 | if (err) | |
baef58b1 SH |
2498 | goto free_rx_ring; |
2499 | ||
8f3f8193 | 2500 | /* Initialize MAC */ |
9cbe330f | 2501 | spin_lock_bh(&hw->phy_lock); |
baef58b1 SH |
2502 | if (hw->chip_id == CHIP_ID_GENESIS) |
2503 | genesis_mac_init(hw, port); | |
2504 | else | |
2505 | yukon_mac_init(hw, port); | |
9cbe330f | 2506 | spin_unlock_bh(&hw->phy_lock); |
baef58b1 SH |
2507 | |
2508 | /* Configure RAMbuffers */ | |
981d0377 | 2509 | chunk = hw->ram_size / ((hw->ports + 1)*2); |
baef58b1 SH |
2510 | ram_addr = hw->ram_offset + 2 * chunk * port; |
2511 | ||
2512 | skge_ramset(hw, rxqaddr[port], ram_addr, chunk); | |
2513 | skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); | |
2514 | ||
2515 | BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); | |
2516 | skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); | |
2517 | skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); | |
2518 | ||
2519 | /* Start receiver BMU */ | |
2520 | wmb(); | |
2521 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | |
6abebb53 | 2522 | skge_led(skge, LED_MODE_ON); |
baef58b1 | 2523 | |
4ebabfcb SH |
2524 | spin_lock_irq(&hw->hw_lock); |
2525 | hw->intr_mask |= portmask[port]; | |
2526 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2527 | spin_unlock_irq(&hw->hw_lock); | |
2528 | ||
bea3348e | 2529 | napi_enable(&skge->napi); |
baef58b1 SH |
2530 | return 0; |
2531 | ||
2532 | free_rx_ring: | |
2533 | skge_rx_clean(skge); | |
2534 | kfree(skge->rx_ring.start); | |
2535 | free_pci_mem: | |
2536 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2537 | skge->mem = NULL; |
baef58b1 SH |
2538 | |
2539 | return err; | |
2540 | } | |
2541 | ||
2542 | static int skge_down(struct net_device *dev) | |
2543 | { | |
2544 | struct skge_port *skge = netdev_priv(dev); | |
2545 | struct skge_hw *hw = skge->hw; | |
2546 | int port = skge->port; | |
2547 | ||
7731a4ea SH |
2548 | if (skge->mem == NULL) |
2549 | return 0; | |
2550 | ||
baef58b1 SH |
2551 | if (netif_msg_ifdown(skge)) |
2552 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
2553 | ||
2554 | netif_stop_queue(dev); | |
692412b3 | 2555 | |
64f6b64d | 2556 | if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) |
9cbe330f | 2557 | del_timer_sync(&skge->link_timer); |
baef58b1 | 2558 | |
bea3348e | 2559 | napi_disable(&skge->napi); |
692412b3 | 2560 | netif_carrier_off(dev); |
4ebabfcb SH |
2561 | |
2562 | spin_lock_irq(&hw->hw_lock); | |
2563 | hw->intr_mask &= ~portmask[port]; | |
2564 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2565 | spin_unlock_irq(&hw->hw_lock); | |
2566 | ||
46a60f2d SH |
2567 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
2568 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2569 | genesis_stop(skge); | |
2570 | else | |
2571 | yukon_stop(skge); | |
2572 | ||
baef58b1 SH |
2573 | /* Stop transmitter */ |
2574 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | |
2575 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
2576 | RB_RST_SET|RB_DIS_OP_MD); | |
2577 | ||
baef58b1 SH |
2578 | |
2579 | /* Disable Force Sync bit and Enable Alloc bit */ | |
6b0c1480 | 2580 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
baef58b1 SH |
2581 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); |
2582 | ||
2583 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
6b0c1480 SH |
2584 | skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); |
2585 | skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
baef58b1 SH |
2586 | |
2587 | /* Reset PCI FIFO */ | |
2588 | skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); | |
2589 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2590 | ||
2591 | /* Reset the RAM Buffer async Tx queue */ | |
2592 | skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); | |
2593 | /* stop receiver */ | |
2594 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); | |
2595 | skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), | |
2596 | RB_RST_SET|RB_DIS_OP_MD); | |
2597 | skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); | |
2598 | ||
2599 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
6b0c1480 SH |
2600 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); |
2601 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); | |
baef58b1 | 2602 | } else { |
6b0c1480 SH |
2603 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
2604 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
2605 | } |
2606 | ||
6abebb53 | 2607 | skge_led(skge, LED_MODE_OFF); |
baef58b1 | 2608 | |
e3a1b99f | 2609 | netif_tx_lock_bh(dev); |
513f533e | 2610 | skge_tx_clean(dev); |
e3a1b99f SH |
2611 | netif_tx_unlock_bh(dev); |
2612 | ||
baef58b1 SH |
2613 | skge_rx_clean(skge); |
2614 | ||
2615 | kfree(skge->rx_ring.start); | |
2616 | kfree(skge->tx_ring.start); | |
2617 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2618 | skge->mem = NULL; |
baef58b1 SH |
2619 | return 0; |
2620 | } | |
2621 | ||
29b4e886 SH |
2622 | static inline int skge_avail(const struct skge_ring *ring) |
2623 | { | |
992c9623 | 2624 | smp_mb(); |
29b4e886 SH |
2625 | return ((ring->to_clean > ring->to_use) ? 0 : ring->count) |
2626 | + (ring->to_clean - ring->to_use) - 1; | |
2627 | } | |
2628 | ||
baef58b1 SH |
2629 | static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
2630 | { | |
2631 | struct skge_port *skge = netdev_priv(dev); | |
2632 | struct skge_hw *hw = skge->hw; | |
baef58b1 SH |
2633 | struct skge_element *e; |
2634 | struct skge_tx_desc *td; | |
2635 | int i; | |
2636 | u32 control, len; | |
2637 | u64 map; | |
baef58b1 | 2638 | |
5b057c6b | 2639 | if (skb_padto(skb, ETH_ZLEN)) |
baef58b1 SH |
2640 | return NETDEV_TX_OK; |
2641 | ||
513f533e | 2642 | if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) |
baef58b1 | 2643 | return NETDEV_TX_BUSY; |
baef58b1 | 2644 | |
7c442fa1 | 2645 | e = skge->tx_ring.to_use; |
baef58b1 | 2646 | td = e->desc; |
7c442fa1 | 2647 | BUG_ON(td->control & BMU_OWN); |
baef58b1 SH |
2648 | e->skb = skb; |
2649 | len = skb_headlen(skb); | |
2650 | map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2651 | pci_unmap_addr_set(e, mapaddr, map); | |
2652 | pci_unmap_len_set(e, maplen, len); | |
2653 | ||
2654 | td->dma_lo = map; | |
2655 | td->dma_hi = map >> 32; | |
2656 | ||
84fa7933 | 2657 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
ea2ae17d | 2658 | const int offset = skb_transport_offset(skb); |
baef58b1 SH |
2659 | |
2660 | /* This seems backwards, but it is what the sk98lin | |
2661 | * does. Looks like hardware is wrong? | |
2662 | */ | |
b0061ce4 | 2663 | if (ipip_hdr(skb)->protocol == IPPROTO_UDP |
981d0377 | 2664 | && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) |
baef58b1 SH |
2665 | control = BMU_TCP_CHECK; |
2666 | else | |
2667 | control = BMU_UDP_CHECK; | |
2668 | ||
2669 | td->csum_offs = 0; | |
2670 | td->csum_start = offset; | |
ff1dcadb | 2671 | td->csum_write = offset + skb->csum_offset; |
baef58b1 SH |
2672 | } else |
2673 | control = BMU_CHECK; | |
2674 | ||
2675 | if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ | |
2676 | control |= BMU_EOF| BMU_IRQ_EOF; | |
2677 | else { | |
2678 | struct skge_tx_desc *tf = td; | |
2679 | ||
2680 | control |= BMU_STFWD; | |
2681 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2682 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2683 | ||
2684 | map = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
2685 | frag->size, PCI_DMA_TODEVICE); | |
2686 | ||
2687 | e = e->next; | |
7c442fa1 | 2688 | e->skb = skb; |
baef58b1 | 2689 | tf = e->desc; |
7c442fa1 SH |
2690 | BUG_ON(tf->control & BMU_OWN); |
2691 | ||
baef58b1 SH |
2692 | tf->dma_lo = map; |
2693 | tf->dma_hi = (u64) map >> 32; | |
2694 | pci_unmap_addr_set(e, mapaddr, map); | |
2695 | pci_unmap_len_set(e, maplen, frag->size); | |
2696 | ||
2697 | tf->control = BMU_OWN | BMU_SW | control | frag->size; | |
2698 | } | |
2699 | tf->control |= BMU_EOF | BMU_IRQ_EOF; | |
2700 | } | |
2701 | /* Make sure all the descriptors written */ | |
2702 | wmb(); | |
2703 | td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; | |
2704 | wmb(); | |
2705 | ||
2706 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); | |
2707 | ||
7c442fa1 | 2708 | if (unlikely(netif_msg_tx_queued(skge))) |
0b2d7fea | 2709 | printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n", |
7c442fa1 | 2710 | dev->name, e - skge->tx_ring.start, skb->len); |
baef58b1 | 2711 | |
7c442fa1 | 2712 | skge->tx_ring.to_use = e->next; |
992c9623 SH |
2713 | smp_wmb(); |
2714 | ||
9db96479 | 2715 | if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { |
baef58b1 SH |
2716 | pr_debug("%s: transmit queue full\n", dev->name); |
2717 | netif_stop_queue(dev); | |
2718 | } | |
2719 | ||
c68ce71a SH |
2720 | dev->trans_start = jiffies; |
2721 | ||
baef58b1 SH |
2722 | return NETDEV_TX_OK; |
2723 | } | |
2724 | ||
7c442fa1 SH |
2725 | |
2726 | /* Free resources associated with this reing element */ | |
2727 | static void skge_tx_free(struct skge_port *skge, struct skge_element *e, | |
2728 | u32 control) | |
866b4f3e SH |
2729 | { |
2730 | struct pci_dev *pdev = skge->hw->pdev; | |
866b4f3e | 2731 | |
7c442fa1 SH |
2732 | /* skb header vs. fragment */ |
2733 | if (control & BMU_STF) | |
866b4f3e | 2734 | pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr), |
7c442fa1 SH |
2735 | pci_unmap_len(e, maplen), |
2736 | PCI_DMA_TODEVICE); | |
2737 | else | |
2738 | pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr), | |
2739 | pci_unmap_len(e, maplen), | |
2740 | PCI_DMA_TODEVICE); | |
866b4f3e | 2741 | |
7c442fa1 SH |
2742 | if (control & BMU_EOF) { |
2743 | if (unlikely(netif_msg_tx_done(skge))) | |
2744 | printk(KERN_DEBUG PFX "%s: tx done slot %td\n", | |
2745 | skge->netdev->name, e - skge->tx_ring.start); | |
866b4f3e | 2746 | |
513f533e | 2747 | dev_kfree_skb(e->skb); |
baef58b1 SH |
2748 | } |
2749 | } | |
2750 | ||
7c442fa1 | 2751 | /* Free all buffers in transmit ring */ |
513f533e | 2752 | static void skge_tx_clean(struct net_device *dev) |
baef58b1 | 2753 | { |
513f533e | 2754 | struct skge_port *skge = netdev_priv(dev); |
7c442fa1 | 2755 | struct skge_element *e; |
baef58b1 | 2756 | |
7c442fa1 SH |
2757 | for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { |
2758 | struct skge_tx_desc *td = e->desc; | |
2759 | skge_tx_free(skge, e, td->control); | |
2760 | td->control = 0; | |
2761 | } | |
2762 | ||
2763 | skge->tx_ring.to_clean = e; | |
513f533e | 2764 | netif_wake_queue(dev); |
baef58b1 SH |
2765 | } |
2766 | ||
2767 | static void skge_tx_timeout(struct net_device *dev) | |
2768 | { | |
2769 | struct skge_port *skge = netdev_priv(dev); | |
2770 | ||
2771 | if (netif_msg_timer(skge)) | |
2772 | printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); | |
2773 | ||
2774 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); | |
513f533e | 2775 | skge_tx_clean(dev); |
baef58b1 SH |
2776 | } |
2777 | ||
2778 | static int skge_change_mtu(struct net_device *dev, int new_mtu) | |
2779 | { | |
7731a4ea | 2780 | int err; |
baef58b1 | 2781 | |
95566065 | 2782 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
baef58b1 SH |
2783 | return -EINVAL; |
2784 | ||
7731a4ea SH |
2785 | if (!netif_running(dev)) { |
2786 | dev->mtu = new_mtu; | |
2787 | return 0; | |
2788 | } | |
2789 | ||
2790 | skge_down(dev); | |
baef58b1 | 2791 | |
19a33d4e | 2792 | dev->mtu = new_mtu; |
7731a4ea SH |
2793 | |
2794 | err = skge_up(dev); | |
2795 | if (err) | |
2796 | dev_close(dev); | |
baef58b1 SH |
2797 | |
2798 | return err; | |
2799 | } | |
2800 | ||
c4cd29d2 SH |
2801 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; |
2802 | ||
2803 | static void genesis_add_filter(u8 filter[8], const u8 *addr) | |
2804 | { | |
2805 | u32 crc, bit; | |
2806 | ||
2807 | crc = ether_crc_le(ETH_ALEN, addr); | |
2808 | bit = ~crc & 0x3f; | |
2809 | filter[bit/8] |= 1 << (bit%8); | |
2810 | } | |
2811 | ||
baef58b1 SH |
2812 | static void genesis_set_multicast(struct net_device *dev) |
2813 | { | |
2814 | struct skge_port *skge = netdev_priv(dev); | |
2815 | struct skge_hw *hw = skge->hw; | |
2816 | int port = skge->port; | |
2817 | int i, count = dev->mc_count; | |
2818 | struct dev_mc_list *list = dev->mc_list; | |
2819 | u32 mode; | |
2820 | u8 filter[8]; | |
2821 | ||
6b0c1480 | 2822 | mode = xm_read32(hw, port, XM_MODE); |
baef58b1 SH |
2823 | mode |= XM_MD_ENA_HASH; |
2824 | if (dev->flags & IFF_PROMISC) | |
2825 | mode |= XM_MD_ENA_PROM; | |
2826 | else | |
2827 | mode &= ~XM_MD_ENA_PROM; | |
2828 | ||
2829 | if (dev->flags & IFF_ALLMULTI) | |
2830 | memset(filter, 0xff, sizeof(filter)); | |
2831 | else { | |
2832 | memset(filter, 0, sizeof(filter)); | |
c4cd29d2 SH |
2833 | |
2834 | if (skge->flow_status == FLOW_STAT_REM_SEND | |
2835 | || skge->flow_status == FLOW_STAT_SYMMETRIC) | |
2836 | genesis_add_filter(filter, pause_mc_addr); | |
2837 | ||
2838 | for (i = 0; list && i < count; i++, list = list->next) | |
2839 | genesis_add_filter(filter, list->dmi_addr); | |
baef58b1 SH |
2840 | } |
2841 | ||
6b0c1480 | 2842 | xm_write32(hw, port, XM_MODE, mode); |
45bada65 | 2843 | xm_outhash(hw, port, XM_HSM, filter); |
baef58b1 SH |
2844 | } |
2845 | ||
c4cd29d2 SH |
2846 | static void yukon_add_filter(u8 filter[8], const u8 *addr) |
2847 | { | |
2848 | u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; | |
2849 | filter[bit/8] |= 1 << (bit%8); | |
2850 | } | |
2851 | ||
baef58b1 SH |
2852 | static void yukon_set_multicast(struct net_device *dev) |
2853 | { | |
2854 | struct skge_port *skge = netdev_priv(dev); | |
2855 | struct skge_hw *hw = skge->hw; | |
2856 | int port = skge->port; | |
2857 | struct dev_mc_list *list = dev->mc_list; | |
c4cd29d2 SH |
2858 | int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND |
2859 | || skge->flow_status == FLOW_STAT_SYMMETRIC); | |
baef58b1 SH |
2860 | u16 reg; |
2861 | u8 filter[8]; | |
2862 | ||
2863 | memset(filter, 0, sizeof(filter)); | |
2864 | ||
6b0c1480 | 2865 | reg = gma_read16(hw, port, GM_RX_CTRL); |
baef58b1 SH |
2866 | reg |= GM_RXCR_UCF_ENA; |
2867 | ||
8f3f8193 | 2868 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
baef58b1 SH |
2869 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
2870 | else if (dev->flags & IFF_ALLMULTI) /* all multicast */ | |
2871 | memset(filter, 0xff, sizeof(filter)); | |
c4cd29d2 | 2872 | else if (dev->mc_count == 0 && !rx_pause)/* no multicast */ |
baef58b1 SH |
2873 | reg &= ~GM_RXCR_MCF_ENA; |
2874 | else { | |
2875 | int i; | |
2876 | reg |= GM_RXCR_MCF_ENA; | |
2877 | ||
c4cd29d2 SH |
2878 | if (rx_pause) |
2879 | yukon_add_filter(filter, pause_mc_addr); | |
2880 | ||
2881 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) | |
2882 | yukon_add_filter(filter, list->dmi_addr); | |
baef58b1 SH |
2883 | } |
2884 | ||
2885 | ||
6b0c1480 | 2886 | gma_write16(hw, port, GM_MC_ADDR_H1, |
baef58b1 | 2887 | (u16)filter[0] | ((u16)filter[1] << 8)); |
6b0c1480 | 2888 | gma_write16(hw, port, GM_MC_ADDR_H2, |
baef58b1 | 2889 | (u16)filter[2] | ((u16)filter[3] << 8)); |
6b0c1480 | 2890 | gma_write16(hw, port, GM_MC_ADDR_H3, |
baef58b1 | 2891 | (u16)filter[4] | ((u16)filter[5] << 8)); |
6b0c1480 | 2892 | gma_write16(hw, port, GM_MC_ADDR_H4, |
baef58b1 SH |
2893 | (u16)filter[6] | ((u16)filter[7] << 8)); |
2894 | ||
6b0c1480 | 2895 | gma_write16(hw, port, GM_RX_CTRL, reg); |
baef58b1 SH |
2896 | } |
2897 | ||
383181ac SH |
2898 | static inline u16 phy_length(const struct skge_hw *hw, u32 status) |
2899 | { | |
2900 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2901 | return status >> XMR_FS_LEN_SHIFT; | |
2902 | else | |
2903 | return status >> GMR_FS_LEN_SHIFT; | |
2904 | } | |
2905 | ||
baef58b1 SH |
2906 | static inline int bad_phy_status(const struct skge_hw *hw, u32 status) |
2907 | { | |
2908 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2909 | return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; | |
2910 | else | |
2911 | return (status & GMR_FS_ANY_ERR) || | |
2912 | (status & GMR_FS_RX_OK) == 0; | |
2913 | } | |
2914 | ||
19a33d4e SH |
2915 | |
2916 | /* Get receive buffer from descriptor. | |
2917 | * Handles copy of small buffers and reallocation failures | |
2918 | */ | |
c54f9765 SH |
2919 | static struct sk_buff *skge_rx_get(struct net_device *dev, |
2920 | struct skge_element *e, | |
2921 | u32 control, u32 status, u16 csum) | |
19a33d4e | 2922 | { |
c54f9765 | 2923 | struct skge_port *skge = netdev_priv(dev); |
383181ac SH |
2924 | struct sk_buff *skb; |
2925 | u16 len = control & BMU_BBC; | |
2926 | ||
2927 | if (unlikely(netif_msg_rx_status(skge))) | |
2928 | printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", | |
c54f9765 | 2929 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2930 | status, len); |
2931 | ||
2932 | if (len > skge->rx_buf_size) | |
2933 | goto error; | |
2934 | ||
2935 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) | |
2936 | goto error; | |
2937 | ||
2938 | if (bad_phy_status(skge->hw, status)) | |
2939 | goto error; | |
2940 | ||
2941 | if (phy_length(skge->hw, status) != len) | |
2942 | goto error; | |
19a33d4e SH |
2943 | |
2944 | if (len < RX_COPY_THRESHOLD) { | |
c54f9765 | 2945 | skb = netdev_alloc_skb(dev, len + 2); |
383181ac SH |
2946 | if (!skb) |
2947 | goto resubmit; | |
19a33d4e | 2948 | |
383181ac | 2949 | skb_reserve(skb, 2); |
19a33d4e SH |
2950 | pci_dma_sync_single_for_cpu(skge->hw->pdev, |
2951 | pci_unmap_addr(e, mapaddr), | |
2952 | len, PCI_DMA_FROMDEVICE); | |
d626f62b | 2953 | skb_copy_from_linear_data(e->skb, skb->data, len); |
19a33d4e SH |
2954 | pci_dma_sync_single_for_device(skge->hw->pdev, |
2955 | pci_unmap_addr(e, mapaddr), | |
2956 | len, PCI_DMA_FROMDEVICE); | |
19a33d4e | 2957 | skge_rx_reuse(e, skge->rx_buf_size); |
19a33d4e | 2958 | } else { |
383181ac | 2959 | struct sk_buff *nskb; |
c54f9765 | 2960 | nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN); |
383181ac SH |
2961 | if (!nskb) |
2962 | goto resubmit; | |
19a33d4e | 2963 | |
901ccefb | 2964 | skb_reserve(nskb, NET_IP_ALIGN); |
19a33d4e SH |
2965 | pci_unmap_single(skge->hw->pdev, |
2966 | pci_unmap_addr(e, mapaddr), | |
2967 | pci_unmap_len(e, maplen), | |
2968 | PCI_DMA_FROMDEVICE); | |
2969 | skb = e->skb; | |
383181ac | 2970 | prefetch(skb->data); |
19a33d4e | 2971 | skge_rx_setup(skge, e, nskb, skge->rx_buf_size); |
baef58b1 | 2972 | } |
383181ac SH |
2973 | |
2974 | skb_put(skb, len); | |
383181ac SH |
2975 | if (skge->rx_csum) { |
2976 | skb->csum = csum; | |
84fa7933 | 2977 | skb->ip_summed = CHECKSUM_COMPLETE; |
383181ac SH |
2978 | } |
2979 | ||
c54f9765 | 2980 | skb->protocol = eth_type_trans(skb, dev); |
383181ac SH |
2981 | |
2982 | return skb; | |
2983 | error: | |
2984 | ||
2985 | if (netif_msg_rx_err(skge)) | |
2986 | printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n", | |
c54f9765 | 2987 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2988 | control, status); |
2989 | ||
2990 | if (skge->hw->chip_id == CHIP_ID_GENESIS) { | |
2991 | if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) | |
2992 | skge->net_stats.rx_length_errors++; | |
2993 | if (status & XMR_FS_FRA_ERR) | |
2994 | skge->net_stats.rx_frame_errors++; | |
2995 | if (status & XMR_FS_FCS_ERR) | |
2996 | skge->net_stats.rx_crc_errors++; | |
2997 | } else { | |
2998 | if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) | |
2999 | skge->net_stats.rx_length_errors++; | |
3000 | if (status & GMR_FS_FRAGMENT) | |
3001 | skge->net_stats.rx_frame_errors++; | |
3002 | if (status & GMR_FS_CRC_ERR) | |
3003 | skge->net_stats.rx_crc_errors++; | |
3004 | } | |
3005 | ||
3006 | resubmit: | |
3007 | skge_rx_reuse(e, skge->rx_buf_size); | |
3008 | return NULL; | |
baef58b1 SH |
3009 | } |
3010 | ||
7c442fa1 | 3011 | /* Free all buffers in Tx ring which are no longer owned by device */ |
513f533e | 3012 | static void skge_tx_done(struct net_device *dev) |
00a6cae2 | 3013 | { |
7c442fa1 | 3014 | struct skge_port *skge = netdev_priv(dev); |
00a6cae2 | 3015 | struct skge_ring *ring = &skge->tx_ring; |
7c442fa1 SH |
3016 | struct skge_element *e; |
3017 | ||
513f533e | 3018 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); |
00a6cae2 | 3019 | |
866b4f3e | 3020 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { |
992c9623 | 3021 | u32 control = ((const struct skge_tx_desc *) e->desc)->control; |
00a6cae2 | 3022 | |
992c9623 | 3023 | if (control & BMU_OWN) |
00a6cae2 SH |
3024 | break; |
3025 | ||
992c9623 | 3026 | skge_tx_free(skge, e, control); |
00a6cae2 | 3027 | } |
7c442fa1 | 3028 | skge->tx_ring.to_clean = e; |
866b4f3e | 3029 | |
992c9623 SH |
3030 | /* Can run lockless until we need to synchronize to restart queue. */ |
3031 | smp_mb(); | |
3032 | ||
3033 | if (unlikely(netif_queue_stopped(dev) && | |
3034 | skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { | |
3035 | netif_tx_lock(dev); | |
3036 | if (unlikely(netif_queue_stopped(dev) && | |
3037 | skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { | |
3038 | netif_wake_queue(dev); | |
00a6cae2 | 3039 | |
992c9623 SH |
3040 | } |
3041 | netif_tx_unlock(dev); | |
3042 | } | |
00a6cae2 | 3043 | } |
19a33d4e | 3044 | |
bea3348e | 3045 | static int skge_poll(struct napi_struct *napi, int to_do) |
baef58b1 | 3046 | { |
bea3348e SH |
3047 | struct skge_port *skge = container_of(napi, struct skge_port, napi); |
3048 | struct net_device *dev = skge->netdev; | |
baef58b1 SH |
3049 | struct skge_hw *hw = skge->hw; |
3050 | struct skge_ring *ring = &skge->rx_ring; | |
3051 | struct skge_element *e; | |
00a6cae2 SH |
3052 | int work_done = 0; |
3053 | ||
513f533e SH |
3054 | skge_tx_done(dev); |
3055 | ||
3056 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); | |
3057 | ||
1631aef1 | 3058 | for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { |
baef58b1 | 3059 | struct skge_rx_desc *rd = e->desc; |
19a33d4e | 3060 | struct sk_buff *skb; |
383181ac | 3061 | u32 control; |
baef58b1 SH |
3062 | |
3063 | rmb(); | |
3064 | control = rd->control; | |
3065 | if (control & BMU_OWN) | |
3066 | break; | |
3067 | ||
c54f9765 | 3068 | skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); |
19a33d4e | 3069 | if (likely(skb)) { |
19a33d4e SH |
3070 | dev->last_rx = jiffies; |
3071 | netif_receive_skb(skb); | |
baef58b1 | 3072 | |
19a33d4e | 3073 | ++work_done; |
5a011447 | 3074 | } |
baef58b1 SH |
3075 | } |
3076 | ring->to_clean = e; | |
3077 | ||
baef58b1 SH |
3078 | /* restart receiver */ |
3079 | wmb(); | |
a9cdab86 | 3080 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); |
baef58b1 | 3081 | |
bea3348e SH |
3082 | if (work_done < to_do) { |
3083 | spin_lock_irq(&hw->hw_lock); | |
3084 | __netif_rx_complete(dev, napi); | |
3085 | hw->intr_mask |= napimask[skge->port]; | |
3086 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
3087 | skge_read32(hw, B0_IMSK); | |
3088 | spin_unlock_irq(&hw->hw_lock); | |
3089 | } | |
1631aef1 | 3090 | |
bea3348e | 3091 | return work_done; |
baef58b1 SH |
3092 | } |
3093 | ||
f6620cab SH |
3094 | /* Parity errors seem to happen when Genesis is connected to a switch |
3095 | * with no other ports present. Heartbeat error?? | |
3096 | */ | |
baef58b1 SH |
3097 | static void skge_mac_parity(struct skge_hw *hw, int port) |
3098 | { | |
f6620cab SH |
3099 | struct net_device *dev = hw->dev[port]; |
3100 | ||
3101 | if (dev) { | |
3102 | struct skge_port *skge = netdev_priv(dev); | |
3103 | ++skge->net_stats.tx_heartbeat_errors; | |
3104 | } | |
baef58b1 SH |
3105 | |
3106 | if (hw->chip_id == CHIP_ID_GENESIS) | |
6b0c1480 | 3107 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), |
baef58b1 SH |
3108 | MFF_CLR_PERR); |
3109 | else | |
3110 | /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ | |
6b0c1480 | 3111 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), |
981d0377 | 3112 | (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) |
baef58b1 SH |
3113 | ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); |
3114 | } | |
3115 | ||
baef58b1 SH |
3116 | static void skge_mac_intr(struct skge_hw *hw, int port) |
3117 | { | |
95566065 | 3118 | if (hw->chip_id == CHIP_ID_GENESIS) |
baef58b1 SH |
3119 | genesis_mac_intr(hw, port); |
3120 | else | |
3121 | yukon_mac_intr(hw, port); | |
3122 | } | |
3123 | ||
3124 | /* Handle device specific framing and timeout interrupts */ | |
3125 | static void skge_error_irq(struct skge_hw *hw) | |
3126 | { | |
1479d13c | 3127 | struct pci_dev *pdev = hw->pdev; |
baef58b1 SH |
3128 | u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3129 | ||
3130 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3131 | /* clear xmac errors */ | |
3132 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | |
46a60f2d | 3133 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
baef58b1 | 3134 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
46a60f2d | 3135 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
baef58b1 SH |
3136 | } else { |
3137 | /* Timestamp (unused) overflow */ | |
3138 | if (hwstatus & IS_IRQ_TIST_OV) | |
3139 | skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); | |
baef58b1 SH |
3140 | } |
3141 | ||
3142 | if (hwstatus & IS_RAM_RD_PAR) { | |
1479d13c | 3143 | dev_err(&pdev->dev, "Ram read data parity error\n"); |
baef58b1 SH |
3144 | skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); |
3145 | } | |
3146 | ||
3147 | if (hwstatus & IS_RAM_WR_PAR) { | |
1479d13c | 3148 | dev_err(&pdev->dev, "Ram write data parity error\n"); |
baef58b1 SH |
3149 | skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); |
3150 | } | |
3151 | ||
3152 | if (hwstatus & IS_M1_PAR_ERR) | |
3153 | skge_mac_parity(hw, 0); | |
3154 | ||
3155 | if (hwstatus & IS_M2_PAR_ERR) | |
3156 | skge_mac_parity(hw, 1); | |
3157 | ||
b9d64acc | 3158 | if (hwstatus & IS_R1_PAR_ERR) { |
1479d13c SH |
3159 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3160 | hw->dev[0]->name); | |
baef58b1 | 3161 | skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3162 | } |
baef58b1 | 3163 | |
b9d64acc | 3164 | if (hwstatus & IS_R2_PAR_ERR) { |
1479d13c SH |
3165 | dev_err(&pdev->dev, "%s: receive queue parity error\n", |
3166 | hw->dev[1]->name); | |
baef58b1 | 3167 | skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); |
b9d64acc | 3168 | } |
baef58b1 SH |
3169 | |
3170 | if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { | |
b9d64acc SH |
3171 | u16 pci_status, pci_cmd; |
3172 | ||
1479d13c SH |
3173 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
3174 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
baef58b1 | 3175 | |
1479d13c SH |
3176 | dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", |
3177 | pci_cmd, pci_status); | |
b9d64acc SH |
3178 | |
3179 | /* Write the error bits back to clear them. */ | |
3180 | pci_status &= PCI_STATUS_ERROR_BITS; | |
3181 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
1479d13c | 3182 | pci_write_config_word(pdev, PCI_COMMAND, |
b9d64acc | 3183 | pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); |
1479d13c | 3184 | pci_write_config_word(pdev, PCI_STATUS, pci_status); |
b9d64acc | 3185 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
baef58b1 | 3186 | |
050ec18a | 3187 | /* if error still set then just ignore it */ |
baef58b1 SH |
3188 | hwstatus = skge_read32(hw, B0_HWE_ISRC); |
3189 | if (hwstatus & IS_IRQ_STAT) { | |
1479d13c | 3190 | dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); |
baef58b1 SH |
3191 | hw->intr_mask &= ~IS_HW_ERR; |
3192 | } | |
3193 | } | |
3194 | } | |
3195 | ||
3196 | /* | |
9cbe330f | 3197 | * Interrupt from PHY are handled in tasklet (softirq) |
baef58b1 SH |
3198 | * because accessing phy registers requires spin wait which might |
3199 | * cause excess interrupt latency. | |
3200 | */ | |
9cbe330f | 3201 | static void skge_extirq(unsigned long arg) |
baef58b1 | 3202 | { |
9cbe330f | 3203 | struct skge_hw *hw = (struct skge_hw *) arg; |
baef58b1 SH |
3204 | int port; |
3205 | ||
cfc3ed79 | 3206 | for (port = 0; port < hw->ports; port++) { |
baef58b1 SH |
3207 | struct net_device *dev = hw->dev[port]; |
3208 | ||
cfc3ed79 | 3209 | if (netif_running(dev)) { |
9cbe330f SH |
3210 | struct skge_port *skge = netdev_priv(dev); |
3211 | ||
3212 | spin_lock(&hw->phy_lock); | |
baef58b1 SH |
3213 | if (hw->chip_id != CHIP_ID_GENESIS) |
3214 | yukon_phy_intr(skge); | |
64f6b64d | 3215 | else if (hw->phy_type == SK_PHY_BCOM) |
45bada65 | 3216 | bcom_phy_intr(skge); |
9cbe330f | 3217 | spin_unlock(&hw->phy_lock); |
baef58b1 SH |
3218 | } |
3219 | } | |
baef58b1 | 3220 | |
7c442fa1 | 3221 | spin_lock_irq(&hw->hw_lock); |
baef58b1 SH |
3222 | hw->intr_mask |= IS_EXT_REG; |
3223 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
78bc2186 | 3224 | skge_read32(hw, B0_IMSK); |
7c442fa1 | 3225 | spin_unlock_irq(&hw->hw_lock); |
baef58b1 SH |
3226 | } |
3227 | ||
7d12e780 | 3228 | static irqreturn_t skge_intr(int irq, void *dev_id) |
baef58b1 SH |
3229 | { |
3230 | struct skge_hw *hw = dev_id; | |
cfc3ed79 | 3231 | u32 status; |
29365c90 | 3232 | int handled = 0; |
baef58b1 | 3233 | |
29365c90 | 3234 | spin_lock(&hw->hw_lock); |
cfc3ed79 SH |
3235 | /* Reading this register masks IRQ */ |
3236 | status = skge_read32(hw, B0_SP_ISRC); | |
0486a8c8 | 3237 | if (status == 0 || status == ~0) |
29365c90 | 3238 | goto out; |
baef58b1 | 3239 | |
29365c90 | 3240 | handled = 1; |
7c442fa1 | 3241 | status &= hw->intr_mask; |
cfc3ed79 SH |
3242 | if (status & IS_EXT_REG) { |
3243 | hw->intr_mask &= ~IS_EXT_REG; | |
9cbe330f | 3244 | tasklet_schedule(&hw->phy_task); |
cfc3ed79 SH |
3245 | } |
3246 | ||
513f533e | 3247 | if (status & (IS_XA1_F|IS_R1_F)) { |
bea3348e | 3248 | struct skge_port *skge = netdev_priv(hw->dev[0]); |
513f533e | 3249 | hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); |
bea3348e | 3250 | netif_rx_schedule(hw->dev[0], &skge->napi); |
baef58b1 SH |
3251 | } |
3252 | ||
7c442fa1 SH |
3253 | if (status & IS_PA_TO_TX1) |
3254 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); | |
cfc3ed79 | 3255 | |
d25f5a67 SH |
3256 | if (status & IS_PA_TO_RX1) { |
3257 | struct skge_port *skge = netdev_priv(hw->dev[0]); | |
d25f5a67 | 3258 | |
d25f5a67 | 3259 | ++skge->net_stats.rx_over_errors; |
7c442fa1 | 3260 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); |
d25f5a67 SH |
3261 | } |
3262 | ||
d25f5a67 | 3263 | |
baef58b1 SH |
3264 | if (status & IS_MAC1) |
3265 | skge_mac_intr(hw, 0); | |
95566065 | 3266 | |
7c442fa1 | 3267 | if (hw->dev[1]) { |
bea3348e SH |
3268 | struct skge_port *skge = netdev_priv(hw->dev[1]); |
3269 | ||
513f533e SH |
3270 | if (status & (IS_XA2_F|IS_R2_F)) { |
3271 | hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); | |
bea3348e | 3272 | netif_rx_schedule(hw->dev[1], &skge->napi); |
7c442fa1 SH |
3273 | } |
3274 | ||
3275 | if (status & IS_PA_TO_RX2) { | |
7c442fa1 SH |
3276 | ++skge->net_stats.rx_over_errors; |
3277 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); | |
3278 | } | |
3279 | ||
3280 | if (status & IS_PA_TO_TX2) | |
3281 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); | |
3282 | ||
3283 | if (status & IS_MAC2) | |
3284 | skge_mac_intr(hw, 1); | |
3285 | } | |
baef58b1 SH |
3286 | |
3287 | if (status & IS_HW_ERR) | |
3288 | skge_error_irq(hw); | |
3289 | ||
7e676d91 | 3290 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 3291 | skge_read32(hw, B0_IMSK); |
29365c90 | 3292 | out: |
7c442fa1 | 3293 | spin_unlock(&hw->hw_lock); |
baef58b1 | 3294 | |
29365c90 | 3295 | return IRQ_RETVAL(handled); |
baef58b1 SH |
3296 | } |
3297 | ||
3298 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3299 | static void skge_netpoll(struct net_device *dev) | |
3300 | { | |
3301 | struct skge_port *skge = netdev_priv(dev); | |
3302 | ||
3303 | disable_irq(dev->irq); | |
7d12e780 | 3304 | skge_intr(dev->irq, skge->hw); |
baef58b1 SH |
3305 | enable_irq(dev->irq); |
3306 | } | |
3307 | #endif | |
3308 | ||
3309 | static int skge_set_mac_address(struct net_device *dev, void *p) | |
3310 | { | |
3311 | struct skge_port *skge = netdev_priv(dev); | |
c2681dd8 SH |
3312 | struct skge_hw *hw = skge->hw; |
3313 | unsigned port = skge->port; | |
3314 | const struct sockaddr *addr = p; | |
2eb3e621 | 3315 | u16 ctrl; |
baef58b1 SH |
3316 | |
3317 | if (!is_valid_ether_addr(addr->sa_data)) | |
3318 | return -EADDRNOTAVAIL; | |
3319 | ||
baef58b1 | 3320 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
c2681dd8 | 3321 | |
9cbe330f SH |
3322 | if (!netif_running(dev)) { |
3323 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); | |
3324 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); | |
3325 | } else { | |
3326 | /* disable Rx */ | |
3327 | spin_lock_bh(&hw->phy_lock); | |
3328 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
3329 | gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); | |
2eb3e621 | 3330 | |
9cbe330f SH |
3331 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); |
3332 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); | |
2eb3e621 | 3333 | |
2eb3e621 SH |
3334 | if (hw->chip_id == CHIP_ID_GENESIS) |
3335 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
3336 | else { | |
3337 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
3338 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3339 | } | |
2eb3e621 | 3340 | |
9cbe330f SH |
3341 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
3342 | spin_unlock_bh(&hw->phy_lock); | |
3343 | } | |
c2681dd8 SH |
3344 | |
3345 | return 0; | |
baef58b1 SH |
3346 | } |
3347 | ||
3348 | static const struct { | |
3349 | u8 id; | |
3350 | const char *name; | |
3351 | } skge_chips[] = { | |
3352 | { CHIP_ID_GENESIS, "Genesis" }, | |
3353 | { CHIP_ID_YUKON, "Yukon" }, | |
3354 | { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, | |
3355 | { CHIP_ID_YUKON_LP, "Yukon-LP"}, | |
baef58b1 SH |
3356 | }; |
3357 | ||
3358 | static const char *skge_board_name(const struct skge_hw *hw) | |
3359 | { | |
3360 | int i; | |
3361 | static char buf[16]; | |
3362 | ||
3363 | for (i = 0; i < ARRAY_SIZE(skge_chips); i++) | |
3364 | if (skge_chips[i].id == hw->chip_id) | |
3365 | return skge_chips[i].name; | |
3366 | ||
3367 | snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); | |
3368 | return buf; | |
3369 | } | |
3370 | ||
3371 | ||
3372 | /* | |
3373 | * Setup the board data structure, but don't bring up | |
3374 | * the port(s) | |
3375 | */ | |
3376 | static int skge_reset(struct skge_hw *hw) | |
3377 | { | |
adba9e23 | 3378 | u32 reg; |
b9d64acc | 3379 | u16 ctst, pci_status; |
64f6b64d | 3380 | u8 t8, mac_cfg, pmd_type; |
981d0377 | 3381 | int i; |
baef58b1 SH |
3382 | |
3383 | ctst = skge_read16(hw, B0_CTST); | |
3384 | ||
3385 | /* do a SW reset */ | |
3386 | skge_write8(hw, B0_CTST, CS_RST_SET); | |
3387 | skge_write8(hw, B0_CTST, CS_RST_CLR); | |
3388 | ||
3389 | /* clear PCI errors, if any */ | |
b9d64acc SH |
3390 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
3391 | skge_write8(hw, B2_TST_CTRL2, 0); | |
baef58b1 | 3392 | |
b9d64acc SH |
3393 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); |
3394 | pci_write_config_word(hw->pdev, PCI_STATUS, | |
3395 | pci_status | PCI_STATUS_ERROR_BITS); | |
3396 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
baef58b1 SH |
3397 | skge_write8(hw, B0_CTST, CS_MRST_CLR); |
3398 | ||
3399 | /* restore CLK_RUN bits (for Yukon-Lite) */ | |
3400 | skge_write16(hw, B0_CTST, | |
3401 | ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); | |
3402 | ||
3403 | hw->chip_id = skge_read8(hw, B2_CHIP_ID); | |
64f6b64d | 3404 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; |
5e1705dd SH |
3405 | pmd_type = skge_read8(hw, B2_PMD_TYP); |
3406 | hw->copper = (pmd_type == 'T' || pmd_type == '1'); | |
baef58b1 | 3407 | |
95566065 | 3408 | switch (hw->chip_id) { |
baef58b1 | 3409 | case CHIP_ID_GENESIS: |
64f6b64d SH |
3410 | switch (hw->phy_type) { |
3411 | case SK_PHY_XMAC: | |
3412 | hw->phy_addr = PHY_ADDR_XMAC; | |
3413 | break; | |
baef58b1 SH |
3414 | case SK_PHY_BCOM: |
3415 | hw->phy_addr = PHY_ADDR_BCOM; | |
3416 | break; | |
3417 | default: | |
1479d13c SH |
3418 | dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", |
3419 | hw->phy_type); | |
baef58b1 SH |
3420 | return -EOPNOTSUPP; |
3421 | } | |
3422 | break; | |
3423 | ||
3424 | case CHIP_ID_YUKON: | |
3425 | case CHIP_ID_YUKON_LITE: | |
3426 | case CHIP_ID_YUKON_LP: | |
64f6b64d | 3427 | if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') |
5e1705dd | 3428 | hw->copper = 1; |
baef58b1 SH |
3429 | |
3430 | hw->phy_addr = PHY_ADDR_MARV; | |
baef58b1 SH |
3431 | break; |
3432 | ||
3433 | default: | |
1479d13c SH |
3434 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3435 | hw->chip_id); | |
baef58b1 SH |
3436 | return -EOPNOTSUPP; |
3437 | } | |
3438 | ||
981d0377 SH |
3439 | mac_cfg = skge_read8(hw, B2_MAC_CFG); |
3440 | hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; | |
3441 | hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; | |
baef58b1 SH |
3442 | |
3443 | /* read the adapters RAM size */ | |
3444 | t8 = skge_read8(hw, B2_E_0); | |
3445 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3446 | if (t8 == 3) { | |
3447 | /* special case: 4 x 64k x 36, offset = 0x80000 */ | |
3448 | hw->ram_size = 0x100000; | |
3449 | hw->ram_offset = 0x80000; | |
3450 | } else | |
3451 | hw->ram_size = t8 * 512; | |
3452 | } | |
3453 | else if (t8 == 0) | |
3454 | hw->ram_size = 0x20000; | |
3455 | else | |
3456 | hw->ram_size = t8 * 4096; | |
3457 | ||
4ebabfcb | 3458 | hw->intr_mask = IS_HW_ERR; |
cfc3ed79 | 3459 | |
4ebabfcb | 3460 | /* Use PHY IRQ for all but fiber based Genesis board */ |
64f6b64d SH |
3461 | if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) |
3462 | hw->intr_mask |= IS_EXT_REG; | |
3463 | ||
baef58b1 SH |
3464 | if (hw->chip_id == CHIP_ID_GENESIS) |
3465 | genesis_init(hw); | |
3466 | else { | |
3467 | /* switch power to VCC (WA for VAUX problem) */ | |
3468 | skge_write8(hw, B0_POWER_CTRL, | |
3469 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
adba9e23 | 3470 | |
050ec18a SH |
3471 | /* avoid boards with stuck Hardware error bits */ |
3472 | if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && | |
3473 | (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { | |
1479d13c | 3474 | dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); |
050ec18a SH |
3475 | hw->intr_mask &= ~IS_HW_ERR; |
3476 | } | |
3477 | ||
adba9e23 SH |
3478 | /* Clear PHY COMA */ |
3479 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3480 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); | |
3481 | reg &= ~PCI_PHY_COMA; | |
3482 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); | |
3483 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
3484 | ||
3485 | ||
981d0377 | 3486 | for (i = 0; i < hw->ports; i++) { |
6b0c1480 SH |
3487 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); |
3488 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
baef58b1 SH |
3489 | } |
3490 | } | |
3491 | ||
3492 | /* turn off hardware timer (unused) */ | |
3493 | skge_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3494 | skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
3495 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
3496 | ||
3497 | /* enable the Tx Arbiters */ | |
981d0377 | 3498 | for (i = 0; i < hw->ports; i++) |
6b0c1480 | 3499 | skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); |
baef58b1 SH |
3500 | |
3501 | /* Initialize ram interface */ | |
3502 | skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); | |
3503 | ||
3504 | skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); | |
3505 | skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); | |
3506 | skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); | |
3507 | skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); | |
3508 | skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); | |
3509 | skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); | |
3510 | skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); | |
3511 | skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); | |
3512 | skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); | |
3513 | skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); | |
3514 | skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); | |
3515 | skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); | |
3516 | ||
3517 | skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); | |
3518 | ||
3519 | /* Set interrupt moderation for Transmit only | |
3520 | * Receive interrupts avoided by NAPI | |
3521 | */ | |
3522 | skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); | |
3523 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); | |
3524 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
3525 | ||
baef58b1 SH |
3526 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3527 | ||
981d0377 | 3528 | for (i = 0; i < hw->ports; i++) { |
baef58b1 SH |
3529 | if (hw->chip_id == CHIP_ID_GENESIS) |
3530 | genesis_reset(hw, i); | |
3531 | else | |
3532 | yukon_reset(hw, i); | |
3533 | } | |
baef58b1 SH |
3534 | |
3535 | return 0; | |
3536 | } | |
3537 | ||
3538 | /* Initialize network device */ | |
981d0377 SH |
3539 | static struct net_device *skge_devinit(struct skge_hw *hw, int port, |
3540 | int highmem) | |
baef58b1 SH |
3541 | { |
3542 | struct skge_port *skge; | |
3543 | struct net_device *dev = alloc_etherdev(sizeof(*skge)); | |
3544 | ||
3545 | if (!dev) { | |
1479d13c | 3546 | dev_err(&hw->pdev->dev, "etherdev alloc failed\n"); |
baef58b1 SH |
3547 | return NULL; |
3548 | } | |
3549 | ||
baef58b1 SH |
3550 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
3551 | dev->open = skge_up; | |
3552 | dev->stop = skge_down; | |
2cd8e5d3 | 3553 | dev->do_ioctl = skge_ioctl; |
baef58b1 SH |
3554 | dev->hard_start_xmit = skge_xmit_frame; |
3555 | dev->get_stats = skge_get_stats; | |
3556 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3557 | dev->set_multicast_list = genesis_set_multicast; | |
3558 | else | |
3559 | dev->set_multicast_list = yukon_set_multicast; | |
3560 | ||
3561 | dev->set_mac_address = skge_set_mac_address; | |
3562 | dev->change_mtu = skge_change_mtu; | |
3563 | SET_ETHTOOL_OPS(dev, &skge_ethtool_ops); | |
3564 | dev->tx_timeout = skge_tx_timeout; | |
3565 | dev->watchdog_timeo = TX_WATCHDOG; | |
baef58b1 SH |
3566 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3567 | dev->poll_controller = skge_netpoll; | |
3568 | #endif | |
3569 | dev->irq = hw->pdev->irq; | |
513f533e | 3570 | |
981d0377 SH |
3571 | if (highmem) |
3572 | dev->features |= NETIF_F_HIGHDMA; | |
baef58b1 SH |
3573 | |
3574 | skge = netdev_priv(dev); | |
bea3348e | 3575 | netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT); |
baef58b1 SH |
3576 | skge->netdev = dev; |
3577 | skge->hw = hw; | |
3578 | skge->msg_enable = netif_msg_init(debug, default_msg); | |
9cbe330f | 3579 | |
baef58b1 SH |
3580 | skge->tx_ring.count = DEFAULT_TX_RING_SIZE; |
3581 | skge->rx_ring.count = DEFAULT_RX_RING_SIZE; | |
3582 | ||
3583 | /* Auto speed and flow control */ | |
3584 | skge->autoneg = AUTONEG_ENABLE; | |
5d5c8e03 | 3585 | skge->flow_control = FLOW_MODE_SYM_OR_REM; |
baef58b1 SH |
3586 | skge->duplex = -1; |
3587 | skge->speed = -1; | |
31b619c5 | 3588 | skge->advertising = skge_supported_modes(hw); |
5b982c5b SH |
3589 | |
3590 | if (pci_wake_enabled(hw->pdev)) | |
3591 | skge->wol = wol_supported(hw) & WAKE_MAGIC; | |
baef58b1 SH |
3592 | |
3593 | hw->dev[port] = dev; | |
3594 | ||
3595 | skge->port = port; | |
3596 | ||
64f6b64d | 3597 | /* Only used for Genesis XMAC */ |
9cbe330f | 3598 | setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge); |
64f6b64d | 3599 | |
baef58b1 SH |
3600 | if (hw->chip_id != CHIP_ID_GENESIS) { |
3601 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
3602 | skge->rx_csum = 1; | |
3603 | } | |
3604 | ||
3605 | /* read the mac address */ | |
3606 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); | |
56230d53 | 3607 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
baef58b1 SH |
3608 | |
3609 | /* device is off until link detection */ | |
3610 | netif_carrier_off(dev); | |
3611 | netif_stop_queue(dev); | |
3612 | ||
3613 | return dev; | |
3614 | } | |
3615 | ||
3616 | static void __devinit skge_show_addr(struct net_device *dev) | |
3617 | { | |
3618 | const struct skge_port *skge = netdev_priv(dev); | |
0795af57 | 3619 | DECLARE_MAC_BUF(mac); |
baef58b1 SH |
3620 | |
3621 | if (netif_msg_probe(skge)) | |
0795af57 JP |
3622 | printk(KERN_INFO PFX "%s: addr %s\n", |
3623 | dev->name, print_mac(mac, dev->dev_addr)); | |
baef58b1 SH |
3624 | } |
3625 | ||
3626 | static int __devinit skge_probe(struct pci_dev *pdev, | |
3627 | const struct pci_device_id *ent) | |
3628 | { | |
3629 | struct net_device *dev, *dev1; | |
3630 | struct skge_hw *hw; | |
3631 | int err, using_dac = 0; | |
3632 | ||
203babb6 SH |
3633 | err = pci_enable_device(pdev); |
3634 | if (err) { | |
1479d13c | 3635 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
baef58b1 SH |
3636 | goto err_out; |
3637 | } | |
3638 | ||
203babb6 SH |
3639 | err = pci_request_regions(pdev, DRV_NAME); |
3640 | if (err) { | |
1479d13c | 3641 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
baef58b1 SH |
3642 | goto err_out_disable_pdev; |
3643 | } | |
3644 | ||
3645 | pci_set_master(pdev); | |
3646 | ||
93aea718 | 3647 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
baef58b1 | 3648 | using_dac = 1; |
77783a78 | 3649 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
93aea718 SH |
3650 | } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { |
3651 | using_dac = 0; | |
3652 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3653 | } | |
3654 | ||
3655 | if (err) { | |
1479d13c | 3656 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
93aea718 | 3657 | goto err_out_free_regions; |
baef58b1 SH |
3658 | } |
3659 | ||
3660 | #ifdef __BIG_ENDIAN | |
8f3f8193 | 3661 | /* byte swap descriptors in hardware */ |
baef58b1 SH |
3662 | { |
3663 | u32 reg; | |
3664 | ||
3665 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3666 | reg |= PCI_REV_DESC; | |
3667 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3668 | } | |
3669 | #endif | |
3670 | ||
3671 | err = -ENOMEM; | |
7e863061 | 3672 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
baef58b1 | 3673 | if (!hw) { |
1479d13c | 3674 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
baef58b1 SH |
3675 | goto err_out_free_regions; |
3676 | } | |
3677 | ||
baef58b1 | 3678 | hw->pdev = pdev; |
d38efdd6 | 3679 | spin_lock_init(&hw->hw_lock); |
9cbe330f SH |
3680 | spin_lock_init(&hw->phy_lock); |
3681 | tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw); | |
baef58b1 SH |
3682 | |
3683 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3684 | if (!hw->regs) { | |
1479d13c | 3685 | dev_err(&pdev->dev, "cannot map device registers\n"); |
baef58b1 SH |
3686 | goto err_out_free_hw; |
3687 | } | |
3688 | ||
baef58b1 SH |
3689 | err = skge_reset(hw); |
3690 | if (err) | |
ccdaa2a9 | 3691 | goto err_out_iounmap; |
baef58b1 | 3692 | |
7c7459d1 GKH |
3693 | printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n", |
3694 | (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, | |
981d0377 | 3695 | skge_board_name(hw), hw->chip_rev); |
baef58b1 | 3696 | |
ccdaa2a9 SH |
3697 | dev = skge_devinit(hw, 0, using_dac); |
3698 | if (!dev) | |
baef58b1 SH |
3699 | goto err_out_led_off; |
3700 | ||
fae87592 | 3701 | /* Some motherboards are broken and has zero in ROM. */ |
1479d13c SH |
3702 | if (!is_valid_ether_addr(dev->dev_addr)) |
3703 | dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); | |
631ae320 | 3704 | |
203babb6 SH |
3705 | err = register_netdev(dev); |
3706 | if (err) { | |
1479d13c | 3707 | dev_err(&pdev->dev, "cannot register net device\n"); |
baef58b1 SH |
3708 | goto err_out_free_netdev; |
3709 | } | |
3710 | ||
ccdaa2a9 SH |
3711 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw); |
3712 | if (err) { | |
1479d13c | 3713 | dev_err(&pdev->dev, "%s: cannot assign irq %d\n", |
ccdaa2a9 SH |
3714 | dev->name, pdev->irq); |
3715 | goto err_out_unregister; | |
3716 | } | |
baef58b1 SH |
3717 | skge_show_addr(dev); |
3718 | ||
981d0377 | 3719 | if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { |
baef58b1 SH |
3720 | if (register_netdev(dev1) == 0) |
3721 | skge_show_addr(dev1); | |
3722 | else { | |
3723 | /* Failure to register second port need not be fatal */ | |
1479d13c | 3724 | dev_warn(&pdev->dev, "register of second port failed\n"); |
baef58b1 SH |
3725 | hw->dev[1] = NULL; |
3726 | free_netdev(dev1); | |
3727 | } | |
3728 | } | |
ccdaa2a9 | 3729 | pci_set_drvdata(pdev, hw); |
baef58b1 SH |
3730 | |
3731 | return 0; | |
3732 | ||
ccdaa2a9 SH |
3733 | err_out_unregister: |
3734 | unregister_netdev(dev); | |
baef58b1 SH |
3735 | err_out_free_netdev: |
3736 | free_netdev(dev); | |
3737 | err_out_led_off: | |
3738 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
baef58b1 SH |
3739 | err_out_iounmap: |
3740 | iounmap(hw->regs); | |
3741 | err_out_free_hw: | |
3742 | kfree(hw); | |
3743 | err_out_free_regions: | |
3744 | pci_release_regions(pdev); | |
3745 | err_out_disable_pdev: | |
3746 | pci_disable_device(pdev); | |
3747 | pci_set_drvdata(pdev, NULL); | |
3748 | err_out: | |
3749 | return err; | |
3750 | } | |
3751 | ||
3752 | static void __devexit skge_remove(struct pci_dev *pdev) | |
3753 | { | |
3754 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3755 | struct net_device *dev0, *dev1; | |
3756 | ||
95566065 | 3757 | if (!hw) |
baef58b1 SH |
3758 | return; |
3759 | ||
208491d8 SH |
3760 | flush_scheduled_work(); |
3761 | ||
baef58b1 SH |
3762 | if ((dev1 = hw->dev[1])) |
3763 | unregister_netdev(dev1); | |
3764 | dev0 = hw->dev[0]; | |
3765 | unregister_netdev(dev0); | |
3766 | ||
9cbe330f SH |
3767 | tasklet_disable(&hw->phy_task); |
3768 | ||
7c442fa1 SH |
3769 | spin_lock_irq(&hw->hw_lock); |
3770 | hw->intr_mask = 0; | |
46a60f2d | 3771 | skge_write32(hw, B0_IMSK, 0); |
78bc2186 | 3772 | skge_read32(hw, B0_IMSK); |
7c442fa1 SH |
3773 | spin_unlock_irq(&hw->hw_lock); |
3774 | ||
46a60f2d | 3775 | skge_write16(hw, B0_LED, LED_STAT_OFF); |
46a60f2d SH |
3776 | skge_write8(hw, B0_CTST, CS_RST_SET); |
3777 | ||
baef58b1 SH |
3778 | free_irq(pdev->irq, hw); |
3779 | pci_release_regions(pdev); | |
3780 | pci_disable_device(pdev); | |
3781 | if (dev1) | |
3782 | free_netdev(dev1); | |
3783 | free_netdev(dev0); | |
46a60f2d | 3784 | |
baef58b1 SH |
3785 | iounmap(hw->regs); |
3786 | kfree(hw); | |
3787 | pci_set_drvdata(pdev, NULL); | |
3788 | } | |
3789 | ||
3790 | #ifdef CONFIG_PM | |
2a569579 | 3791 | static int skge_suspend(struct pci_dev *pdev, pm_message_t state) |
baef58b1 SH |
3792 | { |
3793 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
a504e64a SH |
3794 | int i, err, wol = 0; |
3795 | ||
e3b7df17 SH |
3796 | if (!hw) |
3797 | return 0; | |
3798 | ||
a504e64a SH |
3799 | err = pci_save_state(pdev); |
3800 | if (err) | |
3801 | return err; | |
baef58b1 | 3802 | |
d38efdd6 | 3803 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 3804 | struct net_device *dev = hw->dev[i]; |
a504e64a | 3805 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 | 3806 | |
a504e64a SH |
3807 | if (netif_running(dev)) |
3808 | skge_down(dev); | |
3809 | if (skge->wol) | |
3810 | skge_wol_init(skge); | |
d38efdd6 | 3811 | |
a504e64a | 3812 | wol |= skge->wol; |
baef58b1 SH |
3813 | } |
3814 | ||
d38efdd6 | 3815 | skge_write32(hw, B0_IMSK, 0); |
2a569579 | 3816 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
baef58b1 SH |
3817 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
3818 | ||
3819 | return 0; | |
3820 | } | |
3821 | ||
3822 | static int skge_resume(struct pci_dev *pdev) | |
3823 | { | |
3824 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
d38efdd6 | 3825 | int i, err; |
baef58b1 | 3826 | |
e3b7df17 SH |
3827 | if (!hw) |
3828 | return 0; | |
3829 | ||
a504e64a SH |
3830 | err = pci_set_power_state(pdev, PCI_D0); |
3831 | if (err) | |
3832 | goto out; | |
3833 | ||
3834 | err = pci_restore_state(pdev); | |
3835 | if (err) | |
3836 | goto out; | |
3837 | ||
baef58b1 SH |
3838 | pci_enable_wake(pdev, PCI_D0, 0); |
3839 | ||
d38efdd6 SH |
3840 | err = skge_reset(hw); |
3841 | if (err) | |
3842 | goto out; | |
baef58b1 | 3843 | |
d38efdd6 | 3844 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 3845 | struct net_device *dev = hw->dev[i]; |
d38efdd6 | 3846 | |
d38efdd6 SH |
3847 | if (netif_running(dev)) { |
3848 | err = skge_up(dev); | |
3849 | ||
3850 | if (err) { | |
3851 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3852 | dev->name, err); | |
edd702e8 | 3853 | dev_close(dev); |
d38efdd6 SH |
3854 | goto out; |
3855 | } | |
baef58b1 SH |
3856 | } |
3857 | } | |
d38efdd6 SH |
3858 | out: |
3859 | return err; | |
baef58b1 SH |
3860 | } |
3861 | #endif | |
3862 | ||
692412b3 SH |
3863 | static void skge_shutdown(struct pci_dev *pdev) |
3864 | { | |
3865 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3866 | int i, wol = 0; | |
3867 | ||
e3b7df17 SH |
3868 | if (!hw) |
3869 | return; | |
3870 | ||
692412b3 SH |
3871 | for (i = 0; i < hw->ports; i++) { |
3872 | struct net_device *dev = hw->dev[i]; | |
3873 | struct skge_port *skge = netdev_priv(dev); | |
3874 | ||
3875 | if (skge->wol) | |
3876 | skge_wol_init(skge); | |
3877 | wol |= skge->wol; | |
3878 | } | |
3879 | ||
3880 | pci_enable_wake(pdev, PCI_D3hot, wol); | |
3881 | pci_enable_wake(pdev, PCI_D3cold, wol); | |
3882 | ||
3883 | pci_disable_device(pdev); | |
3884 | pci_set_power_state(pdev, PCI_D3hot); | |
3885 | ||
3886 | } | |
3887 | ||
baef58b1 SH |
3888 | static struct pci_driver skge_driver = { |
3889 | .name = DRV_NAME, | |
3890 | .id_table = skge_id_table, | |
3891 | .probe = skge_probe, | |
3892 | .remove = __devexit_p(skge_remove), | |
3893 | #ifdef CONFIG_PM | |
3894 | .suspend = skge_suspend, | |
3895 | .resume = skge_resume, | |
3896 | #endif | |
692412b3 | 3897 | .shutdown = skge_shutdown, |
baef58b1 SH |
3898 | }; |
3899 | ||
3900 | static int __init skge_init_module(void) | |
3901 | { | |
29917620 | 3902 | return pci_register_driver(&skge_driver); |
baef58b1 SH |
3903 | } |
3904 | ||
3905 | static void __exit skge_cleanup_module(void) | |
3906 | { | |
3907 | pci_unregister_driver(&skge_driver); | |
3908 | } | |
3909 | ||
3910 | module_init(skge_init_module); | |
3911 | module_exit(skge_cleanup_module); |