Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
cd28ab6a | 26 | #include <linux/config.h> |
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a SH |
28 | #include <linux/kernel.h> |
29 | #include <linux/version.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
d0bbccfa | 32 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
33 | #include <linux/etherdevice.h> |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/delay.h> | |
91c86df5 | 40 | #include <linux/workqueue.h> |
d1f13708 | 41 | #include <linux/if_vlan.h> |
d70cd51a | 42 | #include <linux/prefetch.h> |
ef743d33 | 43 | #include <linux/mii.h> |
cd28ab6a SH |
44 | |
45 | #include <asm/irq.h> | |
46 | ||
d1f13708 | 47 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
48 | #define SKY2_VLAN_TAG_USED 1 | |
49 | #endif | |
50 | ||
cd28ab6a SH |
51 | #include "sky2.h" |
52 | ||
53 | #define DRV_NAME "sky2" | |
fa8d3549 | 54 | #define DRV_VERSION "0.15" |
cd28ab6a SH |
55 | #define PFX DRV_NAME " " |
56 | ||
57 | /* | |
58 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
59 | * that are organized into three (receive, transmit, status) different rings | |
60 | * similar to Tigon3. A transmit can require several elements; | |
61 | * a receive requires one (or two if using 64 bit dma). | |
62 | */ | |
63 | ||
cd28ab6a | 64 | #define is_ec_a1(hw) \ |
21437643 | 65 | unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \ |
66 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
cd28ab6a | 67 | |
13210ce5 | 68 | #define RX_LE_SIZE 512 |
cd28ab6a | 69 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 70 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 71 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 72 | #define RX_SKB_ALIGN 8 |
793b883e SH |
73 | |
74 | #define TX_RING_SIZE 512 | |
75 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
76 | #define TX_MIN_PENDING 64 | |
77 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 78 | |
793b883e | 79 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
80 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
81 | #define ETH_JUMBO_MTU 9000 | |
82 | #define TX_WATCHDOG (5 * HZ) | |
83 | #define NAPI_WEIGHT 64 | |
84 | #define PHY_RETRIES 1000 | |
85 | ||
86 | static const u32 default_msg = | |
793b883e SH |
87 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
88 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 89 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 90 | |
793b883e | 91 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
92 | module_param(debug, int, 0); |
93 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
94 | ||
bdb5c58e SH |
95 | static int copybreak __read_mostly = 256; |
96 | module_param(copybreak, int, 0); | |
97 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
98 | ||
4d52b48b SH |
99 | static int disable_msi = 0; |
100 | module_param(disable_msi, int, 0); | |
101 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
102 | ||
cd28ab6a | 103 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
123 | { 0 } |
124 | }; | |
793b883e | 125 | |
cd28ab6a SH |
126 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
127 | ||
128 | /* Avoid conditionals by using array */ | |
129 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
130 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
131 | ||
92f965e8 SH |
132 | /* This driver supports yukon2 chipset only */ |
133 | static const char *yukon2_name[] = { | |
134 | "XL", /* 0xb3 */ | |
135 | "EC Ultra", /* 0xb4 */ | |
136 | "UNKNOWN", /* 0xb5 */ | |
137 | "EC", /* 0xb6 */ | |
138 | "FE", /* 0xb7 */ | |
793b883e SH |
139 | }; |
140 | ||
793b883e | 141 | /* Access to external PHY */ |
ef743d33 | 142 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
143 | { |
144 | int i; | |
145 | ||
146 | gma_write16(hw, port, GM_SMI_DATA, val); | |
147 | gma_write16(hw, port, GM_SMI_CTRL, | |
148 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
149 | ||
150 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 151 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 152 | return 0; |
793b883e | 153 | udelay(1); |
cd28ab6a | 154 | } |
ef743d33 | 155 | |
793b883e | 156 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 157 | return -ETIMEDOUT; |
cd28ab6a SH |
158 | } |
159 | ||
ef743d33 | 160 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
161 | { |
162 | int i; | |
163 | ||
793b883e | 164 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
165 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
166 | ||
167 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 | 168 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
169 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
170 | return 0; | |
171 | } | |
172 | ||
793b883e | 173 | udelay(1); |
cd28ab6a SH |
174 | } |
175 | ||
ef743d33 | 176 | return -ETIMEDOUT; |
177 | } | |
178 | ||
179 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
180 | { | |
181 | u16 v; | |
182 | ||
183 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
184 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
185 | return v; | |
cd28ab6a SH |
186 | } |
187 | ||
5afa0a9c | 188 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
189 | { | |
190 | u16 power_control; | |
191 | u32 reg1; | |
192 | int vaux; | |
193 | int ret = 0; | |
194 | ||
195 | pr_debug("sky2_set_power_state %d\n", state); | |
196 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
197 | ||
198 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | |
08c06d8a | 199 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
5afa0a9c | 200 | (power_control & PCI_PM_CAP_PME_D3cold); |
201 | ||
202 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | |
203 | ||
204 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
205 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
206 | ||
207 | switch (state) { | |
208 | case PCI_D0: | |
209 | /* switch power to VCC (WA for VAUX problem) */ | |
210 | sky2_write8(hw, B0_POWER_CTRL, | |
211 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
212 | ||
213 | /* disable Core Clock Division, */ | |
214 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
215 | ||
216 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
217 | /* enable bits are inverted */ | |
218 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
219 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
220 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
221 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
222 | else | |
223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
224 | ||
225 | /* Turn off phy power saving */ | |
226 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
227 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
228 | ||
d571b694 | 229 | /* looks like this XL is back asswards .. */ |
5afa0a9c | 230 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
231 | reg1 |= PCI_Y2_PHY1_COMA; | |
232 | if (hw->ports > 1) | |
233 | reg1 |= PCI_Y2_PHY2_COMA; | |
234 | } | |
977bdf06 SH |
235 | |
236 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
237 | pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0); | |
238 | pci_read_config_dword(hw->pdev, PCI_DEV_REG4, ®1); | |
239 | reg1 &= P_ASPM_CONTROL_MSK; | |
240 | pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1); | |
241 | pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0); | |
242 | } | |
243 | ||
5afa0a9c | 244 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); |
977bdf06 | 245 | |
5afa0a9c | 246 | break; |
247 | ||
248 | case PCI_D3hot: | |
249 | case PCI_D3cold: | |
250 | /* Turn on phy power saving */ | |
251 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
252 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
253 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
254 | else | |
255 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
256 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
257 | ||
258 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
259 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
260 | else | |
261 | /* enable bits are inverted */ | |
262 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
263 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
264 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
265 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
266 | ||
267 | /* switch power to VAUX */ | |
268 | if (vaux && state != PCI_D3cold) | |
269 | sky2_write8(hw, B0_POWER_CTRL, | |
270 | (PC_VAUX_ENA | PC_VCC_ENA | | |
271 | PC_VAUX_ON | PC_VCC_OFF)); | |
272 | break; | |
273 | default: | |
274 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
275 | ret = -1; | |
276 | } | |
277 | ||
278 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | |
279 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
280 | return ret; | |
281 | } | |
282 | ||
cd28ab6a SH |
283 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
284 | { | |
285 | u16 reg; | |
286 | ||
287 | /* disable all GMAC IRQ's */ | |
288 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
289 | /* disable PHY IRQs */ | |
290 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 291 | |
cd28ab6a SH |
292 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
293 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
294 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
295 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
296 | ||
297 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
298 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
299 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
300 | } | |
301 | ||
302 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
303 | { | |
304 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 305 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 306 | |
793b883e | 307 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
308 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
309 | ||
310 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 311 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
312 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
313 | ||
314 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
315 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
316 | else | |
317 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
318 | ||
319 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
320 | } | |
321 | ||
322 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
323 | if (hw->copper) { | |
324 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
325 | /* enable automatic crossover */ | |
326 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
327 | } else { | |
328 | /* disable energy detect */ | |
329 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
330 | ||
331 | /* enable automatic crossover */ | |
332 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
333 | ||
334 | if (sky2->autoneg == AUTONEG_ENABLE && | |
335 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
336 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
337 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
338 | } | |
339 | } | |
340 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
341 | } else { | |
342 | /* workaround for deviation #4.88 (CRC errors) */ | |
343 | /* disable Automatic Crossover */ | |
344 | ||
345 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
346 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
347 | ||
348 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
349 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
350 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
351 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
352 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
353 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
354 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
355 | ||
356 | /* select page 1 to access Fiber registers */ | |
357 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
358 | } | |
cd28ab6a SH |
359 | } |
360 | ||
361 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
362 | if (sky2->autoneg == AUTONEG_DISABLE) | |
363 | ctrl &= ~PHY_CT_ANE; | |
364 | else | |
365 | ctrl |= PHY_CT_ANE; | |
366 | ||
367 | ctrl |= PHY_CT_RESET; | |
368 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
369 | ||
370 | ctrl = 0; | |
371 | ct1000 = 0; | |
372 | adv = PHY_AN_CSMA; | |
373 | ||
374 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
375 | if (hw->copper) { | |
376 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
377 | ct1000 |= PHY_M_1000C_AFD; | |
378 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
379 | ct1000 |= PHY_M_1000C_AHD; | |
380 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
381 | adv |= PHY_M_AN_100_FD; | |
382 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
383 | adv |= PHY_M_AN_100_HD; | |
384 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
385 | adv |= PHY_M_AN_10_FD; | |
386 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
387 | adv |= PHY_M_AN_10_HD; | |
793b883e | 388 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
389 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
390 | ||
391 | /* Set Flow-control capabilities */ | |
392 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 393 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 394 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 395 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
396 | else if (!sky2->rx_pause && sky2->tx_pause) |
397 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
398 | ||
399 | /* Restart Auto-negotiation */ | |
400 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
401 | } else { | |
402 | /* forced speed/duplex settings */ | |
403 | ct1000 = PHY_M_1000C_MSE; | |
404 | ||
405 | if (sky2->duplex == DUPLEX_FULL) | |
406 | ctrl |= PHY_CT_DUP_MD; | |
407 | ||
408 | switch (sky2->speed) { | |
409 | case SPEED_1000: | |
410 | ctrl |= PHY_CT_SP1000; | |
411 | break; | |
412 | case SPEED_100: | |
413 | ctrl |= PHY_CT_SP100; | |
414 | break; | |
415 | } | |
416 | ||
417 | ctrl |= PHY_CT_RESET; | |
418 | } | |
419 | ||
420 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
421 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
422 | ||
423 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
424 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
425 | ||
426 | /* Setup Phy LED's */ | |
427 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
428 | ledover = 0; | |
429 | ||
430 | switch (hw->chip_id) { | |
431 | case CHIP_ID_YUKON_FE: | |
432 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
433 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
434 | ||
435 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
436 | ||
437 | /* delete ACT LED control bits */ | |
438 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
439 | /* change ACT LED control to blink mode */ | |
440 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
441 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
442 | break; | |
443 | ||
444 | case CHIP_ID_YUKON_XL: | |
793b883e | 445 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
446 | |
447 | /* select page 3 to access LED control register */ | |
448 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
449 | ||
450 | /* set LED Function Control register */ | |
793b883e SH |
451 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
452 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
453 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
454 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
455 | |
456 | /* set Polarity Control register */ | |
457 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
458 | (PHY_M_POLC_LS1_P_MIX(4) | |
459 | PHY_M_POLC_IS0_P_MIX(4) | | |
460 | PHY_M_POLC_LOS_CTRL(2) | | |
461 | PHY_M_POLC_INIT_CTRL(2) | | |
462 | PHY_M_POLC_STA1_CTRL(2) | | |
463 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
464 | |
465 | /* restore page register */ | |
793b883e | 466 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
467 | break; |
468 | ||
469 | default: | |
470 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
471 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
472 | /* turn off the Rx LED (LED_RX) */ | |
473 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
474 | } | |
475 | ||
977bdf06 SH |
476 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { |
477 | /* apply fixes in PHY AFE */ | |
478 | gm_phy_write(hw, port, 22, 255); | |
479 | /* increase differential signal amplitude in 10BASE-T */ | |
480 | gm_phy_write(hw, port, 24, 0xaa99); | |
481 | gm_phy_write(hw, port, 23, 0x2011); | |
cd28ab6a | 482 | |
977bdf06 SH |
483 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
484 | gm_phy_write(hw, port, 24, 0xa204); | |
485 | gm_phy_write(hw, port, 23, 0x2002); | |
486 | ||
487 | /* set page register to 0 */ | |
488 | gm_phy_write(hw, port, 22, 0); | |
489 | } else { | |
490 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
cd28ab6a | 491 | |
977bdf06 SH |
492 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
493 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
494 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
495 | } | |
cd28ab6a | 496 | |
977bdf06 SH |
497 | if (ledover) |
498 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
499 | ||
500 | } | |
d571b694 | 501 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
502 | if (sky2->autoneg == AUTONEG_ENABLE) |
503 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
504 | else | |
505 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
506 | } | |
507 | ||
1b537565 SH |
508 | /* Force a renegotiation */ |
509 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
510 | { | |
511 | down(&sky2->phy_sema); | |
512 | sky2_phy_init(sky2->hw, sky2->port); | |
513 | up(&sky2->phy_sema); | |
514 | } | |
515 | ||
cd28ab6a SH |
516 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
517 | { | |
518 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
519 | u16 reg; | |
520 | int i; | |
521 | const u8 *addr = hw->dev[port]->dev_addr; | |
522 | ||
42eeea01 | 523 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
524 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
525 | |
526 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
527 | ||
793b883e | 528 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
529 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
530 | /* clear GMAC 1 Control reset */ | |
531 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
532 | do { | |
533 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
534 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
535 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
536 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
537 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
538 | } | |
539 | ||
cd28ab6a SH |
540 | if (sky2->autoneg == AUTONEG_DISABLE) { |
541 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
542 | reg |= GM_GPCR_AU_ALL_DIS; | |
543 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
544 | gma_read16(hw, port, GM_GP_CTRL); | |
545 | ||
cd28ab6a SH |
546 | switch (sky2->speed) { |
547 | case SPEED_1000: | |
6f4c56b2 | 548 | reg &= ~GM_GPCR_SPEED_100; |
cd28ab6a | 549 | reg |= GM_GPCR_SPEED_1000; |
6f4c56b2 | 550 | break; |
cd28ab6a | 551 | case SPEED_100: |
6f4c56b2 | 552 | reg &= ~GM_GPCR_SPEED_1000; |
cd28ab6a | 553 | reg |= GM_GPCR_SPEED_100; |
6f4c56b2 SH |
554 | break; |
555 | case SPEED_10: | |
556 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
557 | break; | |
cd28ab6a SH |
558 | } |
559 | ||
560 | if (sky2->duplex == DUPLEX_FULL) | |
561 | reg |= GM_GPCR_DUP_FULL; | |
562 | } else | |
563 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
564 | ||
565 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
566 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
567 | reg |= |
568 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
569 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
570 | /* disable Rx flow-control */ |
571 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
572 | } | |
573 | ||
574 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
575 | ||
793b883e | 576 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 577 | |
91c86df5 | 578 | down(&sky2->phy_sema); |
cd28ab6a | 579 | sky2_phy_init(hw, port); |
91c86df5 | 580 | up(&sky2->phy_sema); |
cd28ab6a SH |
581 | |
582 | /* MIB clear */ | |
583 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
584 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
585 | ||
586 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 587 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
588 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
589 | ||
590 | /* transmit control */ | |
591 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
592 | ||
593 | /* receive control reg: unicast + multicast + no FCS */ | |
594 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 595 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
596 | |
597 | /* transmit flow control */ | |
598 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
599 | ||
600 | /* transmit parameter */ | |
601 | gma_write16(hw, port, GM_TX_PARAM, | |
602 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
603 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
604 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
605 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
606 | ||
607 | /* serial mode register */ | |
608 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 609 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 610 | |
6b1a3aef | 611 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
612 | reg |= GM_SMOD_JUMBO_ENA; |
613 | ||
614 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
615 | ||
cd28ab6a SH |
616 | /* virtual address for data */ |
617 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
618 | ||
793b883e SH |
619 | /* physical address: used for pause frames */ |
620 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
621 | ||
622 | /* ignore counter overflows */ | |
cd28ab6a SH |
623 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
624 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
625 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
626 | ||
627 | /* Configure Rx MAC FIFO */ | |
628 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 629 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
d1f13708 | 630 | GMF_RX_CTRL_DEF); |
cd28ab6a | 631 | |
d571b694 | 632 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 633 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 634 | |
793b883e SH |
635 | /* Set threshold to 0xa (64 bytes) |
636 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
637 | */ |
638 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
639 | ||
640 | /* Configure Tx MAC FIFO */ | |
641 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
642 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 643 | |
644 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
645 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
646 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
647 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
648 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
649 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
650 | /* Disable Store & Forward mode for TX */ | |
651 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
652 | } | |
653 | } | |
654 | ||
cd28ab6a SH |
655 | } |
656 | ||
1c28f6ba SH |
657 | /* Assign Ram Buffer allocation. |
658 | * start and end are in units of 4k bytes | |
659 | * ram registers are in units of 64bit words | |
660 | */ | |
661 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 662 | { |
1c28f6ba | 663 | u32 start, end; |
cd28ab6a | 664 | |
1c28f6ba SH |
665 | start = startk * 4096/8; |
666 | end = (endk * 4096/8) - 1; | |
793b883e | 667 | |
cd28ab6a SH |
668 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
669 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
670 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
671 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
672 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
673 | ||
674 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
675 | u32 space = (endk - startk) * 4096/8; |
676 | u32 tp = space - space/4; | |
793b883e | 677 | |
1c28f6ba SH |
678 | /* On receive queue's set the thresholds |
679 | * give receiver priority when > 3/4 full | |
680 | * send pause when down to 2K | |
681 | */ | |
682 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
683 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 684 | |
1c28f6ba SH |
685 | tp = space - 2048/8; |
686 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
687 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
688 | } else { |
689 | /* Enable store & forward on Tx queue's because | |
690 | * Tx FIFO is only 1K on Yukon | |
691 | */ | |
692 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
693 | } | |
694 | ||
695 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 696 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
697 | } |
698 | ||
cd28ab6a | 699 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 700 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
701 | { |
702 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
703 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
704 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 705 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
706 | } |
707 | ||
cd28ab6a SH |
708 | /* Setup prefetch unit registers. This is the interface between |
709 | * hardware and driver list elements | |
710 | */ | |
8cc048e3 | 711 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
712 | u64 addr, u32 last) |
713 | { | |
cd28ab6a SH |
714 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
715 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
716 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
717 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
718 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
719 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
720 | |
721 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
722 | } |
723 | ||
793b883e SH |
724 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
725 | { | |
726 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
727 | ||
728 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
729 | return le; | |
730 | } | |
cd28ab6a SH |
731 | |
732 | /* | |
d571b694 | 733 | * This is a workaround code taken from SysKonnect sk98lin driver |
793b883e | 734 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a | 735 | */ |
28bd181a | 736 | static void sky2_put_idx(struct sky2_hw *hw, unsigned q, |
cd28ab6a | 737 | u16 idx, u16 *last, u16 size) |
cd28ab6a | 738 | { |
762c2de2 | 739 | wmb(); |
cd28ab6a SH |
740 | if (is_ec_a1(hw) && idx < *last) { |
741 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
742 | ||
743 | if (hwget == 0) { | |
744 | /* Start prefetching again */ | |
793b883e | 745 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
746 | goto setnew; |
747 | } | |
748 | ||
793b883e | 749 | if (hwget == size - 1) { |
cd28ab6a SH |
750 | /* set watermark to one list element */ |
751 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
752 | ||
753 | /* set put index to first list element */ | |
754 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
755 | } else /* have hardware go to end of list */ |
756 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
757 | size - 1); | |
cd28ab6a | 758 | } else { |
793b883e | 759 | setnew: |
cd28ab6a | 760 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 761 | } |
bea86103 | 762 | *last = idx; |
762c2de2 | 763 | mmiowb(); |
cd28ab6a SH |
764 | } |
765 | ||
793b883e | 766 | |
cd28ab6a SH |
767 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
768 | { | |
769 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
770 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
771 | return le; | |
772 | } | |
773 | ||
a018e330 | 774 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
775 | static inline u32 high32(dma_addr_t a) | |
776 | { | |
a036119f | 777 | return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; |
a018e330 | 778 | } |
779 | ||
793b883e | 780 | /* Build description to hardware about buffer */ |
28bd181a | 781 | static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
782 | { |
783 | struct sky2_rx_le *le; | |
734d1868 SH |
784 | u32 hi = high32(map); |
785 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 786 | |
793b883e | 787 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 788 | le = sky2_next_rx(sky2); |
793b883e | 789 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
790 | le->ctrl = 0; |
791 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 792 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 793 | } |
793b883e | 794 | |
cd28ab6a | 795 | le = sky2_next_rx(sky2); |
734d1868 SH |
796 | le->addr = cpu_to_le32((u32) map); |
797 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
798 | le->ctrl = 0; |
799 | le->opcode = OP_PACKET | HW_OWNER; | |
800 | } | |
801 | ||
793b883e | 802 | |
cd28ab6a SH |
803 | /* Tell chip where to start receive checksum. |
804 | * Actually has two checksums, but set both same to avoid possible byte | |
805 | * order problems. | |
806 | */ | |
793b883e | 807 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
808 | { |
809 | struct sky2_rx_le *le; | |
810 | ||
cd28ab6a | 811 | le = sky2_next_rx(sky2); |
793b883e | 812 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
813 | le->ctrl = 0; |
814 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 815 | |
793b883e SH |
816 | sky2_write32(sky2->hw, |
817 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
818 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
819 | |
820 | } | |
821 | ||
6b1a3aef | 822 | /* |
823 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
824 | * reach the end of packet and since we can't make sure that we have | |
825 | * incoming data, we must reset the BMU while it is not doing a DMA | |
826 | * transfer. Since it is possible that the RX path is still active, | |
827 | * the RX RAM buffer will be stopped first, so any possible incoming | |
828 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
829 | * BMU is polled until any DMA in progress is ended and only then it | |
830 | * will be reset. | |
831 | */ | |
832 | static void sky2_rx_stop(struct sky2_port *sky2) | |
833 | { | |
834 | struct sky2_hw *hw = sky2->hw; | |
835 | unsigned rxq = rxqaddr[sky2->port]; | |
836 | int i; | |
837 | ||
838 | /* disable the RAM Buffer receive queue */ | |
839 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
840 | ||
841 | for (i = 0; i < 0xffff; i++) | |
842 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
843 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
844 | goto stopped; | |
845 | ||
846 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
847 | sky2->netdev->name); | |
848 | stopped: | |
849 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
850 | ||
851 | /* reset the Rx prefetch unit */ | |
852 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
853 | } | |
793b883e | 854 | |
d571b694 | 855 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
856 | static void sky2_rx_clean(struct sky2_port *sky2) |
857 | { | |
858 | unsigned i; | |
859 | ||
860 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 861 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
862 | struct ring_info *re = sky2->rx_ring + i; |
863 | ||
864 | if (re->skb) { | |
793b883e | 865 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 866 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
867 | PCI_DMA_FROMDEVICE); |
868 | kfree_skb(re->skb); | |
869 | re->skb = NULL; | |
870 | } | |
871 | } | |
872 | } | |
873 | ||
ef743d33 | 874 | /* Basic MII support */ |
875 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
876 | { | |
877 | struct mii_ioctl_data *data = if_mii(ifr); | |
878 | struct sky2_port *sky2 = netdev_priv(dev); | |
879 | struct sky2_hw *hw = sky2->hw; | |
880 | int err = -EOPNOTSUPP; | |
881 | ||
882 | if (!netif_running(dev)) | |
883 | return -ENODEV; /* Phy still in reset */ | |
884 | ||
885 | switch(cmd) { | |
886 | case SIOCGMIIPHY: | |
887 | data->phy_id = PHY_ADDR_MARV; | |
888 | ||
889 | /* fallthru */ | |
890 | case SIOCGMIIREG: { | |
891 | u16 val = 0; | |
91c86df5 SH |
892 | |
893 | down(&sky2->phy_sema); | |
ef743d33 | 894 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
91c86df5 SH |
895 | up(&sky2->phy_sema); |
896 | ||
ef743d33 | 897 | data->val_out = val; |
898 | break; | |
899 | } | |
900 | ||
901 | case SIOCSMIIREG: | |
902 | if (!capable(CAP_NET_ADMIN)) | |
903 | return -EPERM; | |
904 | ||
91c86df5 | 905 | down(&sky2->phy_sema); |
ef743d33 | 906 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
907 | data->val_in); | |
91c86df5 | 908 | up(&sky2->phy_sema); |
ef743d33 | 909 | break; |
910 | } | |
911 | return err; | |
912 | } | |
913 | ||
d1f13708 | 914 | #ifdef SKY2_VLAN_TAG_USED |
915 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
916 | { | |
917 | struct sky2_port *sky2 = netdev_priv(dev); | |
918 | struct sky2_hw *hw = sky2->hw; | |
919 | u16 port = sky2->port; | |
d1f13708 | 920 | |
302d1252 | 921 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 | 922 | |
923 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
924 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
925 | sky2->vlgrp = grp; | |
926 | ||
302d1252 | 927 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 | 928 | } |
929 | ||
930 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
931 | { | |
932 | struct sky2_port *sky2 = netdev_priv(dev); | |
933 | struct sky2_hw *hw = sky2->hw; | |
934 | u16 port = sky2->port; | |
d1f13708 | 935 | |
302d1252 | 936 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 | 937 | |
938 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
939 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
940 | if (sky2->vlgrp) | |
941 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
942 | ||
302d1252 | 943 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 | 944 | } |
945 | #endif | |
946 | ||
82788c7a SH |
947 | /* |
948 | * It appears the hardware has a bug in the FIFO logic that | |
949 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
950 | * is not aligned. ALso alloc_skb() won't align properly if slab | |
951 | * debugging is enabled. | |
952 | */ | |
953 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | |
954 | { | |
955 | struct sk_buff *skb; | |
956 | ||
957 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | |
958 | if (likely(skb)) { | |
959 | unsigned long p = (unsigned long) skb->data; | |
960 | skb_reserve(skb, | |
961 | ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p); | |
962 | } | |
963 | ||
964 | return skb; | |
965 | } | |
966 | ||
cd28ab6a SH |
967 | /* |
968 | * Allocate and setup receiver buffer pool. | |
969 | * In case of 64 bit dma, there are 2X as many list elements | |
970 | * available as ring entries | |
971 | * and need to reserve one list element so we don't wrap around. | |
972 | */ | |
6b1a3aef | 973 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 974 | { |
6b1a3aef | 975 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef | 976 | unsigned rxq = rxqaddr[sky2->port]; |
977 | int i; | |
cd28ab6a | 978 | |
6b1a3aef | 979 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 980 | sky2_qset(hw, rxq); |
977bdf06 SH |
981 | |
982 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | |
983 | /* MAC Rx RAM Read is controlled by hardware */ | |
984 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | |
985 | } | |
986 | ||
6b1a3aef | 987 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
988 | ||
989 | rx_set_checksum(sky2); | |
793b883e | 990 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 991 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 992 | |
82788c7a | 993 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); |
cd28ab6a SH |
994 | if (!re->skb) |
995 | goto nomem; | |
996 | ||
6b1a3aef | 997 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
998 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
999 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
1000 | } |
1001 | ||
6b1a3aef | 1002 | /* Tell chip about available buffers */ |
1003 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
1004 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
1005 | return 0; |
1006 | nomem: | |
1007 | sky2_rx_clean(sky2); | |
1008 | return -ENOMEM; | |
1009 | } | |
1010 | ||
1011 | /* Bring up network interface. */ | |
1012 | static int sky2_up(struct net_device *dev) | |
1013 | { | |
1014 | struct sky2_port *sky2 = netdev_priv(dev); | |
1015 | struct sky2_hw *hw = sky2->hw; | |
1016 | unsigned port = sky2->port; | |
1017 | u32 ramsize, rxspace; | |
1018 | int err = -ENOMEM; | |
1019 | ||
1020 | if (netif_msg_ifup(sky2)) | |
1021 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
1022 | ||
1023 | /* must be power of 2 */ | |
1024 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
1025 | TX_RING_SIZE * |
1026 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
1027 | &sky2->tx_le_map); |
1028 | if (!sky2->tx_le) | |
1029 | goto err_out; | |
1030 | ||
6cdbbdf3 | 1031 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1032 | GFP_KERNEL); |
1033 | if (!sky2->tx_ring) | |
1034 | goto err_out; | |
1035 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
1036 | |
1037 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1038 | &sky2->rx_le_map); | |
1039 | if (!sky2->rx_le) | |
1040 | goto err_out; | |
1041 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1042 | ||
6cdbbdf3 | 1043 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1044 | GFP_KERNEL); |
1045 | if (!sky2->rx_ring) | |
1046 | goto err_out; | |
1047 | ||
1048 | sky2_mac_init(hw, port); | |
1049 | ||
1c28f6ba SH |
1050 | /* Determine available ram buffer space (in 4K blocks). |
1051 | * Note: not sure about the FE setting below yet | |
1052 | */ | |
1053 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1054 | ramsize = 4; | |
1055 | else | |
1056 | ramsize = sky2_read8(hw, B2_E_0); | |
1057 | ||
1058 | /* Give transmitter one third (rounded up) */ | |
1059 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1060 | |
cd28ab6a | 1061 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1062 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1063 | |
793b883e SH |
1064 | /* Make sure SyncQ is disabled */ |
1065 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1066 | RB_RST_SET); | |
1067 | ||
af4ed7e6 | 1068 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1069 | |
977bdf06 SH |
1070 | /* Set almost empty threshold */ |
1071 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) | |
1072 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
5a5b1ea0 | 1073 | |
6b1a3aef | 1074 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1075 | TX_RING_SIZE - 1); | |
cd28ab6a | 1076 | |
6b1a3aef | 1077 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1078 | if (err) |
1079 | goto err_out; | |
1080 | ||
cd28ab6a SH |
1081 | /* Enable interrupts from phy/mac for port */ |
1082 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1083 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1084 | return 0; | |
1085 | ||
1086 | err_out: | |
1b537565 | 1087 | if (sky2->rx_le) { |
cd28ab6a SH |
1088 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1089 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1090 | sky2->rx_le = NULL; |
1091 | } | |
1092 | if (sky2->tx_le) { | |
cd28ab6a SH |
1093 | pci_free_consistent(hw->pdev, |
1094 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1095 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1096 | sky2->tx_le = NULL; |
1097 | } | |
1098 | kfree(sky2->tx_ring); | |
1099 | kfree(sky2->rx_ring); | |
cd28ab6a | 1100 | |
1b537565 SH |
1101 | sky2->tx_ring = NULL; |
1102 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1103 | return err; |
1104 | } | |
1105 | ||
793b883e SH |
1106 | /* Modular subtraction in ring */ |
1107 | static inline int tx_dist(unsigned tail, unsigned head) | |
1108 | { | |
129372d0 | 1109 | return (head - tail) % TX_RING_SIZE; |
793b883e | 1110 | } |
cd28ab6a | 1111 | |
793b883e SH |
1112 | /* Number of list elements available for next tx */ |
1113 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1114 | { |
793b883e | 1115 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1116 | } |
1117 | ||
793b883e | 1118 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1119 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1120 | { |
793b883e SH |
1121 | unsigned count; |
1122 | ||
1123 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1124 | count += skb_shinfo(skb)->nr_frags * count; | |
1125 | ||
1126 | if (skb_shinfo(skb)->tso_size) | |
1127 | ++count; | |
1128 | ||
0e3ff6aa | 1129 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1130 | ++count; |
1131 | ||
1132 | return count; | |
cd28ab6a SH |
1133 | } |
1134 | ||
793b883e SH |
1135 | /* |
1136 | * Put one packet in ring for transmit. | |
1137 | * A single packet can generate multiple list elements, and | |
1138 | * the number of ring elements will probably be less than the number | |
1139 | * of list elements used. | |
f2e46561 SH |
1140 | * |
1141 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1142 | */ |
cd28ab6a SH |
1143 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1144 | { | |
1145 | struct sky2_port *sky2 = netdev_priv(dev); | |
1146 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1147 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1148 | struct tx_ring_info *re; |
cd28ab6a SH |
1149 | unsigned i, len; |
1150 | dma_addr_t mapping; | |
1151 | u32 addr64; | |
1152 | u16 mss; | |
1153 | u8 ctrl; | |
1154 | ||
302d1252 SH |
1155 | /* No BH disabling for tx_lock here. We are running in BH disabled |
1156 | * context and TX reclaim runs via poll inside of a software | |
1157 | * interrupt, and no related locks in IRQ processing. | |
1158 | */ | |
f2e46561 | 1159 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1160 | return NETDEV_TX_LOCKED; |
1161 | ||
793b883e | 1162 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1163 | /* There is a known but harmless race with lockless tx |
1164 | * and netif_stop_queue. | |
1165 | */ | |
1166 | if (!netif_queue_stopped(dev)) { | |
1167 | netif_stop_queue(dev); | |
3be92a70 SH |
1168 | if (net_ratelimit()) |
1169 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1170 | dev->name); | |
8c463ef7 | 1171 | } |
f2e46561 | 1172 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1173 | |
cd28ab6a SH |
1174 | return NETDEV_TX_BUSY; |
1175 | } | |
1176 | ||
793b883e | 1177 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1178 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1179 | dev->name, sky2->tx_prod, skb->len); | |
1180 | ||
cd28ab6a SH |
1181 | len = skb_headlen(skb); |
1182 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1183 | addr64 = high32(mapping); |
793b883e SH |
1184 | |
1185 | re = sky2->tx_ring + sky2->tx_prod; | |
1186 | ||
a018e330 | 1187 | /* Send high bits if changed or crosses boundary */ |
1188 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1189 | le = get_tx_le(sky2); |
1190 | le->tx.addr = cpu_to_le32(addr64); | |
1191 | le->ctrl = 0; | |
1192 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1193 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1194 | } |
cd28ab6a SH |
1195 | |
1196 | /* Check for TCP Segmentation Offload */ | |
1197 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1198 | if (mss != 0) { |
cd28ab6a SH |
1199 | /* just drop the packet if non-linear expansion fails */ |
1200 | if (skb_header_cloned(skb) && | |
1201 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
1202 | dev_kfree_skb_any(skb); |
1203 | goto out_unlock; | |
cd28ab6a SH |
1204 | } |
1205 | ||
1206 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1207 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1208 | mss += ETH_HLEN; | |
793b883e | 1209 | } |
cd28ab6a | 1210 | |
793b883e | 1211 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1212 | le = get_tx_le(sky2); |
1213 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1214 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1215 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1216 | le->ctrl = 0; |
793b883e | 1217 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1218 | } |
1219 | ||
cd28ab6a | 1220 | ctrl = 0; |
d1f13708 | 1221 | #ifdef SKY2_VLAN_TAG_USED |
1222 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1223 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1224 | if (!le) { | |
1225 | le = get_tx_le(sky2); | |
1226 | le->tx.addr = 0; | |
1227 | le->opcode = OP_VLAN|HW_OWNER; | |
1228 | le->ctrl = 0; | |
1229 | } else | |
1230 | le->opcode |= OP_VLAN; | |
1231 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1232 | ctrl |= INS_VLAN; | |
1233 | } | |
1234 | #endif | |
1235 | ||
1236 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1237 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1238 | u16 hdr = skb->h.raw - skb->data; |
1239 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1240 | |
1241 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1242 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1243 | ctrl |= UDPTCP; | |
1244 | ||
1245 | le = get_tx_le(sky2); | |
1246 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1247 | le->tx.csum.offset = cpu_to_le16(offset); |
1248 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1249 | le->ctrl = 1; /* one packet */ |
793b883e | 1250 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1251 | } |
1252 | ||
1253 | le = get_tx_le(sky2); | |
1254 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1255 | le->length = cpu_to_le16(len); | |
1256 | le->ctrl = ctrl; | |
793b883e | 1257 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1258 | |
793b883e | 1259 | /* Record the transmit mapping info */ |
cd28ab6a | 1260 | re->skb = skb; |
6cdbbdf3 | 1261 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1262 | |
1263 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1264 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1265 | struct tx_ring_info *fre; |
cd28ab6a SH |
1266 | |
1267 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1268 | frag->size, PCI_DMA_TODEVICE); | |
a036119f | 1269 | addr64 = high32(mapping); |
793b883e SH |
1270 | if (addr64 != sky2->tx_addr64) { |
1271 | le = get_tx_le(sky2); | |
1272 | le->tx.addr = cpu_to_le32(addr64); | |
1273 | le->ctrl = 0; | |
1274 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1275 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1276 | } |
1277 | ||
1278 | le = get_tx_le(sky2); | |
1279 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1280 | le->length = cpu_to_le16(frag->size); | |
1281 | le->ctrl = ctrl; | |
793b883e | 1282 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1283 | |
793b883e SH |
1284 | fre = sky2->tx_ring |
1285 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
6cdbbdf3 | 1286 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1287 | } |
6cdbbdf3 | 1288 | |
793b883e | 1289 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1290 | le->ctrl |= EOP; |
1291 | ||
724bca3c | 1292 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod, |
cd28ab6a SH |
1293 | &sky2->tx_last_put, TX_RING_SIZE); |
1294 | ||
0e3ff6aa | 1295 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
cd28ab6a | 1296 | netif_stop_queue(dev); |
793b883e SH |
1297 | |
1298 | out_unlock: | |
f2e46561 | 1299 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1300 | |
1301 | dev->trans_start = jiffies; | |
1302 | return NETDEV_TX_OK; | |
1303 | } | |
1304 | ||
cd28ab6a | 1305 | /* |
793b883e SH |
1306 | * Free ring elements from starting at tx_cons until "done" |
1307 | * | |
1308 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1309 | * buffers; these are deferred until completion. |
cd28ab6a | 1310 | */ |
d11c13e7 | 1311 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1312 | { |
d11c13e7 | 1313 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1314 | struct pci_dev *pdev = sky2->hw->pdev; |
1315 | u16 nxt, put; | |
793b883e | 1316 | unsigned i; |
cd28ab6a | 1317 | |
0e3ff6aa | 1318 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1319 | |
d11c13e7 | 1320 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1321 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1322 | dev->name, done); |
cd28ab6a | 1323 | |
af2a58ac SH |
1324 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1325 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1326 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1327 | |
af2a58ac SH |
1328 | nxt = re->idx; |
1329 | BUG_ON(nxt >= TX_RING_SIZE); | |
d70cd51a | 1330 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1331 | |
793b883e | 1332 | /* Check for partial status */ |
af2a58ac SH |
1333 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1334 | break; | |
793b883e SH |
1335 | |
1336 | skb = re->skb; | |
af2a58ac | 1337 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1338 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1339 | |
1340 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1341 | struct tx_ring_info *fre; |
af2a58ac SH |
1342 | fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; |
1343 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), | |
1344 | skb_shinfo(skb)->frags[i].size, | |
734d1868 | 1345 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1346 | } |
1347 | ||
cd28ab6a | 1348 | dev_kfree_skb_any(skb); |
793b883e | 1349 | } |
793b883e | 1350 | |
af2a58ac | 1351 | sky2->tx_cons = put; |
793b883e | 1352 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a | 1353 | netif_wake_queue(dev); |
cd28ab6a SH |
1354 | } |
1355 | ||
1356 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1357 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1358 | { |
302d1252 | 1359 | spin_lock_bh(&sky2->tx_lock); |
d11c13e7 | 1360 | sky2_tx_complete(sky2, sky2->tx_prod); |
302d1252 | 1361 | spin_unlock_bh(&sky2->tx_lock); |
cd28ab6a SH |
1362 | } |
1363 | ||
1364 | /* Network shutdown */ | |
1365 | static int sky2_down(struct net_device *dev) | |
1366 | { | |
1367 | struct sky2_port *sky2 = netdev_priv(dev); | |
1368 | struct sky2_hw *hw = sky2->hw; | |
1369 | unsigned port = sky2->port; | |
1370 | u16 ctrl; | |
cd28ab6a | 1371 | |
1b537565 SH |
1372 | /* Never really got started! */ |
1373 | if (!sky2->tx_le) | |
1374 | return 0; | |
1375 | ||
cd28ab6a SH |
1376 | if (netif_msg_ifdown(sky2)) |
1377 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1378 | ||
018d1c66 | 1379 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1380 | netif_stop_queue(dev); |
1381 | ||
018d1c66 | 1382 | /* Disable port IRQ */ |
1383 | local_irq_disable(); | |
1384 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1385 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1386 | local_irq_enable(); | |
1387 | ||
91c86df5 | 1388 | flush_scheduled_work(); |
018d1c66 | 1389 | |
793b883e SH |
1390 | sky2_phy_reset(hw, port); |
1391 | ||
cd28ab6a SH |
1392 | /* Stop transmitter */ |
1393 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1394 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1395 | ||
1396 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1397 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1398 | |
1399 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1400 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1401 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1402 | ||
1403 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1404 | ||
1405 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1406 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1407 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1408 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1409 | ||
1410 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1411 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1412 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1413 | ||
1414 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1415 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1416 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1417 | ||
1418 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1419 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1420 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1421 | |
1422 | /* Reset the Tx prefetch units */ | |
1423 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1424 | PREF_UNIT_RST_SET); | |
1425 | ||
1426 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1427 | ||
6b1a3aef | 1428 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1429 | |
1430 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1431 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1432 | ||
d571b694 | 1433 | /* turn off LED's */ |
cd28ab6a SH |
1434 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1435 | ||
018d1c66 | 1436 | synchronize_irq(hw->pdev->irq); |
1437 | ||
cd28ab6a SH |
1438 | sky2_tx_clean(sky2); |
1439 | sky2_rx_clean(sky2); | |
1440 | ||
1441 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1442 | sky2->rx_le, sky2->rx_le_map); | |
1443 | kfree(sky2->rx_ring); | |
1444 | ||
1445 | pci_free_consistent(hw->pdev, | |
1446 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1447 | sky2->tx_le, sky2->tx_le_map); | |
1448 | kfree(sky2->tx_ring); | |
1449 | ||
1b537565 SH |
1450 | sky2->tx_le = NULL; |
1451 | sky2->rx_le = NULL; | |
1452 | ||
1453 | sky2->rx_ring = NULL; | |
1454 | sky2->tx_ring = NULL; | |
1455 | ||
cd28ab6a SH |
1456 | return 0; |
1457 | } | |
1458 | ||
1459 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1460 | { | |
793b883e SH |
1461 | if (!hw->copper) |
1462 | return SPEED_1000; | |
1463 | ||
cd28ab6a SH |
1464 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1465 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1466 | ||
1467 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1468 | case PHY_M_PS_SPEED_1000: | |
1469 | return SPEED_1000; | |
1470 | case PHY_M_PS_SPEED_100: | |
1471 | return SPEED_100; | |
1472 | default: | |
1473 | return SPEED_10; | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | static void sky2_link_up(struct sky2_port *sky2) | |
1478 | { | |
1479 | struct sky2_hw *hw = sky2->hw; | |
1480 | unsigned port = sky2->port; | |
1481 | u16 reg; | |
1482 | ||
1483 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1484 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1485 | |
1486 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
6f4c56b2 SH |
1487 | if (sky2->autoneg == AUTONEG_DISABLE) { |
1488 | reg |= GM_GPCR_AU_ALL_DIS; | |
1489 | ||
1490 | /* Is write/read necessary? Copied from sky2_mac_init */ | |
1491 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1492 | gma_read16(hw, port, GM_GP_CTRL); | |
1493 | ||
1494 | switch (sky2->speed) { | |
1495 | case SPEED_1000: | |
1496 | reg &= ~GM_GPCR_SPEED_100; | |
1497 | reg |= GM_GPCR_SPEED_1000; | |
1498 | break; | |
1499 | case SPEED_100: | |
1500 | reg &= ~GM_GPCR_SPEED_1000; | |
1501 | reg |= GM_GPCR_SPEED_100; | |
1502 | break; | |
1503 | case SPEED_10: | |
1504 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1505 | break; | |
1506 | } | |
1507 | } else | |
1508 | reg &= ~GM_GPCR_AU_ALL_DIS; | |
1509 | ||
cd28ab6a SH |
1510 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) |
1511 | reg |= GM_GPCR_DUP_FULL; | |
1512 | ||
cd28ab6a SH |
1513 | /* enable Rx/Tx */ |
1514 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1515 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1516 | gma_read16(hw, port, GM_GP_CTRL); | |
1517 | ||
1518 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1519 | ||
1520 | netif_carrier_on(sky2->netdev); | |
1521 | netif_wake_queue(sky2->netdev); | |
1522 | ||
1523 | /* Turn on link LED */ | |
793b883e | 1524 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1525 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1526 | ||
793b883e SH |
1527 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1528 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1529 | ||
1530 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1531 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1532 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1533 | SPEED_10 ? 7 : 0) | | |
1534 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1535 | SPEED_100 ? 7 : 0) | | |
1536 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1537 | SPEED_1000 ? 7 : 0)); | |
1538 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1539 | } | |
1540 | ||
cd28ab6a SH |
1541 | if (netif_msg_link(sky2)) |
1542 | printk(KERN_INFO PFX | |
d571b694 | 1543 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1544 | sky2->netdev->name, sky2->speed, |
1545 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1546 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1547 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1548 | } |
1549 | ||
1550 | static void sky2_link_down(struct sky2_port *sky2) | |
1551 | { | |
1552 | struct sky2_hw *hw = sky2->hw; | |
1553 | unsigned port = sky2->port; | |
1554 | u16 reg; | |
1555 | ||
1556 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1557 | ||
1558 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1559 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1560 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1561 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1562 | ||
1563 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1564 | /* restore Asymmetric Pause bit */ | |
1565 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1566 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1567 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1568 | } |
1569 | ||
cd28ab6a SH |
1570 | netif_carrier_off(sky2->netdev); |
1571 | netif_stop_queue(sky2->netdev); | |
1572 | ||
1573 | /* Turn on link LED */ | |
1574 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1575 | ||
1576 | if (netif_msg_link(sky2)) | |
1577 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1578 | sky2_phy_init(hw, port); | |
1579 | } | |
1580 | ||
793b883e SH |
1581 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1582 | { | |
1583 | struct sky2_hw *hw = sky2->hw; | |
1584 | unsigned port = sky2->port; | |
1585 | u16 lpa; | |
1586 | ||
1587 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1588 | ||
1589 | if (lpa & PHY_M_AN_RF) { | |
1590 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1591 | return -1; | |
1592 | } | |
1593 | ||
1594 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1595 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1596 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1597 | sky2->netdev->name); | |
1598 | return -1; | |
1599 | } | |
1600 | ||
1601 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1602 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1603 | sky2->netdev->name); | |
1604 | return -1; | |
1605 | } | |
1606 | ||
1607 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1608 | ||
1609 | sky2->speed = sky2_phy_speed(hw, aux); | |
1610 | ||
1611 | /* Pause bits are offset (9..8) */ | |
1612 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1613 | aux >>= 6; | |
1614 | ||
1615 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1616 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1617 | ||
1618 | if ((sky2->tx_pause || sky2->rx_pause) | |
1619 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1620 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1621 | else | |
1622 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1623 | ||
1624 | return 0; | |
1625 | } | |
cd28ab6a SH |
1626 | |
1627 | /* | |
91c86df5 | 1628 | * Interrupt from PHY are handled outside of interrupt context |
cd28ab6a SH |
1629 | * because accessing phy registers requires spin wait which might |
1630 | * cause excess interrupt latency. | |
1631 | */ | |
91c86df5 | 1632 | static void sky2_phy_task(void *arg) |
cd28ab6a | 1633 | { |
91c86df5 | 1634 | struct sky2_port *sky2 = arg; |
cd28ab6a | 1635 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1636 | u16 istatus, phystat; |
1637 | ||
91c86df5 | 1638 | down(&sky2->phy_sema); |
793b883e SH |
1639 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); |
1640 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1641 | |
1642 | if (netif_msg_intr(sky2)) | |
1643 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1644 | sky2->netdev->name, istatus, phystat); | |
1645 | ||
1646 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1647 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1648 | sky2_link_up(sky2); | |
1649 | goto out; | |
1650 | } | |
cd28ab6a | 1651 | |
793b883e SH |
1652 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1653 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1654 | |
793b883e SH |
1655 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1656 | sky2->duplex = | |
1657 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1658 | |
793b883e SH |
1659 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1660 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1661 | sky2_link_up(sky2); |
793b883e SH |
1662 | else |
1663 | sky2_link_down(sky2); | |
cd28ab6a | 1664 | } |
793b883e | 1665 | out: |
91c86df5 | 1666 | up(&sky2->phy_sema); |
cd28ab6a SH |
1667 | |
1668 | local_irq_disable(); | |
793b883e | 1669 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1670 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1671 | local_irq_enable(); | |
1672 | } | |
1673 | ||
302d1252 SH |
1674 | |
1675 | /* Transmit timeout is only called if we are running, carries is up | |
1676 | * and tx queue is full (stopped). | |
1677 | */ | |
cd28ab6a SH |
1678 | static void sky2_tx_timeout(struct net_device *dev) |
1679 | { | |
1680 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1681 | struct sky2_hw *hw = sky2->hw; |
1682 | unsigned txq = txqaddr[sky2->port]; | |
302d1252 SH |
1683 | u16 ridx; |
1684 | ||
1685 | /* Maybe we just missed an status interrupt */ | |
1686 | spin_lock(&sky2->tx_lock); | |
1687 | ridx = sky2_read16(hw, | |
1688 | sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); | |
1689 | sky2_tx_complete(sky2, ridx); | |
1690 | spin_unlock(&sky2->tx_lock); | |
1691 | ||
1692 | if (!netif_queue_stopped(dev)) { | |
1693 | if (net_ratelimit()) | |
1694 | pr_info(PFX "transmit interrupt missed? recovered\n"); | |
1695 | return; | |
1696 | } | |
cd28ab6a SH |
1697 | |
1698 | if (netif_msg_timer(sky2)) | |
1699 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1700 | ||
8cc048e3 | 1701 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); |
8cc048e3 | 1702 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
cd28ab6a SH |
1703 | |
1704 | sky2_tx_clean(sky2); | |
8cc048e3 SH |
1705 | |
1706 | sky2_qset(hw, txq); | |
1707 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
cd28ab6a SH |
1708 | } |
1709 | ||
734d1868 SH |
1710 | |
1711 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) | |
1712 | /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */ | |
1713 | static inline unsigned sky2_buf_size(int mtu) | |
1714 | { | |
1715 | return roundup(mtu + ETH_HLEN + 4, 8); | |
1716 | } | |
1717 | ||
cd28ab6a SH |
1718 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1719 | { | |
6b1a3aef | 1720 | struct sky2_port *sky2 = netdev_priv(dev); |
1721 | struct sky2_hw *hw = sky2->hw; | |
1722 | int err; | |
1723 | u16 ctl, mode; | |
cd28ab6a SH |
1724 | |
1725 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1726 | return -EINVAL; | |
1727 | ||
5a5b1ea0 | 1728 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1729 | return -EINVAL; | |
1730 | ||
6b1a3aef | 1731 | if (!netif_running(dev)) { |
1732 | dev->mtu = new_mtu; | |
1733 | return 0; | |
1734 | } | |
1735 | ||
6b1a3aef | 1736 | sky2_write32(hw, B0_IMSK, 0); |
1737 | ||
018d1c66 | 1738 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1739 | netif_stop_queue(dev); | |
1740 | netif_poll_disable(hw->dev[0]); | |
1741 | ||
6b1a3aef | 1742 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1743 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1744 | sky2_rx_stop(sky2); | |
1745 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1746 | |
1747 | dev->mtu = new_mtu; | |
734d1868 | 1748 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef | 1749 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1750 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1751 | ||
1752 | if (dev->mtu > ETH_DATA_LEN) | |
1753 | mode |= GM_SMOD_JUMBO_ENA; | |
1754 | ||
1755 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1756 | |
6b1a3aef | 1757 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1758 | |
6b1a3aef | 1759 | err = sky2_rx_start(sky2); |
6b1a3aef | 1760 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
018d1c66 | 1761 | |
1b537565 SH |
1762 | if (err) |
1763 | dev_close(dev); | |
1764 | else { | |
1765 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1766 | ||
1767 | netif_poll_enable(hw->dev[0]); | |
1768 | netif_wake_queue(dev); | |
1769 | } | |
1770 | ||
cd28ab6a SH |
1771 | return err; |
1772 | } | |
1773 | ||
1774 | /* | |
1775 | * Receive one packet. | |
1776 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1777 | * For larger packets, get new buffer. |
cd28ab6a | 1778 | */ |
d11c13e7 | 1779 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1780 | u16 length, u32 status) |
1781 | { | |
cd28ab6a | 1782 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1783 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1784 | |
1785 | if (unlikely(netif_msg_rx_status(sky2))) | |
1786 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1787 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1788 | |
793b883e | 1789 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1790 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1791 | |
42eeea01 | 1792 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1793 | goto error; |
1794 | ||
42eeea01 | 1795 | if (!(status & GMR_FS_RX_OK)) |
1796 | goto resubmit; | |
1797 | ||
6e15b712 SH |
1798 | if ((status >> 16) != length || length > sky2->rx_bufsize) |
1799 | goto oversize; | |
1800 | ||
bdb5c58e | 1801 | if (length < copybreak) { |
79e57d32 SH |
1802 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1803 | if (!skb) | |
793b883e SH |
1804 | goto resubmit; |
1805 | ||
79e57d32 | 1806 | skb_reserve(skb, 2); |
793b883e SH |
1807 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1808 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1809 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 | 1810 | skb->ip_summed = re->skb->ip_summed; |
1811 | skb->csum = re->skb->csum; | |
793b883e SH |
1812 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1813 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1814 | } else { |
79e57d32 SH |
1815 | struct sk_buff *nskb; |
1816 | ||
82788c7a | 1817 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1818 | if (!nskb) |
1819 | goto resubmit; | |
cd28ab6a | 1820 | |
793b883e | 1821 | skb = re->skb; |
79e57d32 | 1822 | re->skb = nskb; |
793b883e | 1823 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1824 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1825 | prefetch(skb->data); |
cd28ab6a | 1826 | |
793b883e | 1827 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1828 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1829 | } |
cd28ab6a | 1830 | |
79e57d32 | 1831 | skb_put(skb, length); |
793b883e | 1832 | resubmit: |
d11c13e7 | 1833 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1834 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1835 | |
bea86103 | 1836 | /* Tell receiver about new buffers. */ |
1837 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
1838 | &sky2->rx_last_put, RX_LE_SIZE); | |
1839 | ||
cd28ab6a SH |
1840 | return skb; |
1841 | ||
6e15b712 SH |
1842 | oversize: |
1843 | ++sky2->net_stats.rx_over_errors; | |
1844 | goto resubmit; | |
1845 | ||
cd28ab6a | 1846 | error: |
6e15b712 SH |
1847 | ++sky2->net_stats.rx_errors; |
1848 | ||
3be92a70 | 1849 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a SH |
1850 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
1851 | sky2->netdev->name, status, length); | |
793b883e SH |
1852 | |
1853 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1854 | sky2->net_stats.rx_length_errors++; |
1855 | if (status & GMR_FS_FRAGMENT) | |
1856 | sky2->net_stats.rx_frame_errors++; | |
1857 | if (status & GMR_FS_CRC_ERR) | |
1858 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1859 | if (status & GMR_FS_RX_FF_OV) |
1860 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1861 | |
793b883e | 1862 | goto resubmit; |
cd28ab6a SH |
1863 | } |
1864 | ||
2224795d | 1865 | /* |
1866 | * Check for transmit complete | |
793b883e | 1867 | */ |
13b97b74 | 1868 | #define TX_NO_STATUS 0xffff |
2224795d | 1869 | |
28bd181a | 1870 | static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last) |
13b97b74 SH |
1871 | { |
1872 | if (last != TX_NO_STATUS) { | |
1873 | struct net_device *dev = hw->dev[port]; | |
1874 | if (dev && netif_running(dev)) { | |
1875 | struct sky2_port *sky2 = netdev_priv(dev); | |
302d1252 SH |
1876 | |
1877 | spin_lock(&sky2->tx_lock); | |
13b97b74 | 1878 | sky2_tx_complete(sky2, last); |
302d1252 | 1879 | spin_unlock(&sky2->tx_lock); |
13b97b74 | 1880 | } |
2224795d | 1881 | } |
cd28ab6a SH |
1882 | } |
1883 | ||
1884 | /* | |
cd28ab6a SH |
1885 | * Both ports share the same status interrupt, therefore there is only |
1886 | * one poll routine. | |
cd28ab6a | 1887 | */ |
d11c13e7 | 1888 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 1889 | { |
d11c13e7 | 1890 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
1891 | unsigned int to_do = min(dev0->quota, *budget); | |
cd28ab6a | 1892 | unsigned int work_done = 0; |
793b883e | 1893 | u16 hwidx; |
13b97b74 | 1894 | u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS }; |
cd28ab6a | 1895 | |
f9a66c7f SH |
1896 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
1897 | ||
a8fd6266 SH |
1898 | /* |
1899 | * Kick the STAT_LEV_TIMER_CTRL timer. | |
1900 | * This fixes my hangs on Yukon-EC (0xb6) rev 1. | |
1901 | * The if clause is there to start the timer only if it has been | |
1902 | * configured correctly and not been disabled via ethtool. | |
1903 | */ | |
1904 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) { | |
1905 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
1906 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
1907 | } | |
1908 | ||
793b883e | 1909 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1910 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
af2a58ac | 1911 | rmb(); |
bea86103 | 1912 | |
13210ce5 | 1913 | while (hwidx != hw->st_idx) { |
1914 | struct sky2_status_le *le = hw->st_le + hw->st_idx; | |
1915 | struct net_device *dev; | |
d11c13e7 | 1916 | struct sky2_port *sky2; |
cd28ab6a | 1917 | struct sk_buff *skb; |
cd28ab6a SH |
1918 | u32 status; |
1919 | u16 length; | |
1920 | ||
13210ce5 | 1921 | le = hw->st_le + hw->st_idx; |
bea86103 | 1922 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
13210ce5 | 1923 | prefetch(hw->st_le + hw->st_idx); |
bea86103 | 1924 | |
13210ce5 | 1925 | BUG_ON(le->link >= 2); |
1926 | dev = hw->dev[le->link]; | |
1927 | if (dev == NULL || !netif_running(dev)) | |
1928 | continue; | |
1929 | ||
1930 | sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1931 | status = le32_to_cpu(le->status); |
1932 | length = le16_to_cpu(le->length); | |
cd28ab6a | 1933 | |
dc4d5ea2 | 1934 | switch (le->opcode & ~HW_OWNER) { |
cd28ab6a | 1935 | case OP_RXSTAT: |
d11c13e7 | 1936 | skb = sky2_receive(sky2, length, status); |
d1f13708 | 1937 | if (!skb) |
1938 | break; | |
13210ce5 | 1939 | |
1940 | skb->dev = dev; | |
1941 | skb->protocol = eth_type_trans(skb, dev); | |
1942 | dev->last_rx = jiffies; | |
1943 | ||
d1f13708 | 1944 | #ifdef SKY2_VLAN_TAG_USED |
1945 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1946 | vlan_hwaccel_receive_skb(skb, | |
1947 | sky2->vlgrp, | |
1948 | be16_to_cpu(sky2->rx_tag)); | |
1949 | } else | |
1950 | #endif | |
cd28ab6a | 1951 | netif_receive_skb(skb); |
13210ce5 | 1952 | |
1953 | if (++work_done >= to_do) | |
1954 | goto exit_loop; | |
cd28ab6a SH |
1955 | break; |
1956 | ||
d1f13708 | 1957 | #ifdef SKY2_VLAN_TAG_USED |
1958 | case OP_RXVLAN: | |
1959 | sky2->rx_tag = length; | |
1960 | break; | |
1961 | ||
1962 | case OP_RXCHKSVLAN: | |
1963 | sky2->rx_tag = length; | |
1964 | /* fall through */ | |
1965 | #endif | |
cd28ab6a | 1966 | case OP_RXCHKS: |
d11c13e7 | 1967 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1968 | skb->ip_summed = CHECKSUM_HW; | |
1969 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1970 | break; |
1971 | ||
1972 | case OP_TXINDEXLE: | |
13b97b74 SH |
1973 | /* TX index reports status for both ports */ |
1974 | tx_done[0] = status & 0xffff; | |
1975 | tx_done[1] = ((status >> 24) & 0xff) | |
1976 | | (u16)(length & 0xf) << 8; | |
cd28ab6a SH |
1977 | break; |
1978 | ||
cd28ab6a SH |
1979 | default: |
1980 | if (net_ratelimit()) | |
793b883e | 1981 | printk(KERN_WARNING PFX |
dc4d5ea2 | 1982 | "unknown status opcode 0x%x\n", le->opcode); |
cd28ab6a SH |
1983 | break; |
1984 | } | |
13210ce5 | 1985 | } |
cd28ab6a | 1986 | |
13210ce5 | 1987 | exit_loop: |
13b97b74 SH |
1988 | sky2_tx_check(hw, 0, tx_done[0]); |
1989 | sky2_tx_check(hw, 1, tx_done[1]); | |
1990 | ||
f9a66c7f | 1991 | if (likely(work_done < to_do)) { |
13b97b74 | 1992 | /* need to restart TX timer */ |
cd28ab6a SH |
1993 | if (is_ec_a1(hw)) { |
1994 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1995 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1996 | } | |
1997 | ||
bea86103 | 1998 | netif_rx_complete(dev0); |
cd28ab6a SH |
1999 | hw->intr_mask |= Y2_IS_STAT_BMU; |
2000 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
13210ce5 | 2001 | return 0; |
2002 | } else { | |
2003 | *budget -= work_done; | |
2004 | dev0->quota -= work_done; | |
2005 | return 1; | |
cd28ab6a | 2006 | } |
cd28ab6a SH |
2007 | } |
2008 | ||
2009 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2010 | { | |
2011 | struct net_device *dev = hw->dev[port]; | |
2012 | ||
3be92a70 SH |
2013 | if (net_ratelimit()) |
2014 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
2015 | dev->name, status); | |
cd28ab6a SH |
2016 | |
2017 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
2018 | if (net_ratelimit()) |
2019 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
2020 | dev->name); | |
cd28ab6a SH |
2021 | /* Clear IRQ */ |
2022 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2023 | } | |
2024 | ||
2025 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
2026 | if (net_ratelimit()) |
2027 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
2028 | dev->name); | |
cd28ab6a SH |
2029 | |
2030 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2031 | } | |
2032 | ||
2033 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
2034 | if (net_ratelimit()) |
2035 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
2036 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2037 | } | |
2038 | ||
2039 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
2040 | if (net_ratelimit()) |
2041 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
2042 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2043 | } | |
2044 | ||
2045 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
2046 | if (net_ratelimit()) |
2047 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
2048 | dev->name); | |
cd28ab6a SH |
2049 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2050 | } | |
2051 | } | |
2052 | ||
2053 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2054 | { | |
2055 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
2056 | ||
793b883e | 2057 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2058 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2059 | |
2060 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2061 | u16 pci_err; |
2062 | ||
2063 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
3be92a70 SH |
2064 | if (net_ratelimit()) |
2065 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | |
2066 | pci_name(hw->pdev), pci_err); | |
cd28ab6a SH |
2067 | |
2068 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
2069 | pci_write_config_word(hw->pdev, PCI_STATUS, |
2070 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2071 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2072 | } | |
2073 | ||
2074 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2075 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
2076 | u32 pex_err; |
2077 | ||
2078 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 2079 | |
3be92a70 SH |
2080 | if (net_ratelimit()) |
2081 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | |
2082 | pci_name(hw->pdev), pex_err); | |
cd28ab6a SH |
2083 | |
2084 | /* clear the interrupt */ | |
2085 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
2086 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
2087 | 0xffffffffUL); | |
cd28ab6a SH |
2088 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2089 | ||
2090 | if (pex_err & PEX_FATAL_ERRORS) { | |
2091 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
2092 | hwmsk &= ~Y2_IS_PCI_EXP; | |
2093 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
2094 | } | |
2095 | } | |
2096 | ||
2097 | if (status & Y2_HWE_L1_MASK) | |
2098 | sky2_hw_error(hw, 0, status); | |
2099 | status >>= 8; | |
2100 | if (status & Y2_HWE_L1_MASK) | |
2101 | sky2_hw_error(hw, 1, status); | |
2102 | } | |
2103 | ||
2104 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2105 | { | |
2106 | struct net_device *dev = hw->dev[port]; | |
2107 | struct sky2_port *sky2 = netdev_priv(dev); | |
2108 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2109 | ||
2110 | if (netif_msg_intr(sky2)) | |
2111 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2112 | dev->name, status); | |
2113 | ||
2114 | if (status & GM_IS_RX_FF_OR) { | |
2115 | ++sky2->net_stats.rx_fifo_errors; | |
2116 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2117 | } | |
2118 | ||
2119 | if (status & GM_IS_TX_FF_UR) { | |
2120 | ++sky2->net_stats.tx_fifo_errors; | |
2121 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2122 | } | |
cd28ab6a SH |
2123 | } |
2124 | ||
2125 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
2126 | { | |
2127 | struct net_device *dev = hw->dev[port]; | |
2128 | struct sky2_port *sky2 = netdev_priv(dev); | |
2129 | ||
2130 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
2131 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
91c86df5 | 2132 | schedule_work(&sky2->phy_task); |
cd28ab6a SH |
2133 | } |
2134 | ||
2135 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2136 | { | |
2137 | struct sky2_hw *hw = dev_id; | |
bea86103 | 2138 | struct net_device *dev0 = hw->dev[0]; |
cd28ab6a SH |
2139 | u32 status; |
2140 | ||
2141 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 2142 | if (status == 0 || status == ~0) |
cd28ab6a SH |
2143 | return IRQ_NONE; |
2144 | ||
2145 | if (status & Y2_IS_HW_ERR) | |
2146 | sky2_hw_intr(hw); | |
2147 | ||
793b883e | 2148 | /* Do NAPI for Rx and Tx status */ |
bea86103 | 2149 | if (status & Y2_IS_STAT_BMU) { |
cd28ab6a SH |
2150 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
2151 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
bea86103 | 2152 | |
0a122576 | 2153 | if (likely(__netif_rx_schedule_prep(dev0))) { |
2154 | prefetch(&hw->st_le[hw->st_idx]); | |
bea86103 | 2155 | __netif_rx_schedule(dev0); |
0a122576 | 2156 | } |
cd28ab6a SH |
2157 | } |
2158 | ||
793b883e | 2159 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
2160 | sky2_phy_intr(hw, 0); |
2161 | ||
2162 | if (status & Y2_IS_IRQ_PHY2) | |
2163 | sky2_phy_intr(hw, 1); | |
2164 | ||
2165 | if (status & Y2_IS_IRQ_MAC1) | |
2166 | sky2_mac_intr(hw, 0); | |
2167 | ||
2168 | if (status & Y2_IS_IRQ_MAC2) | |
2169 | sky2_mac_intr(hw, 1); | |
2170 | ||
cd28ab6a | 2171 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
2172 | |
2173 | sky2_read32(hw, B0_IMSK); | |
2174 | ||
cd28ab6a SH |
2175 | return IRQ_HANDLED; |
2176 | } | |
2177 | ||
2178 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2179 | static void sky2_netpoll(struct net_device *dev) | |
2180 | { | |
2181 | struct sky2_port *sky2 = netdev_priv(dev); | |
2182 | ||
793b883e | 2183 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2184 | } |
2185 | #endif | |
2186 | ||
2187 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2188 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2189 | { |
793b883e | 2190 | switch (hw->chip_id) { |
cd28ab6a | 2191 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2192 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2193 | return 125; /* 125 Mhz */ |
cd28ab6a | 2194 | case CHIP_ID_YUKON_FE: |
fb17358f | 2195 | return 100; /* 100 Mhz */ |
793b883e | 2196 | default: /* YUKON_XL */ |
fb17358f | 2197 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2198 | } |
2199 | } | |
2200 | ||
fb17358f | 2201 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2202 | { |
fb17358f | 2203 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2204 | } |
2205 | ||
fb17358f | 2206 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2207 | { |
fb17358f | 2208 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2209 | } |
2210 | ||
fb17358f | 2211 | |
cd28ab6a SH |
2212 | static int sky2_reset(struct sky2_hw *hw) |
2213 | { | |
cd28ab6a SH |
2214 | u16 status; |
2215 | u8 t8, pmd_type; | |
2d42d21f | 2216 | int i, err; |
cd28ab6a | 2217 | |
cd28ab6a | 2218 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2219 | |
cd28ab6a SH |
2220 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
2221 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2222 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2223 | pci_name(hw->pdev), hw->chip_id); | |
2224 | return -EOPNOTSUPP; | |
2225 | } | |
2226 | ||
2227 | /* disable ASF */ | |
2228 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2229 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2230 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2231 | } | |
2232 | ||
2233 | /* do a SW reset */ | |
2234 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2235 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2236 | ||
2237 | /* clear PCI errors, if any */ | |
2d42d21f SH |
2238 | err = pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
2239 | if (err) | |
2240 | goto pci_err; | |
2241 | ||
cd28ab6a | 2242 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2d42d21f SH |
2243 | err = pci_write_config_word(hw->pdev, PCI_STATUS, |
2244 | status | PCI_STATUS_ERROR_BITS); | |
2245 | if (err) | |
2246 | goto pci_err; | |
cd28ab6a SH |
2247 | |
2248 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2249 | ||
2250 | /* clear any PEX errors */ | |
2d42d21f SH |
2251 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) { |
2252 | err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
2253 | 0xffffffffUL); | |
2254 | if (err) | |
2255 | goto pci_err; | |
cd28ab6a SH |
2256 | } |
2257 | ||
2258 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2259 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2260 | ||
2261 | hw->ports = 1; | |
2262 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2263 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2264 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2265 | ++hw->ports; | |
2266 | } | |
2267 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
2268 | ||
5afa0a9c | 2269 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2270 | |
2271 | for (i = 0; i < hw->ports; i++) { | |
2272 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2273 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2274 | } | |
2275 | ||
2276 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2277 | ||
793b883e SH |
2278 | /* Clear I2C IRQ noise */ |
2279 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2280 | |
2281 | /* turn off hardware timer (unused) */ | |
2282 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2283 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2284 | |
cd28ab6a SH |
2285 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2286 | ||
69634ee7 SH |
2287 | /* Turn off descriptor polling */ |
2288 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2289 | |
2290 | /* Turn off receive timestamp */ | |
2291 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2292 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2293 | |
2294 | /* enable the Tx Arbiters */ | |
2295 | for (i = 0; i < hw->ports; i++) | |
2296 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2297 | ||
2298 | /* Initialize ram interface */ | |
2299 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2300 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2301 | |
2302 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2303 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2304 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2305 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2306 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2307 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2308 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2309 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2310 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2311 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2312 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2313 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2314 | } | |
2315 | ||
cd28ab6a SH |
2316 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2317 | ||
cd28ab6a SH |
2318 | for (i = 0; i < hw->ports; i++) |
2319 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2320 | |
cd28ab6a SH |
2321 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2322 | hw->st_idx = 0; | |
2323 | ||
2324 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2325 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2326 | ||
2327 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2328 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2329 | |
2330 | /* Set the list last index */ | |
793b883e | 2331 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2332 | |
793b883e | 2333 | /* These status setup values are copied from SysKonnect's driver */ |
cd28ab6a SH |
2334 | if (is_ec_a1(hw)) { |
2335 | /* WA for dev. #4.3 */ | |
793b883e | 2336 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
2337 | |
2338 | /* set Status-FIFO watermark */ | |
2339 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
2340 | ||
2341 | /* set Status-FIFO ISR watermark */ | |
793b883e | 2342 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
69634ee7 | 2343 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000)); |
cd28ab6a | 2344 | } else { |
69634ee7 SH |
2345 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2346 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a SH |
2347 | |
2348 | /* set Status-FIFO ISR watermark */ | |
2349 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
69634ee7 SH |
2350 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); |
2351 | else | |
2352 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2353 | |
69634ee7 SH |
2354 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
2355 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
2356 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); | |
cd28ab6a SH |
2357 | } |
2358 | ||
793b883e | 2359 | /* enable status unit */ |
cd28ab6a SH |
2360 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2361 | ||
2362 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2363 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2364 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2365 | ||
2366 | return 0; | |
2d42d21f SH |
2367 | |
2368 | pci_err: | |
2369 | /* This is to catch a BIOS bug workaround where | |
2370 | * mmconfig table doesn't have other buses. | |
2371 | */ | |
2372 | printk(KERN_ERR PFX "%s: can't access PCI config space\n", | |
2373 | pci_name(hw->pdev)); | |
2374 | return err; | |
cd28ab6a SH |
2375 | } |
2376 | ||
28bd181a | 2377 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a SH |
2378 | { |
2379 | u32 modes; | |
2380 | if (hw->copper) { | |
793b883e SH |
2381 | modes = SUPPORTED_10baseT_Half |
2382 | | SUPPORTED_10baseT_Full | |
2383 | | SUPPORTED_100baseT_Half | |
2384 | | SUPPORTED_100baseT_Full | |
2385 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2386 | |
2387 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2388 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2389 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2390 | } else |
2391 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2392 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2393 | return modes; |
2394 | } | |
2395 | ||
793b883e | 2396 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2397 | { |
2398 | struct sky2_port *sky2 = netdev_priv(dev); | |
2399 | struct sky2_hw *hw = sky2->hw; | |
2400 | ||
2401 | ecmd->transceiver = XCVR_INTERNAL; | |
2402 | ecmd->supported = sky2_supported_modes(hw); | |
2403 | ecmd->phy_address = PHY_ADDR_MARV; | |
2404 | if (hw->copper) { | |
2405 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2406 | | SUPPORTED_10baseT_Full |
2407 | | SUPPORTED_100baseT_Half | |
2408 | | SUPPORTED_100baseT_Full | |
2409 | | SUPPORTED_1000baseT_Half | |
2410 | | SUPPORTED_1000baseT_Full | |
2411 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2412 | ecmd->port = PORT_TP; |
2413 | } else | |
2414 | ecmd->port = PORT_FIBRE; | |
2415 | ||
2416 | ecmd->advertising = sky2->advertising; | |
2417 | ecmd->autoneg = sky2->autoneg; | |
2418 | ecmd->speed = sky2->speed; | |
2419 | ecmd->duplex = sky2->duplex; | |
2420 | return 0; | |
2421 | } | |
2422 | ||
2423 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2424 | { | |
2425 | struct sky2_port *sky2 = netdev_priv(dev); | |
2426 | const struct sky2_hw *hw = sky2->hw; | |
2427 | u32 supported = sky2_supported_modes(hw); | |
2428 | ||
2429 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2430 | ecmd->advertising = supported; | |
2431 | sky2->duplex = -1; | |
2432 | sky2->speed = -1; | |
2433 | } else { | |
2434 | u32 setting; | |
2435 | ||
793b883e | 2436 | switch (ecmd->speed) { |
cd28ab6a SH |
2437 | case SPEED_1000: |
2438 | if (ecmd->duplex == DUPLEX_FULL) | |
2439 | setting = SUPPORTED_1000baseT_Full; | |
2440 | else if (ecmd->duplex == DUPLEX_HALF) | |
2441 | setting = SUPPORTED_1000baseT_Half; | |
2442 | else | |
2443 | return -EINVAL; | |
2444 | break; | |
2445 | case SPEED_100: | |
2446 | if (ecmd->duplex == DUPLEX_FULL) | |
2447 | setting = SUPPORTED_100baseT_Full; | |
2448 | else if (ecmd->duplex == DUPLEX_HALF) | |
2449 | setting = SUPPORTED_100baseT_Half; | |
2450 | else | |
2451 | return -EINVAL; | |
2452 | break; | |
2453 | ||
2454 | case SPEED_10: | |
2455 | if (ecmd->duplex == DUPLEX_FULL) | |
2456 | setting = SUPPORTED_10baseT_Full; | |
2457 | else if (ecmd->duplex == DUPLEX_HALF) | |
2458 | setting = SUPPORTED_10baseT_Half; | |
2459 | else | |
2460 | return -EINVAL; | |
2461 | break; | |
2462 | default: | |
2463 | return -EINVAL; | |
2464 | } | |
2465 | ||
2466 | if ((setting & supported) == 0) | |
2467 | return -EINVAL; | |
2468 | ||
2469 | sky2->speed = ecmd->speed; | |
2470 | sky2->duplex = ecmd->duplex; | |
2471 | } | |
2472 | ||
2473 | sky2->autoneg = ecmd->autoneg; | |
2474 | sky2->advertising = ecmd->advertising; | |
2475 | ||
1b537565 SH |
2476 | if (netif_running(dev)) |
2477 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2478 | |
2479 | return 0; | |
2480 | } | |
2481 | ||
2482 | static void sky2_get_drvinfo(struct net_device *dev, | |
2483 | struct ethtool_drvinfo *info) | |
2484 | { | |
2485 | struct sky2_port *sky2 = netdev_priv(dev); | |
2486 | ||
2487 | strcpy(info->driver, DRV_NAME); | |
2488 | strcpy(info->version, DRV_VERSION); | |
2489 | strcpy(info->fw_version, "N/A"); | |
2490 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2491 | } | |
2492 | ||
2493 | static const struct sky2_stat { | |
793b883e SH |
2494 | char name[ETH_GSTRING_LEN]; |
2495 | u16 offset; | |
cd28ab6a SH |
2496 | } sky2_stats[] = { |
2497 | { "tx_bytes", GM_TXO_OK_HI }, | |
2498 | { "rx_bytes", GM_RXO_OK_HI }, | |
2499 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2500 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2501 | { "tx_multicast", GM_TXF_MC_OK }, | |
2502 | { "rx_multicast", GM_RXF_MC_OK }, | |
2503 | { "tx_unicast", GM_TXF_UC_OK }, | |
2504 | { "rx_unicast", GM_RXF_UC_OK }, | |
2505 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2506 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2507 | { "collisions", GM_TXF_SNG_COL }, | |
2508 | { "late_collision",GM_TXF_LAT_COL }, | |
2509 | { "aborted", GM_TXF_ABO_COL }, | |
2510 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2511 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2512 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2513 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2514 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2515 | { "rx_runt", GM_RXE_FRAG }, | |
2516 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2517 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2518 | }; | |
2519 | ||
cd28ab6a SH |
2520 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2521 | { | |
2522 | struct sky2_port *sky2 = netdev_priv(dev); | |
2523 | ||
2524 | return sky2->rx_csum; | |
2525 | } | |
2526 | ||
2527 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2528 | { | |
2529 | struct sky2_port *sky2 = netdev_priv(dev); | |
2530 | ||
2531 | sky2->rx_csum = data; | |
793b883e | 2532 | |
cd28ab6a SH |
2533 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2534 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2535 | ||
2536 | return 0; | |
2537 | } | |
2538 | ||
2539 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2540 | { | |
2541 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2542 | return sky2->msg_enable; | |
2543 | } | |
2544 | ||
9a7ae0a9 SH |
2545 | static int sky2_nway_reset(struct net_device *dev) |
2546 | { | |
2547 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2548 | |
2549 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2550 | return -EINVAL; | |
2551 | ||
1b537565 | 2552 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2553 | |
2554 | return 0; | |
2555 | } | |
2556 | ||
793b883e | 2557 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2558 | { |
2559 | struct sky2_hw *hw = sky2->hw; | |
2560 | unsigned port = sky2->port; | |
2561 | int i; | |
2562 | ||
2563 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2564 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2565 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2566 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2567 | |
793b883e | 2568 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2569 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2570 | } | |
2571 | ||
cd28ab6a SH |
2572 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2573 | { | |
2574 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2575 | sky2->msg_enable = value; | |
2576 | } | |
2577 | ||
2578 | static int sky2_get_stats_count(struct net_device *dev) | |
2579 | { | |
2580 | return ARRAY_SIZE(sky2_stats); | |
2581 | } | |
2582 | ||
2583 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2584 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2585 | { |
2586 | struct sky2_port *sky2 = netdev_priv(dev); | |
2587 | ||
793b883e | 2588 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2589 | } |
2590 | ||
793b883e | 2591 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2592 | { |
2593 | int i; | |
2594 | ||
2595 | switch (stringset) { | |
2596 | case ETH_SS_STATS: | |
2597 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2598 | memcpy(data + i * ETH_GSTRING_LEN, | |
2599 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2600 | break; | |
2601 | } | |
2602 | } | |
2603 | ||
2604 | /* Use hardware MIB variables for critical path statistics and | |
2605 | * transmit feedback not reported at interrupt. | |
2606 | * Other errors are accounted for in interrupt handler. | |
2607 | */ | |
2608 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2609 | { | |
2610 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2611 | u64 data[13]; |
cd28ab6a | 2612 | |
793b883e | 2613 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2614 | |
2615 | sky2->net_stats.tx_bytes = data[0]; | |
2616 | sky2->net_stats.rx_bytes = data[1]; | |
2617 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2618 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2619 | sky2->net_stats.multicast = data[5] + data[7]; | |
2620 | sky2->net_stats.collisions = data[10]; | |
2621 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2622 | ||
2623 | return &sky2->net_stats; | |
2624 | } | |
2625 | ||
2626 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2627 | { | |
2628 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
2629 | struct sky2_hw *hw = sky2->hw; |
2630 | unsigned port = sky2->port; | |
2631 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
2632 | |
2633 | if (!is_valid_ether_addr(addr->sa_data)) | |
2634 | return -EADDRNOTAVAIL; | |
2635 | ||
cd28ab6a | 2636 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 2637 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 2638 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 2639 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 2640 | dev->dev_addr, ETH_ALEN); |
1b537565 | 2641 | |
a8ab1ec0 SH |
2642 | /* virtual address for data */ |
2643 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2644 | ||
2645 | /* physical address: used for pause frames */ | |
2646 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
2647 | |
2648 | return 0; | |
cd28ab6a SH |
2649 | } |
2650 | ||
2651 | static void sky2_set_multicast(struct net_device *dev) | |
2652 | { | |
2653 | struct sky2_port *sky2 = netdev_priv(dev); | |
2654 | struct sky2_hw *hw = sky2->hw; | |
2655 | unsigned port = sky2->port; | |
2656 | struct dev_mc_list *list = dev->mc_list; | |
2657 | u16 reg; | |
2658 | u8 filter[8]; | |
2659 | ||
2660 | memset(filter, 0, sizeof(filter)); | |
2661 | ||
2662 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2663 | reg |= GM_RXCR_UCF_ENA; | |
2664 | ||
d571b694 | 2665 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2666 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2667 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2668 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2669 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2670 | reg &= ~GM_RXCR_MCF_ENA; |
2671 | else { | |
2672 | int i; | |
2673 | reg |= GM_RXCR_MCF_ENA; | |
2674 | ||
2675 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2676 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2677 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2678 | } |
2679 | } | |
2680 | ||
cd28ab6a | 2681 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2682 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2683 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2684 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2685 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2686 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2687 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2688 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2689 | |
2690 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2691 | } | |
2692 | ||
2693 | /* Can have one global because blinking is controlled by | |
2694 | * ethtool and that is always under RTNL mutex | |
2695 | */ | |
91c86df5 | 2696 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2697 | { |
793b883e SH |
2698 | u16 pg; |
2699 | ||
793b883e SH |
2700 | switch (hw->chip_id) { |
2701 | case CHIP_ID_YUKON_XL: | |
2702 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2703 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2704 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2705 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2706 | PHY_M_LEDC_INIT_CTRL(7) | | |
2707 | PHY_M_LEDC_STA1_CTRL(7) | | |
2708 | PHY_M_LEDC_STA0_CTRL(7)) | |
2709 | : 0); | |
2710 | ||
2711 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2712 | break; | |
2713 | ||
2714 | default: | |
2715 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2716 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2717 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2718 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2719 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2720 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2721 | PHY_M_LED_MO_RX(MO_LED_ON) |
2722 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2723 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2724 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2725 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2726 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2727 | ||
793b883e | 2728 | } |
cd28ab6a SH |
2729 | } |
2730 | ||
2731 | /* blink LED's for finding board */ | |
2732 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2733 | { | |
2734 | struct sky2_port *sky2 = netdev_priv(dev); | |
2735 | struct sky2_hw *hw = sky2->hw; | |
2736 | unsigned port = sky2->port; | |
793b883e | 2737 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2738 | long ms; |
91c86df5 | 2739 | int interrupted; |
cd28ab6a SH |
2740 | int onoff = 1; |
2741 | ||
793b883e | 2742 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2743 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2744 | else | |
2745 | ms = data * 1000; | |
2746 | ||
2747 | /* save initial values */ | |
91c86df5 | 2748 | down(&sky2->phy_sema); |
793b883e SH |
2749 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2750 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2751 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2752 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2753 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2754 | } else { | |
2755 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2756 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2757 | } | |
cd28ab6a | 2758 | |
91c86df5 SH |
2759 | interrupted = 0; |
2760 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2761 | sky2_led(hw, port, onoff); |
2762 | onoff = !onoff; | |
2763 | ||
91c86df5 SH |
2764 | up(&sky2->phy_sema); |
2765 | interrupted = msleep_interruptible(250); | |
2766 | down(&sky2->phy_sema); | |
2767 | ||
cd28ab6a SH |
2768 | ms -= 250; |
2769 | } | |
2770 | ||
2771 | /* resume regularly scheduled programming */ | |
793b883e SH |
2772 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2773 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2774 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2775 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2776 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2777 | } else { | |
2778 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2779 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2780 | } | |
91c86df5 | 2781 | up(&sky2->phy_sema); |
cd28ab6a SH |
2782 | |
2783 | return 0; | |
2784 | } | |
2785 | ||
2786 | static void sky2_get_pauseparam(struct net_device *dev, | |
2787 | struct ethtool_pauseparam *ecmd) | |
2788 | { | |
2789 | struct sky2_port *sky2 = netdev_priv(dev); | |
2790 | ||
2791 | ecmd->tx_pause = sky2->tx_pause; | |
2792 | ecmd->rx_pause = sky2->rx_pause; | |
2793 | ecmd->autoneg = sky2->autoneg; | |
2794 | } | |
2795 | ||
2796 | static int sky2_set_pauseparam(struct net_device *dev, | |
2797 | struct ethtool_pauseparam *ecmd) | |
2798 | { | |
2799 | struct sky2_port *sky2 = netdev_priv(dev); | |
2800 | int err = 0; | |
2801 | ||
2802 | sky2->autoneg = ecmd->autoneg; | |
2803 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2804 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2805 | ||
1b537565 | 2806 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2807 | |
2808 | return err; | |
2809 | } | |
2810 | ||
2811 | #ifdef CONFIG_PM | |
2812 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2813 | { | |
2814 | struct sky2_port *sky2 = netdev_priv(dev); | |
2815 | ||
2816 | wol->supported = WAKE_MAGIC; | |
2817 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2818 | } | |
2819 | ||
2820 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2821 | { | |
2822 | struct sky2_port *sky2 = netdev_priv(dev); | |
2823 | struct sky2_hw *hw = sky2->hw; | |
2824 | ||
2825 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2826 | return -EOPNOTSUPP; | |
2827 | ||
2828 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2829 | ||
2830 | if (sky2->wol) { | |
2831 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2832 | ||
2833 | sky2_write16(hw, WOL_CTRL_STAT, | |
2834 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2835 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2836 | } else | |
2837 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2838 | ||
2839 | return 0; | |
2840 | } | |
2841 | #endif | |
2842 | ||
fb17358f SH |
2843 | static int sky2_get_coalesce(struct net_device *dev, |
2844 | struct ethtool_coalesce *ecmd) | |
2845 | { | |
2846 | struct sky2_port *sky2 = netdev_priv(dev); | |
2847 | struct sky2_hw *hw = sky2->hw; | |
2848 | ||
2849 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2850 | ecmd->tx_coalesce_usecs = 0; | |
2851 | else { | |
2852 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2853 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2854 | } | |
2855 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2856 | ||
2857 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2858 | ecmd->rx_coalesce_usecs = 0; | |
2859 | else { | |
2860 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2861 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2862 | } | |
2863 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2864 | ||
2865 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2866 | ecmd->rx_coalesce_usecs_irq = 0; | |
2867 | else { | |
2868 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2869 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2870 | } | |
2871 | ||
2872 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2873 | ||
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | /* Note: this affect both ports */ | |
2878 | static int sky2_set_coalesce(struct net_device *dev, | |
2879 | struct ethtool_coalesce *ecmd) | |
2880 | { | |
2881 | struct sky2_port *sky2 = netdev_priv(dev); | |
2882 | struct sky2_hw *hw = sky2->hw; | |
2883 | const u32 tmin = sky2_clk2us(hw, 1); | |
2884 | const u32 tmax = 5000; | |
2885 | ||
2886 | if (ecmd->tx_coalesce_usecs != 0 && | |
2887 | (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax)) | |
2888 | return -EINVAL; | |
2889 | ||
2890 | if (ecmd->rx_coalesce_usecs != 0 && | |
2891 | (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax)) | |
2892 | return -EINVAL; | |
2893 | ||
2894 | if (ecmd->rx_coalesce_usecs_irq != 0 && | |
2895 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) | |
2896 | return -EINVAL; | |
2897 | ||
ff81fbbe | 2898 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
fb17358f | 2899 | return -EINVAL; |
ff81fbbe | 2900 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 2901 | return -EINVAL; |
ff81fbbe | 2902 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
fb17358f SH |
2903 | return -EINVAL; |
2904 | ||
2905 | if (ecmd->tx_coalesce_usecs == 0) | |
2906 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2907 | else { | |
2908 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2909 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2910 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2911 | } | |
2912 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2913 | ||
2914 | if (ecmd->rx_coalesce_usecs == 0) | |
2915 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2916 | else { | |
2917 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2918 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2919 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2920 | } | |
2921 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2922 | ||
2923 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2924 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2925 | else { | |
d28d4870 | 2926 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
2927 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
2928 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2929 | } | |
2930 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2931 | return 0; | |
2932 | } | |
2933 | ||
793b883e SH |
2934 | static void sky2_get_ringparam(struct net_device *dev, |
2935 | struct ethtool_ringparam *ering) | |
2936 | { | |
2937 | struct sky2_port *sky2 = netdev_priv(dev); | |
2938 | ||
2939 | ering->rx_max_pending = RX_MAX_PENDING; | |
2940 | ering->rx_mini_max_pending = 0; | |
2941 | ering->rx_jumbo_max_pending = 0; | |
2942 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2943 | ||
2944 | ering->rx_pending = sky2->rx_pending; | |
2945 | ering->rx_mini_pending = 0; | |
2946 | ering->rx_jumbo_pending = 0; | |
2947 | ering->tx_pending = sky2->tx_pending; | |
2948 | } | |
2949 | ||
2950 | static int sky2_set_ringparam(struct net_device *dev, | |
2951 | struct ethtool_ringparam *ering) | |
2952 | { | |
2953 | struct sky2_port *sky2 = netdev_priv(dev); | |
2954 | int err = 0; | |
2955 | ||
2956 | if (ering->rx_pending > RX_MAX_PENDING || | |
2957 | ering->rx_pending < 8 || | |
2958 | ering->tx_pending < MAX_SKB_TX_LE || | |
2959 | ering->tx_pending > TX_RING_SIZE - 1) | |
2960 | return -EINVAL; | |
2961 | ||
2962 | if (netif_running(dev)) | |
2963 | sky2_down(dev); | |
2964 | ||
2965 | sky2->rx_pending = ering->rx_pending; | |
2966 | sky2->tx_pending = ering->tx_pending; | |
2967 | ||
1b537565 | 2968 | if (netif_running(dev)) { |
793b883e | 2969 | err = sky2_up(dev); |
1b537565 SH |
2970 | if (err) |
2971 | dev_close(dev); | |
6ed995bb SH |
2972 | else |
2973 | sky2_set_multicast(dev); | |
1b537565 | 2974 | } |
793b883e SH |
2975 | |
2976 | return err; | |
2977 | } | |
2978 | ||
793b883e SH |
2979 | static int sky2_get_regs_len(struct net_device *dev) |
2980 | { | |
6e4cbb34 | 2981 | return 0x4000; |
793b883e SH |
2982 | } |
2983 | ||
2984 | /* | |
2985 | * Returns copy of control register region | |
6e4cbb34 | 2986 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2987 | */ |
2988 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2989 | void *p) | |
2990 | { | |
2991 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2992 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2993 | |
6e4cbb34 | 2994 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2995 | regs->version = 1; |
6e4cbb34 | 2996 | memset(p, 0, regs->len); |
793b883e | 2997 | |
6e4cbb34 SH |
2998 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2999 | ||
3000 | memcpy_fromio(p + B3_RI_WTO_R1, | |
3001 | io + B3_RI_WTO_R1, | |
3002 | regs->len - B3_RI_WTO_R1); | |
793b883e | 3003 | } |
cd28ab6a SH |
3004 | |
3005 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
3006 | .get_settings = sky2_get_settings, |
3007 | .set_settings = sky2_set_settings, | |
3008 | .get_drvinfo = sky2_get_drvinfo, | |
3009 | .get_msglevel = sky2_get_msglevel, | |
3010 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 3011 | .nway_reset = sky2_nway_reset, |
793b883e SH |
3012 | .get_regs_len = sky2_get_regs_len, |
3013 | .get_regs = sky2_get_regs, | |
3014 | .get_link = ethtool_op_get_link, | |
3015 | .get_sg = ethtool_op_get_sg, | |
3016 | .set_sg = ethtool_op_set_sg, | |
3017 | .get_tx_csum = ethtool_op_get_tx_csum, | |
3018 | .set_tx_csum = ethtool_op_set_tx_csum, | |
3019 | .get_tso = ethtool_op_get_tso, | |
3020 | .set_tso = ethtool_op_set_tso, | |
3021 | .get_rx_csum = sky2_get_rx_csum, | |
3022 | .set_rx_csum = sky2_set_rx_csum, | |
3023 | .get_strings = sky2_get_strings, | |
fb17358f SH |
3024 | .get_coalesce = sky2_get_coalesce, |
3025 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
3026 | .get_ringparam = sky2_get_ringparam, |
3027 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
3028 | .get_pauseparam = sky2_get_pauseparam, |
3029 | .set_pauseparam = sky2_set_pauseparam, | |
3030 | #ifdef CONFIG_PM | |
793b883e SH |
3031 | .get_wol = sky2_get_wol, |
3032 | .set_wol = sky2_set_wol, | |
cd28ab6a | 3033 | #endif |
793b883e | 3034 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
3035 | .get_stats_count = sky2_get_stats_count, |
3036 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 3037 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
3038 | }; |
3039 | ||
3040 | /* Initialize network device */ | |
3041 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
3042 | unsigned port, int highmem) | |
3043 | { | |
3044 | struct sky2_port *sky2; | |
3045 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3046 | ||
3047 | if (!dev) { | |
3048 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
3049 | return NULL; | |
3050 | } | |
3051 | ||
3052 | SET_MODULE_OWNER(dev); | |
3053 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 3054 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3055 | dev->open = sky2_up; |
3056 | dev->stop = sky2_down; | |
ef743d33 | 3057 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
3058 | dev->hard_start_xmit = sky2_xmit_frame; |
3059 | dev->get_stats = sky2_get_stats; | |
3060 | dev->set_multicast_list = sky2_set_multicast; | |
3061 | dev->set_mac_address = sky2_set_mac_address; | |
3062 | dev->change_mtu = sky2_change_mtu; | |
3063 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3064 | dev->tx_timeout = sky2_tx_timeout; | |
3065 | dev->watchdog_timeo = TX_WATCHDOG; | |
3066 | if (port == 0) | |
3067 | dev->poll = sky2_poll; | |
3068 | dev->weight = NAPI_WEIGHT; | |
3069 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3070 | dev->poll_controller = sky2_netpoll; | |
3071 | #endif | |
cd28ab6a SH |
3072 | |
3073 | sky2 = netdev_priv(dev); | |
3074 | sky2->netdev = dev; | |
3075 | sky2->hw = hw; | |
3076 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3077 | ||
3078 | spin_lock_init(&sky2->tx_lock); | |
3079 | /* Auto speed and flow control */ | |
3080 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 3081 | sky2->tx_pause = 1; |
cd28ab6a SH |
3082 | sky2->rx_pause = 1; |
3083 | sky2->duplex = -1; | |
3084 | sky2->speed = -1; | |
3085 | sky2->advertising = sky2_supported_modes(hw); | |
75d070c5 SH |
3086 | |
3087 | /* Receive checksum disabled for Yukon XL | |
3088 | * because of observed problems with incorrect | |
3089 | * values when multiple packets are received in one interrupt | |
3090 | */ | |
3091 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); | |
3092 | ||
91c86df5 SH |
3093 | INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2); |
3094 | init_MUTEX(&sky2->phy_sema); | |
793b883e SH |
3095 | sky2->tx_pending = TX_DEF_PENDING; |
3096 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
734d1868 | 3097 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
3098 | |
3099 | hw->dev[port] = dev; | |
3100 | ||
3101 | sky2->port = port; | |
3102 | ||
5a5b1ea0 | 3103 | dev->features |= NETIF_F_LLTX; |
3104 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3105 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3106 | if (highmem) |
3107 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3108 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3109 | |
d1f13708 | 3110 | #ifdef SKY2_VLAN_TAG_USED |
3111 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3112 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3113 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3114 | #endif | |
3115 | ||
cd28ab6a | 3116 | /* read the mac address */ |
793b883e | 3117 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3118 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3119 | |
3120 | /* device is off until link detection */ | |
3121 | netif_carrier_off(dev); | |
3122 | netif_stop_queue(dev); | |
3123 | ||
3124 | return dev; | |
3125 | } | |
3126 | ||
28bd181a | 3127 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
3128 | { |
3129 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3130 | ||
3131 | if (netif_msg_probe(sky2)) | |
3132 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3133 | dev->name, | |
3134 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3135 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3136 | } | |
3137 | ||
4d52b48b SH |
3138 | /* Handle software interrupt used during MSI test */ |
3139 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, | |
3140 | struct pt_regs *regs) | |
3141 | { | |
3142 | struct sky2_hw *hw = dev_id; | |
3143 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
3144 | ||
3145 | if (status == 0) | |
3146 | return IRQ_NONE; | |
3147 | ||
3148 | if (status & Y2_IS_IRQ_SW) { | |
3149 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3150 | hw->msi = 1; | |
3151 | } | |
3152 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
3153 | ||
3154 | sky2_read32(hw, B0_IMSK); | |
3155 | return IRQ_HANDLED; | |
3156 | } | |
3157 | ||
3158 | /* Test interrupt path by forcing a a software IRQ */ | |
3159 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
3160 | { | |
3161 | struct pci_dev *pdev = hw->pdev; | |
3162 | int i, err; | |
3163 | ||
3164 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); | |
3165 | ||
3166 | err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw); | |
3167 | if (err) { | |
3168 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3169 | pci_name(pdev), pdev->irq); | |
3170 | return err; | |
3171 | } | |
3172 | ||
3173 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); | |
3174 | wmb(); | |
3175 | ||
3176 | for (i = 0; i < 10; i++) { | |
3177 | barrier(); | |
3178 | if (hw->msi) | |
3179 | goto found; | |
3180 | mdelay(1); | |
3181 | } | |
3182 | ||
3183 | err = -EOPNOTSUPP; | |
3184 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3185 | found: | |
3186 | sky2_write32(hw, B0_IMSK, 0); | |
3187 | ||
3188 | free_irq(pdev->irq, hw); | |
3189 | ||
3190 | return err; | |
3191 | } | |
3192 | ||
cd28ab6a SH |
3193 | static int __devinit sky2_probe(struct pci_dev *pdev, |
3194 | const struct pci_device_id *ent) | |
3195 | { | |
793b883e | 3196 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3197 | struct sky2_hw *hw; |
5afa0a9c | 3198 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3199 | |
793b883e SH |
3200 | err = pci_enable_device(pdev); |
3201 | if (err) { | |
cd28ab6a SH |
3202 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3203 | pci_name(pdev)); | |
3204 | goto err_out; | |
3205 | } | |
3206 | ||
793b883e SH |
3207 | err = pci_request_regions(pdev, DRV_NAME); |
3208 | if (err) { | |
cd28ab6a SH |
3209 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3210 | pci_name(pdev)); | |
793b883e | 3211 | goto err_out; |
cd28ab6a SH |
3212 | } |
3213 | ||
3214 | pci_set_master(pdev); | |
3215 | ||
5afa0a9c | 3216 | /* Find power-management capability. */ |
3217 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3218 | if (pm_cap == 0) { | |
3219 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3220 | "aborting.\n"); | |
3221 | err = -EIO; | |
3222 | goto err_out_free_regions; | |
3223 | } | |
3224 | ||
d1f3d4dd SH |
3225 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3226 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3227 | using_dac = 1; | |
3228 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3229 | if (err < 0) { | |
3230 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3231 | "for consistent allocations\n", pci_name(pdev)); | |
3232 | goto err_out_free_regions; | |
3233 | } | |
cd28ab6a | 3234 | |
d1f3d4dd | 3235 | } else { |
cd28ab6a SH |
3236 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3237 | if (err) { | |
3238 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3239 | pci_name(pdev)); | |
3240 | goto err_out_free_regions; | |
3241 | } | |
3242 | } | |
d1f3d4dd | 3243 | |
cd28ab6a | 3244 | #ifdef __BIG_ENDIAN |
d571b694 | 3245 | /* byte swap descriptors in hardware */ |
cd28ab6a SH |
3246 | { |
3247 | u32 reg; | |
3248 | ||
3249 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3250 | reg |= PCI_REV_DESC; | |
3251 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3252 | } | |
3253 | #endif | |
3254 | ||
3255 | err = -ENOMEM; | |
6aad85d6 | 3256 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a SH |
3257 | if (!hw) { |
3258 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3259 | pci_name(pdev)); | |
3260 | goto err_out_free_regions; | |
3261 | } | |
3262 | ||
cd28ab6a | 3263 | hw->pdev = pdev; |
cd28ab6a SH |
3264 | |
3265 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3266 | if (!hw->regs) { | |
3267 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3268 | pci_name(pdev)); | |
3269 | goto err_out_free_hw; | |
3270 | } | |
5afa0a9c | 3271 | hw->pm_cap = pm_cap; |
cd28ab6a | 3272 | |
08c06d8a SH |
3273 | /* ring for status responses */ |
3274 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
3275 | &hw->st_dma); | |
3276 | if (!hw->st_le) | |
3277 | goto err_out_iounmap; | |
3278 | ||
cd28ab6a SH |
3279 | err = sky2_reset(hw); |
3280 | if (err) | |
793b883e | 3281 | goto err_out_iounmap; |
cd28ab6a | 3282 | |
5f4f9dc1 | 3283 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3284 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3285 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3286 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3287 | |
793b883e SH |
3288 | dev = sky2_init_netdev(hw, 0, using_dac); |
3289 | if (!dev) | |
cd28ab6a SH |
3290 | goto err_out_free_pci; |
3291 | ||
793b883e SH |
3292 | err = register_netdev(dev); |
3293 | if (err) { | |
cd28ab6a SH |
3294 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3295 | pci_name(pdev)); | |
3296 | goto err_out_free_netdev; | |
3297 | } | |
3298 | ||
3299 | sky2_show_addr(dev); | |
3300 | ||
3301 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3302 | if (register_netdev(dev1) == 0) | |
3303 | sky2_show_addr(dev1); | |
3304 | else { | |
3305 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3306 | printk(KERN_WARNING PFX |
3307 | "register of second port failed\n"); | |
cd28ab6a SH |
3308 | hw->dev[1] = NULL; |
3309 | free_netdev(dev1); | |
3310 | } | |
3311 | } | |
3312 | ||
4d52b48b SH |
3313 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
3314 | err = sky2_test_msi(hw); | |
3315 | if (err == -EOPNOTSUPP) { | |
3316 | /* MSI test failed, go back to INTx mode */ | |
3317 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
3318 | "switching to INTx mode. Please report this failure to " | |
3319 | "the PCI maintainer and include system chipset information.\n", | |
3320 | pci_name(pdev)); | |
3321 | pci_disable_msi(pdev); | |
3322 | } | |
3323 | else if (err) | |
3324 | goto err_out_unregister; | |
3325 | } | |
3326 | ||
db992c97 SH |
3327 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM, |
3328 | DRV_NAME, hw); | |
793b883e SH |
3329 | if (err) { |
3330 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3331 | pci_name(pdev), pdev->irq); | |
3332 | goto err_out_unregister; | |
3333 | } | |
3334 | ||
3335 | hw->intr_mask = Y2_IS_BASE; | |
3336 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
3337 | ||
3338 | pci_set_drvdata(pdev, hw); | |
3339 | ||
cd28ab6a SH |
3340 | return 0; |
3341 | ||
793b883e | 3342 | err_out_unregister: |
4d52b48b SH |
3343 | if (hw->msi) |
3344 | pci_disable_msi(pdev); | |
793b883e SH |
3345 | if (dev1) { |
3346 | unregister_netdev(dev1); | |
3347 | free_netdev(dev1); | |
3348 | } | |
3349 | unregister_netdev(dev); | |
cd28ab6a SH |
3350 | err_out_free_netdev: |
3351 | free_netdev(dev); | |
cd28ab6a | 3352 | err_out_free_pci: |
793b883e | 3353 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3354 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3355 | err_out_iounmap: | |
3356 | iounmap(hw->regs); | |
3357 | err_out_free_hw: | |
3358 | kfree(hw); | |
3359 | err_out_free_regions: | |
3360 | pci_release_regions(pdev); | |
cd28ab6a | 3361 | pci_disable_device(pdev); |
cd28ab6a SH |
3362 | err_out: |
3363 | return err; | |
3364 | } | |
3365 | ||
3366 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3367 | { | |
793b883e | 3368 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3369 | struct net_device *dev0, *dev1; |
3370 | ||
793b883e | 3371 | if (!hw) |
cd28ab6a SH |
3372 | return; |
3373 | ||
cd28ab6a | 3374 | dev0 = hw->dev[0]; |
793b883e SH |
3375 | dev1 = hw->dev[1]; |
3376 | if (dev1) | |
3377 | unregister_netdev(dev1); | |
cd28ab6a SH |
3378 | unregister_netdev(dev0); |
3379 | ||
793b883e | 3380 | sky2_write32(hw, B0_IMSK, 0); |
5afa0a9c | 3381 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3382 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3383 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3384 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3385 | |
3386 | free_irq(pdev->irq, hw); | |
4d52b48b SH |
3387 | if (hw->msi) |
3388 | pci_disable_msi(pdev); | |
793b883e | 3389 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3390 | pci_release_regions(pdev); |
3391 | pci_disable_device(pdev); | |
793b883e | 3392 | |
cd28ab6a SH |
3393 | if (dev1) |
3394 | free_netdev(dev1); | |
3395 | free_netdev(dev0); | |
3396 | iounmap(hw->regs); | |
3397 | kfree(hw); | |
5afa0a9c | 3398 | |
cd28ab6a SH |
3399 | pci_set_drvdata(pdev, NULL); |
3400 | } | |
3401 | ||
3402 | #ifdef CONFIG_PM | |
3403 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3404 | { | |
793b883e | 3405 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3406 | int i; |
cd28ab6a SH |
3407 | |
3408 | for (i = 0; i < 2; i++) { | |
3409 | struct net_device *dev = hw->dev[i]; | |
3410 | ||
3411 | if (dev) { | |
5afa0a9c | 3412 | if (!netif_running(dev)) |
3413 | continue; | |
3414 | ||
3415 | sky2_down(dev); | |
cd28ab6a | 3416 | netif_device_detach(dev); |
cd28ab6a SH |
3417 | } |
3418 | } | |
3419 | ||
5afa0a9c | 3420 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3421 | } |
3422 | ||
3423 | static int sky2_resume(struct pci_dev *pdev) | |
3424 | { | |
793b883e | 3425 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 3426 | int i, err; |
cd28ab6a | 3427 | |
cd28ab6a SH |
3428 | pci_restore_state(pdev); |
3429 | pci_enable_wake(pdev, PCI_D0, 0); | |
08c06d8a SH |
3430 | err = sky2_set_power_state(hw, PCI_D0); |
3431 | if (err) | |
3432 | goto out; | |
cd28ab6a | 3433 | |
08c06d8a SH |
3434 | err = sky2_reset(hw); |
3435 | if (err) | |
3436 | goto out; | |
cd28ab6a SH |
3437 | |
3438 | for (i = 0; i < 2; i++) { | |
3439 | struct net_device *dev = hw->dev[i]; | |
08c06d8a SH |
3440 | if (dev && netif_running(dev)) { |
3441 | netif_device_attach(dev); | |
3442 | err = sky2_up(dev); | |
3443 | if (err) { | |
3444 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3445 | dev->name, err); | |
3446 | dev_close(dev); | |
3447 | break; | |
5afa0a9c | 3448 | } |
cd28ab6a SH |
3449 | } |
3450 | } | |
08c06d8a SH |
3451 | out: |
3452 | return err; | |
cd28ab6a SH |
3453 | } |
3454 | #endif | |
3455 | ||
3456 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3457 | .name = DRV_NAME, |
3458 | .id_table = sky2_id_table, | |
3459 | .probe = sky2_probe, | |
3460 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3461 | #ifdef CONFIG_PM |
793b883e SH |
3462 | .suspend = sky2_suspend, |
3463 | .resume = sky2_resume, | |
cd28ab6a SH |
3464 | #endif |
3465 | }; | |
3466 | ||
3467 | static int __init sky2_init_module(void) | |
3468 | { | |
50241c4c | 3469 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3470 | } |
3471 | ||
3472 | static void __exit sky2_cleanup_module(void) | |
3473 | { | |
3474 | pci_unregister_driver(&sky2_driver); | |
3475 | } | |
3476 | ||
3477 | module_init(sky2_init_module); | |
3478 | module_exit(sky2_cleanup_module); | |
3479 | ||
3480 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3481 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3482 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3483 | MODULE_VERSION(DRV_VERSION); |