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via-velocity : cleanups.
[deliverable/linux.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14 1/*
047584ce 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14 26#include <linux/dma-mapping.h>
ce973b14 27#include <linux/mii.h>
728de4c9 28#include <linux/phy.h>
df19b6b0 29#include <linux/workqueue.h>
0b9da337 30#include <linux/of_mdio.h>
4b6ba8aa 31#include <linux/of_net.h>
55b6c8e9 32#include <linux/of_platform.h>
ce973b14
LY		 33
34#include <asm/uaccess.h>
35#include <asm/irq.h>
36#include <asm/io.h>
37#include <asm/immap_qe.h>
38#include <asm/qe.h>
39#include <asm/ucc.h>
40#include <asm/ucc_fast.h>
81abb43a 41#include <asm/machdep.h>
ce973b14
LY		 42
43#include "ucc_geth.h"
1577ecef 44#include "fsl_pq_mdio.h"
ce973b14
LY		 45
46#undef DEBUG
47
ce973b14
LY		 48#define ugeth_printk(level, format, arg...) \
49 printk(level format "\n", ## arg)
50
51#define ugeth_dbg(format, arg...) \
52 ugeth_printk(KERN_DEBUG , format , ## arg)
53#define ugeth_err(format, arg...) \
54 ugeth_printk(KERN_ERR , format , ## arg)
55#define ugeth_info(format, arg...) \
56 ugeth_printk(KERN_INFO , format , ## arg)
57#define ugeth_warn(format, arg...) \
58 ugeth_printk(KERN_WARNING , format , ## arg)
59
60#ifdef UGETH_VERBOSE_DEBUG
61#define ugeth_vdbg ugeth_dbg
62#else
63#define ugeth_vdbg(fmt, args...) do { } while (0)
64#endif /* UGETH_VERBOSE_DEBUG */
890de95e 65#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 66
88a15f2e 67
ce973b14
LY		 68static DEFINE_SPINLOCK(ugeth_lock);
69
890de95e
LY		 70static struct {
71 u32 msg_enable;
72} debug = { -1 };
73
74module_param_named(debug, debug.msg_enable, int, 0);
75MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
76
18a8e864 77static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 78 .uf_info = {
79 .bd_mem_part = MEM_PART_SYSTEM,
80 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
81 .max_rx_buf_length = 1536,
728de4c9 82 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 83 .urfs = UCC_GETH_URFS_INIT,
84 .urfet = UCC_GETH_URFET_INIT,
85 .urfset = UCC_GETH_URFSET_INIT,
86 .utfs = UCC_GETH_UTFS_INIT,
87 .utfet = UCC_GETH_UTFET_INIT,
88 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 89 .ufpt = 256,
90 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
91 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
92 .tenc = UCC_FAST_TX_ENCODING_NRZ,
93 .renc = UCC_FAST_RX_ENCODING_NRZ,
94 .tcrc = UCC_FAST_16_BIT_CRC,
95 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
96 },
97 .numQueuesTx = 1,
98 .numQueuesRx = 1,
99 .extendedFilteringChainPointer = ((uint32_t) NULL),
100 .typeorlen = 3072 /*1536 */ ,
101 .nonBackToBackIfgPart1 = 0x40,
102 .nonBackToBackIfgPart2 = 0x60,
103 .miminumInterFrameGapEnforcement = 0x50,
104 .backToBackInterFrameGap = 0x60,
105 .mblinterval = 128,
106 .nortsrbytetime = 5,
107 .fracsiz = 1,
108 .strictpriorityq = 0xff,
109 .altBebTruncation = 0xa,
110 .excessDefer = 1,
111 .maxRetransmission = 0xf,
112 .collisionWindow = 0x37,
113 .receiveFlowControl = 1,
ac421852 114 .transmitFlowControl = 1,
ce973b14
LY		 115 .maxGroupAddrInHash = 4,
116 .maxIndAddrInHash = 4,
117 .prel = 7,
118 .maxFrameLength = 1518,
119 .minFrameLength = 64,
120 .maxD1Length = 1520,
121 .maxD2Length = 1520,
122 .vlantype = 0x8100,
123 .ecamptr = ((uint32_t) NULL),
124 .eventRegMask = UCCE_OTHER,
125 .pausePeriod = 0xf000,
126 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
127 .bdRingLenTx = {
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN,
134 TX_BD_RING_LEN,
135 TX_BD_RING_LEN},
136
137 .bdRingLenRx = {
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN,
144 RX_BD_RING_LEN,
145 RX_BD_RING_LEN},
146
147 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
148 .largestexternallookupkeysize =
149 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 150 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
152 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 153 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
154 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
155 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
156 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
157 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 158 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
159 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 160 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
162};
163
18a8e864 164static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 165
166#ifdef DEBUG
167static void mem_disp(u8 *addr, int size)
168{
169 u8 *i;
170 int size16Aling = (size >> 4) << 4;
171 int size4Aling = (size >> 2) << 2;
172 int notAlign = 0;
173 if (size % 16)
174 notAlign = 1;
175
176 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
177 printk("0x%08x: %08x %08x %08x %08x\r\n",
178 (u32) i,
179 *((u32 *) (i)),
180 *((u32 *) (i + 4)),
181 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
182 if (notAlign == 1)
183 printk("0x%08x: ", (u32) i);
184 for (; (u32) i < (u32) addr + size4Aling; i += 4)
185 printk("%08x ", *((u32 *) (i)));
186 for (; (u32) i < (u32) addr + size; i++)
187 printk("%02x", *((u8 *) (i)));
188 if (notAlign == 1)
189 printk("\r\n");
190}
191#endif /* DEBUG */
192
ce973b14
LY		 193static struct list_head *dequeue(struct list_head *lh)
194{
195 unsigned long flags;
196
1083cfe1 197 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 198 if (!list_empty(lh)) {
199 struct list_head *node = lh->next;
200 list_del(node);
1083cfe1 201 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 202 return node;
203 } else {
1083cfe1 204 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 205 return NULL;
206 }
207}
208
6fee40e9
AF		 209static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
210 u8 __iomem *bd)
ce973b14
LY		 211{
212 struct sk_buff *skb = NULL;
213
50f238fd
AV		 214 skb = __skb_dequeue(&ugeth->rx_recycle);
215 if (!skb)
216 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
217 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
ce973b14
LY		 218 if (skb == NULL)
219 return NULL;
220
221 /* We need the data buffer to be aligned properly. We will reserve
222 * as many bytes as needed to align the data properly
223 */
224 skb_reserve(skb,
225 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
226 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
227 1)));
228
da1aa63e 229 skb->dev = ugeth->ndev;
ce973b14 230
6fee40e9 231 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 232 dma_map_single(ugeth->dev,
ce973b14
LY		 233 skb->data,
234 ugeth->ug_info->uf_info.max_rx_buf_length +
235 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
236 DMA_FROM_DEVICE));
237
6fee40e9
AF		 238 out_be32((u32 __iomem *)bd,
239 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 240
241 return skb;
242}
243
18a8e864 244static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 245{
6fee40e9 246 u8 __iomem *bd;
ce973b14
LY		 247 u32 bd_status;
248 struct sk_buff *skb;
249 int i;
250
251 bd = ugeth->p_rx_bd_ring[rxQ];
252 i = 0;
253
254 do {
6fee40e9 255 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 256 skb = get_new_skb(ugeth, bd);
257
258 if (!skb) /* If can not allocate data buffer,
259 abort. Cleanup will be elsewhere */
260 return -ENOMEM;
261
262 ugeth->rx_skbuff[rxQ][i] = skb;
263
264 /* advance the BD pointer */
18a8e864 265 bd += sizeof(struct qe_bd);
ce973b14
LY		 266 i++;
267 } while (!(bd_status & R_W));
268
269 return 0;
270}
271
18a8e864 272static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 273 u32 *p_start,
ce973b14
LY		 274 u8 num_entries,
275 u32 thread_size,
276 u32 thread_alignment,
345f8422 277 unsigned int risc,
ce973b14
LY		 278 int skip_page_for_first_entry)
279{
280 u32 init_enet_offset;
281 u8 i;
282 int snum;
283
284 for (i = 0; i < num_entries; i++) {
285 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 286 if (netif_msg_ifup(ugeth))
287 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 288 return snum;
289 }
290 if ((i == 0) && skip_page_for_first_entry)
291 /* First entry of Rx does not have page */
292 init_enet_offset = 0;
293 else {
294 init_enet_offset =
295 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 296 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 297 if (netif_msg_ifup(ugeth))
298 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 299 qe_put_snum((u8) snum);
300 return -ENOMEM;
301 }
302 }
303 *(p_start++) =
304 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
305 | risc;
306 }
307
308 return 0;
309}
310
18a8e864 311static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 312 u32 *p_start,
ce973b14 313 u8 num_entries,
345f8422 314 unsigned int risc,
ce973b14
LY		 315 int skip_page_for_first_entry)
316{
317 u32 init_enet_offset;
318 u8 i;
319 int snum;
320
321 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 322 u32 val = *p_start;
323
ce973b14
LY		 324 /* Check that this entry was actually valid --
325 needed in case failed in allocations */
6fee40e9 326 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 327 snum =
6fee40e9 328 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 329 ENET_INIT_PARAM_SNUM_SHIFT;
330 qe_put_snum((u8) snum);
331 if (!((i == 0) && skip_page_for_first_entry)) {
332 /* First entry of Rx does not have page */
333 init_enet_offset =
6fee40e9 334 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 335 qe_muram_free(init_enet_offset);
336 }
6fee40e9 337 *p_start++ = 0;
ce973b14
LY		 338 }
339 }
340
341 return 0;
342}
343
344#ifdef DEBUG
18a8e864 345static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 346 u32 __iomem *p_start,
ce973b14
LY		 347 u8 num_entries,
348 u32 thread_size,
345f8422 349 unsigned int risc,
ce973b14
LY		 350 int skip_page_for_first_entry)
351{
352 u32 init_enet_offset;
353 u8 i;
354 int snum;
355
356 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 357 u32 val = in_be32(p_start);
358
ce973b14
LY		 359 /* Check that this entry was actually valid --
360 needed in case failed in allocations */
6fee40e9 361 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 362 snum =
6fee40e9 363 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 364 ENET_INIT_PARAM_SNUM_SHIFT;
365 qe_put_snum((u8) snum);
366 if (!((i == 0) && skip_page_for_first_entry)) {
367 /* First entry of Rx does not have page */
368 init_enet_offset =
369 (in_be32(p_start) &
370 ENET_INIT_PARAM_PTR_MASK);
371 ugeth_info("Init enet entry %d:", i);
372 ugeth_info("Base address: 0x%08x",
373 (u32)
374 qe_muram_addr(init_enet_offset));
375 mem_disp(qe_muram_addr(init_enet_offset),
376 thread_size);
377 }
378 p_start++;
379 }
380 }
381
382 return 0;
383}
384#endif
385
18a8e864 386static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 387{
388 kfree(enet_addr_cont);
389}
390
df19b6b0 391static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 392{
393 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
394 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
395 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
396}
397
18a8e864 398static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 399{
6fee40e9 400 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 401
402 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 403 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 404 return -EINVAL;
405 }
406
407 p_82xx_addr_filt =
6fee40e9 408 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 409 addressfiltering;
410
411 /* Writing address ff.ff.ff.ff.ff.ff disables address
412 recognition for this register */
413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
414 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
415 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
416
417 return 0;
418}
419
18a8e864
LY		 420static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
421 u8 *p_enet_addr)
ce973b14 422{
6fee40e9 423 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 424 u32 cecr_subblock;
425
426 p_82xx_addr_filt =
6fee40e9 427 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 428 addressfiltering;
429
430 cecr_subblock =
431 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
432
433 /* Ethernet frames are defined in Little Endian mode,
3ad2f3fb 434 therefore to insert */
ce973b14 435 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 436
437 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 438
439 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 440 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 441}
442
18a8e864 443static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 444{
445 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
446}
447
448#ifdef DEBUG
18a8e864
LY		 449static void get_statistics(struct ucc_geth_private *ugeth,
450 struct ucc_geth_tx_firmware_statistics *
ce973b14 451 tx_firmware_statistics,
18a8e864 452 struct ucc_geth_rx_firmware_statistics *
ce973b14 453 rx_firmware_statistics,
18a8e864 454 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 455{
6fee40e9
AF		 456 struct ucc_fast __iomem *uf_regs;
457 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 458 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
459 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 460
461 ug_regs = ugeth->ug_regs;
6fee40e9 462 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 463 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
464 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
465
466 /* Tx firmware only if user handed pointer and driver actually
467 gathers Tx firmware statistics */
468 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
469 tx_firmware_statistics->sicoltx =
470 in_be32(&p_tx_fw_statistics_pram->sicoltx);
471 tx_firmware_statistics->mulcoltx =
472 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
473 tx_firmware_statistics->latecoltxfr =
474 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
475 tx_firmware_statistics->frabortduecol =
476 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
477 tx_firmware_statistics->frlostinmactxer =
478 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
479 tx_firmware_statistics->carriersenseertx =
480 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
481 tx_firmware_statistics->frtxok =
482 in_be32(&p_tx_fw_statistics_pram->frtxok);
483 tx_firmware_statistics->txfrexcessivedefer =
484 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
485 tx_firmware_statistics->txpkts256 =
486 in_be32(&p_tx_fw_statistics_pram->txpkts256);
487 tx_firmware_statistics->txpkts512 =
488 in_be32(&p_tx_fw_statistics_pram->txpkts512);
489 tx_firmware_statistics->txpkts1024 =
490 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
491 tx_firmware_statistics->txpktsjumbo =
492 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
493 }
494
495 /* Rx firmware only if user handed pointer and driver actually
496 * gathers Rx firmware statistics */
497 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
498 int i;
499 rx_firmware_statistics->frrxfcser =
500 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
501 rx_firmware_statistics->fraligner =
502 in_be32(&p_rx_fw_statistics_pram->fraligner);
503 rx_firmware_statistics->inrangelenrxer =
504 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
505 rx_firmware_statistics->outrangelenrxer =
506 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
507 rx_firmware_statistics->frtoolong =
508 in_be32(&p_rx_fw_statistics_pram->frtoolong);
509 rx_firmware_statistics->runt =
510 in_be32(&p_rx_fw_statistics_pram->runt);
511 rx_firmware_statistics->verylongevent =
512 in_be32(&p_rx_fw_statistics_pram->verylongevent);
513 rx_firmware_statistics->symbolerror =
514 in_be32(&p_rx_fw_statistics_pram->symbolerror);
515 rx_firmware_statistics->dropbsy =
516 in_be32(&p_rx_fw_statistics_pram->dropbsy);
517 for (i = 0; i < 0x8; i++)
518 rx_firmware_statistics->res0[i] =
519 p_rx_fw_statistics_pram->res0[i];
520 rx_firmware_statistics->mismatchdrop =
521 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
522 rx_firmware_statistics->underpkts =
523 in_be32(&p_rx_fw_statistics_pram->underpkts);
524 rx_firmware_statistics->pkts256 =
525 in_be32(&p_rx_fw_statistics_pram->pkts256);
526 rx_firmware_statistics->pkts512 =
527 in_be32(&p_rx_fw_statistics_pram->pkts512);
528 rx_firmware_statistics->pkts1024 =
529 in_be32(&p_rx_fw_statistics_pram->pkts1024);
530 rx_firmware_statistics->pktsjumbo =
531 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
532 rx_firmware_statistics->frlossinmacer =
533 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
534 rx_firmware_statistics->pausefr =
535 in_be32(&p_rx_fw_statistics_pram->pausefr);
536 for (i = 0; i < 0x4; i++)
537 rx_firmware_statistics->res1[i] =
538 p_rx_fw_statistics_pram->res1[i];
539 rx_firmware_statistics->removevlan =
540 in_be32(&p_rx_fw_statistics_pram->removevlan);
541 rx_firmware_statistics->replacevlan =
542 in_be32(&p_rx_fw_statistics_pram->replacevlan);
543 rx_firmware_statistics->insertvlan =
544 in_be32(&p_rx_fw_statistics_pram->insertvlan);
545 }
546
547 /* Hardware only if user handed pointer and driver actually
548 gathers hardware statistics */
3bc53427
TT		 549 if (hardware_statistics &&
550 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 551 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
552 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
553 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
554 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
555 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
556 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
557 hardware_statistics->txok = in_be32(&ug_regs->txok);
558 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
559 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
560 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
561 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
562 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
563 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
564 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
565 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
566 }
567}
568
18a8e864 569static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 570{
571 int i;
572 int length;
573
574 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
575 if (ugeth->p_tx_bd_ring[i]) {
576 length =
577 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 578 sizeof(struct qe_bd));
ce973b14
LY		 579 ugeth_info("TX BDs[%d]", i);
580 mem_disp(ugeth->p_tx_bd_ring[i], length);
581 }
582 }
583 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
584 if (ugeth->p_rx_bd_ring[i]) {
585 length =
586 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 587 sizeof(struct qe_bd));
ce973b14
LY		 588 ugeth_info("RX BDs[%d]", i);
589 mem_disp(ugeth->p_rx_bd_ring[i], length);
590 }
591 }
592}
593
18a8e864 594static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 595{
596 int i;
597
3ac37746 598 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1);
ce973b14
LY		 599 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
600
601 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
602 (u32) & ugeth->ug_regs->maccfg1,
603 in_be32(&ugeth->ug_regs->maccfg1));
604 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
605 (u32) & ugeth->ug_regs->maccfg2,
606 in_be32(&ugeth->ug_regs->maccfg2));
607 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
608 (u32) & ugeth->ug_regs->ipgifg,
609 in_be32(&ugeth->ug_regs->ipgifg));
610 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
611 (u32) & ugeth->ug_regs->hafdup,
612 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 613 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
614 (u32) & ugeth->ug_regs->ifctl,
615 in_be32(&ugeth->ug_regs->ifctl));
616 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
617 (u32) & ugeth->ug_regs->ifstat,
618 in_be32(&ugeth->ug_regs->ifstat));
619 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
620 (u32) & ugeth->ug_regs->macstnaddr1,
621 in_be32(&ugeth->ug_regs->macstnaddr1));
622 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
623 (u32) & ugeth->ug_regs->macstnaddr2,
624 in_be32(&ugeth->ug_regs->macstnaddr2));
625 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
626 (u32) & ugeth->ug_regs->uempr,
627 in_be32(&ugeth->ug_regs->uempr));
628 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
629 (u32) & ugeth->ug_regs->utbipar,
630 in_be32(&ugeth->ug_regs->utbipar));
631 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
632 (u32) & ugeth->ug_regs->uescr,
633 in_be16(&ugeth->ug_regs->uescr));
634 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
635 (u32) & ugeth->ug_regs->tx64,
636 in_be32(&ugeth->ug_regs->tx64));
637 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
638 (u32) & ugeth->ug_regs->tx127,
639 in_be32(&ugeth->ug_regs->tx127));
640 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
641 (u32) & ugeth->ug_regs->tx255,
642 in_be32(&ugeth->ug_regs->tx255));
643 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
644 (u32) & ugeth->ug_regs->rx64,
645 in_be32(&ugeth->ug_regs->rx64));
646 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
647 (u32) & ugeth->ug_regs->rx127,
648 in_be32(&ugeth->ug_regs->rx127));
649 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
650 (u32) & ugeth->ug_regs->rx255,
651 in_be32(&ugeth->ug_regs->rx255));
652 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
653 (u32) & ugeth->ug_regs->txok,
654 in_be32(&ugeth->ug_regs->txok));
655 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
656 (u32) & ugeth->ug_regs->txcf,
657 in_be16(&ugeth->ug_regs->txcf));
658 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
659 (u32) & ugeth->ug_regs->tmca,
660 in_be32(&ugeth->ug_regs->tmca));
661 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
662 (u32) & ugeth->ug_regs->tbca,
663 in_be32(&ugeth->ug_regs->tbca));
664 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
665 (u32) & ugeth->ug_regs->rxfok,
666 in_be32(&ugeth->ug_regs->rxfok));
667 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
668 (u32) & ugeth->ug_regs->rxbok,
669 in_be32(&ugeth->ug_regs->rxbok));
670 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
671 (u32) & ugeth->ug_regs->rbyt,
672 in_be32(&ugeth->ug_regs->rbyt));
673 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
674 (u32) & ugeth->ug_regs->rmca,
675 in_be32(&ugeth->ug_regs->rmca));
676 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
677 (u32) & ugeth->ug_regs->rbca,
678 in_be32(&ugeth->ug_regs->rbca));
679 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
680 (u32) & ugeth->ug_regs->scar,
681 in_be32(&ugeth->ug_regs->scar));
682 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
683 (u32) & ugeth->ug_regs->scam,
684 in_be32(&ugeth->ug_regs->scam));
685
686 if (ugeth->p_thread_data_tx) {
687 int numThreadsTxNumerical;
688 switch (ugeth->ug_info->numThreadsTx) {
689 case UCC_GETH_NUM_OF_THREADS_1:
690 numThreadsTxNumerical = 1;
691 break;
692 case UCC_GETH_NUM_OF_THREADS_2:
693 numThreadsTxNumerical = 2;
694 break;
695 case UCC_GETH_NUM_OF_THREADS_4:
696 numThreadsTxNumerical = 4;
697 break;
698 case UCC_GETH_NUM_OF_THREADS_6:
699 numThreadsTxNumerical = 6;
700 break;
701 case UCC_GETH_NUM_OF_THREADS_8:
702 numThreadsTxNumerical = 8;
703 break;
704 default:
705 numThreadsTxNumerical = 0;
706 break;
707 }
708
709 ugeth_info("Thread data TXs:");
710 ugeth_info("Base address: 0x%08x",
711 (u32) ugeth->p_thread_data_tx);
712 for (i = 0; i < numThreadsTxNumerical; i++) {
713 ugeth_info("Thread data TX[%d]:", i);
714 ugeth_info("Base address: 0x%08x",
715 (u32) & ugeth->p_thread_data_tx[i]);
716 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 717 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 718 }
719 }
720 if (ugeth->p_thread_data_rx) {
721 int numThreadsRxNumerical;
722 switch (ugeth->ug_info->numThreadsRx) {
723 case UCC_GETH_NUM_OF_THREADS_1:
724 numThreadsRxNumerical = 1;
725 break;
726 case UCC_GETH_NUM_OF_THREADS_2:
727 numThreadsRxNumerical = 2;
728 break;
729 case UCC_GETH_NUM_OF_THREADS_4:
730 numThreadsRxNumerical = 4;
731 break;
732 case UCC_GETH_NUM_OF_THREADS_6:
733 numThreadsRxNumerical = 6;
734 break;
735 case UCC_GETH_NUM_OF_THREADS_8:
736 numThreadsRxNumerical = 8;
737 break;
738 default:
739 numThreadsRxNumerical = 0;
740 break;
741 }
742
743 ugeth_info("Thread data RX:");
744 ugeth_info("Base address: 0x%08x",
745 (u32) ugeth->p_thread_data_rx);
746 for (i = 0; i < numThreadsRxNumerical; i++) {
747 ugeth_info("Thread data RX[%d]:", i);
748 ugeth_info("Base address: 0x%08x",
749 (u32) & ugeth->p_thread_data_rx[i]);
750 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 751 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 752 }
753 }
754 if (ugeth->p_exf_glbl_param) {
755 ugeth_info("EXF global param:");
756 ugeth_info("Base address: 0x%08x",
757 (u32) ugeth->p_exf_glbl_param);
758 mem_disp((u8 *) ugeth->p_exf_glbl_param,
759 sizeof(*ugeth->p_exf_glbl_param));
760 }
761 if (ugeth->p_tx_glbl_pram) {
762 ugeth_info("TX global param:");
763 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
764 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
765 (u32) & ugeth->p_tx_glbl_pram->temoder,
766 in_be16(&ugeth->p_tx_glbl_pram->temoder));
767 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
768 (u32) & ugeth->p_tx_glbl_pram->sqptr,
769 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
770 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
771 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
772 in_be32(&ugeth->p_tx_glbl_pram->
773 schedulerbasepointer));
774 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
775 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
776 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
777 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
778 (u32) & ugeth->p_tx_glbl_pram->tstate,
779 in_be32(&ugeth->p_tx_glbl_pram->tstate));
780 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
781 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
782 ugeth->p_tx_glbl_pram->iphoffset[0]);
783 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
784 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
785 ugeth->p_tx_glbl_pram->iphoffset[1]);
786 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
787 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
788 ugeth->p_tx_glbl_pram->iphoffset[2]);
789 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
790 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
791 ugeth->p_tx_glbl_pram->iphoffset[3]);
792 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
793 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
794 ugeth->p_tx_glbl_pram->iphoffset[4]);
795 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
796 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
797 ugeth->p_tx_glbl_pram->iphoffset[5]);
798 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
799 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
800 ugeth->p_tx_glbl_pram->iphoffset[6]);
801 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
802 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
803 ugeth->p_tx_glbl_pram->iphoffset[7]);
804 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
805 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
806 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
807 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
808 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
809 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
810 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
811 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
812 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
813 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
814 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
815 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
816 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
817 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
818 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
819 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
820 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
821 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
822 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
823 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
824 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
825 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
826 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
827 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
828 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
829 (u32) & ugeth->p_tx_glbl_pram->tqptr,
830 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
831 }
832 if (ugeth->p_rx_glbl_pram) {
833 ugeth_info("RX global param:");
834 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
835 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
836 (u32) & ugeth->p_rx_glbl_pram->remoder,
837 in_be32(&ugeth->p_rx_glbl_pram->remoder));
838 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
839 (u32) & ugeth->p_rx_glbl_pram->rqptr,
840 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
841 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
842 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
843 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
844 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
845 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
846 ugeth->p_rx_glbl_pram->rxgstpack);
847 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
848 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
849 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
850 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
851 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
852 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
853 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
854 (u32) & ugeth->p_rx_glbl_pram->rstate,
855 ugeth->p_rx_glbl_pram->rstate);
856 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
857 (u32) & ugeth->p_rx_glbl_pram->mrblr,
858 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
859 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
860 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
861 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
862 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
863 (u32) & ugeth->p_rx_glbl_pram->mflr,
864 in_be16(&ugeth->p_rx_glbl_pram->mflr));
865 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
866 (u32) & ugeth->p_rx_glbl_pram->minflr,
867 in_be16(&ugeth->p_rx_glbl_pram->minflr));
868 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
869 (u32) & ugeth->p_rx_glbl_pram->maxd1,
870 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
871 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
872 (u32) & ugeth->p_rx_glbl_pram->maxd2,
873 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
874 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
875 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
876 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
877 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
878 (u32) & ugeth->p_rx_glbl_pram->l2qt,
879 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
880 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
881 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
882 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
883 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
884 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
885 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
886 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
887 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
888 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
889 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
890 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
891 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
892 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
893 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
894 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
895 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
896 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
897 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
898 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
899 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
900 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
901 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
902 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
903 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
904 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
905 (u32) & ugeth->p_rx_glbl_pram->vlantype,
906 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
907 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
908 (u32) & ugeth->p_rx_glbl_pram->vlantci,
909 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
910 for (i = 0; i < 64; i++)
911 ugeth_info
912 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
913 i,
914 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
915 ugeth->p_rx_glbl_pram->addressfiltering[i]);
916 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
917 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
918 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
919 }
920 if (ugeth->p_send_q_mem_reg) {
921 ugeth_info("Send Q memory registers:");
922 ugeth_info("Base address: 0x%08x",
923 (u32) ugeth->p_send_q_mem_reg);
924 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
925 ugeth_info("SQQD[%d]:", i);
926 ugeth_info("Base address: 0x%08x",
927 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
928 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 929 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 930 }
931 }
932 if (ugeth->p_scheduler) {
933 ugeth_info("Scheduler:");
934 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
935 mem_disp((u8 *) ugeth->p_scheduler,
936 sizeof(*ugeth->p_scheduler));
937 }
938 if (ugeth->p_tx_fw_statistics_pram) {
939 ugeth_info("TX FW statistics pram:");
940 ugeth_info("Base address: 0x%08x",
941 (u32) ugeth->p_tx_fw_statistics_pram);
942 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
943 sizeof(*ugeth->p_tx_fw_statistics_pram));
944 }
945 if (ugeth->p_rx_fw_statistics_pram) {
946 ugeth_info("RX FW statistics pram:");
947 ugeth_info("Base address: 0x%08x",
948 (u32) ugeth->p_rx_fw_statistics_pram);
949 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
950 sizeof(*ugeth->p_rx_fw_statistics_pram));
951 }
952 if (ugeth->p_rx_irq_coalescing_tbl) {
953 ugeth_info("RX IRQ coalescing tables:");
954 ugeth_info("Base address: 0x%08x",
955 (u32) ugeth->p_rx_irq_coalescing_tbl);
956 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
957 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
958 ugeth_info("Base address: 0x%08x",
959 (u32) & ugeth->p_rx_irq_coalescing_tbl->
960 coalescingentry[i]);
961 ugeth_info
962 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
963 (u32) & ugeth->p_rx_irq_coalescing_tbl->
964 coalescingentry[i].interruptcoalescingmaxvalue,
965 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
966 coalescingentry[i].
967 interruptcoalescingmaxvalue));
968 ugeth_info
969 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
970 (u32) & ugeth->p_rx_irq_coalescing_tbl->
971 coalescingentry[i].interruptcoalescingcounter,
972 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
973 coalescingentry[i].
974 interruptcoalescingcounter));
975 }
976 }
977 if (ugeth->p_rx_bd_qs_tbl) {
978 ugeth_info("RX BD QS tables:");
979 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
980 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
981 ugeth_info("RX BD QS table[%d]:", i);
982 ugeth_info("Base address: 0x%08x",
983 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
984 ugeth_info
985 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
986 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
987 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
988 ugeth_info
989 ("bdptr : addr - 0x%08x, val - 0x%08x",
990 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
991 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
992 ugeth_info
993 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
994 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
995 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
996 externalbdbaseptr));
997 ugeth_info
998 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
999 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1000 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1001 ugeth_info("ucode RX Prefetched BDs:");
1002 ugeth_info("Base address: 0x%08x",
1003 (u32)
1004 qe_muram_addr(in_be32
1005 (&ugeth->p_rx_bd_qs_tbl[i].
1006 bdbaseptr)));
1007 mem_disp((u8 *)
1008 qe_muram_addr(in_be32
1009 (&ugeth->p_rx_bd_qs_tbl[i].
1010 bdbaseptr)),
18a8e864 1011 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1012 }
1013 }
1014 if (ugeth->p_init_enet_param_shadow) {
1015 int size;
1016 ugeth_info("Init enet param shadow:");
1017 ugeth_info("Base address: 0x%08x",
1018 (u32) ugeth->p_init_enet_param_shadow);
1019 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1020 sizeof(*ugeth->p_init_enet_param_shadow));
1021
18a8e864 1022 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1023 if (ugeth->ug_info->rxExtendedFiltering) {
1024 size +=
1025 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1026 if (ugeth->ug_info->largestexternallookupkeysize ==
1027 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1028 size +=
1029 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1030 if (ugeth->ug_info->largestexternallookupkeysize ==
1031 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1032 size +=
1033 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1034 }
1035
1036 dump_init_enet_entries(ugeth,
1037 &(ugeth->p_init_enet_param_shadow->
1038 txthread[0]),
1039 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1040 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1041 ugeth->ug_info->riscTx, 0);
1042 dump_init_enet_entries(ugeth,
1043 &(ugeth->p_init_enet_param_shadow->
1044 rxthread[0]),
1045 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1046 ugeth->ug_info->riscRx, 1);
1047 }
1048}
1049#endif /* DEBUG */
1050
6fee40e9
AF		 1051static void init_default_reg_vals(u32 __iomem *upsmr_register,
1052 u32 __iomem *maccfg1_register,
1053 u32 __iomem *maccfg2_register)
ce973b14
LY		 1054{
1055 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1056 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1057 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1058}
1059
1060static int init_half_duplex_params(int alt_beb,
1061 int back_pressure_no_backoff,
1062 int no_backoff,
1063 int excess_defer,
1064 u8 alt_beb_truncation,
1065 u8 max_retransmissions,
1066 u8 collision_window,
6fee40e9 1067 u32 __iomem *hafdup_register)
ce973b14
LY		 1068{
1069 u32 value = 0;
1070
1071 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1072 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1073 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1074 return -EINVAL;
1075
1076 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1077
1078 if (alt_beb)
1079 value |= HALFDUP_ALT_BEB;
1080 if (back_pressure_no_backoff)
1081 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1082 if (no_backoff)
1083 value |= HALFDUP_NO_BACKOFF;
1084 if (excess_defer)
1085 value |= HALFDUP_EXCESSIVE_DEFER;
1086
1087 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1088
1089 value |= collision_window;
1090
1091 out_be32(hafdup_register, value);
1092 return 0;
1093}
1094
1095static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1096 u8 non_btb_ipg,
1097 u8 min_ifg,
1098 u8 btb_ipg,
6fee40e9 1099 u32 __iomem *ipgifg_register)
ce973b14
LY		 1100{
1101 u32 value = 0;
1102
1103 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1104 IPG part 2 */
1105 if (non_btb_cs_ipg > non_btb_ipg)
1106 return -EINVAL;
1107
1108 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1109 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1110 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1111 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1112 return -EINVAL;
1113
1114 value |=
1115 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1116 IPGIFG_NBTB_CS_IPG_MASK);
1117 value |=
1118 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1119 IPGIFG_NBTB_IPG_MASK);
1120 value |=
1121 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1122 IPGIFG_MIN_IFG_MASK);
1123 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1124
1125 out_be32(ipgifg_register, value);
1126 return 0;
1127}
1128
ac421852 1129int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1130 int rx_flow_control_enable,
1131 int tx_flow_control_enable,
1132 u16 pause_period,
1133 u16 extension_field,
6fee40e9
AF		 1134 u32 __iomem *upsmr_register,
1135 u32 __iomem *uempr_register,
1136 u32 __iomem *maccfg1_register)
ce973b14
LY		 1137{
1138 u32 value = 0;
1139
1140 /* Set UEMPR register */
1141 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1142 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1143 out_be32(uempr_register, value);
1144
1145 /* Set UPSMR register */
3bc53427 1146 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1147
1148 value = in_be32(maccfg1_register);
1149 if (rx_flow_control_enable)
1150 value |= MACCFG1_FLOW_RX;
1151 if (tx_flow_control_enable)
1152 value |= MACCFG1_FLOW_TX;
1153 out_be32(maccfg1_register, value);
1154
1155 return 0;
1156}
1157
1158static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1159 int auto_zero_hardware_statistics,
6fee40e9
AF		 1160 u32 __iomem *upsmr_register,
1161 u16 __iomem *uescr_register)
ce973b14 1162{
ce973b14 1163 u16 uescr_value = 0;
3bc53427 1164
ce973b14 1165 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1166 if (enable_hardware_statistics)
1167 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1168
1169 /* Clear hardware statistics counters */
1170 uescr_value = in_be16(uescr_register);
1171 uescr_value |= UESCR_CLRCNT;
1172 /* Automatically zero hardware statistics counters on read,
1173 if requested */
1174 if (auto_zero_hardware_statistics)
1175 uescr_value |= UESCR_AUTOZ;
1176 out_be16(uescr_register, uescr_value);
1177
1178 return 0;
1179}
1180
1181static int init_firmware_statistics_gathering_mode(int
1182 enable_tx_firmware_statistics,
1183 int enable_rx_firmware_statistics,
6fee40e9 1184 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1185 u32 tx_firmware_statistics_structure_address,
6fee40e9 1186 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1187 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1188 u16 __iomem *temoder_register,
1189 u32 __iomem *remoder_register)
ce973b14
LY		 1190{
1191 /* Note: this function does not check if */
1192 /* the parameters it receives are NULL */
ce973b14
LY		 1193
1194 if (enable_tx_firmware_statistics) {
1195 out_be32(tx_rmon_base_ptr,
1196 tx_firmware_statistics_structure_address);
3bc53427 1197 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1198 }
1199
1200 if (enable_rx_firmware_statistics) {
1201 out_be32(rx_rmon_base_ptr,
1202 rx_firmware_statistics_structure_address);
3bc53427 1203 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1204 }
1205
1206 return 0;
1207}
1208
1209static int init_mac_station_addr_regs(u8 address_byte_0,
1210 u8 address_byte_1,
1211 u8 address_byte_2,
1212 u8 address_byte_3,
1213 u8 address_byte_4,
1214 u8 address_byte_5,
6fee40e9
AF		 1215 u32 __iomem *macstnaddr1_register,
1216 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1217{
1218 u32 value = 0;
1219
1220 /* Example: for a station address of 0x12345678ABCD, */
1221 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1222
1223 /* MACSTNADDR1 Register: */
1224
1225 /* 0 7 8 15 */
1226 /* station address byte 5 station address byte 4 */
1227 /* 16 23 24 31 */
1228 /* station address byte 3 station address byte 2 */
1229 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1230 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1231 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1232 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1233
1234 out_be32(macstnaddr1_register, value);
1235
1236 /* MACSTNADDR2 Register: */
1237
1238 /* 0 7 8 15 */
1239 /* station address byte 1 station address byte 0 */
1240 /* 16 23 24 31 */
1241 /* reserved reserved */
1242 value = 0;
1243 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1244 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1245
1246 out_be32(macstnaddr2_register, value);
1247
1248 return 0;
1249}
1250
ce973b14 1251static int init_check_frame_length_mode(int length_check,
6fee40e9 1252 u32 __iomem *maccfg2_register)
ce973b14
LY		 1253{
1254 u32 value = 0;
1255
1256 value = in_be32(maccfg2_register);
1257
1258 if (length_check)
1259 value |= MACCFG2_LC;
1260 else
1261 value &= ~MACCFG2_LC;
1262
1263 out_be32(maccfg2_register, value);
1264 return 0;
1265}
1266
1267static int init_preamble_length(u8 preamble_length,
6fee40e9 1268 u32 __iomem *maccfg2_register)
ce973b14 1269{
ce973b14
LY		 1270 if ((preamble_length < 3) || (preamble_length > 7))
1271 return -EINVAL;
1272
3bc53427
TT		 1273 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1274 preamble_length << MACCFG2_PREL_SHIFT);
1275
ce973b14
LY		 1276 return 0;
1277}
1278
ce973b14
LY		 1279static int init_rx_parameters(int reject_broadcast,
1280 int receive_short_frames,
6fee40e9 1281 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1282{
1283 u32 value = 0;
1284
1285 value = in_be32(upsmr_register);
1286
1287 if (reject_broadcast)
3bc53427 1288 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1289 else
3bc53427 1290 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1291
1292 if (receive_short_frames)
3bc53427 1293 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1294 else
3bc53427 1295 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1296
1297 if (promiscuous)
3bc53427 1298 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1299 else
3bc53427 1300 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1301
1302 out_be32(upsmr_register, value);
1303
1304 return 0;
1305}
1306
1307static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1308 u16 __iomem *mrblr_register)
ce973b14
LY		 1309{
1310 /* max_rx_buf_len value must be a multiple of 128 */
8e95a202
JP		 1311 if ((max_rx_buf_len == 0) ||
1312 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
ce973b14
LY		 1313 return -EINVAL;
1314
1315 out_be16(mrblr_register, max_rx_buf_len);
1316 return 0;
1317}
1318
1319static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1320 u16 __iomem *minflr_register,
1321 u16 __iomem *mrblr_register)
ce973b14
LY		 1322{
1323 u16 mrblr_value = 0;
1324
1325 mrblr_value = in_be16(mrblr_register);
1326 if (min_frame_length >= (mrblr_value - 4))
1327 return -EINVAL;
1328
1329 out_be16(minflr_register, min_frame_length);
1330 return 0;
1331}
1332
18a8e864 1333static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1334{
18a8e864 1335 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1336 struct ucc_geth __iomem *ug_regs;
1337 struct ucc_fast __iomem *uf_regs;
728de4c9 1338 int ret_val;
81abb43a 1339 u32 upsmr, maccfg2;
ce973b14
LY		 1340 u16 value;
1341
b39d66a8 1342 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1343
1344 ug_info = ugeth->ug_info;
1345 ug_regs = ugeth->ug_regs;
1346 uf_regs = ugeth->uccf->uf_regs;
1347
ce973b14
LY		 1348 /* Set MACCFG2 */
1349 maccfg2 = in_be32(&ug_regs->maccfg2);
1350 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1351 if ((ugeth->max_speed == SPEED_10) ||
1352 (ugeth->max_speed == SPEED_100))
ce973b14 1353 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1354 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1355 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1356 maccfg2 |= ug_info->padAndCrc;
1357 out_be32(&ug_regs->maccfg2, maccfg2);
1358
1359 /* Set UPSMR */
1360 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1361 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1362 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1363 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1367 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1368 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1369 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1370 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1371 switch (ugeth->max_speed) {
1372 case SPEED_10:
3bc53427 1373 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1374 /* FALLTHROUGH */
1375 case SPEED_100:
1376 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1377 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1378 }
1379 }
1380 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1381 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1382 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1383 }
047584ce
HW		 1384 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1385 upsmr |= UCC_GETH_UPSMR_SGMM;
1386
ce973b14
LY		 1387 out_be32(&uf_regs->upsmr, upsmr);
1388
ce973b14
LY		 1389 /* Disable autonegotiation in tbi mode, because by default it
1390 comes up in autonegotiation mode. */
1391 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1392 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1393 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
81abb43a
LYB		 1394 struct ucc_geth_info *ug_info = ugeth->ug_info;
1395 struct phy_device *tbiphy;
1396
1397 if (!ug_info->tbi_node)
1398 ugeth_warn("TBI mode requires that the device "
1399 "tree specify a tbi-handle\n");
1400
1401 tbiphy = of_phy_find_device(ug_info->tbi_node);
1402 if (!tbiphy)
1403 ugeth_warn("Could not get TBI device\n");
1404
1405 value = phy_read(tbiphy, ENET_TBI_MII_CR);
ce973b14 1406 value &= ~0x1000; /* Turn off autonegotiation */
81abb43a 1407 phy_write(tbiphy, ENET_TBI_MII_CR, value);
ce973b14
LY		 1408 }
1409
1410 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1411
1412 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1413 if (ret_val != 0) {
890de95e
LY		 1414 if (netif_msg_probe(ugeth))
1415 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1416 __func__);
ce973b14
LY		 1417 return ret_val;
1418 }
1419
1420 return 0;
1421}
1422
7de8ee78
AV		 1423static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1424{
1425 struct ucc_fast_private *uccf;
1426 u32 cecr_subblock;
1427 u32 temp;
1428 int i = 10;
1429
1430 uccf = ugeth->uccf;
1431
1432 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1433 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1434 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1435
1436 /* Issue host command */
1437 cecr_subblock =
1438 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1439 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1440 QE_CR_PROTOCOL_ETHERNET, 0);
1441
1442 /* Wait for command to complete */
1443 do {
1444 msleep(10);
1445 temp = in_be32(uccf->p_ucce);
1446 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1447
1448 uccf->stopped_tx = 1;
1449
1450 return 0;
1451}
1452
1453static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1454{
1455 struct ucc_fast_private *uccf;
1456 u32 cecr_subblock;
1457 u8 temp;
1458 int i = 10;
1459
1460 uccf = ugeth->uccf;
1461
1462 /* Clear acknowledge bit */
1463 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1464 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1465 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1466
1467 /* Keep issuing command and checking acknowledge bit until
1468 it is asserted, according to spec */
1469 do {
1470 /* Issue host command */
1471 cecr_subblock =
1472 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1473 ucc_num);
1474 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1475 QE_CR_PROTOCOL_ETHERNET, 0);
1476 msleep(10);
1477 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1478 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1479
1480 uccf->stopped_rx = 1;
1481
1482 return 0;
1483}
1484
1485static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1486{
1487 struct ucc_fast_private *uccf;
1488 u32 cecr_subblock;
1489
1490 uccf = ugeth->uccf;
1491
1492 cecr_subblock =
1493 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1494 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1495 uccf->stopped_tx = 0;
1496
1497 return 0;
1498}
1499
1500static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1501{
1502 struct ucc_fast_private *uccf;
1503 u32 cecr_subblock;
1504
1505 uccf = ugeth->uccf;
1506
1507 cecr_subblock =
1508 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1509 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1510 0);
1511 uccf->stopped_rx = 0;
1512
1513 return 0;
1514}
1515
1516static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1517{
1518 struct ucc_fast_private *uccf;
1519 int enabled_tx, enabled_rx;
1520
1521 uccf = ugeth->uccf;
1522
1523 /* check if the UCC number is in range. */
1524 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1525 if (netif_msg_probe(ugeth))
1526 ugeth_err("%s: ucc_num out of range.", __func__);
1527 return -EINVAL;
1528 }
1529
1530 enabled_tx = uccf->enabled_tx;
1531 enabled_rx = uccf->enabled_rx;
1532
1533 /* Get Tx and Rx going again, in case this channel was actively
1534 disabled. */
1535 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1536 ugeth_restart_tx(ugeth);
1537 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1538 ugeth_restart_rx(ugeth);
1539
1540 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1541
1542 return 0;
1543
1544}
1545
1546static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1547{
1548 struct ucc_fast_private *uccf;
1549
1550 uccf = ugeth->uccf;
1551
1552 /* check if the UCC number is in range. */
1553 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1554 if (netif_msg_probe(ugeth))
1555 ugeth_err("%s: ucc_num out of range.", __func__);
1556 return -EINVAL;
1557 }
1558
1559 /* Stop any transmissions */
1560 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1561 ugeth_graceful_stop_tx(ugeth);
1562
1563 /* Stop any receptions */
1564 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1565 ugeth_graceful_stop_rx(ugeth);
1566
1567 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1568
1569 return 0;
1570}
1571
864fdf88
AV		 1572static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1573{
08b5e1c9
AV		 1574 /* Prevent any further xmits, plus detach the device. */
1575 netif_device_detach(ugeth->ndev);
1576
1577 /* Wait for any current xmits to finish. */
864fdf88
AV		 1578 netif_tx_disable(ugeth->ndev);
1579
1580 /* Disable the interrupt to avoid NAPI rescheduling. */
1581 disable_irq(ugeth->ug_info->uf_info.irq);
1582
1583 /* Stop NAPI, and possibly wait for its completion. */
1584 napi_disable(&ugeth->napi);
1585}
1586
1587static void ugeth_activate(struct ucc_geth_private *ugeth)
1588{
1589 napi_enable(&ugeth->napi);
1590 enable_irq(ugeth->ug_info->uf_info.irq);
08b5e1c9 1591 netif_device_attach(ugeth->ndev);
864fdf88
AV		 1592}
1593
ce973b14
LY		 1594/* Called every time the controller might need to be made
1595 * aware of new link state. The PHY code conveys this
1596 * information through variables in the ugeth structure, and this
1597 * function converts those variables into the appropriate
1598 * register values, and can bring down the device if needed.
1599 */
728de4c9 1600
ce973b14
LY		 1601static void adjust_link(struct net_device *dev)
1602{
18a8e864 1603 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1604 struct ucc_geth __iomem *ug_regs;
1605 struct ucc_fast __iomem *uf_regs;
728de4c9 1606 struct phy_device *phydev = ugeth->phydev;
728de4c9 1607 int new_state = 0;
ce973b14
LY		 1608
1609 ug_regs = ugeth->ug_regs;
728de4c9 1610 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1611
728de4c9
KP		 1612 if (phydev->link) {
1613 u32 tempval = in_be32(&ug_regs->maccfg2);
1614 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1615 /* Now we make sure that we can be in full duplex mode.
1616 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1617 if (phydev->duplex != ugeth->oldduplex) {
1618 new_state = 1;
1619 if (!(phydev->duplex))
ce973b14 1620 tempval &= ~(MACCFG2_FDX);
728de4c9 1621 else
ce973b14 1622 tempval |= MACCFG2_FDX;
728de4c9 1623 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1624 }
1625
728de4c9
KP		 1626 if (phydev->speed != ugeth->oldspeed) {
1627 new_state = 1;
1628 switch (phydev->speed) {
1629 case SPEED_1000:
1630 tempval = ((tempval &
1631 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1632 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1633 break;
728de4c9
KP		 1634 case SPEED_100:
1635 case SPEED_10:
1636 tempval = ((tempval &
1637 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1638 MACCFG2_INTERFACE_MODE_NIBBLE);
1639 /* if reduced mode, re-set UPSMR.R10M */
1640 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1641 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1642 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1643 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1644 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1645 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1646 if (phydev->speed == SPEED_10)
3bc53427 1647 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1648 else
3bc53427 1649 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1650 }
ce973b14
LY		 1651 break;
1652 default:
728de4c9
KP		 1653 if (netif_msg_link(ugeth))
1654 ugeth_warn(
1655 "%s: Ack! Speed (%d) is not 10/100/1000!",
1656 dev->name, phydev->speed);
ce973b14
LY		 1657 break;
1658 }
728de4c9 1659 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1660 }
1661
1662 if (!ugeth->oldlink) {
728de4c9 1663 new_state = 1;
ce973b14 1664 ugeth->oldlink = 1;
ce973b14 1665 }
08fafd84
AV		 1666
1667 if (new_state) {
1668 /*
1669 * To change the MAC configuration we need to disable
1670 * the controller. To do so, we have to either grab
1671 * ugeth->lock, which is a bad idea since 'graceful
1672 * stop' commands might take quite a while, or we can
1673 * quiesce driver's activity.
1674 */
1675 ugeth_quiesce(ugeth);
1676 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1677
1678 out_be32(&ug_regs->maccfg2, tempval);
1679 out_be32(&uf_regs->upsmr, upsmr);
1680
1681 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1682 ugeth_activate(ugeth);
1683 }
728de4c9
KP		 1684 } else if (ugeth->oldlink) {
1685 new_state = 1;
ce973b14
LY		 1686 ugeth->oldlink = 0;
1687 ugeth->oldspeed = 0;
1688 ugeth->oldduplex = -1;
ce973b14 1689 }
728de4c9
KP		 1690
1691 if (new_state && netif_msg_link(ugeth))
1692 phy_print_status(phydev);
ce973b14
LY		 1693}
1694
fb1001f3
HW		 1695/* Initialize TBI PHY interface for communicating with the
1696 * SERDES lynx PHY on the chip. We communicate with this PHY
1697 * through the MDIO bus on each controller, treating it as a
1698 * "normal" PHY at the address found in the UTBIPA register. We assume
1699 * that the UTBIPA register is valid. Either the MDIO bus code will set
1700 * it to a value that doesn't conflict with other PHYs on the bus, or the
1701 * value doesn't matter, as there are no other PHYs on the bus.
1702 */
1703static void uec_configure_serdes(struct net_device *dev)
1704{
1705 struct ucc_geth_private *ugeth = netdev_priv(dev);
1706 struct ucc_geth_info *ug_info = ugeth->ug_info;
1707 struct phy_device *tbiphy;
1708
1709 if (!ug_info->tbi_node) {
1710 dev_warn(&dev->dev, "SGMII mode requires that the device "
1711 "tree specify a tbi-handle\n");
1712 return;
1713 }
1714
1715 tbiphy = of_phy_find_device(ug_info->tbi_node);
1716 if (!tbiphy) {
1717 dev_err(&dev->dev, "error: Could not get TBI device\n");
1718 return;
1719 }
1720
1721 /*
1722 * If the link is already up, we must already be ok, and don't need to
1723 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1724 * everything for us? Resetting it takes the link down and requires
1725 * several seconds for it to come back.
1726 */
1727 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1728 return;
1729
1730 /* Single clk mode, mii mode off(for serdes communication) */
1731 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1732
1733 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1734
1735 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1736}
1737
ce973b14
LY		 1738/* Configure the PHY for dev.
1739 * returns 0 if success. -1 if failure
1740 */
1741static int init_phy(struct net_device *dev)
1742{
728de4c9 1743 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1744 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1745 struct phy_device *phydev;
ce973b14 1746
728de4c9
KP		 1747 priv->oldlink = 0;
1748 priv->oldspeed = 0;
1749 priv->oldduplex = -1;
ce973b14 1750
0b9da337
GL		 1751 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1752 priv->phy_interface);
3104a6ff
AV		 1753 if (!phydev)
1754 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1755 priv->phy_interface);
0b9da337 1756 if (!phydev) {
3104a6ff 1757 dev_err(&dev->dev, "Could not attach to PHY\n");
0b9da337 1758 return -ENODEV;
ce973b14
LY		 1759 }
1760
047584ce
HW		 1761 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1762 uec_configure_serdes(dev);
1763
728de4c9 1764 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1765 ADVERTISED_10baseT_Full |
1766 ADVERTISED_100baseT_Half |
728de4c9 1767 ADVERTISED_100baseT_Full);
ce973b14 1768
728de4c9
KP		 1769 if (priv->max_speed == SPEED_1000)
1770 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1771
728de4c9 1772 phydev->advertising = phydev->supported;
68dc44af 1773
728de4c9 1774 priv->phydev = phydev;
ce973b14
LY		 1775
1776 return 0;
ce973b14
LY		 1777}
1778
18a8e864 1779static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1780{
1781#ifdef DEBUG
1782 ucc_fast_dump_regs(ugeth->uccf);
1783 dump_regs(ugeth);
1784 dump_bds(ugeth);
1785#endif
1786}
1787
18a8e864 1788static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1789 ugeth,
18a8e864 1790 enum enet_addr_type
ce973b14
LY		 1791 enet_addr_type)
1792{
6fee40e9 1793 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1794 struct ucc_fast_private *uccf;
1795 enum comm_dir comm_dir;
ce973b14
LY		 1796 struct list_head *p_lh;
1797 u16 i, num;
6fee40e9
AF		 1798 u32 __iomem *addr_h;
1799 u32 __iomem *addr_l;
ce973b14
LY		 1800 u8 *p_counter;
1801
1802 uccf = ugeth->uccf;
1803
1804 p_82xx_addr_filt =
6fee40e9
AF		 1805 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1806 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1807
1808 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1809 addr_h = &(p_82xx_addr_filt->gaddr_h);
1810 addr_l = &(p_82xx_addr_filt->gaddr_l);
1811 p_lh = &ugeth->group_hash_q;
1812 p_counter = &(ugeth->numGroupAddrInHash);
1813 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1814 addr_h = &(p_82xx_addr_filt->iaddr_h);
1815 addr_l = &(p_82xx_addr_filt->iaddr_l);
1816 p_lh = &ugeth->ind_hash_q;
1817 p_counter = &(ugeth->numIndAddrInHash);
1818 } else
1819 return -EINVAL;
1820
1821 comm_dir = 0;
1822 if (uccf->enabled_tx)
1823 comm_dir |= COMM_DIR_TX;
1824 if (uccf->enabled_rx)
1825 comm_dir |= COMM_DIR_RX;
1826 if (comm_dir)
1827 ugeth_disable(ugeth, comm_dir);
1828
1829 /* Clear the hash table. */
1830 out_be32(addr_h, 0x00000000);
1831 out_be32(addr_l, 0x00000000);
1832
1833 if (!p_lh)
1834 return 0;
1835
1836 num = *p_counter;
1837
1838 /* Delete all remaining CQ elements */
1839 for (i = 0; i < num; i++)
1840 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1841
1842 *p_counter = 0;
1843
1844 if (comm_dir)
1845 ugeth_enable(ugeth, comm_dir);
1846
1847 return 0;
1848}
1849
18a8e864 1850static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1851 u8 paddr_num)
1852{
1853 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1854 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1855}
1856
18a8e864 1857static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 1858{
1859 u16 i, j;
6fee40e9 1860 u8 __iomem *bd;
ce973b14
LY		 1861
1862 if (!ugeth)
1863 return;
1864
80a9fad8 1865 if (ugeth->uccf) {
ce973b14 1866 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1867 ugeth->uccf = NULL;
1868 }
ce973b14
LY		 1869
1870 if (ugeth->p_thread_data_tx) {
1871 qe_muram_free(ugeth->thread_dat_tx_offset);
1872 ugeth->p_thread_data_tx = NULL;
1873 }
1874 if (ugeth->p_thread_data_rx) {
1875 qe_muram_free(ugeth->thread_dat_rx_offset);
1876 ugeth->p_thread_data_rx = NULL;
1877 }
1878 if (ugeth->p_exf_glbl_param) {
1879 qe_muram_free(ugeth->exf_glbl_param_offset);
1880 ugeth->p_exf_glbl_param = NULL;
1881 }
1882 if (ugeth->p_rx_glbl_pram) {
1883 qe_muram_free(ugeth->rx_glbl_pram_offset);
1884 ugeth->p_rx_glbl_pram = NULL;
1885 }
1886 if (ugeth->p_tx_glbl_pram) {
1887 qe_muram_free(ugeth->tx_glbl_pram_offset);
1888 ugeth->p_tx_glbl_pram = NULL;
1889 }
1890 if (ugeth->p_send_q_mem_reg) {
1891 qe_muram_free(ugeth->send_q_mem_reg_offset);
1892 ugeth->p_send_q_mem_reg = NULL;
1893 }
1894 if (ugeth->p_scheduler) {
1895 qe_muram_free(ugeth->scheduler_offset);
1896 ugeth->p_scheduler = NULL;
1897 }
1898 if (ugeth->p_tx_fw_statistics_pram) {
1899 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1900 ugeth->p_tx_fw_statistics_pram = NULL;
1901 }
1902 if (ugeth->p_rx_fw_statistics_pram) {
1903 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1904 ugeth->p_rx_fw_statistics_pram = NULL;
1905 }
1906 if (ugeth->p_rx_irq_coalescing_tbl) {
1907 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1908 ugeth->p_rx_irq_coalescing_tbl = NULL;
1909 }
1910 if (ugeth->p_rx_bd_qs_tbl) {
1911 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1912 ugeth->p_rx_bd_qs_tbl = NULL;
1913 }
1914 if (ugeth->p_init_enet_param_shadow) {
1915 return_init_enet_entries(ugeth,
1916 &(ugeth->p_init_enet_param_shadow->
1917 rxthread[0]),
1918 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1919 ugeth->ug_info->riscRx, 1);
1920 return_init_enet_entries(ugeth,
1921 &(ugeth->p_init_enet_param_shadow->
1922 txthread[0]),
1923 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1924 ugeth->ug_info->riscTx, 0);
1925 kfree(ugeth->p_init_enet_param_shadow);
1926 ugeth->p_init_enet_param_shadow = NULL;
1927 }
1928 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1929 bd = ugeth->p_tx_bd_ring[i];
3a8205ea
NIP		 1930 if (!bd)
1931 continue;
ce973b14
LY		 1932 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1933 if (ugeth->tx_skbuff[i][j]) {
da1aa63e 1934 dma_unmap_single(ugeth->dev,
6fee40e9
AF		 1935 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1936 (in_be32((u32 __iomem *)bd) &
ce973b14
LY		 1937 BD_LENGTH_MASK),
1938 DMA_TO_DEVICE);
1939 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1940 ugeth->tx_skbuff[i][j] = NULL;
1941 }
1942 }
1943
1944 kfree(ugeth->tx_skbuff[i]);
1945
1946 if (ugeth->p_tx_bd_ring[i]) {
1947 if (ugeth->ug_info->uf_info.bd_mem_part ==
1948 MEM_PART_SYSTEM)
1949 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1950 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1951 MEM_PART_MURAM)
1952 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1953 ugeth->p_tx_bd_ring[i] = NULL;
1954 }
1955 }
1956 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1957 if (ugeth->p_rx_bd_ring[i]) {
1958 /* Return existing data buffers in ring */
1959 bd = ugeth->p_rx_bd_ring[i];
1960 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1961 if (ugeth->rx_skbuff[i][j]) {
da1aa63e 1962 dma_unmap_single(ugeth->dev,
6fee40e9 1963 in_be32(&((struct qe_bd __iomem *)bd)->buf),
18a8e864
LY		 1964 ugeth->ug_info->
1965 uf_info.max_rx_buf_length +
1966 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1967 DMA_FROM_DEVICE);
1968 dev_kfree_skb_any(
1969 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 1970 ugeth->rx_skbuff[i][j] = NULL;
1971 }
18a8e864 1972 bd += sizeof(struct qe_bd);
ce973b14
LY		 1973 }
1974
1975 kfree(ugeth->rx_skbuff[i]);
1976
1977 if (ugeth->ug_info->uf_info.bd_mem_part ==
1978 MEM_PART_SYSTEM)
1979 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1980 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1981 MEM_PART_MURAM)
1982 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1983 ugeth->p_rx_bd_ring[i] = NULL;
1984 }
1985 }
1986 while (!list_empty(&ugeth->group_hash_q))
1987 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1988 (dequeue(&ugeth->group_hash_q)));
1989 while (!list_empty(&ugeth->ind_hash_q))
1990 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1991 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1992 if (ugeth->ug_regs) {
1993 iounmap(ugeth->ug_regs);
1994 ugeth->ug_regs = NULL;
1995 }
50f238fd
AV		 1996
1997 skb_queue_purge(&ugeth->rx_recycle);
ce973b14
LY		 1998}
1999
2000static void ucc_geth_set_multi(struct net_device *dev)
2001{
18a8e864 2002 struct ucc_geth_private *ugeth;
22bedad3 2003 struct netdev_hw_addr *ha;
6fee40e9
AF		 2004 struct ucc_fast __iomem *uf_regs;
2005 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 2006
2007 ugeth = netdev_priv(dev);
2008
2009 uf_regs = ugeth->uccf->uf_regs;
2010
2011 if (dev->flags & IFF_PROMISC) {
3bc53427 2012 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 2013 } else {
3bc53427 2014 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 2015
2016 p_82xx_addr_filt =
6fee40e9 2017 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2018 p_rx_glbl_pram->addressfiltering;
2019
2020 if (dev->flags & IFF_ALLMULTI) {
2021 /* Catch all multicast addresses, so set the
2022 * filter to all 1's.
2023 */
2024 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2025 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2026 } else {
2027 /* Clear filter and add the addresses in the list.
2028 */
2029 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2030 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2031
22bedad3 2032 netdev_for_each_mc_addr(ha, dev) {
ce973b14
LY		 2033 /* Ask CPM to run CRC and set bit in
2034 * filter mask.
2035 */
22bedad3 2036 hw_add_addr_in_hash(ugeth, ha->addr);
ce973b14
LY		 2037 }
2038 }
2039 }
2040}
2041
18a8e864 2042static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2043{
6fee40e9 2044 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2045 struct phy_device *phydev = ugeth->phydev;
ce973b14 2046
b39d66a8 2047 ugeth_vdbg("%s: IN", __func__);
ce973b14 2048
75e60474
JT		 2049 /*
2050 * Tell the kernel the link is down.
2051 * Must be done before disabling the controller
2052 * or deadlock may happen.
2053 */
2054 phy_stop(phydev);
2055
ce973b14
LY		 2056 /* Disable the controller */
2057 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2058
ce973b14 2059 /* Mask all interrupts */
c6f5047b 2060 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2061
2062 /* Clear all interrupts */
2063 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2064
2065 /* Disable Rx and Tx */
3bc53427 2066 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2067
ce973b14
LY		 2068 ucc_geth_memclean(ugeth);
2069}
2070
728de4c9 2071static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2072{
18a8e864
LY		 2073 struct ucc_geth_info *ug_info;
2074 struct ucc_fast_info *uf_info;
728de4c9 2075 int i;
ce973b14
LY		 2076
2077 ug_info = ugeth->ug_info;
2078 uf_info = &ug_info->uf_info;
2079
2080 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2081 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2082 if (netif_msg_probe(ugeth))
2083 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2084 __func__);
ce973b14
LY		 2085 return -EINVAL;
2086 }
2087
2088 /* Rx BD lengths */
2089 for (i = 0; i < ug_info->numQueuesRx; i++) {
2090 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2091 (ug_info->bdRingLenRx[i] %
2092 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2093 if (netif_msg_probe(ugeth))
2094 ugeth_err
2095 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2096 __func__);
ce973b14
LY		 2097 return -EINVAL;
2098 }
2099 }
2100
2101 /* Tx BD lengths */
2102 for (i = 0; i < ug_info->numQueuesTx; i++) {
2103 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2104 if (netif_msg_probe(ugeth))
2105 ugeth_err
2106 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2107 __func__);
ce973b14
LY		 2108 return -EINVAL;
2109 }
2110 }
2111
2112 /* mrblr */
2113 if ((uf_info->max_rx_buf_length == 0) ||
2114 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2115 if (netif_msg_probe(ugeth))
2116 ugeth_err
2117 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2118 __func__);
ce973b14
LY		 2119 return -EINVAL;
2120 }
2121
2122 /* num Tx queues */
2123 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2124 if (netif_msg_probe(ugeth))
b39d66a8 2125 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2126 return -EINVAL;
2127 }
2128
2129 /* num Rx queues */
2130 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2131 if (netif_msg_probe(ugeth))
b39d66a8 2132 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2133 return -EINVAL;
2134 }
2135
2136 /* l2qt */
2137 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2138 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2139 if (netif_msg_probe(ugeth))
2140 ugeth_err
2141 ("%s: VLAN priority table entry must not be"
2142 " larger than number of Rx queues.",
b39d66a8 2143 __func__);
ce973b14
LY		 2144 return -EINVAL;
2145 }
2146 }
2147
2148 /* l3qt */
2149 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2150 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2151 if (netif_msg_probe(ugeth))
2152 ugeth_err
2153 ("%s: IP priority table entry must not be"
2154 " larger than number of Rx queues.",
b39d66a8 2155 __func__);
ce973b14
LY		 2156 return -EINVAL;
2157 }
2158 }
2159
2160 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2161 if (netif_msg_probe(ugeth))
2162 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2163 __func__);
ce973b14
LY		 2164 return -EINVAL;
2165 }
2166
2167 if ((ug_info->numStationAddresses !=
8e95a202
JP		 2168 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2169 ug_info->rxExtendedFiltering) {
890de95e
LY		 2170 if (netif_msg_probe(ugeth))
2171 ugeth_err("%s: Number of station addresses greater than 1 "
2172 "not allowed in extended parsing mode.",
b39d66a8 2173 __func__);
ce973b14
LY		 2174 return -EINVAL;
2175 }
2176
2177 /* Generate uccm_mask for receive */
2178 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2179 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2180 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2181
2182 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2183 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2184 /* Initialize the general fast UCC block. */
728de4c9 2185 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2186 if (netif_msg_probe(ugeth))
b39d66a8 2187 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2188 return -ENOMEM;
2189 }
728de4c9 2190
345f8422
HW		 2191 /* read the number of risc engines, update the riscTx and riscRx
2192 * if there are 4 riscs in QE
2193 */
2194 if (qe_get_num_of_risc() == 4) {
2195 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2196 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2197 }
2198
3e73fc9a
AV		 2199 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2200 if (!ugeth->ug_regs) {
2201 if (netif_msg_probe(ugeth))
2202 ugeth_err("%s: Failed to ioremap regs.", __func__);
2203 return -ENOMEM;
2204 }
728de4c9 2205
50f238fd
AV		 2206 skb_queue_head_init(&ugeth->rx_recycle);
2207
728de4c9
KP		 2208 return 0;
2209}
2210
2211static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2212{
6fee40e9
AF		 2213 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2214 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2215 struct ucc_fast_private *uccf;
2216 struct ucc_geth_info *ug_info;
2217 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2218 struct ucc_fast __iomem *uf_regs;
2219 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2220 int ret_val = -EINVAL;
2221 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2222 u32 init_enet_pram_offset, cecr_subblock, command;
728de4c9
KP		 2223 u32 ifstat, i, j, size, l2qt, l3qt, length;
2224 u16 temoder = UCC_GETH_TEMODER_INIT;
2225 u16 test;
2226 u8 function_code = 0;
6fee40e9
AF		 2227 u8 __iomem *bd;
2228 u8 __iomem *endOfRing;
728de4c9
KP		 2229 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2230
b39d66a8 2231 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2232 uccf = ugeth->uccf;
2233 ug_info = ugeth->ug_info;
2234 uf_info = &ug_info->uf_info;
2235 uf_regs = uccf->uf_regs;
2236 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2237
2238 switch (ug_info->numThreadsRx) {
2239 case UCC_GETH_NUM_OF_THREADS_1:
2240 numThreadsRxNumerical = 1;
2241 break;
2242 case UCC_GETH_NUM_OF_THREADS_2:
2243 numThreadsRxNumerical = 2;
2244 break;
2245 case UCC_GETH_NUM_OF_THREADS_4:
2246 numThreadsRxNumerical = 4;
2247 break;
2248 case UCC_GETH_NUM_OF_THREADS_6:
2249 numThreadsRxNumerical = 6;
2250 break;
2251 case UCC_GETH_NUM_OF_THREADS_8:
2252 numThreadsRxNumerical = 8;
2253 break;
2254 default:
890de95e
LY		 2255 if (netif_msg_ifup(ugeth))
2256 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2257 __func__);
ce973b14
LY		 2258 return -EINVAL;
2259 break;
2260 }
2261
2262 switch (ug_info->numThreadsTx) {
2263 case UCC_GETH_NUM_OF_THREADS_1:
2264 numThreadsTxNumerical = 1;
2265 break;
2266 case UCC_GETH_NUM_OF_THREADS_2:
2267 numThreadsTxNumerical = 2;
2268 break;
2269 case UCC_GETH_NUM_OF_THREADS_4:
2270 numThreadsTxNumerical = 4;
2271 break;
2272 case UCC_GETH_NUM_OF_THREADS_6:
2273 numThreadsTxNumerical = 6;
2274 break;
2275 case UCC_GETH_NUM_OF_THREADS_8:
2276 numThreadsTxNumerical = 8;
2277 break;
2278 default:
890de95e
LY		 2279 if (netif_msg_ifup(ugeth))
2280 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2281 __func__);
ce973b14
LY		 2282 return -EINVAL;
2283 break;
2284 }
2285
2286 /* Calculate rx_extended_features */
2287 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2288 ug_info->ipAddressAlignment ||
2289 (ug_info->numStationAddresses !=
2290 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2291
2292 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
8e95a202
JP		 2293 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2294 (ug_info->vlanOperationNonTagged !=
2295 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
ce973b14 2296
ce973b14
LY		 2297 init_default_reg_vals(&uf_regs->upsmr,
2298 &ug_regs->maccfg1, &ug_regs->maccfg2);
2299
2300 /* Set UPSMR */
2301 /* For more details see the hardware spec. */
2302 init_rx_parameters(ug_info->bro,
2303 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2304
2305 /* We're going to ignore other registers for now, */
2306 /* except as needed to get up and running */
2307
2308 /* Set MACCFG1 */
2309 /* For more details see the hardware spec. */
2310 init_flow_control_params(ug_info->aufc,
2311 ug_info->receiveFlowControl,
ac421852 2312 ug_info->transmitFlowControl,
ce973b14
LY		 2313 ug_info->pausePeriod,
2314 ug_info->extensionField,
2315 &uf_regs->upsmr,
2316 &ug_regs->uempr, &ug_regs->maccfg1);
2317
3bc53427 2318 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2319
2320 /* Set IPGIFG */
2321 /* For more details see the hardware spec. */
2322 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2323 ug_info->nonBackToBackIfgPart2,
2324 ug_info->
2325 miminumInterFrameGapEnforcement,
2326 ug_info->backToBackInterFrameGap,
2327 &ug_regs->ipgifg);
2328 if (ret_val != 0) {
890de95e
LY		 2329 if (netif_msg_ifup(ugeth))
2330 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2331 __func__);
ce973b14
LY		 2332 return ret_val;
2333 }
2334
2335 /* Set HAFDUP */
2336 /* For more details see the hardware spec. */
2337 ret_val = init_half_duplex_params(ug_info->altBeb,
2338 ug_info->backPressureNoBackoff,
2339 ug_info->noBackoff,
2340 ug_info->excessDefer,
2341 ug_info->altBebTruncation,
2342 ug_info->maxRetransmission,
2343 ug_info->collisionWindow,
2344 &ug_regs->hafdup);
2345 if (ret_val != 0) {
890de95e
LY		 2346 if (netif_msg_ifup(ugeth))
2347 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2348 __func__);
ce973b14
LY		 2349 return ret_val;
2350 }
2351
2352 /* Set IFSTAT */
2353 /* For more details see the hardware spec. */
2354 /* Read only - resets upon read */
2355 ifstat = in_be32(&ug_regs->ifstat);
2356
2357 /* Clear UEMPR */
2358 /* For more details see the hardware spec. */
2359 out_be32(&ug_regs->uempr, 0);
2360
2361 /* Set UESCR */
2362 /* For more details see the hardware spec. */
2363 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2364 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2365 0, &uf_regs->upsmr, &ug_regs->uescr);
2366
2367 /* Allocate Tx bds */
2368 for (j = 0; j < ug_info->numQueuesTx; j++) {
2369 /* Allocate in multiple of
2370 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2371 according to spec */
18a8e864 2372 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2373 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2374 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2375 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2376 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2377 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2378 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2379 u32 align = 4;
2380 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2381 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2382 ugeth->tx_bd_ring_offset[j] =
6fee40e9 2383 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
04b588d7 2384
ce973b14
LY		 2385 if (ugeth->tx_bd_ring_offset[j] != 0)
2386 ugeth->p_tx_bd_ring[j] =
6fee40e9 2387 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
ce973b14
LY		 2388 align) & ~(align - 1));
2389 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2390 ugeth->tx_bd_ring_offset[j] =
2391 qe_muram_alloc(length,
2392 UCC_GETH_TX_BD_RING_ALIGNMENT);
4c35630c 2393 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
ce973b14 2394 ugeth->p_tx_bd_ring[j] =
6fee40e9 2395 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2396 tx_bd_ring_offset[j]);
2397 }
2398 if (!ugeth->p_tx_bd_ring[j]) {
890de95e
LY		 2399 if (netif_msg_ifup(ugeth))
2400 ugeth_err
2401 ("%s: Can not allocate memory for Tx bd rings.",
b39d66a8 2402 __func__);
ce973b14
LY		 2403 return -ENOMEM;
2404 }
2405 /* Zero unused end of bd ring, according to spec */
6fee40e9
AF		 2406 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2407 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
18a8e864 2408 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2409 }
2410
2411 /* Allocate Rx bds */
2412 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2413 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2414 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2415 u32 align = 4;
2416 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2417 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2418 ugeth->rx_bd_ring_offset[j] =
6fee40e9 2419 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2420 if (ugeth->rx_bd_ring_offset[j] != 0)
2421 ugeth->p_rx_bd_ring[j] =
6fee40e9 2422 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
ce973b14
LY		 2423 align) & ~(align - 1));
2424 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2425 ugeth->rx_bd_ring_offset[j] =
2426 qe_muram_alloc(length,
2427 UCC_GETH_RX_BD_RING_ALIGNMENT);
4c35630c 2428 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
ce973b14 2429 ugeth->p_rx_bd_ring[j] =
6fee40e9 2430 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2431 rx_bd_ring_offset[j]);
2432 }
2433 if (!ugeth->p_rx_bd_ring[j]) {
890de95e
LY		 2434 if (netif_msg_ifup(ugeth))
2435 ugeth_err
2436 ("%s: Can not allocate memory for Rx bd rings.",
b39d66a8 2437 __func__);
ce973b14
LY		 2438 return -ENOMEM;
2439 }
2440 }
2441
2442 /* Init Tx bds */
2443 for (j = 0; j < ug_info->numQueuesTx; j++) {
2444 /* Setup the skbuff rings */
04b588d7
AD		 2445 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2446 ugeth->ug_info->bdRingLenTx[j],
2447 GFP_KERNEL);
ce973b14
LY		 2448
2449 if (ugeth->tx_skbuff[j] == NULL) {
890de95e
LY		 2450 if (netif_msg_ifup(ugeth))
2451 ugeth_err("%s: Could not allocate tx_skbuff",
b39d66a8 2452 __func__);
ce973b14
LY		 2453 return -ENOMEM;
2454 }
2455
2456 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2457 ugeth->tx_skbuff[j][i] = NULL;
2458
2459 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2460 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2461 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864 2462 /* clear bd buffer */
6fee40e9 2463 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2464 /* set bd status and length */
6fee40e9 2465 out_be32((u32 __iomem *)bd, 0);
18a8e864 2466 bd += sizeof(struct qe_bd);
ce973b14 2467 }
18a8e864
LY		 2468 bd -= sizeof(struct qe_bd);
2469 /* set bd status and length */
6fee40e9 2470 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2471 }
2472
2473 /* Init Rx bds */
2474 for (j = 0; j < ug_info->numQueuesRx; j++) {
2475 /* Setup the skbuff rings */
04b588d7
AD		 2476 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2477 ugeth->ug_info->bdRingLenRx[j],
2478 GFP_KERNEL);
ce973b14
LY		 2479
2480 if (ugeth->rx_skbuff[j] == NULL) {
890de95e
LY		 2481 if (netif_msg_ifup(ugeth))
2482 ugeth_err("%s: Could not allocate rx_skbuff",
b39d66a8 2483 __func__);
ce973b14
LY		 2484 return -ENOMEM;
2485 }
2486
2487 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2488 ugeth->rx_skbuff[j][i] = NULL;
2489
2490 ugeth->skb_currx[j] = 0;
2491 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2492 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864 2493 /* set bd status and length */
6fee40e9 2494 out_be32((u32 __iomem *)bd, R_I);
18a8e864 2495 /* clear bd buffer */
6fee40e9 2496 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2497 bd += sizeof(struct qe_bd);
ce973b14 2498 }
18a8e864
LY		 2499 bd -= sizeof(struct qe_bd);
2500 /* set bd status and length */
6fee40e9 2501 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2502 }
2503
2504 /*
2505 * Global PRAM
2506 */
2507 /* Tx global PRAM */
2508 /* Allocate global tx parameter RAM page */
2509 ugeth->tx_glbl_pram_offset =
18a8e864 2510 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2511 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2512 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2513 if (netif_msg_ifup(ugeth))
2514 ugeth_err
2515 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2516 __func__);
ce973b14
LY		 2517 return -ENOMEM;
2518 }
2519 ugeth->p_tx_glbl_pram =
6fee40e9 2520 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2521 tx_glbl_pram_offset);
2522 /* Zero out p_tx_glbl_pram */
6fee40e9 2523 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2524
2525 /* Fill global PRAM */
2526
2527 /* TQPTR */
2528 /* Size varies with number of Tx threads */
2529 ugeth->thread_dat_tx_offset =
2530 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2531 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2532 32 * (numThreadsTxNumerical == 1),
2533 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2534 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2535 if (netif_msg_ifup(ugeth))
2536 ugeth_err
2537 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2538 __func__);
ce973b14
LY		 2539 return -ENOMEM;
2540 }
2541
2542 ugeth->p_thread_data_tx =
6fee40e9 2543 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2544 thread_dat_tx_offset);
2545 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2546
2547 /* vtagtable */
2548 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2549 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2550 ug_info->vtagtable[i]);
2551
2552 /* iphoffset */
2553 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2554 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2555 ug_info->iphoffset[i]);
ce973b14
LY		 2556
2557 /* SQPTR */
2558 /* Size varies with number of Tx queues */
2559 ugeth->send_q_mem_reg_offset =
2560 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2561 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2562 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2563 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2564 if (netif_msg_ifup(ugeth))
2565 ugeth_err
2566 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2567 __func__);
ce973b14
LY		 2568 return -ENOMEM;
2569 }
2570
2571 ugeth->p_send_q_mem_reg =
6fee40e9 2572 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2573 send_q_mem_reg_offset);
2574 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2575
2576 /* Setup the table */
2577 /* Assume BD rings are already established */
2578 for (i = 0; i < ug_info->numQueuesTx; i++) {
2579 endOfRing =
2580 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2581 1) * sizeof(struct qe_bd);
ce973b14
LY		 2582 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2583 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2584 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2585 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2586 last_bd_completed_address,
2587 (u32) virt_to_phys(endOfRing));
2588 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2589 MEM_PART_MURAM) {
2590 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2591 (u32) immrbar_virt_to_phys(ugeth->
2592 p_tx_bd_ring[i]));
2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2594 last_bd_completed_address,
2595 (u32) immrbar_virt_to_phys(endOfRing));
2596 }
2597 }
2598
2599 /* schedulerbasepointer */
2600
2601 if (ug_info->numQueuesTx > 1) {
2602 /* scheduler exists only if more than 1 tx queue */
2603 ugeth->scheduler_offset =
18a8e864 2604 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2605 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2606 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2607 if (netif_msg_ifup(ugeth))
2608 ugeth_err
2609 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2610 __func__);
ce973b14
LY		 2611 return -ENOMEM;
2612 }
2613
2614 ugeth->p_scheduler =
6fee40e9 2615 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2616 scheduler_offset);
2617 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2618 ugeth->scheduler_offset);
2619 /* Zero out p_scheduler */
6fee40e9 2620 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2621
2622 /* Set values in scheduler */
2623 out_be32(&ugeth->p_scheduler->mblinterval,
2624 ug_info->mblinterval);
2625 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2626 ug_info->nortsrbytetime);
6fee40e9
AF		 2627 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2628 out_8(&ugeth->p_scheduler->strictpriorityq,
2629 ug_info->strictpriorityq);
2630 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2631 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2632 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2633 out_8(&ugeth->p_scheduler->weightfactor[i],
2634 ug_info->weightfactor[i]);
ce973b14
LY		 2635
2636 /* Set pointers to cpucount registers in scheduler */
2637 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2638 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2639 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2640 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2641 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2642 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2643 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2644 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2645 }
2646
2647 /* schedulerbasepointer */
2648 /* TxRMON_PTR (statistics) */
2649 if (ug_info->
2650 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2651 ugeth->tx_fw_statistics_pram_offset =
2652 qe_muram_alloc(sizeof
18a8e864 2653 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2654 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2655 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2656 if (netif_msg_ifup(ugeth))
2657 ugeth_err
2658 ("%s: Can not allocate DPRAM memory for"
2659 " p_tx_fw_statistics_pram.",
b39d66a8 2660 __func__);
ce973b14
LY		 2661 return -ENOMEM;
2662 }
2663 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2664 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2665 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2666 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2667 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2668 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2669 }
2670
2671 /* temoder */
2672 /* Already has speed set */
2673
2674 if (ug_info->numQueuesTx > 1)
2675 temoder |= TEMODER_SCHEDULER_ENABLE;
2676 if (ug_info->ipCheckSumGenerate)
2677 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2678 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2679 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2680
2681 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2682
2683 /* Function code register value to be used later */
6b0b594b 2684 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2685 /* Required for QE */
2686
2687 /* function code register */
2688 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2689
2690 /* Rx global PRAM */
2691 /* Allocate global rx parameter RAM page */
2692 ugeth->rx_glbl_pram_offset =
18a8e864 2693 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2694 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2695 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2696 if (netif_msg_ifup(ugeth))
2697 ugeth_err
2698 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2699 __func__);
ce973b14
LY		 2700 return -ENOMEM;
2701 }
2702 ugeth->p_rx_glbl_pram =
6fee40e9 2703 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2704 rx_glbl_pram_offset);
2705 /* Zero out p_rx_glbl_pram */
6fee40e9 2706 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2707
2708 /* Fill global PRAM */
2709
2710 /* RQPTR */
2711 /* Size varies with number of Rx threads */
2712 ugeth->thread_dat_rx_offset =
2713 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2714 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2715 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2716 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2717 if (netif_msg_ifup(ugeth))
2718 ugeth_err
2719 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2720 __func__);
ce973b14
LY		 2721 return -ENOMEM;
2722 }
2723
2724 ugeth->p_thread_data_rx =
6fee40e9 2725 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2726 thread_dat_rx_offset);
2727 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2728
2729 /* typeorlen */
2730 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2731
2732 /* rxrmonbaseptr (statistics) */
2733 if (ug_info->
2734 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2735 ugeth->rx_fw_statistics_pram_offset =
2736 qe_muram_alloc(sizeof
18a8e864 2737 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2738 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2739 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2740 if (netif_msg_ifup(ugeth))
2741 ugeth_err
2742 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2743 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2744 return -ENOMEM;
2745 }
2746 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2747 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2748 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2749 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2750 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2751 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2752 }
2753
2754 /* intCoalescingPtr */
2755
2756 /* Size varies with number of Rx queues */
2757 ugeth->rx_irq_coalescing_tbl_offset =
2758 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2759 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2760 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2761 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 2762 if (netif_msg_ifup(ugeth))
2763 ugeth_err
2764 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2765 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 2766 return -ENOMEM;
2767 }
2768
2769 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2770 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2771 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2772 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2773 ugeth->rx_irq_coalescing_tbl_offset);
2774
2775 /* Fill interrupt coalescing table */
2776 for (i = 0; i < ug_info->numQueuesRx; i++) {
2777 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2778 interruptcoalescingmaxvalue,
2779 ug_info->interruptcoalescingmaxvalue[i]);
2780 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2781 interruptcoalescingcounter,
2782 ug_info->interruptcoalescingmaxvalue[i]);
2783 }
2784
2785 /* MRBLR */
2786 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2787 &ugeth->p_rx_glbl_pram->mrblr);
2788 /* MFLR */
2789 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2790 /* MINFLR */
2791 init_min_frame_len(ug_info->minFrameLength,
2792 &ugeth->p_rx_glbl_pram->minflr,
2793 &ugeth->p_rx_glbl_pram->mrblr);
2794 /* MAXD1 */
2795 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2796 /* MAXD2 */
2797 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2798
2799 /* l2qt */
2800 l2qt = 0;
2801 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2802 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2803 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2804
2805 /* l3qt */
2806 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2807 l3qt = 0;
2808 for (i = 0; i < 8; i++)
2809 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2810 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2811 }
2812
2813 /* vlantype */
2814 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2815
2816 /* vlantci */
2817 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2818
2819 /* ecamptr */
2820 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2821
2822 /* RBDQPTR */
2823 /* Size varies with number of Rx queues */
2824 ugeth->rx_bd_qs_tbl_offset =
2825 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2826 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2827 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2828 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2829 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 2830 if (netif_msg_ifup(ugeth))
2831 ugeth_err
2832 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 2833 __func__);
ce973b14
LY		 2834 return -ENOMEM;
2835 }
2836
2837 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2838 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2839 rx_bd_qs_tbl_offset);
2840 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2841 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2842 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2843 0,
18a8e864
LY		 2844 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2845 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2846
2847 /* Setup the table */
2848 /* Assume BD rings are already established */
2849 for (i = 0; i < ug_info->numQueuesRx; i++) {
2850 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2851 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2852 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2853 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2854 MEM_PART_MURAM) {
2855 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2856 (u32) immrbar_virt_to_phys(ugeth->
2857 p_rx_bd_ring[i]));
2858 }
2859 /* rest of fields handled by QE */
2860 }
2861
2862 /* remoder */
2863 /* Already has speed set */
2864
2865 if (ugeth->rx_extended_features)
2866 remoder |= REMODER_RX_EXTENDED_FEATURES;
2867 if (ug_info->rxExtendedFiltering)
2868 remoder |= REMODER_RX_EXTENDED_FILTERING;
2869 if (ug_info->dynamicMaxFrameLength)
2870 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2871 if (ug_info->dynamicMinFrameLength)
2872 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2873 remoder |=
2874 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2875 remoder |=
2876 ug_info->
2877 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2878 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2879 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2880 if (ug_info->ipCheckSumCheck)
2881 remoder |= REMODER_IP_CHECKSUM_CHECK;
2882 if (ug_info->ipAddressAlignment)
2883 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2884 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2885
2886 /* Note that this function must be called */
2887 /* ONLY AFTER p_tx_fw_statistics_pram */
2888 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2889 init_firmware_statistics_gathering_mode((ug_info->
2890 statisticsMode &
2891 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2892 (ug_info->statisticsMode &
2893 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2894 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2895 ugeth->tx_fw_statistics_pram_offset,
2896 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2897 ugeth->rx_fw_statistics_pram_offset,
2898 &ugeth->p_tx_glbl_pram->temoder,
2899 &ugeth->p_rx_glbl_pram->remoder);
2900
2901 /* function code register */
6fee40e9 2902 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2903
2904 /* initialize extended filtering */
2905 if (ug_info->rxExtendedFiltering) {
2906 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 2907 if (netif_msg_ifup(ugeth))
2908 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 2909 __func__);
ce973b14
LY		 2910 return -EINVAL;
2911 }
2912
2913 /* Allocate memory for extended filtering Mode Global
2914 Parameters */
2915 ugeth->exf_glbl_param_offset =
18a8e864 2916 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2917 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2918 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 2919 if (netif_msg_ifup(ugeth))
2920 ugeth_err
2921 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2922 " p_exf_glbl_param.", __func__);
ce973b14
LY		 2923 return -ENOMEM;
2924 }
2925
2926 ugeth->p_exf_glbl_param =
6fee40e9 2927 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2928 exf_glbl_param_offset);
2929 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2930 ugeth->exf_glbl_param_offset);
2931 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2932 (u32) ug_info->extendedFilteringChainPointer);
2933
2934 } else { /* initialize 82xx style address filtering */
2935
2936 /* Init individual address recognition registers to disabled */
2937
2938 for (j = 0; j < NUM_OF_PADDRS; j++)
2939 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2940
ce973b14 2941 p_82xx_addr_filt =
6fee40e9 2942 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2943 p_rx_glbl_pram->addressfiltering;
2944
2945 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2946 ENET_ADDR_TYPE_GROUP);
2947 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2948 ENET_ADDR_TYPE_INDIVIDUAL);
2949 }
2950
2951 /*
2952 * Initialize UCC at QE level
2953 */
2954
2955 command = QE_INIT_TX_RX;
2956
2957 /* Allocate shadow InitEnet command parameter structure.
2958 * This is needed because after the InitEnet command is executed,
2959 * the structure in DPRAM is released, because DPRAM is a premium
2960 * resource.
2961 * This shadow structure keeps a copy of what was done so that the
2962 * allocated resources can be released when the channel is freed.
2963 */
2964 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2965 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 2966 if (netif_msg_ifup(ugeth))
2967 ugeth_err
2968 ("%s: Can not allocate memory for"
b39d66a8 2969 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 2970 return -ENOMEM;
2971 }
2972 /* Zero out *p_init_enet_param_shadow */
2973 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2974 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2975
2976 /* Fill shadow InitEnet command parameter structure */
2977
2978 ugeth->p_init_enet_param_shadow->resinit1 =
2979 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2980 ugeth->p_init_enet_param_shadow->resinit2 =
2981 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2982 ugeth->p_init_enet_param_shadow->resinit3 =
2983 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2984 ugeth->p_init_enet_param_shadow->resinit4 =
2985 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2986 ugeth->p_init_enet_param_shadow->resinit5 =
2987 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2988 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2989 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2990 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2991 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2992
2993 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2994 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2995 if ((ug_info->largestexternallookupkeysize !=
8e95a202
JP		 2996 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2997 (ug_info->largestexternallookupkeysize !=
2998 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2999 (ug_info->largestexternallookupkeysize !=
3000 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 3001 if (netif_msg_ifup(ugeth))
3002 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 3003 __func__);
ce973b14
LY		 3004 return -EINVAL;
3005 }
3006 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3007 ug_info->largestexternallookupkeysize;
18a8e864 3008 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 3009 if (ug_info->rxExtendedFiltering) {
3010 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3011 if (ug_info->largestexternallookupkeysize ==
3012 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3013 size +=
3014 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3015 if (ug_info->largestexternallookupkeysize ==
3016 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3017 size +=
3018 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3019 }
3020
3021 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3022 p_init_enet_param_shadow->rxthread[0]),
3023 (u8) (numThreadsRxNumerical + 1)
3024 /* Rx needs one extra for terminator */
3025 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3026 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 3027 if (netif_msg_ifup(ugeth))
3028 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3029 __func__);
ce973b14
LY		 3030 return ret_val;
3031 }
3032
3033 ugeth->p_init_enet_param_shadow->txglobal =
3034 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3035 if ((ret_val =
3036 fill_init_enet_entries(ugeth,
3037 &(ugeth->p_init_enet_param_shadow->
3038 txthread[0]), numThreadsTxNumerical,
18a8e864 3039 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3040 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3041 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 3042 if (netif_msg_ifup(ugeth))
3043 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3044 __func__);
ce973b14
LY		 3045 return ret_val;
3046 }
3047
3048 /* Load Rx bds with buffers */
3049 for (i = 0; i < ug_info->numQueuesRx; i++) {
3050 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 3051 if (netif_msg_ifup(ugeth))
3052 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 3053 __func__);
ce973b14
LY		 3054 return ret_val;
3055 }
3056 }
3057
3058 /* Allocate InitEnet command parameter structure */
18a8e864 3059 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3060 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3061 if (netif_msg_ifup(ugeth))
3062 ugeth_err
3063 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3064 __func__);
ce973b14
LY		 3065 return -ENOMEM;
3066 }
3067 p_init_enet_pram =
6fee40e9 3068 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3069
3070 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3071 out_8(&p_init_enet_pram->resinit1,
3072 ugeth->p_init_enet_param_shadow->resinit1);
3073 out_8(&p_init_enet_pram->resinit2,
3074 ugeth->p_init_enet_param_shadow->resinit2);
3075 out_8(&p_init_enet_pram->resinit3,
3076 ugeth->p_init_enet_param_shadow->resinit3);
3077 out_8(&p_init_enet_pram->resinit4,
3078 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3079 out_be16(&p_init_enet_pram->resinit5,
3080 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3081 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3082 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3083 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3084 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3085 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3086 out_be32(&p_init_enet_pram->rxthread[i],
3087 ugeth->p_init_enet_param_shadow->rxthread[i]);
3088 out_be32(&p_init_enet_pram->txglobal,
3089 ugeth->p_init_enet_param_shadow->txglobal);
3090 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3091 out_be32(&p_init_enet_pram->txthread[i],
3092 ugeth->p_init_enet_param_shadow->txthread[i]);
3093
3094 /* Issue QE command */
3095 cecr_subblock =
3096 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3097 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3098 init_enet_pram_offset);
3099
3100 /* Free InitEnet command parameter */
3101 qe_muram_free(init_enet_pram_offset);
3102
3103 return 0;
3104}
3105
ce973b14
LY		 3106/* This is called by the kernel when a frame is ready for transmission. */
3107/* It is pointed to by the dev->hard_start_xmit function pointer */
3108static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3109{
18a8e864 3110 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3111#ifdef CONFIG_UGETH_TX_ON_DEMAND
3112 struct ucc_fast_private *uccf;
3113#endif
6fee40e9 3114 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3115 u32 bd_status;
3116 u8 txQ = 0;
22580f89 3117 unsigned long flags;
ce973b14 3118
b39d66a8 3119 ugeth_vdbg("%s: IN", __func__);
ce973b14 3120
22580f89 3121 spin_lock_irqsave(&ugeth->lock, flags);
ce973b14 3122
09f75cd7 3123 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3124
3125 /* Start from the next BD that should be filled */
3126 bd = ugeth->txBd[txQ];
6fee40e9 3127 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3128 /* Save the skb pointer so we can free it later */
3129 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3130
3131 /* Update the current skb pointer (wrapping if this was the last) */
3132 ugeth->skb_curtx[txQ] =
3133 (ugeth->skb_curtx[txQ] +
3134 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3135
3136 /* set up the buffer descriptor */
6fee40e9 3137 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3138 dma_map_single(ugeth->dev, skb->data,
7f80202b 3139 skb->len, DMA_TO_DEVICE));
ce973b14 3140
18a8e864 3141 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3142
3143 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3144
18a8e864 3145 /* set bd status and length */
6fee40e9 3146 out_be32((u32 __iomem *)bd, bd_status);
ce973b14 3147
ce973b14
LY		 3148 /* Move to next BD in the ring */
3149 if (!(bd_status & T_W))
a394f013 3150 bd += sizeof(struct qe_bd);
ce973b14 3151 else
a394f013 3152 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3153
3154 /* If the next BD still needs to be cleaned up, then the bds
3155 are full. We need to tell the kernel to stop sending us stuff. */
3156 if (bd == ugeth->confBd[txQ]) {
3157 if (!netif_queue_stopped(dev))
3158 netif_stop_queue(dev);
3159 }
3160
a394f013
LY		 3161 ugeth->txBd[txQ] = bd;
3162
d13d6bff
RC		 3163 skb_tx_timestamp(skb);
3164
ce973b14
LY		 3165 if (ugeth->p_scheduler) {
3166 ugeth->cpucount[txQ]++;
3167 /* Indicate to QE that there are more Tx bds ready for
3168 transmission */
3169 /* This is done by writing a running counter of the bd
3170 count to the scheduler PRAM. */
3171 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3172 }
3173
d5b9049d
MR		 3174#ifdef CONFIG_UGETH_TX_ON_DEMAND
3175 uccf = ugeth->uccf;
3176 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3177#endif
22580f89 3178 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14 3179
6ed10654 3180 return NETDEV_TX_OK;
ce973b14
LY		 3181}
3182
18a8e864 3183static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3184{
3185 struct sk_buff *skb;
6fee40e9 3186 u8 __iomem *bd;
ce973b14
LY		 3187 u16 length, howmany = 0;
3188 u32 bd_status;
3189 u8 *bdBuffer;
4b8fdefa 3190 struct net_device *dev;
ce973b14 3191
b39d66a8 3192 ugeth_vdbg("%s: IN", __func__);
ce973b14 3193
da1aa63e 3194 dev = ugeth->ndev;
88a15f2e 3195
ce973b14
LY		 3196 /* collect received buffers */
3197 bd = ugeth->rxBd[rxQ];
3198
6fee40e9 3199 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3200
3201 /* while there are received buffers and BD is full (~R_E) */
3202 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3203 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3204 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3205 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3206
3207 /* determine whether buffer is first, last, first and last
3208 (single buffer frame) or middle (not first and not last) */
3209 if (!skb ||
3210 (!(bd_status & (R_F | R_L))) ||
3211 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3212 if (netif_msg_rx_err(ugeth))
3213 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3214 __func__, __LINE__, (u32) skb);
50f238fd
AV		 3215 if (skb) {
3216 skb->data = skb->head + NET_SKB_PAD;
db176edc
SM		 3217 skb->len = 0;
3218 skb_reset_tail_pointer(skb);
50f238fd
AV		 3219 __skb_queue_head(&ugeth->rx_recycle, skb);
3220 }
ce973b14
LY		 3221
3222 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3223 dev->stats.rx_dropped++;
ce973b14 3224 } else {
09f75cd7 3225 dev->stats.rx_packets++;
ce973b14
LY		 3226 howmany++;
3227
3228 /* Prep the skb for the packet */
3229 skb_put(skb, length);
3230
3231 /* Tell the skb what kind of packet this is */
da1aa63e 3232 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3233
09f75cd7 3234 dev->stats.rx_bytes += length;
ce973b14 3235 /* Send the packet up the stack */
ce973b14 3236 netif_receive_skb(skb);
ce973b14
LY		 3237 }
3238
ce973b14
LY		 3239 skb = get_new_skb(ugeth, bd);
3240 if (!skb) {
890de95e 3241 if (netif_msg_rx_err(ugeth))
b39d66a8 3242 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3243 dev->stats.rx_dropped++;
ce973b14
LY		 3244 break;
3245 }
3246
3247 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3248
3249 /* update to point at the next skb */
3250 ugeth->skb_currx[rxQ] =
3251 (ugeth->skb_currx[rxQ] +
3252 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3253
3254 if (bd_status & R_W)
3255 bd = ugeth->p_rx_bd_ring[rxQ];
3256 else
18a8e864 3257 bd += sizeof(struct qe_bd);
ce973b14 3258
6fee40e9 3259 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3260 }
3261
3262 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3263 return howmany;
3264}
3265
3266static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3267{
3268 /* Start from the next BD that should be filled */
18a8e864 3269 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3270 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3271 u32 bd_status;
3272
3273 bd = ugeth->confBd[txQ];
6fee40e9 3274 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3275
3276 /* Normal processing. */
3277 while ((bd_status & T_R) == 0) {
50f238fd
AV		 3278 struct sk_buff *skb;
3279
ce973b14
LY		 3280 /* BD contains already transmitted buffer. */
3281 /* Handle the transmitted buffer and release */
3282 /* the BD to be used with the current frame */
3283
34692421
JW		 3284 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3285 if (!skb)
ce973b14
LY		 3286 break;
3287
09f75cd7 3288 dev->stats.tx_packets++;
ce973b14 3289
50f238fd
AV		 3290 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3291 skb_recycle_check(skb,
3292 ugeth->ug_info->uf_info.max_rx_buf_length +
3293 UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3294 __skb_queue_head(&ugeth->rx_recycle, skb);
3295 else
3296 dev_kfree_skb(skb);
3297
ce973b14
LY		 3298 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3299 ugeth->skb_dirtytx[txQ] =
3300 (ugeth->skb_dirtytx[txQ] +
3301 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3302
3303 /* We freed a buffer, so now we can restart transmission */
3304 if (netif_queue_stopped(dev))
3305 netif_wake_queue(dev);
3306
3307 /* Advance the confirmation BD pointer */
3308 if (!(bd_status & T_W))
a394f013 3309 bd += sizeof(struct qe_bd);
ce973b14 3310 else
a394f013 3311 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3312 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3313 }
a394f013 3314 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3315 return 0;
3316}
3317
bea3348e 3318static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3319{
bea3348e 3320 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3321 struct ucc_geth_info *ug_info;
bea3348e 3322 int howmany, i;
ce973b14 3323
702ff12c
MR		 3324 ug_info = ugeth->ug_info;
3325
0cededf3
JT		 3326 /* Tx event processing */
3327 spin_lock(&ugeth->lock);
3328 for (i = 0; i < ug_info->numQueuesTx; i++)
3329 ucc_geth_tx(ugeth->ndev, i);
3330 spin_unlock(&ugeth->lock);
3331
50f238fd
AV		 3332 howmany = 0;
3333 for (i = 0; i < ug_info->numQueuesRx; i++)
3334 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3335
bea3348e 3336 if (howmany < budget) {
288379f0 3337 napi_complete(napi);
0cededf3 3338 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3339 }
ce973b14 3340
bea3348e 3341 return howmany;
ce973b14 3342}
ce973b14 3343
7d12e780 3344static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3345{
06efcad0 3346 struct net_device *dev = info;
18a8e864
LY		 3347 struct ucc_geth_private *ugeth = netdev_priv(dev);
3348 struct ucc_fast_private *uccf;
3349 struct ucc_geth_info *ug_info;
702ff12c
MR		 3350 register u32 ucce;
3351 register u32 uccm;
ce973b14 3352
b39d66a8 3353 ugeth_vdbg("%s: IN", __func__);
ce973b14 3354
ce973b14
LY		 3355 uccf = ugeth->uccf;
3356 ug_info = ugeth->ug_info;
3357
702ff12c
MR		 3358 /* read and clear events */
3359 ucce = (u32) in_be32(uccf->p_ucce);
3360 uccm = (u32) in_be32(uccf->p_uccm);
3361 ucce &= uccm;
3362 out_be32(uccf->p_ucce, ucce);
ce973b14 3363
702ff12c 3364 /* check for receive events that require processing */
0cededf3 3365 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3366 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3367 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3368 out_be32(uccf->p_uccm, uccm);
288379f0 3369 __napi_schedule(&ugeth->napi);
702ff12c 3370 }
702ff12c 3371 }
ce973b14 3372
702ff12c
MR		 3373 /* Errors and other events */
3374 if (ucce & UCCE_OTHER) {
3bc53427 3375 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3376 dev->stats.rx_errors++;
3bc53427 3377 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3378 dev->stats.tx_errors++;
ce973b14 3379 }
ce973b14
LY		 3380
3381 return IRQ_HANDLED;
3382}
3383
26d29ea7
AV		 3384#ifdef CONFIG_NET_POLL_CONTROLLER
3385/*
3386 * Polling 'interrupt' - used by things like netconsole to send skbs
3387 * without having to re-enable interrupts. It's not called while
3388 * the interrupt routine is executing.
3389 */
3390static void ucc_netpoll(struct net_device *dev)
3391{
3392 struct ucc_geth_private *ugeth = netdev_priv(dev);
3393 int irq = ugeth->ug_info->uf_info.irq;
3394
3395 disable_irq(irq);
3396 ucc_geth_irq_handler(irq, dev);
3397 enable_irq(irq);
3398}
3399#endif /* CONFIG_NET_POLL_CONTROLLER */
3400
3d6593e9
KH		 3401static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3402{
3403 struct ucc_geth_private *ugeth = netdev_priv(dev);
3404 struct sockaddr *addr = p;
3405
3406 if (!is_valid_ether_addr(addr->sa_data))
3407 return -EADDRNOTAVAIL;
3408
3409 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3410
3411 /*
3412 * If device is not running, we will set mac addr register
3413 * when opening the device.
3414 */
3415 if (!netif_running(dev))
3416 return 0;
3417
3418 spin_lock_irq(&ugeth->lock);
3419 init_mac_station_addr_regs(dev->dev_addr[0],
3420 dev->dev_addr[1],
3421 dev->dev_addr[2],
3422 dev->dev_addr[3],
3423 dev->dev_addr[4],
3424 dev->dev_addr[5],
3425 &ugeth->ug_regs->macstnaddr1,
3426 &ugeth->ug_regs->macstnaddr2);
3427 spin_unlock_irq(&ugeth->lock);
3428
3429 return 0;
3430}
3431
54b15983 3432static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
ce973b14 3433{
54b15983 3434 struct net_device *dev = ugeth->ndev;
ce973b14
LY		 3435 int err;
3436
728de4c9
KP		 3437 err = ucc_struct_init(ugeth);
3438 if (err) {
890de95e 3439 if (netif_msg_ifup(ugeth))
54b15983
AV		 3440 ugeth_err("%s: Cannot configure internal struct, "
3441 "aborting.", dev->name);
3442 goto err;
728de4c9
KP		 3443 }
3444
ce973b14
LY		 3445 err = ucc_geth_startup(ugeth);
3446 if (err) {
890de95e
LY		 3447 if (netif_msg_ifup(ugeth))
3448 ugeth_err("%s: Cannot configure net device, aborting.",
3449 dev->name);
54b15983 3450 goto err;
ce973b14
LY		 3451 }
3452
3453 err = adjust_enet_interface(ugeth);
3454 if (err) {
890de95e
LY		 3455 if (netif_msg_ifup(ugeth))
3456 ugeth_err("%s: Cannot configure net device, aborting.",
3457 dev->name);
54b15983 3458 goto err;
ce973b14
LY		 3459 }
3460
3461 /* Set MACSTNADDR1, MACSTNADDR2 */
3462 /* For more details see the hardware spec. */
3463 init_mac_station_addr_regs(dev->dev_addr[0],
3464 dev->dev_addr[1],
3465 dev->dev_addr[2],
3466 dev->dev_addr[3],
3467 dev->dev_addr[4],
3468 dev->dev_addr[5],
3469 &ugeth->ug_regs->macstnaddr1,
3470 &ugeth->ug_regs->macstnaddr2);
3471
67c2fb8f 3472 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3473 if (err) {
890de95e 3474 if (netif_msg_ifup(ugeth))
67c2fb8f 3475 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
54b15983
AV		 3476 goto err;
3477 }
3478
3479 return 0;
3480err:
3481 ucc_geth_stop(ugeth);
3482 return err;
3483}
3484
3485/* Called when something needs to use the ethernet device */
3486/* Returns 0 for success. */
3487static int ucc_geth_open(struct net_device *dev)
3488{
3489 struct ucc_geth_private *ugeth = netdev_priv(dev);
3490 int err;
3491
3492 ugeth_vdbg("%s: IN", __func__);
3493
3494 /* Test station address */
3495 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3496 if (netif_msg_ifup(ugeth))
3497 ugeth_err("%s: Multicast address used for station "
3498 "address - is this what you wanted?",
3499 __func__);
3500 return -EINVAL;
3501 }
3502
3503 err = init_phy(dev);
3504 if (err) {
3505 if (netif_msg_ifup(ugeth))
3506 ugeth_err("%s: Cannot initialize PHY, aborting.",
3507 dev->name);
3508 return err;
3509 }
3510
3511 err = ucc_geth_init_mac(ugeth);
3512 if (err) {
3513 if (netif_msg_ifup(ugeth))
3514 ugeth_err("%s: Cannot initialize MAC, aborting.",
3515 dev->name);
3516 goto err;
ce973b14 3517 }
ce973b14 3518
67c2fb8f
AV		 3519 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3520 0, "UCC Geth", dev);
ce973b14 3521 if (err) {
890de95e 3522 if (netif_msg_ifup(ugeth))
67c2fb8f
AV		 3523 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3524 dev->name);
54b15983 3525 goto err;
ce973b14
LY		 3526 }
3527
54b15983
AV		 3528 phy_start(ugeth->phydev);
3529 napi_enable(&ugeth->napi);
ce973b14
LY		 3530 netif_start_queue(dev);
3531
2394905f
AV		 3532 device_set_wakeup_capable(&dev->dev,
3533 qe_alive_during_sleep() || ugeth->phydev->irq);
3534 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3535
ce973b14 3536 return err;
bea3348e 3537
54b15983 3538err:
ba574696 3539 ucc_geth_stop(ugeth);
bea3348e 3540 return err;
ce973b14
LY		 3541}
3542
3543/* Stops the kernel queue, and halts the controller */
3544static int ucc_geth_close(struct net_device *dev)
3545{
18a8e864 3546 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3547
b39d66a8 3548 ugeth_vdbg("%s: IN", __func__);
ce973b14 3549
bea3348e 3550 napi_disable(&ugeth->napi);
bea3348e 3551
2040bd57 3552 cancel_work_sync(&ugeth->timeout_work);
ce973b14 3553 ucc_geth_stop(ugeth);
2040bd57
JT		 3554 phy_disconnect(ugeth->phydev);
3555 ugeth->phydev = NULL;
ce973b14 3556
da1aa63e 3557 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3558
ce973b14
LY		 3559 netif_stop_queue(dev);
3560
3561 return 0;
3562}
3563
fdb614c2
AV		 3564/* Reopen device. This will reset the MAC and PHY. */
3565static void ucc_geth_timeout_work(struct work_struct *work)
3566{
3567 struct ucc_geth_private *ugeth;
3568 struct net_device *dev;
3569
3570 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3571 dev = ugeth->ndev;
fdb614c2
AV		 3572
3573 ugeth_vdbg("%s: IN", __func__);
3574
3575 dev->stats.tx_errors++;
3576
3577 ugeth_dump_regs(ugeth);
3578
3579 if (dev->flags & IFF_UP) {
3580 /*
3581 * Must reset MAC *and* PHY. This is done by reopening
3582 * the device.
3583 */
2040bd57
JT		 3584 netif_tx_stop_all_queues(dev);
3585 ucc_geth_stop(ugeth);
3586 ucc_geth_init_mac(ugeth);
3587 /* Must start PHY here */
3588 phy_start(ugeth->phydev);
3589 netif_tx_start_all_queues(dev);
fdb614c2
AV		 3590 }
3591
3592 netif_tx_schedule_all(dev);
3593}
3594
3595/*
3596 * ucc_geth_timeout gets called when a packet has not been
3597 * transmitted after a set amount of time.
3598 */
3599static void ucc_geth_timeout(struct net_device *dev)
3600{
3601 struct ucc_geth_private *ugeth = netdev_priv(dev);
3602
fdb614c2
AV		 3603 schedule_work(&ugeth->timeout_work);
3604}
3605
2394905f
AV		 3606
3607#ifdef CONFIG_PM
3608
2dc11581 3609static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
2394905f
AV		 3610{
3611 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3612 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3613
3614 if (!netif_running(ndev))
3615 return 0;
3616
29fb00e0 3617 netif_device_detach(ndev);
2394905f
AV		 3618 napi_disable(&ugeth->napi);
3619
3620 /*
3621 * Disable the controller, otherwise we'll wakeup on any network
3622 * activity.
3623 */
3624 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3625
3626 if (ugeth->wol_en & WAKE_MAGIC) {
3627 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3628 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3629 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3630 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3631 phy_stop(ugeth->phydev);
3632 }
3633
3634 return 0;
3635}
3636
2dc11581 3637static int ucc_geth_resume(struct platform_device *ofdev)
2394905f
AV		 3638{
3639 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3640 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3641 int err;
3642
3643 if (!netif_running(ndev))
3644 return 0;
3645
3646 if (qe_alive_during_sleep()) {
3647 if (ugeth->wol_en & WAKE_MAGIC) {
3648 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3649 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3650 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3651 }
3652 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3653 } else {
3654 /*
3655 * Full reinitialization is required if QE shuts down
3656 * during sleep.
3657 */
3658 ucc_geth_memclean(ugeth);
3659
3660 err = ucc_geth_init_mac(ugeth);
3661 if (err) {
3662 ugeth_err("%s: Cannot initialize MAC, aborting.",
3663 ndev->name);
3664 return err;
3665 }
3666 }
3667
3668 ugeth->oldlink = 0;
3669 ugeth->oldspeed = 0;
3670 ugeth->oldduplex = -1;
3671
3672 phy_stop(ugeth->phydev);
3673 phy_start(ugeth->phydev);
3674
3675 napi_enable(&ugeth->napi);
29fb00e0 3676 netif_device_attach(ndev);
2394905f
AV		 3677
3678 return 0;
3679}
3680
3681#else
3682#define ucc_geth_suspend NULL
3683#define ucc_geth_resume NULL
3684#endif
3685
4e19b5c1 3686static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3687{
4e19b5c1 3688 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3689 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3690 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3691 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3692 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3693 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3694 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3695 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3696 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3697 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3698 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3699 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3700 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3701 return PHY_INTERFACE_MODE_RGMII_TXID;
3702 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3703 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3704 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9 3705 return PHY_INTERFACE_MODE_RTBI;
047584ce
HW		 3706 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3707 return PHY_INTERFACE_MODE_SGMII;
728de4c9
KP		 3708
3709 return PHY_INTERFACE_MODE_MII;
3710}
3711
d19b5149
SM		 3712static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3713{
3714 struct ucc_geth_private *ugeth = netdev_priv(dev);
3715
3716 if (!netif_running(dev))
3717 return -EINVAL;
3718
3719 if (!ugeth->phydev)
3720 return -ENODEV;
3721
28b04113 3722 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
d19b5149
SM		 3723}
3724
a9dbae78
JT		 3725static const struct net_device_ops ucc_geth_netdev_ops = {
3726 .ndo_open = ucc_geth_open,
3727 .ndo_stop = ucc_geth_close,
3728 .ndo_start_xmit = ucc_geth_start_xmit,
3729 .ndo_validate_addr = eth_validate_addr,
3d6593e9 3730 .ndo_set_mac_address = ucc_geth_set_mac_addr,
a9dbae78
JT		 3731 .ndo_change_mtu = eth_change_mtu,
3732 .ndo_set_multicast_list = ucc_geth_set_multi,
3733 .ndo_tx_timeout = ucc_geth_timeout,
d19b5149 3734 .ndo_do_ioctl = ucc_geth_ioctl,
a9dbae78
JT		 3735#ifdef CONFIG_NET_POLL_CONTROLLER
3736 .ndo_poll_controller = ucc_netpoll,
3737#endif
3738};
3739
74888760 3740static int ucc_geth_probe(struct platform_device* ofdev)
ce973b14 3741{
18a8e864 3742 struct device *device = &ofdev->dev;
61c7a080 3743 struct device_node *np = ofdev->dev.of_node;
ce973b14
LY		 3744 struct net_device *dev = NULL;
3745 struct ucc_geth_private *ugeth = NULL;
3746 struct ucc_geth_info *ug_info;
18a8e864 3747 struct resource res;
728de4c9 3748 int err, ucc_num, max_speed = 0;
18a8e864 3749 const unsigned int *prop;
9fb1e350 3750 const char *sprop;
9b4c7a4e 3751 const void *mac_addr;
728de4c9
KP		 3752 phy_interface_t phy_interface;
3753 static const int enet_to_speed[] = {
3754 SPEED_10, SPEED_10, SPEED_10,
3755 SPEED_100, SPEED_100, SPEED_100,
3756 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3757 };
3758 static const phy_interface_t enet_to_phy_interface[] = {
3759 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3760 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3761 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3762 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3763 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
047584ce 3764 PHY_INTERFACE_MODE_SGMII,
728de4c9 3765 };
ce973b14 3766
b39d66a8 3767 ugeth_vdbg("%s: IN", __func__);
ce973b14 3768
56626f33
AV		 3769 prop = of_get_property(np, "cell-index", NULL);
3770 if (!prop) {
3771 prop = of_get_property(np, "device-id", NULL);
3772 if (!prop)
3773 return -ENODEV;
3774 }
3775
18a8e864
LY		 3776 ucc_num = *prop - 1;
3777 if ((ucc_num < 0) || (ucc_num > 7))
3778 return -ENODEV;
3779
3780 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3781 if (ug_info == NULL) {
3782 if (netif_msg_probe(&debug))
3783 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3784 __func__, ucc_num);
890de95e
LY		 3785 return -ENODEV;
3786 }
3787
18a8e864 3788 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3789
9fb1e350
TT		 3790 sprop = of_get_property(np, "rx-clock-name", NULL);
3791 if (sprop) {
3792 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3793 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3794 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3795 printk(KERN_ERR
3796 "ucc_geth: invalid rx-clock-name property\n");
3797 return -EINVAL;
3798 }
3799 } else {
3800 prop = of_get_property(np, "rx-clock", NULL);
3801 if (!prop) {
3802 /* If both rx-clock-name and rx-clock are missing,
3803 we want to tell people to use rx-clock-name. */
3804 printk(KERN_ERR
3805 "ucc_geth: missing rx-clock-name property\n");
3806 return -EINVAL;
3807 }
3808 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3809 printk(KERN_ERR
3810 "ucc_geth: invalid rx-clock propperty\n");
3811 return -EINVAL;
3812 }
3813 ug_info->uf_info.rx_clock = *prop;
3814 }
3815
3816 sprop = of_get_property(np, "tx-clock-name", NULL);
3817 if (sprop) {
3818 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3819 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3820 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3821 printk(KERN_ERR
3822 "ucc_geth: invalid tx-clock-name property\n");
3823 return -EINVAL;
3824 }
3825 } else {
e410553f 3826 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3827 if (!prop) {
3828 printk(KERN_ERR
af901ca1 3829 "ucc_geth: missing tx-clock-name property\n");
9fb1e350
TT		 3830 return -EINVAL;
3831 }
3832 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3833 printk(KERN_ERR
3834 "ucc_geth: invalid tx-clock property\n");
3835 return -EINVAL;
3836 }
3837 ug_info->uf_info.tx_clock = *prop;
3838 }
3839
18a8e864
LY		 3840 err = of_address_to_resource(np, 0, &res);
3841 if (err)
3842 return -EINVAL;
3843
3844 ug_info->uf_info.regs = res.start;
3845 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3104a6ff
AV		 3846
3847 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
728de4c9 3848
fb1001f3
HW		 3849 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3850 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3851
728de4c9 3852 /* get the phy interface type, or default to MII */
4e19b5c1 3853 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3854 if (!prop) {
3855 /* handle interface property present in old trees */
3104a6ff 3856 prop = of_get_property(ug_info->phy_node, "interface", NULL);
4e19b5c1 3857 if (prop != NULL) {
728de4c9 3858 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3859 max_speed = enet_to_speed[*prop];
3860 } else
728de4c9
KP		 3861 phy_interface = PHY_INTERFACE_MODE_MII;
3862 } else {
3863 phy_interface = to_phy_interface((const char *)prop);
3864 }
3865
4e19b5c1
KP		 3866 /* get speed, or derive from PHY interface */
3867 if (max_speed == 0)
728de4c9
KP		 3868 switch (phy_interface) {
3869 case PHY_INTERFACE_MODE_GMII:
3870 case PHY_INTERFACE_MODE_RGMII:
3871 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3872 case PHY_INTERFACE_MODE_RGMII_RXID:
3873 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3874 case PHY_INTERFACE_MODE_TBI:
3875 case PHY_INTERFACE_MODE_RTBI:
047584ce 3876 case PHY_INTERFACE_MODE_SGMII:
728de4c9
KP		 3877 max_speed = SPEED_1000;
3878 break;
3879 default:
3880 max_speed = SPEED_100;
3881 break;
3882 }
728de4c9
KP		 3883
3884 if (max_speed == SPEED_1000) {
4e19b5c1 3885 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3886 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3887 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3888 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3889 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3890 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3891 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed 3892 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
674e4f93
HW		 3893
3894 /* If QE's snum number is 46 which means we need to support
3895 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3896 * more Threads to Rx.
3897 */
3898 if (qe_get_num_of_snums() == 46)
3899 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3900 else
3901 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3902 }
3903
890de95e 3904 if (netif_msg_probe(&debug))
2381a55c 3905 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d)\n",
890de95e
LY		 3906 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3907 ug_info->uf_info.irq);
ce973b14 3908
ce973b14
LY		 3909 /* Create an ethernet device instance */
3910 dev = alloc_etherdev(sizeof(*ugeth));
3911
3912 if (dev == NULL)
3913 return -ENOMEM;
3914
3915 ugeth = netdev_priv(dev);
3916 spin_lock_init(&ugeth->lock);
3917
80a9fad8
AV		 3918 /* Create CQs for hash tables */
3919 INIT_LIST_HEAD(&ugeth->group_hash_q);
3920 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3921
ce973b14
LY		 3922 dev_set_drvdata(device, dev);
3923
3924 /* Set the dev->base_addr to the gfar reg region */
3925 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3926
ce973b14
LY		 3927 SET_NETDEV_DEV(dev, device);
3928
3929 /* Fill in the dev structure */
ac421852 3930 uec_set_ethtool_ops(dev);
a9dbae78 3931 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3932 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3933 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3934 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3935 dev->mtu = 1500;
ce973b14 3936
890de95e 3937 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3938 ugeth->phy_interface = phy_interface;
3939 ugeth->max_speed = max_speed;
3940
ce973b14
LY		 3941 err = register_netdev(dev);
3942 if (err) {
890de95e
LY		 3943 if (netif_msg_probe(ugeth))
3944 ugeth_err("%s: Cannot register net device, aborting.",
3945 dev->name);
ce973b14
LY		 3946 free_netdev(dev);
3947 return err;
3948 }
3949
e9eb70c9 3950 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 3951 if (mac_addr)
3952 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 3953
728de4c9 3954 ugeth->ug_info = ug_info;
da1aa63e
AV		 3955 ugeth->dev = device;
3956 ugeth->ndev = dev;
b1c4a9dd 3957 ugeth->node = np;
728de4c9 3958
ce973b14
LY		 3959 return 0;
3960}
3961
2dc11581 3962static int ucc_geth_remove(struct platform_device* ofdev)
ce973b14 3963{
18a8e864 3964 struct device *device = &ofdev->dev;
ce973b14
LY		 3965 struct net_device *dev = dev_get_drvdata(device);
3966 struct ucc_geth_private *ugeth = netdev_priv(dev);
3967
80a9fad8 3968 unregister_netdev(dev);
ce973b14 3969 free_netdev(dev);
80a9fad8
AV		 3970 ucc_geth_memclean(ugeth);
3971 dev_set_drvdata(device, NULL);
ce973b14
LY		 3972
3973 return 0;
3974}
3975
18a8e864
LY		 3976static struct of_device_id ucc_geth_match[] = {
3977 {
3978 .type = "network",
3979 .compatible = "ucc_geth",
3980 },
3981 {},
3982};
3983
3984MODULE_DEVICE_TABLE(of, ucc_geth_match);
3985
74888760 3986static struct platform_driver ucc_geth_driver = {
4018294b
GL		 3987 .driver = {
3988 .name = DRV_NAME,
3989 .owner = THIS_MODULE,
3990 .of_match_table = ucc_geth_match,
3991 },
18a8e864
LY		 3992 .probe = ucc_geth_probe,
3993 .remove = ucc_geth_remove,
2394905f
AV		 3994 .suspend = ucc_geth_suspend,
3995 .resume = ucc_geth_resume,
ce973b14
LY		 3996};
3997
3998static int __init ucc_geth_init(void)
3999{
728de4c9
KP		 4000 int i, ret;
4001
890de95e
LY		 4002 if (netif_msg_drv(&debug))
4003 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 4004 for (i = 0; i < 8; i++)
4005 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4006 sizeof(ugeth_primary_info));
4007
74888760 4008 ret = platform_driver_register(&ucc_geth_driver);
728de4c9 4009
728de4c9 4010 return ret;
ce973b14
LY		 4011}
4012
4013static void __exit ucc_geth_exit(void)
4014{
74888760 4015 platform_driver_unregister(&ucc_geth_driver);
ce973b14
LY		 4016}
4017
4018module_init(ucc_geth_init);
4019module_exit(ucc_geth_exit);
4020
4021MODULE_AUTHOR("Freescale Semiconductor, Inc");
4022MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 4023MODULE_VERSION(DRV_VERSION);
ce973b14 4024MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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