Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / eeprom.h
CommitLineData
394cf0a1 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
394cf0a1
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3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef EEPROM_H
18#define EEPROM_H
19
5bb12791 20#include "../ath.h"
d3236553 21#include <net/cfg80211.h>
15c9ee7a 22#include "ar9003_eeprom.h"
3a702e49 23
394cf0a1
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24#define AH_USE_EEPROM 0x1
25
26#ifdef __BIG_ENDIAN
27#define AR5416_EEPROM_MAGIC 0x5aa5
28#else
29#define AR5416_EEPROM_MAGIC 0xa55a
30#endif
31
32#define CTRY_DEBUG 0x1ff
33#define CTRY_DEFAULT 0
34
35#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
36#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
37#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
38#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
39#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
40#define AR_EEPROM_EEPCAP_MAXQCU_S 4
41#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
42#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
43#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
44
45#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
46#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
47#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
48#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
49#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
50#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
51
52#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
53#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
54
55#define AR5416_EEPROM_MAGIC_OFFSET 0x0
56#define AR5416_EEPROM_S 2
57#define AR5416_EEPROM_OFFSET 0x2000
58#define AR5416_EEPROM_MAX 0xae0
59
60#define AR5416_EEPROM_START_ADDR \
61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
62
63#define SD_NO_CTL 0xE0
64#define NO_CTL 0xff
90487974 65#define CTL_MODE_M 0xf
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66#define CTL_11A 0
67#define CTL_11B 1
68#define CTL_11G 2
69#define CTL_2GHT20 5
70#define CTL_5GHT20 6
71#define CTL_2GHT40 7
72#define CTL_5GHT40 8
73
74#define EXT_ADDITIVE (0x8000)
75#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
76#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
77#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
78
79#define SUB_NUM_CTL_MODES_AT_5G_40 2
80#define SUB_NUM_CTL_MODES_AT_2G_40 3
81
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82#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
83#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
84
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85/*
86 * For AR9285 and later chipsets, the following bits are not being programmed
87 * in EEPROM and so need to be enabled always.
88 *
89 * Bit 0: en_fcc_mid
90 * Bit 1: en_jap_mid
91 * Bit 2: en_fcc_dfs_ht40
92 * Bit 3: en_jap_ht40
93 * Bit 4: en_jap_dfs_ht40
94 */
95#define AR9285_RDEXT_DEFAULT 0x1F
96
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97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100
355363fc 101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
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102#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
a42acef0 104#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
ac88b6ec 105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
d9ae96d9 106
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107#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
108#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
109#define AR_EEPROM_RFSILENT_POLARITY 0x0002
110#define AR_EEPROM_RFSILENT_POLARITY_S 1
111
112#define EEP_RFSILENT_ENABLED 0x0001
113#define EEP_RFSILENT_ENABLED_S 0
114#define EEP_RFSILENT_POLARITY 0x0002
115#define EEP_RFSILENT_POLARITY_S 1
116#define EEP_RFSILENT_GPIO_SEL 0x001c
117#define EEP_RFSILENT_GPIO_SEL_S 2
118
119#define AR5416_OPFLAGS_11A 0x01
120#define AR5416_OPFLAGS_11G 0x02
121#define AR5416_OPFLAGS_N_5G_HT40 0x04
122#define AR5416_OPFLAGS_N_2G_HT40 0x08
123#define AR5416_OPFLAGS_N_5G_HT20 0x10
124#define AR5416_OPFLAGS_N_2G_HT20 0x20
125
126#define AR5416_EEP_NO_BACK_VER 0x1
127#define AR5416_EEP_VER 0xE
128#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
129#define AR5416_EEP_MINOR_VER_2 0x2
130#define AR5416_EEP_MINOR_VER_3 0x3
131#define AR5416_EEP_MINOR_VER_7 0x7
132#define AR5416_EEP_MINOR_VER_9 0x9
133#define AR5416_EEP_MINOR_VER_16 0x10
134#define AR5416_EEP_MINOR_VER_17 0x11
135#define AR5416_EEP_MINOR_VER_19 0x13
136#define AR5416_EEP_MINOR_VER_20 0x14
e41f0bfc 137#define AR5416_EEP_MINOR_VER_21 0x15
06d0f066 138#define AR5416_EEP_MINOR_VER_22 0x16
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139
140#define AR5416_NUM_5G_CAL_PIERS 8
141#define AR5416_NUM_2G_CAL_PIERS 4
142#define AR5416_NUM_5G_20_TARGET_POWERS 8
143#define AR5416_NUM_5G_40_TARGET_POWERS 8
144#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
145#define AR5416_NUM_2G_20_TARGET_POWERS 4
146#define AR5416_NUM_2G_40_TARGET_POWERS 4
147#define AR5416_NUM_CTLS 24
148#define AR5416_NUM_BAND_EDGES 8
149#define AR5416_NUM_PD_GAINS 4
150#define AR5416_PD_GAINS_IN_MASK 4
151#define AR5416_PD_GAIN_ICEPTS 5
152#define AR5416_EEPROM_MODAL_SPURS 5
153#define AR5416_MAX_RATE_POWER 63
154#define AR5416_NUM_PDADC_VALUES 128
155#define AR5416_BCHAN_UNUSED 0xFF
156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
157#define AR5416_MAX_CHAINS 3
df23acaa 158#define AR9300_MAX_CHAINS 3
e41f0bfc 159#define AR5416_PWR_TABLE_OFFSET_DB -5
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160
161/* Rx gain type values */
162#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
163#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
164#define AR5416_EEP_RXGAIN_ORIG 2
165
166/* Tx gain type values */
167#define AR5416_EEP_TXGAIN_ORIGINAL 0
168#define AR5416_EEP_TXGAIN_HIGH_POWER 1
169
170#define AR5416_EEP4K_START_LOC 64
171#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
172#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
173#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
174#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
175#define AR5416_EEP4K_NUM_CTLS 12
176#define AR5416_EEP4K_NUM_BAND_EDGES 4
177#define AR5416_EEP4K_NUM_PD_GAINS 2
178#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
179#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
180#define AR5416_EEP4K_MAX_CHAINS 1
181
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182#define AR9280_TX_GAIN_TABLE_SIZE 22
183
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184#define AR9287_EEP_VER 0xE
185#define AR9287_EEP_VER_MINOR_MASK 0xFFF
186#define AR9287_EEP_MINOR_VER_1 0x1
187#define AR9287_EEP_MINOR_VER_2 0x2
188#define AR9287_EEP_MINOR_VER_3 0x3
189#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
190#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
191#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
192
193#define AR9287_EEP_START_LOC 128
ca6cff1f 194#define AR9287_HTC_EEP_START_LOC 256
ac88b6ec
VN
195#define AR9287_NUM_2G_CAL_PIERS 3
196#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
197#define AR9287_NUM_2G_20_TARGET_POWERS 3
198#define AR9287_NUM_2G_40_TARGET_POWERS 3
199#define AR9287_NUM_CTLS 12
200#define AR9287_NUM_BAND_EDGES 4
201#define AR9287_NUM_PD_GAINS 4
202#define AR9287_PD_GAINS_IN_MASK 4
203#define AR9287_PD_GAIN_ICEPTS 1
204#define AR9287_EEPROM_MODAL_SPURS 5
205#define AR9287_MAX_RATE_POWER 63
206#define AR9287_NUM_PDADC_VALUES 128
207#define AR9287_NUM_RATES 16
208#define AR9287_BCHAN_UNUSED 0xFF
209#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
210#define AR9287_OPFLAGS_11A 0x01
211#define AR9287_OPFLAGS_11G 0x02
212#define AR9287_OPFLAGS_2G_HT40 0x08
213#define AR9287_OPFLAGS_2G_HT20 0x20
214#define AR9287_OPFLAGS_5G_HT40 0x04
215#define AR9287_OPFLAGS_5G_HT20 0x10
216#define AR9287_EEPMISC_BIG_ENDIAN 0x01
217#define AR9287_EEPMISC_WOW 0x02
218#define AR9287_MAX_CHAINS 2
219#define AR9287_ANT_16S 32
220#define AR9287_custdatasize 20
221
222#define AR9287_NUM_ANT_CHAIN_FIELDS 6
223#define AR9287_NUM_ANT_COMMON_FIELDS 4
224#define AR9287_SIZE_ANT_CHAIN_FIELD 2
225#define AR9287_SIZE_ANT_COMMON_FIELD 4
226#define AR9287_ANT_CHAIN_MASK 0x3
227#define AR9287_ANT_COMMON_MASK 0xf
228#define AR9287_CHAIN_0_IDX 0
229#define AR9287_CHAIN_1_IDX 1
230#define AR9287_DATA_SZ 32
231
232#define AR9287_PWR_TABLE_OFFSET_DB -5
233
234#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
235
e702ba18
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236#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
237#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
238
f67e07eb
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239#define LNA_CTL_BUF_MODE BIT(0)
240#define LNA_CTL_ISEL_LO BIT(1)
241#define LNA_CTL_ISEL_HI BIT(2)
242#define LNA_CTL_BUF_IN BIT(3)
243#define LNA_CTL_FEM_BAND BIT(4)
244#define LNA_CTL_LOCAL_BIAS BIT(5)
245#define LNA_CTL_FORCE_XPA BIT(6)
246#define LNA_CTL_USE_ANT1 BIT(7)
247
394cf0a1
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248enum eeprom_param {
249 EEP_NFTHRESH_5,
250 EEP_NFTHRESH_2,
251 EEP_MAC_MSW,
252 EEP_MAC_MID,
253 EEP_MAC_LSW,
254 EEP_REG_0,
255 EEP_REG_1,
256 EEP_OP_CAP,
257 EEP_OP_MODE,
258 EEP_RF_SILENT,
259 EEP_OB_5,
260 EEP_DB_5,
261 EEP_OB_2,
262 EEP_DB_2,
263 EEP_MINOR_REV,
264 EEP_TX_MASK,
265 EEP_RX_MASK,
15c9ee7a 266 EEP_FSTCLK_5G,
394cf0a1 267 EEP_RXGAIN_TYPE,
8bd1d07f 268 EEP_OL_PWRCTRL,
15c9ee7a 269 EEP_TXGAIN_TYPE,
8bd1d07f 270 EEP_RC_CHAIN_MASK,
394cf0a1 271 EEP_DAC_HPWR_5G,
ac88b6ec
VN
272 EEP_FRAC_N_5G,
273 EEP_DEV_TYPE,
274 EEP_TEMPSENSE_SLOPE,
275 EEP_TEMPSENSE_SLOPE_PAL_ON,
15c9ee7a
SB
276 EEP_PWR_TABLE_OFFSET,
277 EEP_DRIVE_STRENGTH,
278 EEP_INTERNAL_REGULATOR,
4935250a
FF
279 EEP_SWREG,
280 EEP_PAPRD,
754dc536
VT
281 EEP_MODAL_VER,
282 EEP_ANT_DIV_CTL1,
ea066d5a 283 EEP_CHAIN_MASK_REDUCE
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284};
285
286enum ar5416_rates {
287 rate6mb, rate9mb, rate12mb, rate18mb,
288 rate24mb, rate36mb, rate48mb, rate54mb,
289 rate1l, rate2l, rate2s, rate5_5l,
290 rate5_5s, rate11l, rate11s, rateXr,
291 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
292 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
293 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
294 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
295 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
296 Ar5416RateSize
297};
298
299enum ath9k_hal_freq_band {
300 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
301 ATH9K_HAL_FREQ_BAND_2GHZ = 1
302};
303
304struct base_eep_header {
305 u16 length;
306 u16 checksum;
307 u16 version;
308 u8 opCapFlags;
309 u8 eepMisc;
310 u16 regDmn[2];
311 u8 macAddr[6];
312 u8 rxMask;
313 u8 txMask;
314 u16 rfSilent;
315 u16 blueToothOptions;
316 u16 deviceCap;
317 u32 binBuildNumber;
318 u8 deviceType;
319 u8 pwdclkind;
5b75d0fc
FF
320 u8 fastClk5g;
321 u8 divChain;
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322 u8 rxGainType;
323 u8 dacHiPwrMode_5G;
8bd1d07f 324 u8 openLoopPwrCntl;
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325 u8 dacLpMode;
326 u8 txGainType;
327 u8 rcChainMask;
328 u8 desiredScaleCCK;
e41f0bfc 329 u8 pwr_table_offset;
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330 u8 frac_n_5g;
331 u8 futureBase_3[21];
394cf0a1
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332} __packed;
333
334struct base_eep_header_4k {
335 u16 length;
336 u16 checksum;
337 u16 version;
338 u8 opCapFlags;
339 u8 eepMisc;
340 u16 regDmn[2];
341 u8 macAddr[6];
342 u8 rxMask;
343 u8 txMask;
344 u16 rfSilent;
345 u16 blueToothOptions;
346 u16 deviceCap;
347 u32 binBuildNumber;
348 u8 deviceType;
4e845168 349 u8 txGainType;
394cf0a1
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350} __packed;
351
352
353struct spur_chan {
354 u16 spurChan;
355 u8 spurRangeLow;
356 u8 spurRangeHigh;
357} __packed;
358
359struct modal_eep_header {
360 u32 antCtrlChain[AR5416_MAX_CHAINS];
361 u32 antCtrlCommon;
362 u8 antennaGainCh[AR5416_MAX_CHAINS];
363 u8 switchSettling;
364 u8 txRxAttenCh[AR5416_MAX_CHAINS];
365 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
366 u8 adcDesiredSize;
367 u8 pgaDesiredSize;
368 u8 xlnaGainCh[AR5416_MAX_CHAINS];
369 u8 txEndToXpaOff;
370 u8 txEndToRxOn;
371 u8 txFrameToXpaOn;
372 u8 thresh62;
373 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
374 u8 xpdGain;
375 u8 xpd;
376 u8 iqCalICh[AR5416_MAX_CHAINS];
377 u8 iqCalQCh[AR5416_MAX_CHAINS];
378 u8 pdGainOverlap;
379 u8 ob;
380 u8 db;
381 u8 xpaBiasLvl;
382 u8 pwrDecreaseFor2Chain;
383 u8 pwrDecreaseFor3Chain;
384 u8 txFrameToDataStart;
385 u8 txFrameToPaOn;
386 u8 ht40PowerIncForPdadc;
387 u8 bswAtten[AR5416_MAX_CHAINS];
388 u8 bswMargin[AR5416_MAX_CHAINS];
389 u8 swSettleHt40;
390 u8 xatten2Db[AR5416_MAX_CHAINS];
391 u8 xatten2Margin[AR5416_MAX_CHAINS];
392 u8 ob_ch1;
393 u8 db_ch1;
f67e07eb 394 u8 lna_ctl;
394cf0a1
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395 u8 miscBits;
396 u16 xpaBiasLvlFreq[3];
397 u8 futureModal[6];
398
399 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
400} __packed;
401
8bd1d07f
SB
402struct calDataPerFreqOpLoop {
403 u8 pwrPdg[2][5];
404 u8 vpdPdg[2][5];
405 u8 pcdac[2][5];
406 u8 empty[2][5];
407} __packed;
408
394cf0a1 409struct modal_eep_4k_header {
c16c9d06
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410 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
411 u32 antCtrlCommon;
412 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
413 u8 switchSettling;
414 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
415 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
416 u8 adcDesiredSize;
417 u8 pgaDesiredSize;
418 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
419 u8 txEndToXpaOff;
420 u8 txEndToRxOn;
421 u8 txFrameToXpaOn;
422 u8 thresh62;
423 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
424 u8 xpdGain;
425 u8 xpd;
426 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
427 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
428 u8 pdGainOverlap;
7f63845f
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429#ifdef __BIG_ENDIAN_BITFIELD
430 u8 ob_1:4, ob_0:4;
431 u8 db1_1:4, db1_0:4;
432#else
433 u8 ob_0:4, ob_1:4;
434 u8 db1_0:4, db1_1:4;
435#endif
c16c9d06
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436 u8 xpaBiasLvl;
437 u8 txFrameToDataStart;
438 u8 txFrameToPaOn;
439 u8 ht40PowerIncForPdadc;
440 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
441 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
442 u8 swSettleHt40;
443 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
444 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
7f63845f
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445#ifdef __BIG_ENDIAN_BITFIELD
446 u8 db2_1:4, db2_0:4;
447#else
448 u8 db2_0:4, db2_1:4;
449#endif
c16c9d06 450 u8 version;
7f63845f
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451#ifdef __BIG_ENDIAN_BITFIELD
452 u8 ob_3:4, ob_2:4;
453 u8 antdiv_ctl1:4, ob_4:4;
454 u8 db1_3:4, db1_2:4;
455 u8 antdiv_ctl2:4, db1_4:4;
456 u8 db2_2:4, db2_3:4;
457 u8 reserved:4, db2_4:4;
458#else
459 u8 ob_2:4, ob_3:4;
460 u8 ob_4:4, antdiv_ctl1:4;
461 u8 db1_2:4, db1_3:4;
462 u8 db1_4:4, antdiv_ctl2:4;
463 u8 db2_2:4, db2_3:4;
464 u8 db2_4:4, reserved:4;
465#endif
c16c9d06 466 u8 futureModal[4];
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467 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
468} __packed;
469
ac88b6ec 470struct base_eep_ar9287_header {
c16c9d06
S
471 u16 length;
472 u16 checksum;
473 u16 version;
474 u8 opCapFlags;
475 u8 eepMisc;
476 u16 regDmn[2];
477 u8 macAddr[6];
478 u8 rxMask;
479 u8 txMask;
480 u16 rfSilent;
481 u16 blueToothOptions;
482 u16 deviceCap;
483 u32 binBuildNumber;
484 u8 deviceType;
485 u8 openLoopPwrCntl;
486 int8_t pwrTableOffset;
487 int8_t tempSensSlope;
488 int8_t tempSensSlopePalOn;
489 u8 futureBase[29];
ac88b6ec
VN
490} __packed;
491
492struct modal_eep_ar9287_header {
c16c9d06
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493 u32 antCtrlChain[AR9287_MAX_CHAINS];
494 u32 antCtrlCommon;
495 int8_t antennaGainCh[AR9287_MAX_CHAINS];
496 u8 switchSettling;
497 u8 txRxAttenCh[AR9287_MAX_CHAINS];
498 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
499 int8_t adcDesiredSize;
500 u8 txEndToXpaOff;
501 u8 txEndToRxOn;
502 u8 txFrameToXpaOn;
503 u8 thresh62;
504 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
505 u8 xpdGain;
506 u8 xpd;
507 int8_t iqCalICh[AR9287_MAX_CHAINS];
508 int8_t iqCalQCh[AR9287_MAX_CHAINS];
509 u8 pdGainOverlap;
510 u8 xpaBiasLvl;
511 u8 txFrameToDataStart;
512 u8 txFrameToPaOn;
513 u8 ht40PowerIncForPdadc;
514 u8 bswAtten[AR9287_MAX_CHAINS];
515 u8 bswMargin[AR9287_MAX_CHAINS];
516 u8 swSettleHt40;
517 u8 version;
518 u8 db1;
519 u8 db2;
520 u8 ob_cck;
521 u8 ob_psk;
522 u8 ob_qam;
523 u8 ob_pal_off;
524 u8 futureModal[30];
525 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
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526} __packed;
527
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528struct cal_data_per_freq {
529 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
530 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
531} __packed;
532
533struct cal_data_per_freq_4k {
534 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
535 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
536} __packed;
537
538struct cal_target_power_leg {
539 u8 bChannel;
540 u8 tPow2x[4];
541} __packed;
542
543struct cal_target_power_ht {
544 u8 bChannel;
545 u8 tPow2x[8];
546} __packed;
547
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548struct cal_ctl_edges {
549 u8 bChannel;
e702ba18 550 u8 ctl;
394cf0a1 551} __packed;
394cf0a1 552
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553struct cal_data_op_loop_ar9287 {
554 u8 pwrPdg[2][5];
555 u8 vpdPdg[2][5];
556 u8 pcdac[2][5];
557 u8 empty[2][5];
558} __packed;
559
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560struct cal_data_per_freq_ar9287 {
561 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
562 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
563} __packed;
564
565union cal_data_per_freq_ar9287_u {
566 struct cal_data_op_loop_ar9287 calDataOpen;
567 struct cal_data_per_freq_ar9287 calDataClose;
568} __packed;
569
570struct cal_ctl_data_ar9287 {
571 struct cal_ctl_edges
572 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
573} __packed;
574
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575struct cal_ctl_data {
576 struct cal_ctl_edges
577 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
578} __packed;
579
580struct cal_ctl_data_4k {
581 struct cal_ctl_edges
582 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
583} __packed;
584
585struct ar5416_eeprom_def {
586 struct base_eep_header baseEepHeader;
587 u8 custData[64];
588 struct modal_eep_header modalHeader[2];
589 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
590 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
591 struct cal_data_per_freq
592 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
593 struct cal_data_per_freq
594 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
595 struct cal_target_power_leg
596 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
597 struct cal_target_power_ht
598 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
599 struct cal_target_power_ht
600 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
601 struct cal_target_power_leg
602 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
603 struct cal_target_power_leg
604 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
605 struct cal_target_power_ht
606 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
607 struct cal_target_power_ht
608 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
609 u8 ctlIndex[AR5416_NUM_CTLS];
610 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
611 u8 padding;
612} __packed;
613
614struct ar5416_eeprom_4k {
615 struct base_eep_header_4k baseEepHeader;
616 u8 custData[20];
617 struct modal_eep_4k_header modalHeader;
618 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
619 struct cal_data_per_freq_4k
620 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
621 struct cal_target_power_leg
622 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
623 struct cal_target_power_leg
624 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
625 struct cal_target_power_ht
626 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
627 struct cal_target_power_ht
628 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
629 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
630 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
631 u8 padding;
632} __packed;
633
475f5989 634struct ar9287_eeprom {
c16c9d06 635 struct base_eep_ar9287_header baseEepHeader;
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636 u8 custData[AR9287_DATA_SZ];
637 struct modal_eep_ar9287_header modalHeader;
638 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
639 union cal_data_per_freq_ar9287_u
c16c9d06 640 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
ac88b6ec 641 struct cal_target_power_leg
c16c9d06 642 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
ac88b6ec 643 struct cal_target_power_leg
c16c9d06 644 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
ac88b6ec 645 struct cal_target_power_ht
c16c9d06 646 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
ac88b6ec 647 struct cal_target_power_ht
c16c9d06 648 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
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649 u8 ctlIndex[AR9287_NUM_CTLS];
650 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
651 u8 padding;
652} __packed;
653
394cf0a1 654enum reg_ext_bitmap {
ebb90cfc 655 REG_EXT_FCC_MIDBAND = 0,
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656 REG_EXT_JAPAN_MIDBAND = 1,
657 REG_EXT_FCC_DFS_HT40 = 2,
658 REG_EXT_JAPAN_NONDFS_HT40 = 3,
659 REG_EXT_JAPAN_DFS_HT40 = 4
660};
661
662struct ath9k_country_entry {
663 u16 countryCode;
664 u16 regDmnEnum;
665 u16 regDmn5G;
666 u16 regDmn2G;
667 u8 isMultidomain;
668 u8 iso[3];
669};
670
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671struct eeprom_ops {
672 int (*check_eeprom)(struct ath_hw *hw);
673 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
674 bool (*fill_eeprom)(struct ath_hw *hw);
675 int (*get_eeprom_ver)(struct ath_hw *hw);
676 int (*get_eeprom_rev)(struct ath_hw *hw);
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677 u8 (*get_num_ant_config)(struct ath_hw *hw,
678 enum ath9k_hal_freq_band band);
601e0cb1 679 u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
e153789d 680 struct ath9k_channel *chan);
d6509151 681 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
e153789d 682 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
8fbff4b8 683 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
e153789d 684 u16 cfgCtl, u8 twiceAntennaReduction,
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685 u8 twiceMaxRegulatoryPower, u8 powerLimit,
686 bool test);
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687 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
688};
689
79d7f4bc 690void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
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691void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
692 u32 shift, u32 val);
693int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
694 int16_t targetLeft,
695 int16_t targetRight);
696bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
697 u16 *indexL, u16 *indexR);
5bb12791 698bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
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699void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
700 u8 *pVpdList, u16 numIntercepts,
701 u8 *pRetVpdList);
702void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
703 struct ath9k_channel *chan,
704 struct cal_target_power_leg *powInfo,
705 u16 numChannels,
706 struct cal_target_power_leg *pNewPower,
707 u16 numRates, bool isExtTarget);
708void ath9k_hw_get_target_powers(struct ath_hw *ah,
709 struct ath9k_channel *chan,
710 struct cal_target_power_ht *powInfo,
711 u16 numChannels,
712 struct cal_target_power_ht *pNewPower,
713 u16 numRates, bool isHt40Target);
714u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
715 bool is2GHz, int num_band_edges);
a55f8588 716void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
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717int ath9k_hw_eeprom_init(struct ath_hw *ah);
718
394cf0a1 719#define ar5416_get_ntxchains(_txchainmask) \
f74df6fb 720 (((_txchainmask >> 2) & 1) + \
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721 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
722
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723extern const struct eeprom_ops eep_def_ops;
724extern const struct eeprom_ops eep_4k_ops;
0b8f6f2b 725extern const struct eeprom_ops eep_ar9287_ops;
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726extern const struct eeprom_ops eep_ar9287_ops;
727extern const struct eeprom_ops eep_ar9300_ops;
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728
729#endif /* EEPROM_H */
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