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Ath5k: suspend/resume fixes
[deliverable/linux.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
274c7c36 46#include <linux/hardirq.h>
fa1c114f 47#include <linux/if.h>
274c7c36 48#include <linux/io.h>
fa1c114f
JS		 49#include <linux/netdevice.h>
50#include <linux/cache.h>
51#include <linux/pci.h>
52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
62
fa1c114f
JS		 63static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
64
65
66/******************\
67* Internal defines *
68\******************/
69
70/* Module info */
71MODULE_AUTHOR("Jiri Slaby");
72MODULE_AUTHOR("Nick Kossifidis");
73MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
74MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
75MODULE_LICENSE("Dual BSD/GPL");
400ec45a 76MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 77
78
79/* Known PCI ids */
80static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
81 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
82 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
83 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
84 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
85 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
86 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
87 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
89 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
96 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
97 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
98 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
99 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
100 { 0 }
101};
102MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
103
104/* Known SREVs */
105static struct ath5k_srev_name srev_names[] = {
106 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
107 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
108 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
109 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
110 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
111 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
112 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
113 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 114 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
115 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 116 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
117 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
118 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
119 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
120 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
121 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 122 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 123 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
124 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
125 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 132 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
133 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
134 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
135 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
136};
137
138/*
139 * Prototypes - PCI stack related functions
140 */
141static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
142 const struct pci_device_id *id);
143static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
144#ifdef CONFIG_PM
145static int ath5k_pci_suspend(struct pci_dev *pdev,
146 pm_message_t state);
147static int ath5k_pci_resume(struct pci_dev *pdev);
148#else
149#define ath5k_pci_suspend NULL
150#define ath5k_pci_resume NULL
151#endif /* CONFIG_PM */
152
04a9e451 153static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 154 .name = "ath5k_pci",
155 .id_table = ath5k_pci_id_table,
156 .probe = ath5k_pci_probe,
157 .remove = __devexit_p(ath5k_pci_remove),
158 .suspend = ath5k_pci_suspend,
159 .resume = ath5k_pci_resume,
160};
161
162
163
164/*
165 * Prototypes - MAC 802.11 stack related functions
166 */
e039fa4a 167static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
fa1c114f
JS		 168static int ath5k_reset(struct ieee80211_hw *hw);
169static int ath5k_start(struct ieee80211_hw *hw);
170static void ath5k_stop(struct ieee80211_hw *hw);
171static int ath5k_add_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173static void ath5k_remove_interface(struct ieee80211_hw *hw,
174 struct ieee80211_if_init_conf *conf);
175static int ath5k_config(struct ieee80211_hw *hw,
176 struct ieee80211_conf *conf);
32bfd35d
JB		 177static int ath5k_config_interface(struct ieee80211_hw *hw,
178 struct ieee80211_vif *vif,
fa1c114f
JS		 179 struct ieee80211_if_conf *conf);
180static void ath5k_configure_filter(struct ieee80211_hw *hw,
181 unsigned int changed_flags,
182 unsigned int *new_flags,
183 int mc_count, struct dev_mc_list *mclist);
184static int ath5k_set_key(struct ieee80211_hw *hw,
185 enum set_key_cmd cmd,
186 const u8 *local_addr, const u8 *addr,
187 struct ieee80211_key_conf *key);
188static int ath5k_get_stats(struct ieee80211_hw *hw,
189 struct ieee80211_low_level_stats *stats);
190static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
191 struct ieee80211_tx_queue_stats *stats);
192static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
193static void ath5k_reset_tsf(struct ieee80211_hw *hw);
194static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 195 struct sk_buff *skb);
fa1c114f
JS		 196
197static struct ieee80211_ops ath5k_hw_ops = {
198 .tx = ath5k_tx,
199 .start = ath5k_start,
200 .stop = ath5k_stop,
201 .add_interface = ath5k_add_interface,
202 .remove_interface = ath5k_remove_interface,
203 .config = ath5k_config,
204 .config_interface = ath5k_config_interface,
205 .configure_filter = ath5k_configure_filter,
206 .set_key = ath5k_set_key,
207 .get_stats = ath5k_get_stats,
208 .conf_tx = NULL,
209 .get_tx_stats = ath5k_get_tx_stats,
210 .get_tsf = ath5k_get_tsf,
211 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 212};
213
214/*
215 * Prototypes - Internal functions
216 */
217/* Attach detach */
218static int ath5k_attach(struct pci_dev *pdev,
219 struct ieee80211_hw *hw);
220static void ath5k_detach(struct pci_dev *pdev,
221 struct ieee80211_hw *hw);
222/* Channel/mode setup */
223static inline short ath5k_ieee2mhz(short chan);
224static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
225 const struct ath5k_rate_table *rt,
226 unsigned int max);
227static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
228 struct ieee80211_channel *channels,
229 unsigned int mode,
230 unsigned int max);
231static int ath5k_getchannels(struct ieee80211_hw *hw);
232static int ath5k_chan_set(struct ath5k_softc *sc,
233 struct ieee80211_channel *chan);
234static void ath5k_setcurmode(struct ath5k_softc *sc,
235 unsigned int mode);
236static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d
LR		 237static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
238
fa1c114f
JS		 239/* Descriptor setup */
240static int ath5k_desc_alloc(struct ath5k_softc *sc,
241 struct pci_dev *pdev);
242static void ath5k_desc_free(struct ath5k_softc *sc,
243 struct pci_dev *pdev);
244/* Buffers setup */
245static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
246 struct ath5k_buf *bf);
247static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 248 struct ath5k_buf *bf);
fa1c114f
JS		 249static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
250 struct ath5k_buf *bf)
251{
252 BUG_ON(!bf);
253 if (!bf->skb)
254 return;
255 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
256 PCI_DMA_TODEVICE);
257 dev_kfree_skb(bf->skb);
258 bf->skb = NULL;
259}
260
261/* Queues setup */
262static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
263 int qtype, int subtype);
264static int ath5k_beaconq_setup(struct ath5k_hw *ah);
265static int ath5k_beaconq_config(struct ath5k_softc *sc);
266static void ath5k_txq_drainq(struct ath5k_softc *sc,
267 struct ath5k_txq *txq);
268static void ath5k_txq_cleanup(struct ath5k_softc *sc);
269static void ath5k_txq_release(struct ath5k_softc *sc);
270/* Rx handling */
271static int ath5k_rx_start(struct ath5k_softc *sc);
272static void ath5k_rx_stop(struct ath5k_softc *sc);
273static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
274 struct ath5k_desc *ds,
b47f407b
BR		 275 struct sk_buff *skb,
276 struct ath5k_rx_status *rs);
fa1c114f
JS		 277static void ath5k_tasklet_rx(unsigned long data);
278/* Tx handling */
279static void ath5k_tx_processq(struct ath5k_softc *sc,
280 struct ath5k_txq *txq);
281static void ath5k_tasklet_tx(unsigned long data);
282/* Beacon handling */
283static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 284 struct ath5k_buf *bf);
fa1c114f
JS		 285static void ath5k_beacon_send(struct ath5k_softc *sc);
286static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 287static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 288
289static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
290{
291 u64 tsf = ath5k_hw_get_tsf64(ah);
292
293 if ((tsf & 0x7fff) < rstamp)
294 tsf -= 0x8000;
295
296 return (tsf & ~0x7fff) | rstamp;
297}
298
299/* Interrupt handling */
300static int ath5k_init(struct ath5k_softc *sc);
301static int ath5k_stop_locked(struct ath5k_softc *sc);
302static int ath5k_stop_hw(struct ath5k_softc *sc);
303static irqreturn_t ath5k_intr(int irq, void *dev_id);
304static void ath5k_tasklet_reset(unsigned long data);
305
306static void ath5k_calibrate(unsigned long data);
307/* LED functions */
3a078876
BC		 308static int ath5k_init_leds(struct ath5k_softc *sc);
309static void ath5k_led_enable(struct ath5k_softc *sc);
310static void ath5k_led_off(struct ath5k_softc *sc);
311static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 312
313/*
314 * Module init/exit functions
315 */
316static int __init
317init_ath5k_pci(void)
318{
319 int ret;
320
321 ath5k_debug_init();
322
04a9e451 323 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 324 if (ret) {
325 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
326 return ret;
327 }
328
329 return 0;
330}
331
332static void __exit
333exit_ath5k_pci(void)
334{
04a9e451 335 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 336
337 ath5k_debug_finish();
338}
339
340module_init(init_ath5k_pci);
341module_exit(exit_ath5k_pci);
342
343
344/********************\
345* PCI Initialization *
346\********************/
347
348static const char *
349ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
350{
351 const char *name = "xxxxx";
352 unsigned int i;
353
354 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
355 if (srev_names[i].sr_type != type)
356 continue;
357 if ((val & 0xff) < srev_names[i + 1].sr_val) {
358 name = srev_names[i].sr_name;
359 break;
360 }
361 }
362
363 return name;
364}
365
366static int __devinit
367ath5k_pci_probe(struct pci_dev *pdev,
368 const struct pci_device_id *id)
369{
370 void __iomem *mem;
371 struct ath5k_softc *sc;
372 struct ieee80211_hw *hw;
373 int ret;
374 u8 csz;
375
376 ret = pci_enable_device(pdev);
377 if (ret) {
378 dev_err(&pdev->dev, "can't enable device\n");
379 goto err;
380 }
381
382 /* XXX 32-bit addressing only */
383 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
384 if (ret) {
385 dev_err(&pdev->dev, "32-bit DMA not available\n");
386 goto err_dis;
387 }
388
389 /*
390 * Cache line size is used to size and align various
391 * structures used to communicate with the hardware.
392 */
393 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
394 if (csz == 0) {
395 /*
396 * Linux 2.4.18 (at least) writes the cache line size
397 * register as a 16-bit wide register which is wrong.
398 * We must have this setup properly for rx buffer
399 * DMA to work so force a reasonable value here if it
400 * comes up zero.
401 */
402 csz = L1_CACHE_BYTES / sizeof(u32);
403 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
404 }
405 /*
406 * The default setting of latency timer yields poor results,
407 * set it to the value used by other systems. It may be worth
408 * tweaking this setting more.
409 */
410 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
411
412 /* Enable bus mastering */
413 pci_set_master(pdev);
414
415 /*
416 * Disable the RETRY_TIMEOUT register (0x41) to keep
417 * PCI Tx retries from interfering with C3 CPU state.
418 */
419 pci_write_config_byte(pdev, 0x41, 0);
420
421 ret = pci_request_region(pdev, 0, "ath5k");
422 if (ret) {
423 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
424 goto err_dis;
425 }
426
427 mem = pci_iomap(pdev, 0, 0);
428 if (!mem) {
429 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
430 ret = -EIO;
431 goto err_reg;
432 }
433
434 /*
435 * Allocate hw (mac80211 main struct)
436 * and hw->priv (driver private data)
437 */
438 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
439 if (hw == NULL) {
440 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
441 ret = -ENOMEM;
442 goto err_map;
443 }
444
445 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
446
447 /* Initialize driver private data */
448 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 449 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
450 IEEE80211_HW_SIGNAL_DBM |
451 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 452 hw->extra_tx_headroom = 2;
453 hw->channel_change_time = 5000;
fa1c114f
JS		 454 sc = hw->priv;
455 sc->hw = hw;
456 sc->pdev = pdev;
457
458 ath5k_debug_init_device(sc);
459
460 /*
461 * Mark the device as detached to avoid processing
462 * interrupts until setup is complete.
463 */
464 __set_bit(ATH_STAT_INVALID, sc->status);
465
466 sc->iobase = mem; /* So we can unmap it on detach */
467 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
468 sc->opmode = IEEE80211_IF_TYPE_STA;
469 mutex_init(&sc->lock);
470 spin_lock_init(&sc->rxbuflock);
471 spin_lock_init(&sc->txbuflock);
472
473 /* Set private data */
474 pci_set_drvdata(pdev, hw);
475
476 /* Enable msi for devices that support it */
477 pci_enable_msi(pdev);
478
479 /* Setup interrupt handler */
480 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
481 if (ret) {
482 ATH5K_ERR(sc, "request_irq failed\n");
483 goto err_free;
484 }
485
486 /* Initialize device */
487 sc->ah = ath5k_hw_attach(sc, id->driver_data);
488 if (IS_ERR(sc->ah)) {
489 ret = PTR_ERR(sc->ah);
490 goto err_irq;
491 }
492
493 /* Finish private driver data initialization */
494 ret = ath5k_attach(pdev, hw);
495 if (ret)
496 goto err_ah;
497
498 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
499 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
500 sc->ah->ah_mac_srev,
501 sc->ah->ah_phy_revision);
502
400ec45a 503 if (!sc->ah->ah_single_chip) {
fa1c114f 504 /* Single chip radio (!RF5111) */
400ec45a
LR		 505 if (sc->ah->ah_radio_5ghz_revision &&
506 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 507 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 508 if (!test_bit(AR5K_MODE_11A,
509 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 510 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 511 ath5k_chip_name(AR5K_VERSION_RAD,
512 sc->ah->ah_radio_5ghz_revision),
513 sc->ah->ah_radio_5ghz_revision);
514 /* No 2GHz support (5110 and some
515 * 5Ghz only cards) -> report 5Ghz radio */
516 } else if (!test_bit(AR5K_MODE_11B,
517 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 518 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 519 ath5k_chip_name(AR5K_VERSION_RAD,
520 sc->ah->ah_radio_5ghz_revision),
521 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 522 /* Multiband radio */
523 } else {
524 ATH5K_INFO(sc, "RF%s multiband radio found"
525 " (0x%x)\n",
400ec45a
LR		 526 ath5k_chip_name(AR5K_VERSION_RAD,
527 sc->ah->ah_radio_5ghz_revision),
528 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 529 }
530 }
400ec45a
LR		 531 /* Multi chip radio (RF5111 - RF2111) ->
532 * report both 2GHz/5GHz radios */
533 else if (sc->ah->ah_radio_5ghz_revision &&
534 sc->ah->ah_radio_2ghz_revision){
fa1c114f 535 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 536 ath5k_chip_name(AR5K_VERSION_RAD,
537 sc->ah->ah_radio_5ghz_revision),
538 sc->ah->ah_radio_5ghz_revision);
fa1c114f 539 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 540 ath5k_chip_name(AR5K_VERSION_RAD,
541 sc->ah->ah_radio_2ghz_revision),
542 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 543 }
544 }
545
546
547 /* ready to process interrupts */
548 __clear_bit(ATH_STAT_INVALID, sc->status);
549
550 return 0;
551err_ah:
552 ath5k_hw_detach(sc->ah);
553err_irq:
554 free_irq(pdev->irq, sc);
555err_free:
556 pci_disable_msi(pdev);
557 ieee80211_free_hw(hw);
558err_map:
559 pci_iounmap(pdev, mem);
560err_reg:
561 pci_release_region(pdev, 0);
562err_dis:
563 pci_disable_device(pdev);
564err:
565 return ret;
566}
567
568static void __devexit
569ath5k_pci_remove(struct pci_dev *pdev)
570{
571 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
572 struct ath5k_softc *sc = hw->priv;
573
574 ath5k_debug_finish_device(sc);
575 ath5k_detach(pdev, hw);
576 ath5k_hw_detach(sc->ah);
577 free_irq(pdev->irq, sc);
578 pci_disable_msi(pdev);
579 pci_iounmap(pdev, sc->iobase);
580 pci_release_region(pdev, 0);
581 pci_disable_device(pdev);
582 ieee80211_free_hw(hw);
583}
584
585#ifdef CONFIG_PM
586static int
587ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
588{
589 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
590 struct ath5k_softc *sc = hw->priv;
591
3a078876 592 ath5k_led_off(sc);
fa1c114f
JS		 593
594 ath5k_stop_hw(sc);
3e4242b9
JS		 595
596 free_irq(pdev->irq, sc);
597 pci_disable_msi(pdev);
fa1c114f
JS		 598 pci_save_state(pdev);
599 pci_disable_device(pdev);
600 pci_set_power_state(pdev, PCI_D3hot);
601
602 return 0;
603}
604
605static int
606ath5k_pci_resume(struct pci_dev *pdev)
607{
608 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
609 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 610 struct ath5k_hw *ah = sc->ah;
611 int i, err;
fa1c114f 612
3e4242b9 613 pci_restore_state(pdev);
fa1c114f
JS		 614
615 err = pci_enable_device(pdev);
616 if (err)
617 return err;
618
fa1c114f
JS		 619 /*
620 * Suspend/Resume resets the PCI configuration space, so we have to
621 * re-disable the RETRY_TIMEOUT register (0x41) to keep
622 * PCI Tx retries from interfering with C3 CPU state
623 */
624 pci_write_config_byte(pdev, 0x41, 0);
625
3e4242b9
JS		 626 pci_enable_msi(pdev);
627
628 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
629 if (err) {
630 ATH5K_ERR(sc, "request_irq failed\n");
631 goto err_msi;
632 }
633
634 err = ath5k_init(sc);
635 if (err)
636 goto err_irq;
3a078876 637 ath5k_led_enable(sc);
fa1c114f 638
247ae449
JL		 639 /*
640 * Reset the key cache since some parts do not
641 * reset the contents on initial power up or resume.
642 *
643 * FIXME: This may need to be revisited when mac80211 becomes
644 * aware of suspend/resume.
645 */
646 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
647 ath5k_hw_reset_key(ah, i);
648
fa1c114f 649 return 0;
3e4242b9
JS		 650err_irq:
651 free_irq(pdev->irq, sc);
652err_msi:
653 pci_disable_msi(pdev);
654 pci_disable_device(pdev);
655 return err;
fa1c114f
JS		 656}
657#endif /* CONFIG_PM */
658
659
660
661/***********************\
662* Driver Initialization *
663\***********************/
664
665static int
666ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
667{
668 struct ath5k_softc *sc = hw->priv;
669 struct ath5k_hw *ah = sc->ah;
670 u8 mac[ETH_ALEN];
671 unsigned int i;
672 int ret;
673
674 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
675
676 /*
677 * Check if the MAC has multi-rate retry support.
678 * We do this by trying to setup a fake extended
679 * descriptor. MAC's that don't have support will
680 * return false w/o doing anything. MAC's that do
681 * support it will return true w/o doing anything.
682 */
b9887638
JS		 683 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
684 if (ret < 0)
685 goto err;
686 if (ret > 0)
fa1c114f
JS		 687 __set_bit(ATH_STAT_MRRETRY, sc->status);
688
689 /*
690 * Reset the key cache since some parts do not
691 * reset the contents on initial power up.
692 */
c65638a7 693 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 694 ath5k_hw_reset_key(ah, i);
695
696 /*
697 * Collect the channel list. The 802.11 layer
698 * is resposible for filtering this list based
699 * on settings like the phy mode and regulatory
700 * domain restrictions.
701 */
702 ret = ath5k_getchannels(hw);
703 if (ret) {
704 ATH5K_ERR(sc, "can't get channels\n");
705 goto err;
706 }
707
d8ee398d
LR		 708 /* Set *_rates so we can map hw rate index */
709 ath5k_set_total_hw_rates(sc);
710
fa1c114f 711 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 712 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
713 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 714 else
d8ee398d 715 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 716
717 /*
718 * Allocate tx+rx descriptors and populate the lists.
719 */
720 ret = ath5k_desc_alloc(sc, pdev);
721 if (ret) {
722 ATH5K_ERR(sc, "can't allocate descriptors\n");
723 goto err;
724 }
725
726 /*
727 * Allocate hardware transmit queues: one queue for
728 * beacon frames and one data queue for each QoS
729 * priority. Note that hw functions handle reseting
730 * these queues at the needed time.
731 */
732 ret = ath5k_beaconq_setup(ah);
733 if (ret < 0) {
734 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
735 goto err_desc;
736 }
737 sc->bhalq = ret;
738
739 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
740 if (IS_ERR(sc->txq)) {
741 ATH5K_ERR(sc, "can't setup xmit queue\n");
742 ret = PTR_ERR(sc->txq);
743 goto err_bhal;
744 }
745
746 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
747 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
748 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
749 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 750
751 ath5k_hw_get_lladdr(ah, mac);
752 SET_IEEE80211_PERM_ADDR(hw, mac);
753 /* All MAC address bits matter for ACKs */
754 memset(sc->bssidmask, 0xff, ETH_ALEN);
755 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
756
757 ret = ieee80211_register_hw(hw);
758 if (ret) {
759 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
760 goto err_queues;
761 }
762
3a078876
BC		 763 ath5k_init_leds(sc);
764
fa1c114f
JS		 765 return 0;
766err_queues:
767 ath5k_txq_release(sc);
768err_bhal:
769 ath5k_hw_release_tx_queue(ah, sc->bhalq);
770err_desc:
771 ath5k_desc_free(sc, pdev);
772err:
773 return ret;
774}
775
776static void
777ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
778{
779 struct ath5k_softc *sc = hw->priv;
780
781 /*
782 * NB: the order of these is important:
783 * o call the 802.11 layer before detaching ath5k_hw to
784 * insure callbacks into the driver to delete global
785 * key cache entries can be handled
786 * o reclaim the tx queue data structures after calling
787 * the 802.11 layer as we'll get called back to reclaim
788 * node state and potentially want to use them
789 * o to cleanup the tx queues the hal is called, so detach
790 * it last
791 * XXX: ??? detach ath5k_hw ???
792 * Other than that, it's straightforward...
793 */
794 ieee80211_unregister_hw(hw);
795 ath5k_desc_free(sc, pdev);
796 ath5k_txq_release(sc);
797 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 798 ath5k_unregister_leds(sc);
fa1c114f
JS		 799
800 /*
801 * NB: can't reclaim these until after ieee80211_ifdetach
802 * returns because we'll get called back to reclaim node
803 * state and potentially want to use them.
804 */
805}
806
807
808
809
810/********************\
811* Channel/mode setup *
812\********************/
813
814/*
815 * Convert IEEE channel number to MHz frequency.
816 */
817static inline short
818ath5k_ieee2mhz(short chan)
819{
820 if (chan <= 14 || chan >= 27)
821 return ieee80211chan2mhz(chan);
822 else
823 return 2212 + chan * 20;
824}
825
826static unsigned int
827ath5k_copy_rates(struct ieee80211_rate *rates,
828 const struct ath5k_rate_table *rt,
829 unsigned int max)
830{
831 unsigned int i, count;
832
833 if (rt == NULL)
834 return 0;
835
836 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
d8ee398d
LR		 837 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
838 rates[count].hw_value = rt->rates[i].rate_code;
839 rates[count].flags = rt->rates[i].modulation;
fa1c114f
JS		 840 count++;
841 max--;
842 }
843
844 return count;
845}
846
847static unsigned int
848ath5k_copy_channels(struct ath5k_hw *ah,
849 struct ieee80211_channel *channels,
850 unsigned int mode,
851 unsigned int max)
852{
d8ee398d 853 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 854
855 if (!test_bit(mode, ah->ah_modes))
856 return 0;
857
fa1c114f 858 switch (mode) {
d8ee398d
LR		 859 case AR5K_MODE_11A:
860 case AR5K_MODE_11A_TURBO:
fa1c114f 861 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 862 size = 220 ;
fa1c114f
JS		 863 chfreq = CHANNEL_5GHZ;
864 break;
d8ee398d
LR		 865 case AR5K_MODE_11B:
866 case AR5K_MODE_11G:
867 case AR5K_MODE_11G_TURBO:
868 size = 26;
fa1c114f
JS		 869 chfreq = CHANNEL_2GHZ;
870 break;
871 default:
872 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
873 return 0;
874 }
875
876 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 877 ch = i + 1 ;
878 freq = ath5k_ieee2mhz(ch);
fa1c114f 879
d8ee398d
LR		 880 /* Check if channel is supported by the chipset */
881 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 882 continue;
883
d8ee398d
LR		 884 /* Write channel info and increment counter */
885 channels[count].center_freq = freq;
a3f4b914
LR		 886 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
887 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 888 switch (mode) {
889 case AR5K_MODE_11A:
890 case AR5K_MODE_11G:
891 channels[count].hw_value = chfreq | CHANNEL_OFDM;
892 break;
893 case AR5K_MODE_11A_TURBO:
894 case AR5K_MODE_11G_TURBO:
895 channels[count].hw_value = chfreq |
896 CHANNEL_OFDM | CHANNEL_TURBO;
897 break;
898 case AR5K_MODE_11B:
d8ee398d
LR		 899 channels[count].hw_value = CHANNEL_B;
900 }
fa1c114f 901
fa1c114f
JS		 902 count++;
903 max--;
904 }
905
906 return count;
907}
908
d8ee398d
LR		 909static int
910ath5k_getchannels(struct ieee80211_hw *hw)
fa1c114f
JS		 911{
912 struct ath5k_softc *sc = hw->priv;
d8ee398d
LR		 913 struct ath5k_hw *ah = sc->ah;
914 struct ieee80211_supported_band *sbands = sc->sbands;
915 const struct ath5k_rate_table *hw_rates;
916 unsigned int max_r, max_c, count_r, count_c;
917 int mode2g = AR5K_MODE_11G;
fa1c114f 918
d8ee398d 919 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
fa1c114f 920
d8ee398d
LR		 921 max_r = ARRAY_SIZE(sc->rates);
922 max_c = ARRAY_SIZE(sc->channels);
923 count_r = count_c = 0;
924
925 /* 2GHz band */
400ec45a 926 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
d8ee398d 927 mode2g = AR5K_MODE_11B;
400ec45a
LR		 928 if (!test_bit(AR5K_MODE_11B,
929 sc->ah->ah_capabilities.cap_mode))
d8ee398d 930 mode2g = -1;
fa1c114f 931 }
fa1c114f 932
400ec45a
LR		 933 if (mode2g > 0) {
934 struct ieee80211_supported_band *sband =
935 &sbands[IEEE80211_BAND_2GHZ];
fa1c114f 936
d8ee398d
LR		 937 sband->bitrates = sc->rates;
938 sband->channels = sc->channels;
fa1c114f 939
d8ee398d
LR		 940 sband->band = IEEE80211_BAND_2GHZ;
941 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
942 mode2g, max_c);
fa1c114f 943
d8ee398d
LR		 944 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
945 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 946 hw_rates, max_r);
fa1c114f 947
d8ee398d
LR		 948 count_c = sband->n_channels;
949 count_r = sband->n_bitrates;
fa1c114f 950
d8ee398d
LR		 951 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
952
953 max_r -= count_r;
954 max_c -= count_c;
fa1c114f 955
fa1c114f
JS		 956 }
957
d8ee398d 958 /* 5GHz band */
fa1c114f 959
400ec45a
LR		 960 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
961 struct ieee80211_supported_band *sband =
962 &sbands[IEEE80211_BAND_5GHZ];
fa1c114f 963
d8ee398d
LR		 964 sband->bitrates = &sc->rates[count_r];
965 sband->channels = &sc->channels[count_c];
fa1c114f 966
d8ee398d
LR		 967 sband->band = IEEE80211_BAND_5GHZ;
968 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
969 AR5K_MODE_11A, max_c);
970
971 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
972 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
400ec45a 973 hw_rates, max_r);
d8ee398d
LR		 974
975 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
976 }
977
b446197c 978 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 979
980 return 0;
fa1c114f
JS		 981}
982
983/*
984 * Set/change channels. If the channel is really being changed,
985 * it's done by reseting the chip. To accomplish this we must
986 * first cleanup any pending DMA, then restart stuff after a la
987 * ath5k_init.
988 */
989static int
990ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
991{
992 struct ath5k_hw *ah = sc->ah;
993 int ret;
994
d8ee398d
LR		 995 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
996 sc->curchan->center_freq, chan->center_freq);
997
998 if (chan->center_freq != sc->curchan->center_freq ||
999 chan->hw_value != sc->curchan->hw_value) {
1000
1001 sc->curchan = chan;
1002 sc->curband = &sc->sbands[chan->band];
fa1c114f 1003
fa1c114f
JS		 1004 /*
1005 * To switch channels clear any pending DMA operations;
1006 * wait long enough for the RX fifo to drain, reset the
1007 * hardware at the new frequency, and then re-enable
1008 * the relevant bits of the h/w.
1009 */
1010 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1011 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1012 ath5k_rx_stop(sc); /* turn off frame recv */
d8ee398d 1013 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
fa1c114f 1014 if (ret) {
d8ee398d
LR		 1015 ATH5K_ERR(sc, "%s: unable to reset channel "
1016 "(%u Mhz)\n", __func__, chan->center_freq);
fa1c114f
JS		 1017 return ret;
1018 }
d8ee398d 1019
fa1c114f
JS		 1020 ath5k_hw_set_txpower_limit(sc->ah, 0);
1021
1022 /*
1023 * Re-enable rx framework.
1024 */
1025 ret = ath5k_rx_start(sc);
1026 if (ret) {
1027 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1028 __func__);
1029 return ret;
1030 }
1031
1032 /*
1033 * Change channels and update the h/w rate map
1034 * if we're switching; e.g. 11a to 11b/g.
1035 *
1036 * XXX needed?
1037 */
1038/* ath5k_chan_change(sc, chan); */
1039
1040 ath5k_beacon_config(sc);
1041 /*
1042 * Re-enable interrupts.
1043 */
1044 ath5k_hw_set_intr(ah, sc->imask);
1045 }
1046
1047 return 0;
1048}
1049
1050static void
1051ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1052{
fa1c114f 1053 sc->curmode = mode;
d8ee398d 1054
400ec45a 1055 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1056 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1057 } else {
1058 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1059 }
fa1c114f
JS		 1060}
1061
1062static void
1063ath5k_mode_setup(struct ath5k_softc *sc)
1064{
1065 struct ath5k_hw *ah = sc->ah;
1066 u32 rfilt;
1067
1068 /* configure rx filter */
1069 rfilt = sc->filter_flags;
1070 ath5k_hw_set_rx_filter(ah, rfilt);
1071
1072 if (ath5k_hw_hasbssidmask(ah))
1073 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1074
1075 /* configure operational mode */
1076 ath5k_hw_set_opmode(ah);
1077
1078 ath5k_hw_set_mcast_filter(ah, 0, 0);
1079 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1080}
1081
d8ee398d
LR		 1082/*
1083 * Match the hw provided rate index (through descriptors)
1084 * to an index for sc->curband->bitrates, so it can be used
1085 * by the stack.
1086 *
1087 * This one is a little bit tricky but i think i'm right
1088 * about this...
1089 *
1090 * We have 4 rate tables in the following order:
1091 * XR (4 rates)
1092 * 802.11a (8 rates)
1093 * 802.11b (4 rates)
1094 * 802.11g (12 rates)
1095 * that make the hw rate table.
1096 *
1097 * Lets take a 5211 for example that supports a and b modes only.
1098 * First comes the 802.11a table and then 802.11b (total 12 rates).
1099 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1100 * if it returns 2 it points to the second 802.11a rate etc.
1101 *
1102 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1103 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1104 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1105 */
1106static void
400ec45a 1107ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
d8ee398d
LR		 1108
1109 struct ath5k_hw *ah = sc->ah;
1110
400ec45a 1111 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
d8ee398d
LR		 1112 sc->a_rates = 8;
1113
400ec45a 1114 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
d8ee398d
LR		 1115 sc->b_rates = 4;
1116
400ec45a 1117 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
d8ee398d
LR		 1118 sc->g_rates = 12;
1119
1120 /* XXX: Need to see what what happens when
1121 xr disable bits in eeprom are set */
400ec45a 1122 if (ah->ah_version >= AR5K_AR5212)
d8ee398d
LR		 1123 sc->xr_rates = 4;
1124
1125}
1126
1127static inline int
400ec45a 1128ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
d8ee398d
LR		 1129
1130 int mac80211_rix;
1131
400ec45a 1132 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
d8ee398d 1133 /* We setup a g ratetable for both b/g modes */
400ec45a
LR		 1134 mac80211_rix =
1135 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
d8ee398d
LR		 1136 } else {
1137 mac80211_rix = hw_rix - sc->xr_rates;
1138 }
1139
1140 /* Something went wrong, fallback to basic rate for this band */
400ec45a
LR		 1141 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1142 (mac80211_rix <= 0 ))
d8ee398d 1143 mac80211_rix = 1;
d8ee398d
LR		 1144
1145 return mac80211_rix;
1146}
1147
fa1c114f
JS		 1148
1149
1150
1151/***************\
1152* Buffers setup *
1153\***************/
1154
1155static int
1156ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1157{
1158 struct ath5k_hw *ah = sc->ah;
1159 struct sk_buff *skb = bf->skb;
1160 struct ath5k_desc *ds;
1161
1162 if (likely(skb == NULL)) {
1163 unsigned int off;
1164
1165 /*
1166 * Allocate buffer with headroom_needed space for the
1167 * fake physical layer header at the start.
1168 */
1169 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1170 if (unlikely(skb == NULL)) {
1171 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1172 sc->rxbufsize + sc->cachelsz - 1);
1173 return -ENOMEM;
1174 }
1175 /*
1176 * Cache-line-align. This is important (for the
1177 * 5210 at least) as not doing so causes bogus data
1178 * in rx'd frames.
1179 */
1180 off = ((unsigned long)skb->data) % sc->cachelsz;
1181 if (off != 0)
1182 skb_reserve(skb, sc->cachelsz - off);
1183
1184 bf->skb = skb;
1185 bf->skbaddr = pci_map_single(sc->pdev,
1186 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1187 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1188 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1189 dev_kfree_skb(skb);
1190 bf->skb = NULL;
1191 return -ENOMEM;
1192 }
1193 }
1194
1195 /*
1196 * Setup descriptors. For receive we always terminate
1197 * the descriptor list with a self-linked entry so we'll
1198 * not get overrun under high load (as can happen with a
1199 * 5212 when ANI processing enables PHY error frames).
1200 *
1201 * To insure the last descriptor is self-linked we create
1202 * each descriptor as self-linked and add it to the end. As
1203 * each additional descriptor is added the previous self-linked
1204 * entry is ``fixed'' naturally. This should be safe even
1205 * if DMA is happening. When processing RX interrupts we
1206 * never remove/process the last, self-linked, entry on the
1207 * descriptor list. This insures the hardware always has
1208 * someplace to write a new frame.
1209 */
1210 ds = bf->desc;
1211 ds->ds_link = bf->daddr; /* link to self */
1212 ds->ds_data = bf->skbaddr;
1213 ath5k_hw_setup_rx_desc(ah, ds,
1214 skb_tailroom(skb), /* buffer size */
1215 0);
1216
1217 if (sc->rxlink != NULL)
1218 *sc->rxlink = bf->daddr;
1219 sc->rxlink = &ds->ds_link;
1220 return 0;
1221}
1222
1223static int
e039fa4a 1224ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1225{
1226 struct ath5k_hw *ah = sc->ah;
1227 struct ath5k_txq *txq = sc->txq;
1228 struct ath5k_desc *ds = bf->desc;
1229 struct sk_buff *skb = bf->skb;
a888d52d 1230 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1231 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1232 int ret;
1233
1234 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1235
fa1c114f
JS		 1236 /* XXX endianness */
1237 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1238 PCI_DMA_TODEVICE);
1239
e039fa4a 1240 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1241 flags |= AR5K_TXDESC_NOACK;
1242
281c56dd 1243 pktlen = skb->len;
fa1c114f 1244
e039fa4a
JB		 1245 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1246 keyidx = info->control.hw_key->hw_key_idx;
1247 pktlen += info->control.icv_len;
fa1c114f 1248 }
fa1c114f
JS		 1249 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1250 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1251 (sc->power_level * 2),
e039fa4a
JB		 1252 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1253 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1254 if (ret)
1255 goto err_unmap;
1256
1257 ds->ds_link = 0;
1258 ds->ds_data = bf->skbaddr;
1259
1260 spin_lock_bh(&txq->lock);
1261 list_add_tail(&bf->list, &txq->q);
57ffc589 1262 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1263 if (txq->link == NULL) /* is this first packet? */
1264 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1265 else /* no, so only link it */
1266 *txq->link = bf->daddr;
1267
1268 txq->link = &ds->ds_link;
1269 ath5k_hw_tx_start(ah, txq->qnum);
274c7c36 1270 mmiowb();
fa1c114f
JS		 1271 spin_unlock_bh(&txq->lock);
1272
1273 return 0;
1274err_unmap:
1275 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1276 return ret;
1277}
1278
1279/*******************\
1280* Descriptors setup *
1281\*******************/
1282
1283static int
1284ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1285{
1286 struct ath5k_desc *ds;
1287 struct ath5k_buf *bf;
1288 dma_addr_t da;
1289 unsigned int i;
1290 int ret;
1291
1292 /* allocate descriptors */
1293 sc->desc_len = sizeof(struct ath5k_desc) *
1294 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1295 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1296 if (sc->desc == NULL) {
1297 ATH5K_ERR(sc, "can't allocate descriptors\n");
1298 ret = -ENOMEM;
1299 goto err;
1300 }
1301 ds = sc->desc;
1302 da = sc->desc_daddr;
1303 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1304 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1305
1306 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1307 sizeof(struct ath5k_buf), GFP_KERNEL);
1308 if (bf == NULL) {
1309 ATH5K_ERR(sc, "can't allocate bufptr\n");
1310 ret = -ENOMEM;
1311 goto err_free;
1312 }
1313 sc->bufptr = bf;
1314
1315 INIT_LIST_HEAD(&sc->rxbuf);
1316 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1317 bf->desc = ds;
1318 bf->daddr = da;
1319 list_add_tail(&bf->list, &sc->rxbuf);
1320 }
1321
1322 INIT_LIST_HEAD(&sc->txbuf);
1323 sc->txbuf_len = ATH_TXBUF;
1324 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1325 da += sizeof(*ds)) {
1326 bf->desc = ds;
1327 bf->daddr = da;
1328 list_add_tail(&bf->list, &sc->txbuf);
1329 }
1330
1331 /* beacon buffer */
1332 bf->desc = ds;
1333 bf->daddr = da;
1334 sc->bbuf = bf;
1335
1336 return 0;
1337err_free:
1338 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1339err:
1340 sc->desc = NULL;
1341 return ret;
1342}
1343
1344static void
1345ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1346{
1347 struct ath5k_buf *bf;
1348
1349 ath5k_txbuf_free(sc, sc->bbuf);
1350 list_for_each_entry(bf, &sc->txbuf, list)
1351 ath5k_txbuf_free(sc, bf);
1352 list_for_each_entry(bf, &sc->rxbuf, list)
1353 ath5k_txbuf_free(sc, bf);
1354
1355 /* Free memory associated with all descriptors */
1356 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1357
1358 kfree(sc->bufptr);
1359 sc->bufptr = NULL;
1360}
1361
1362
1363
1364
1365
1366/**************\
1367* Queues setup *
1368\**************/
1369
1370static struct ath5k_txq *
1371ath5k_txq_setup(struct ath5k_softc *sc,
1372 int qtype, int subtype)
1373{
1374 struct ath5k_hw *ah = sc->ah;
1375 struct ath5k_txq *txq;
1376 struct ath5k_txq_info qi = {
1377 .tqi_subtype = subtype,
1378 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1379 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1380 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1381 };
1382 int qnum;
1383
1384 /*
1385 * Enable interrupts only for EOL and DESC conditions.
1386 * We mark tx descriptors to receive a DESC interrupt
1387 * when a tx queue gets deep; otherwise waiting for the
1388 * EOL to reap descriptors. Note that this is done to
1389 * reduce interrupt load and this only defers reaping
1390 * descriptors, never transmitting frames. Aside from
1391 * reducing interrupts this also permits more concurrency.
1392 * The only potential downside is if the tx queue backs
1393 * up in which case the top half of the kernel may backup
1394 * due to a lack of tx descriptors.
1395 */
1396 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1397 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1398 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1399 if (qnum < 0) {
1400 /*
1401 * NB: don't print a message, this happens
1402 * normally on parts with too few tx queues
1403 */
1404 return ERR_PTR(qnum);
1405 }
1406 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1407 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1408 qnum, ARRAY_SIZE(sc->txqs));
1409 ath5k_hw_release_tx_queue(ah, qnum);
1410 return ERR_PTR(-EINVAL);
1411 }
1412 txq = &sc->txqs[qnum];
1413 if (!txq->setup) {
1414 txq->qnum = qnum;
1415 txq->link = NULL;
1416 INIT_LIST_HEAD(&txq->q);
1417 spin_lock_init(&txq->lock);
1418 txq->setup = true;
1419 }
1420 return &sc->txqs[qnum];
1421}
1422
1423static int
1424ath5k_beaconq_setup(struct ath5k_hw *ah)
1425{
1426 struct ath5k_txq_info qi = {
1427 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1428 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1429 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1430 /* NB: for dynamic turbo, don't enable any other interrupts */
1431 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1432 };
1433
1434 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1435}
1436
1437static int
1438ath5k_beaconq_config(struct ath5k_softc *sc)
1439{
1440 struct ath5k_hw *ah = sc->ah;
1441 struct ath5k_txq_info qi;
1442 int ret;
1443
1444 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1445 if (ret)
1446 return ret;
6d91e1d8 1447 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1448 /*
1449 * Always burst out beacon and CAB traffic
1450 * (aifs = cwmin = cwmax = 0)
1451 */
1452 qi.tqi_aifs = 0;
1453 qi.tqi_cw_min = 0;
1454 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1455 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1456 /*
1457 * Adhoc mode; backoff between 0 and (2 * cw_min).
1458 */
1459 qi.tqi_aifs = 0;
1460 qi.tqi_cw_min = 0;
1461 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1462 }
1463
6d91e1d8
BR		 1464 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1465 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1466 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1467
fa1c114f
JS		 1468 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1469 if (ret) {
1470 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1471 "hardware queue!\n", __func__);
1472 return ret;
1473 }
1474
1475 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1476}
1477
1478static void
1479ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1480{
1481 struct ath5k_buf *bf, *bf0;
1482
1483 /*
1484 * NB: this assumes output has been stopped and
1485 * we do not need to block ath5k_tx_tasklet
1486 */
1487 spin_lock_bh(&txq->lock);
1488 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1489 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1490
1491 ath5k_txbuf_free(sc, bf);
1492
1493 spin_lock_bh(&sc->txbuflock);
57ffc589 1494 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1495 list_move_tail(&bf->list, &sc->txbuf);
1496 sc->txbuf_len++;
1497 spin_unlock_bh(&sc->txbuflock);
1498 }
1499 txq->link = NULL;
1500 spin_unlock_bh(&txq->lock);
1501}
1502
1503/*
1504 * Drain the transmit queues and reclaim resources.
1505 */
1506static void
1507ath5k_txq_cleanup(struct ath5k_softc *sc)
1508{
1509 struct ath5k_hw *ah = sc->ah;
1510 unsigned int i;
1511
1512 /* XXX return value */
1513 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1514 /* don't touch the hardware if marked invalid */
1515 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1516 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1517 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1518 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1519 if (sc->txqs[i].setup) {
1520 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1522 "link %p\n",
1523 sc->txqs[i].qnum,
1524 ath5k_hw_get_tx_buf(ah,
1525 sc->txqs[i].qnum),
1526 sc->txqs[i].link);
1527 }
1528 }
36d6825b 1529 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1530
1531 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1532 if (sc->txqs[i].setup)
1533 ath5k_txq_drainq(sc, &sc->txqs[i]);
1534}
1535
1536static void
1537ath5k_txq_release(struct ath5k_softc *sc)
1538{
1539 struct ath5k_txq *txq = sc->txqs;
1540 unsigned int i;
1541
1542 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1543 if (txq->setup) {
1544 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1545 txq->setup = false;
1546 }
1547}
1548
1549
1550
1551
1552/*************\
1553* RX Handling *
1554\*************/
1555
1556/*
1557 * Enable the receive h/w following a reset.
1558 */
1559static int
1560ath5k_rx_start(struct ath5k_softc *sc)
1561{
1562 struct ath5k_hw *ah = sc->ah;
1563 struct ath5k_buf *bf;
1564 int ret;
1565
1566 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1567
1568 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1569 sc->cachelsz, sc->rxbufsize);
1570
1571 sc->rxlink = NULL;
1572
1573 spin_lock_bh(&sc->rxbuflock);
1574 list_for_each_entry(bf, &sc->rxbuf, list) {
1575 ret = ath5k_rxbuf_setup(sc, bf);
1576 if (ret != 0) {
1577 spin_unlock_bh(&sc->rxbuflock);
1578 goto err;
1579 }
1580 }
1581 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1582 spin_unlock_bh(&sc->rxbuflock);
1583
1584 ath5k_hw_put_rx_buf(ah, bf->daddr);
1585 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1586 ath5k_mode_setup(sc); /* set filters, etc. */
1587 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1588
1589 return 0;
1590err:
1591 return ret;
1592}
1593
1594/*
1595 * Disable the receive h/w in preparation for a reset.
1596 */
1597static void
1598ath5k_rx_stop(struct ath5k_softc *sc)
1599{
1600 struct ath5k_hw *ah = sc->ah;
1601
1602 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1603 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1604 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1605
1606 ath5k_debug_printrxbuffs(sc, ah);
1607
1608 sc->rxlink = NULL; /* just in case */
1609}
1610
1611static unsigned int
1612ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1613 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1614{
1615 struct ieee80211_hdr *hdr = (void *)skb->data;
1616 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1617
b47f407b
BR		 1618 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1619 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1620 return RX_FLAG_DECRYPTED;
1621
1622 /* Apparently when a default key is used to decrypt the packet
1623 the hw does not set the index used to decrypt. In such cases
1624 get the index from the packet. */
24b56e70
HH		 1625 if (ieee80211_has_protected(hdr->frame_control) &&
1626 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1627 skb->len >= hlen + 4) {
fa1c114f
JS		 1628 keyix = skb->data[hlen + 3] >> 6;
1629
1630 if (test_bit(keyix, sc->keymap))
1631 return RX_FLAG_DECRYPTED;
1632 }
1633
1634 return 0;
1635}
1636
036cd1ec
BR		 1637
1638static void
6ba81c2c
BR		 1639ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1640 struct ieee80211_rx_status *rxs)
036cd1ec 1641{
6ba81c2c 1642 u64 tsf, bc_tstamp;
036cd1ec
BR		 1643 u32 hw_tu;
1644 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1645
24b56e70 1646 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1647 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1648 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1649 /*
6ba81c2c
BR		 1650 * Received an IBSS beacon with the same BSSID. Hardware *must*
1651 * have updated the local TSF. We have to work around various
1652 * hardware bugs, though...
036cd1ec 1653 */
6ba81c2c
BR		 1654 tsf = ath5k_hw_get_tsf64(sc->ah);
1655 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1656 hw_tu = TSF_TO_TU(tsf);
1657
1658 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1659 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1660 (unsigned long long)bc_tstamp,
1661 (unsigned long long)rxs->mactime,
1662 (unsigned long long)(rxs->mactime - bc_tstamp),
1663 (unsigned long long)tsf);
6ba81c2c
BR		 1664
1665 /*
1666 * Sometimes the HW will give us a wrong tstamp in the rx
1667 * status, causing the timestamp extension to go wrong.
1668 * (This seems to happen especially with beacon frames bigger
1669 * than 78 byte (incl. FCS))
1670 * But we know that the receive timestamp must be later than the
1671 * timestamp of the beacon since HW must have synced to that.
1672 *
1673 * NOTE: here we assume mactime to be after the frame was
1674 * received, not like mac80211 which defines it at the start.
1675 */
1676 if (bc_tstamp > rxs->mactime) {
036cd1ec 1677 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1678 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1679 (unsigned long long)rxs->mactime,
1680 (unsigned long long)tsf);
6ba81c2c 1681 rxs->mactime = tsf;
036cd1ec 1682 }
6ba81c2c
BR		 1683
1684 /*
1685 * Local TSF might have moved higher than our beacon timers,
1686 * in that case we have to update them to continue sending
1687 * beacons. This also takes care of synchronizing beacon sending
1688 * times with other stations.
1689 */
1690 if (hw_tu >= sc->nexttbtt)
1691 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1692 }
1693}
1694
1695
fa1c114f
JS		 1696static void
1697ath5k_tasklet_rx(unsigned long data)
1698{
1699 struct ieee80211_rx_status rxs = {};
b47f407b 1700 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1701 struct sk_buff *skb;
1702 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1703 struct ath5k_buf *bf, *bf_last;
fa1c114f 1704 struct ath5k_desc *ds;
fa1c114f
JS		 1705 int ret;
1706 int hdrlen;
1707 int pad;
1708
1709 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1710 if (list_empty(&sc->rxbuf)) {
1711 ATH5K_WARN(sc, "empty rx buf pool\n");
1712 goto unlock;
1713 }
1714 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1715 do {
d6894b5b
BC		 1716 rxs.flag = 0;
1717
fa1c114f
JS		 1718 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1719 BUG_ON(bf->skb == NULL);
1720 skb = bf->skb;
1721 ds = bf->desc;
1722
3a0f2c87
JS		 1723 /*
1724 * last buffer must not be freed to ensure proper hardware
1725 * function. When the hardware finishes also a packet next to
1726 * it, we are sure, it doesn't use it anymore and we can go on.
1727 */
1728 if (bf_last == bf)
1729 bf->flags |= 1;
1730 if (bf->flags) {
1731 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1732 struct ath5k_buf, list);
1733 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1734 &rs);
1735 if (ret)
1736 break;
1737 bf->flags &= ~1;
1738 /* skip the overwritten one (even status is martian) */
1739 goto next;
1740 }
fa1c114f 1741
b47f407b 1742 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1743 if (unlikely(ret == -EINPROGRESS))
1744 break;
1745 else if (unlikely(ret)) {
1746 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1747 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1748 return;
1749 }
1750
b47f407b 1751 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1752 ATH5K_WARN(sc, "unsupported jumbo\n");
1753 goto next;
1754 }
1755
b47f407b
BR		 1756 if (unlikely(rs.rs_status)) {
1757 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1758 goto next;
b47f407b 1759 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1760 /*
1761 * Decrypt error. If the error occurred
1762 * because there was no hardware key, then
1763 * let the frame through so the upper layers
1764 * can process it. This is necessary for 5210
1765 * parts which have no way to setup a ``clear''
1766 * key cache entry.
1767 *
1768 * XXX do key cache faulting
1769 */
b47f407b
BR		 1770 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1771 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1772 goto accept;
1773 }
b47f407b 1774 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1775 rxs.flag |= RX_FLAG_MMIC_ERROR;
1776 goto accept;
1777 }
1778
1779 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1780 if ((rs.rs_status &
1781 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1782 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1783 goto next;
1784 }
1785accept:
fa1c114f
JS		 1786 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1787 PCI_DMA_FROMDEVICE);
1788 bf->skb = NULL;
1789
b47f407b 1790 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1791
1792 /*
1793 * the hardware adds a padding to 4 byte boundaries between
1794 * the header and the payload data if the header length is
1795 * not multiples of 4 - remove it
1796 */
1797 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1798 if (hdrlen & 3) {
1799 pad = hdrlen % 4;
1800 memmove(skb->data + pad, skb->data, hdrlen);
1801 skb_pull(skb, pad);
1802 }
1803
c0e1899b
BR		 1804 /*
1805 * always extend the mac timestamp, since this information is
1806 * also needed for proper IBSS merging.
1807 *
1808 * XXX: it might be too late to do it here, since rs_tstamp is
1809 * 15bit only. that means TSF extension has to be done within
1810 * 32768usec (about 32ms). it might be necessary to move this to
1811 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1812 *
1813 * Unfortunately we don't know when the hardware takes the rx
1814 * timestamp (beginning of phy frame, data frame, end of rx?).
1815 * The only thing we know is that it is hardware specific...
1816 * On AR5213 it seems the rx timestamp is at the end of the
1817 * frame, but i'm not sure.
1818 *
1819 * NOTE: mac80211 defines mactime at the beginning of the first
1820 * data symbol. Since we don't have any time references it's
1821 * impossible to comply to that. This affects IBSS merge only
1822 * right now, so it's not too bad...
c0e1899b 1823 */
b47f407b 1824 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1825 rxs.flag |= RX_FLAG_TSFT;
1826
d8ee398d
LR		 1827 rxs.freq = sc->curchan->center_freq;
1828 rxs.band = sc->curband->band;
fa1c114f 1829
fa1c114f 1830 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1831 rxs.signal = rxs.noise + rs.rs_rssi;
1832 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1833
b47f407b
BR		 1834 rxs.antenna = rs.rs_antenna;
1835 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1836 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f
JS		 1837
1838 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1839
036cd1ec
BR		 1840 /* check beacons in IBSS mode */
1841 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1842 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1843
fa1c114f 1844 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1845next:
1846 list_move_tail(&bf->list, &sc->rxbuf);
1847 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1848unlock:
fa1c114f
JS		 1849 spin_unlock(&sc->rxbuflock);
1850}
1851
1852
1853
1854
1855/*************\
1856* TX Handling *
1857\*************/
1858
1859static void
1860ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1861{
b47f407b 1862 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1863 struct ath5k_buf *bf, *bf0;
1864 struct ath5k_desc *ds;
1865 struct sk_buff *skb;
e039fa4a 1866 struct ieee80211_tx_info *info;
fa1c114f
JS		 1867 int ret;
1868
1869 spin_lock(&txq->lock);
1870 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1871 ds = bf->desc;
1872
b47f407b 1873 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1874 if (unlikely(ret == -EINPROGRESS))
1875 break;
1876 else if (unlikely(ret)) {
1877 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1878 ret, txq->qnum);
1879 break;
1880 }
1881
1882 skb = bf->skb;
a888d52d 1883 info = IEEE80211_SKB_CB(skb);
fa1c114f 1884 bf->skb = NULL;
e039fa4a 1885
fa1c114f
JS		 1886 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1887 PCI_DMA_TODEVICE);
1888
e039fa4a 1889 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1890 if (unlikely(ts.ts_status)) {
fa1c114f 1891 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1892 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1893 info->status.excessive_retries = 1;
b47f407b 1894 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1895 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1896 } else {
e039fa4a
JB		 1897 info->flags |= IEEE80211_TX_STAT_ACK;
1898 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1899 }
1900
e039fa4a 1901 ieee80211_tx_status(sc->hw, skb);
57ffc589 1902 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1903
1904 spin_lock(&sc->txbuflock);
57ffc589 1905 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1906 list_move_tail(&bf->list, &sc->txbuf);
1907 sc->txbuf_len++;
1908 spin_unlock(&sc->txbuflock);
1909 }
1910 if (likely(list_empty(&txq->q)))
1911 txq->link = NULL;
1912 spin_unlock(&txq->lock);
1913 if (sc->txbuf_len > ATH_TXBUF / 5)
1914 ieee80211_wake_queues(sc->hw);
1915}
1916
1917static void
1918ath5k_tasklet_tx(unsigned long data)
1919{
1920 struct ath5k_softc *sc = (void *)data;
1921
1922 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1923}
1924
1925
fa1c114f
JS		 1926/*****************\
1927* Beacon handling *
1928\*****************/
1929
1930/*
1931 * Setup the beacon frame for transmit.
1932 */
1933static int
e039fa4a 1934ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1935{
1936 struct sk_buff *skb = bf->skb;
a888d52d 1937 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1938 struct ath5k_hw *ah = sc->ah;
1939 struct ath5k_desc *ds;
1940 int ret, antenna = 0;
1941 u32 flags;
1942
1943 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1944 PCI_DMA_TODEVICE);
1945 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1946 "skbaddr %llx\n", skb, skb->data, skb->len,
1947 (unsigned long long)bf->skbaddr);
8d8bb39b 1948 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1949 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1950 return -EIO;
1951 }
1952
1953 ds = bf->desc;
1954
1955 flags = AR5K_TXDESC_NOACK;
1956 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1957 ds->ds_link = bf->daddr; /* self-linked */
1958 flags |= AR5K_TXDESC_VEOL;
1959 /*
1960 * Let hardware handle antenna switching if txantenna is not set
1961 */
1962 } else {
1963 ds->ds_link = 0;
1964 /*
1965 * Switch antenna every 4 beacons if txantenna is not set
1966 * XXX assumes two antennas
1967 */
1968 if (antenna == 0)
1969 antenna = sc->bsent & 4 ? 2 : 1;
1970 }
1971
1972 ds->ds_data = bf->skbaddr;
281c56dd 1973 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1974 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1975 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1976 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1977 1, AR5K_TXKEYIX_INVALID,
400ec45a 1978 antenna, flags, 0, 0);
fa1c114f
JS		 1979 if (ret)
1980 goto err_unmap;
1981
1982 return 0;
1983err_unmap:
1984 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1985 return ret;
1986}
1987
1988/*
1989 * Transmit a beacon frame at SWBA. Dynamic updates to the
1990 * frame contents are done as needed and the slot time is
1991 * also adjusted based on current state.
1992 *
1993 * this is usually called from interrupt context (ath5k_intr())
1994 * but also from ath5k_beacon_config() in IBSS mode which in turn
1995 * can be called from a tasklet and user context
1996 */
1997static void
1998ath5k_beacon_send(struct ath5k_softc *sc)
1999{
2000 struct ath5k_buf *bf = sc->bbuf;
2001 struct ath5k_hw *ah = sc->ah;
2002
be9b7259 2003 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 2004
2005 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
2006 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2007 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2008 return;
2009 }
2010 /*
2011 * Check if the previous beacon has gone out. If
2012 * not don't don't try to post another, skip this
2013 * period and wait for the next. Missed beacons
2014 * indicate a problem and should not occur. If we
2015 * miss too many consecutive beacons reset the device.
2016 */
2017 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2018 sc->bmisscount++;
be9b7259 2019 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2020 "missed %u consecutive beacons\n", sc->bmisscount);
2021 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2022 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2023 "stuck beacon time (%u missed)\n",
2024 sc->bmisscount);
2025 tasklet_schedule(&sc->restq);
2026 }
2027 return;
2028 }
2029 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2030 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2031 "resume beacon xmit after %u misses\n",
2032 sc->bmisscount);
2033 sc->bmisscount = 0;
2034 }
2035
2036 /*
2037 * Stop any current dma and put the new frame on the queue.
2038 * This should never fail since we check above that no frames
2039 * are still pending on the queue.
2040 */
2041 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2042 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2043 /* NB: hw still stops DMA, so proceed */
2044 }
fa1c114f
JS		 2045
2046 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2047 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2048 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2049 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2050
2051 sc->bsent++;
2052}
2053
2054
9804b98d
BR		 2055/**
2056 * ath5k_beacon_update_timers - update beacon timers
2057 *
2058 * @sc: struct ath5k_softc pointer we are operating on
2059 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2060 * beacon timer update based on the current HW TSF.
2061 *
2062 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2063 * of a received beacon or the current local hardware TSF and write it to the
2064 * beacon timer registers.
2065 *
2066 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2067 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2068 * when we otherwise know we have to update the timers, but we keep it in this
2069 * function to have it all together in one place.
2070 */
fa1c114f 2071static void
9804b98d 2072ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2073{
2074 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2075 u32 nexttbtt, intval, hw_tu, bc_tu;
2076 u64 hw_tsf;
fa1c114f
JS		 2077
2078 intval = sc->bintval & AR5K_BEACON_PERIOD;
2079 if (WARN_ON(!intval))
2080 return;
2081
9804b98d
BR		 2082 /* beacon TSF converted to TU */
2083 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2084
9804b98d
BR		 2085 /* current TSF converted to TU */
2086 hw_tsf = ath5k_hw_get_tsf64(ah);
2087 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2088
9804b98d
BR		 2089#define FUDGE 3
2090 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2091 if (bc_tsf == -1) {
2092 /*
2093 * no beacons received, called internally.
2094 * just need to refresh timers based on HW TSF.
2095 */
2096 nexttbtt = roundup(hw_tu + FUDGE, intval);
2097 } else if (bc_tsf == 0) {
2098 /*
2099 * no beacon received, probably called by ath5k_reset_tsf().
2100 * reset TSF to start with 0.
2101 */
2102 nexttbtt = intval;
2103 intval |= AR5K_BEACON_RESET_TSF;
2104 } else if (bc_tsf > hw_tsf) {
2105 /*
2106 * beacon received, SW merge happend but HW TSF not yet updated.
2107 * not possible to reconfigure timers yet, but next time we
2108 * receive a beacon with the same BSSID, the hardware will
2109 * automatically update the TSF and then we need to reconfigure
2110 * the timers.
2111 */
2112 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2113 "need to wait for HW TSF sync\n");
2114 return;
2115 } else {
2116 /*
2117 * most important case for beacon synchronization between STA.
2118 *
2119 * beacon received and HW TSF has been already updated by HW.
2120 * update next TBTT based on the TSF of the beacon, but make
2121 * sure it is ahead of our local TSF timer.
2122 */
2123 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2124 }
2125#undef FUDGE
fa1c114f 2126
036cd1ec
BR		 2127 sc->nexttbtt = nexttbtt;
2128
fa1c114f 2129 intval |= AR5K_BEACON_ENA;
fa1c114f 2130 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2131
2132 /*
2133 * debugging output last in order to preserve the time critical aspect
2134 * of this function
2135 */
2136 if (bc_tsf == -1)
2137 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2138 "reconfigured timers based on HW TSF\n");
2139 else if (bc_tsf == 0)
2140 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2141 "reset HW TSF and timers\n");
2142 else
2143 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2144 "updated timers based on beacon TSF\n");
2145
2146 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2147 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2148 (unsigned long long) bc_tsf,
2149 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2150 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2151 intval & AR5K_BEACON_PERIOD,
2152 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2153 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2154}
2155
2156
036cd1ec
BR		 2157/**
2158 * ath5k_beacon_config - Configure the beacon queues and interrupts
2159 *
2160 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2161 *
2162 * When operating in station mode we want to receive a BMISS interrupt when we
2163 * stop seeing beacons from the AP we've associated with so we can look for
2164 * another AP to associate with.
2165 *
036cd1ec 2166 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2167 * interrupts to detect TSF updates only.
036cd1ec
BR		 2168 *
2169 * AP mode is missing.
fa1c114f
JS		 2170 */
2171static void
2172ath5k_beacon_config(struct ath5k_softc *sc)
2173{
2174 struct ath5k_hw *ah = sc->ah;
2175
2176 ath5k_hw_set_intr(ah, 0);
2177 sc->bmisscount = 0;
2178
2179 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2180 sc->imask |= AR5K_INT_BMISS;
2181 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2182 /*
036cd1ec
BR		 2183 * In IBSS mode we use a self-linked tx descriptor and let the
2184 * hardware send the beacons automatically. We have to load it
fa1c114f 2185 * only once here.
036cd1ec 2186 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2187 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2188 */
2189 ath5k_beaconq_config(sc);
fa1c114f 2190
036cd1ec
BR		 2191 sc->imask |= AR5K_INT_SWBA;
2192
2193 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2194 ath5k_beacon_send(sc);
2195 }
2196 /* TODO else AP */
2197
2198 ath5k_hw_set_intr(ah, sc->imask);
2199}
2200
2201
2202/********************\
2203* Interrupt handling *
2204\********************/
2205
2206static int
2207ath5k_init(struct ath5k_softc *sc)
2208{
2209 int ret;
2210
2211 mutex_lock(&sc->lock);
2212
2213 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2214
2215 /*
2216 * Stop anything previously setup. This is safe
2217 * no matter this is the first time through or not.
2218 */
2219 ath5k_stop_locked(sc);
2220
2221 /*
2222 * The basic interface to setting the hardware in a good
2223 * state is ``reset''. On return the hardware is known to
2224 * be powered up and with interrupts disabled. This must
2225 * be followed by initialization of the appropriate bits
2226 * and then setup of the interrupt mask.
2227 */
d8ee398d
LR		 2228 sc->curchan = sc->hw->conf.channel;
2229 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f
JS		 2230 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2231 if (ret) {
2232 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2233 goto done;
2234 }
2235 /*
2236 * This is needed only to setup initial state
2237 * but it's best done after a reset.
2238 */
2239 ath5k_hw_set_txpower_limit(sc->ah, 0);
2240
2241 /*
2242 * Setup the hardware after reset: the key cache
2243 * is filled as needed and the receive engine is
2244 * set going. Frame transmit is handled entirely
2245 * in the frame output path; there's nothing to do
2246 * here except setup the interrupt mask.
2247 */
2248 ret = ath5k_rx_start(sc);
2249 if (ret)
2250 goto done;
2251
2252 /*
2253 * Enable interrupts.
2254 */
2255 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2256 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2257 AR5K_INT_MIB;
fa1c114f
JS		 2258
2259 ath5k_hw_set_intr(sc->ah, sc->imask);
2260 /* Set ack to be sent at low bit-rates */
2261 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2262
2263 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2264 msecs_to_jiffies(ath5k_calinterval * 1000)));
2265
2266 ret = 0;
2267done:
274c7c36 2268 mmiowb();
fa1c114f
JS		 2269 mutex_unlock(&sc->lock);
2270 return ret;
2271}
2272
2273static int
2274ath5k_stop_locked(struct ath5k_softc *sc)
2275{
2276 struct ath5k_hw *ah = sc->ah;
2277
2278 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2279 test_bit(ATH_STAT_INVALID, sc->status));
2280
2281 /*
2282 * Shutdown the hardware and driver:
2283 * stop output from above
2284 * disable interrupts
2285 * turn off timers
2286 * turn off the radio
2287 * clear transmit machinery
2288 * clear receive machinery
2289 * drain and release tx queues
2290 * reclaim beacon resources
2291 * power down hardware
2292 *
2293 * Note that some of this work is not possible if the
2294 * hardware is gone (invalid).
2295 */
2296 ieee80211_stop_queues(sc->hw);
2297
2298 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2299 ath5k_led_off(sc);
fa1c114f 2300 ath5k_hw_set_intr(ah, 0);
274c7c36 2301 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2302 }
2303 ath5k_txq_cleanup(sc);
2304 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2305 ath5k_rx_stop(sc);
2306 ath5k_hw_phy_disable(ah);
2307 } else
2308 sc->rxlink = NULL;
2309
2310 return 0;
2311}
2312
2313/*
2314 * Stop the device, grabbing the top-level lock to protect
2315 * against concurrent entry through ath5k_init (which can happen
2316 * if another thread does a system call and the thread doing the
2317 * stop is preempted).
2318 */
2319static int
2320ath5k_stop_hw(struct ath5k_softc *sc)
2321{
2322 int ret;
2323
2324 mutex_lock(&sc->lock);
2325 ret = ath5k_stop_locked(sc);
2326 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2327 /*
2328 * Set the chip in full sleep mode. Note that we are
2329 * careful to do this only when bringing the interface
2330 * completely to a stop. When the chip is in this state
2331 * it must be carefully woken up or references to
2332 * registers in the PCI clock domain may freeze the bus
2333 * (and system). This varies by chip and is mostly an
2334 * issue with newer parts that go to sleep more quickly.
2335 */
2336 if (sc->ah->ah_mac_srev >= 0x78) {
2337 /*
2338 * XXX
2339 * don't put newer MAC revisions > 7.8 to sleep because
2340 * of the above mentioned problems
2341 */
2342 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2343 "not putting device to sleep\n");
2344 } else {
2345 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2346 "putting device to full sleep\n");
2347 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2348 }
2349 }
2350 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2351 mmiowb();
fa1c114f
JS		 2352 mutex_unlock(&sc->lock);
2353
2354 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2355 tasklet_kill(&sc->rxtq);
2356 tasklet_kill(&sc->txtq);
2357 tasklet_kill(&sc->restq);
fa1c114f
JS		 2358
2359 return ret;
2360}
2361
2362static irqreturn_t
2363ath5k_intr(int irq, void *dev_id)
2364{
2365 struct ath5k_softc *sc = dev_id;
2366 struct ath5k_hw *ah = sc->ah;
2367 enum ath5k_int status;
2368 unsigned int counter = 1000;
2369
2370 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2371 !ath5k_hw_is_intr_pending(ah)))
2372 return IRQ_NONE;
2373
2374 do {
2375 /*
2376 * Figure out the reason(s) for the interrupt. Note
2377 * that get_isr returns a pseudo-ISR that may include
2378 * bits we haven't explicitly enabled so we mask the
2379 * value to insure we only process bits we requested.
2380 */
2381 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2382 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2383 status, sc->imask);
2384 status &= sc->imask; /* discard unasked for bits */
2385 if (unlikely(status & AR5K_INT_FATAL)) {
2386 /*
2387 * Fatal errors are unrecoverable.
2388 * Typically these are caused by DMA errors.
2389 */
2390 tasklet_schedule(&sc->restq);
2391 } else if (unlikely(status & AR5K_INT_RXORN)) {
2392 tasklet_schedule(&sc->restq);
2393 } else {
2394 if (status & AR5K_INT_SWBA) {
2395 /*
2396 * Software beacon alert--time to send a beacon.
2397 * Handle beacon transmission directly; deferring
2398 * this is too slow to meet timing constraints
2399 * under load.
036cd1ec
BR		 2400 *
2401 * In IBSS mode we use this interrupt just to
2402 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2403 * transmission time) in order to detect wether
2404 * automatic TSF updates happened.
fa1c114f 2405 */
036cd1ec
BR		 2406 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2407 /* XXX: only if VEOL suppported */
2408 u64 tsf = ath5k_hw_get_tsf64(ah);
2409 sc->nexttbtt += sc->bintval;
2410 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2411 "SWBA nexttbtt: %x hw_tu: %x "
2412 "TSF: %llx\n",
2413 sc->nexttbtt,
2414 TSF_TO_TU(tsf),
2415 (unsigned long long) tsf);
036cd1ec
BR		 2416 } else {
2417 ath5k_beacon_send(sc);
2418 }
fa1c114f
JS		 2419 }
2420 if (status & AR5K_INT_RXEOL) {
2421 /*
2422 * NB: the hardware should re-read the link when
2423 * RXE bit is written, but it doesn't work at
2424 * least on older hardware revs.
2425 */
2426 sc->rxlink = NULL;
2427 }
2428 if (status & AR5K_INT_TXURN) {
2429 /* bump tx trigger level */
2430 ath5k_hw_update_tx_triglevel(ah, true);
2431 }
2432 if (status & AR5K_INT_RX)
2433 tasklet_schedule(&sc->rxtq);
2434 if (status & AR5K_INT_TX)
2435 tasklet_schedule(&sc->txtq);
2436 if (status & AR5K_INT_BMISS) {
2437 }
2438 if (status & AR5K_INT_MIB) {
194828a2
NK		 2439 /*
2440 * These stats are also used for ANI i think
2441 * so how about updating them more often ?
2442 */
2443 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2444 }
2445 }
2446 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2447
2448 if (unlikely(!counter))
2449 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2450
2451 return IRQ_HANDLED;
2452}
2453
2454static void
2455ath5k_tasklet_reset(unsigned long data)
2456{
2457 struct ath5k_softc *sc = (void *)data;
2458
2459 ath5k_reset(sc->hw);
2460}
2461
2462/*
2463 * Periodically recalibrate the PHY to account
2464 * for temperature/environment changes.
2465 */
2466static void
2467ath5k_calibrate(unsigned long data)
2468{
2469 struct ath5k_softc *sc = (void *)data;
2470 struct ath5k_hw *ah = sc->ah;
2471
2472 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2473 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2474 sc->curchan->hw_value);
fa1c114f
JS		 2475
2476 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2477 /*
2478 * Rfgain is out of bounds, reset the chip
2479 * to load new gain values.
2480 */
2481 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2482 ath5k_reset(sc->hw);
2483 }
2484 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2485 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2486 ieee80211_frequency_to_channel(
2487 sc->curchan->center_freq));
fa1c114f
JS		 2488
2489 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2490 msecs_to_jiffies(ath5k_calinterval * 1000)));
2491}
2492
2493
2494
2495/***************\
2496* LED functions *
2497\***************/
2498
2499static void
3a078876 2500ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2501{
3a078876
BC		 2502 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2503 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2504 ath5k_led_off(sc);
fa1c114f
JS		 2505 }
2506}
2507
fa1c114f 2508static void
3a078876 2509ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2510{
3a078876
BC		 2511 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2512 return;
fa1c114f 2513 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2514}
2515
2516static void
3a078876 2517ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2518{
3a078876 2519 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2520 return;
3a078876
BC		 2521 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2522}
2523
2524static void
2525ath5k_led_brightness_set(struct led_classdev *led_dev,
2526 enum led_brightness brightness)
2527{
2528 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2529 led_dev);
2530
2531 if (brightness == LED_OFF)
2532 ath5k_led_off(led->sc);
2533 else
2534 ath5k_led_on(led->sc);
2535}
2536
2537static int
2538ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2539 const char *name, char *trigger)
2540{
2541 int err;
2542
2543 led->sc = sc;
2544 strncpy(led->name, name, sizeof(led->name));
2545 led->led_dev.name = led->name;
2546 led->led_dev.default_trigger = trigger;
2547 led->led_dev.brightness_set = ath5k_led_brightness_set;
2548
2549 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2550 if (err)
2551 {
2552 ATH5K_WARN(sc, "could not register LED %s\n", name);
2553 led->sc = NULL;
fa1c114f 2554 }
3a078876 2555 return err;
fa1c114f
JS		 2556}
2557
3a078876
BC		 2558static void
2559ath5k_unregister_led(struct ath5k_led *led)
2560{
2561 if (!led->sc)
2562 return;
2563 led_classdev_unregister(&led->led_dev);
2564 ath5k_led_off(led->sc);
2565 led->sc = NULL;
2566}
2567
2568static void
2569ath5k_unregister_leds(struct ath5k_softc *sc)
2570{
2571 ath5k_unregister_led(&sc->rx_led);
2572 ath5k_unregister_led(&sc->tx_led);
2573}
2574
2575
2576static int
2577ath5k_init_leds(struct ath5k_softc *sc)
2578{
2579 int ret = 0;
2580 struct ieee80211_hw *hw = sc->hw;
2581 struct pci_dev *pdev = sc->pdev;
2582 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2583
2584 sc->led_on = 0; /* active low */
fa1c114f 2585
3a078876
BC		 2586 /*
2587 * Auto-enable soft led processing for IBM cards and for
2588 * 5211 minipci cards.
2589 */
2590 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2591 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2592 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2593 sc->led_pin = 0;
2594 }
2595 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2596 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2597 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2598 sc->led_pin = 1;
2599 }
2600 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2601 goto out;
2602
2603 ath5k_led_enable(sc);
2604
2605 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2606 ret = ath5k_register_led(sc, &sc->rx_led, name,
2607 ieee80211_get_rx_led_name(hw));
2608 if (ret)
2609 goto out;
2610
2611 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2612 ret = ath5k_register_led(sc, &sc->tx_led, name,
2613 ieee80211_get_tx_led_name(hw));
2614out:
2615 return ret;
2616}
fa1c114f
JS		 2617
2618
2619/********************\
2620* Mac80211 functions *
2621\********************/
2622
2623static int
e039fa4a 2624ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2625{
2626 struct ath5k_softc *sc = hw->priv;
2627 struct ath5k_buf *bf;
2628 unsigned long flags;
2629 int hdrlen;
2630 int pad;
2631
2632 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2633
2634 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2635 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2636
2637 /*
2638 * the hardware expects the header padded to 4 byte boundaries
2639 * if this is not the case we add the padding after the header
2640 */
2641 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2642 if (hdrlen & 3) {
2643 pad = hdrlen % 4;
2644 if (skb_headroom(skb) < pad) {
2645 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2646 " headroom to pad %d\n", hdrlen, pad);
2647 return -1;
2648 }
2649 skb_push(skb, pad);
2650 memmove(skb->data, skb->data+pad, hdrlen);
2651 }
2652
fa1c114f
JS		 2653 spin_lock_irqsave(&sc->txbuflock, flags);
2654 if (list_empty(&sc->txbuf)) {
2655 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2656 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2657 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2658 return -1;
2659 }
2660 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2661 list_del(&bf->list);
2662 sc->txbuf_len--;
2663 if (list_empty(&sc->txbuf))
2664 ieee80211_stop_queues(hw);
2665 spin_unlock_irqrestore(&sc->txbuflock, flags);
2666
2667 bf->skb = skb;
2668
e039fa4a 2669 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2670 bf->skb = NULL;
2671 spin_lock_irqsave(&sc->txbuflock, flags);
2672 list_add_tail(&bf->list, &sc->txbuf);
2673 sc->txbuf_len++;
2674 spin_unlock_irqrestore(&sc->txbuflock, flags);
2675 dev_kfree_skb_any(skb);
2676 return 0;
2677 }
2678
2679 return 0;
2680}
2681
2682static int
2683ath5k_reset(struct ieee80211_hw *hw)
2684{
2685 struct ath5k_softc *sc = hw->priv;
2686 struct ath5k_hw *ah = sc->ah;
2687 int ret;
2688
2689 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f
JS		 2690
2691 ath5k_hw_set_intr(ah, 0);
2692 ath5k_txq_cleanup(sc);
2693 ath5k_rx_stop(sc);
2694
2695 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2696 if (unlikely(ret)) {
2697 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2698 goto err;
2699 }
2700 ath5k_hw_set_txpower_limit(sc->ah, 0);
2701
2702 ret = ath5k_rx_start(sc);
2703 if (unlikely(ret)) {
2704 ATH5K_ERR(sc, "can't start recv logic\n");
2705 goto err;
2706 }
2707 /*
2708 * We may be doing a reset in response to an ioctl
2709 * that changes the channel so update any state that
2710 * might change as a result.
2711 *
2712 * XXX needed?
2713 */
2714/* ath5k_chan_change(sc, c); */
2715 ath5k_beacon_config(sc);
2716 /* intrs are started by ath5k_beacon_config */
2717
2718 ieee80211_wake_queues(hw);
2719
2720 return 0;
2721err:
2722 return ret;
2723}
2724
2725static int ath5k_start(struct ieee80211_hw *hw)
2726{
2727 return ath5k_init(hw->priv);
2728}
2729
2730static void ath5k_stop(struct ieee80211_hw *hw)
2731{
2732 ath5k_stop_hw(hw->priv);
2733}
2734
2735static int ath5k_add_interface(struct ieee80211_hw *hw,
2736 struct ieee80211_if_init_conf *conf)
2737{
2738 struct ath5k_softc *sc = hw->priv;
2739 int ret;
2740
2741 mutex_lock(&sc->lock);
32bfd35d 2742 if (sc->vif) {
fa1c114f
JS		 2743 ret = 0;
2744 goto end;
2745 }
2746
32bfd35d 2747 sc->vif = conf->vif;
fa1c114f
JS		 2748
2749 switch (conf->type) {
2750 case IEEE80211_IF_TYPE_STA:
2751 case IEEE80211_IF_TYPE_IBSS:
2752 case IEEE80211_IF_TYPE_MNTR:
2753 sc->opmode = conf->type;
2754 break;
2755 default:
2756 ret = -EOPNOTSUPP;
2757 goto end;
2758 }
2759 ret = 0;
2760end:
2761 mutex_unlock(&sc->lock);
2762 return ret;
2763}
2764
2765static void
2766ath5k_remove_interface(struct ieee80211_hw *hw,
2767 struct ieee80211_if_init_conf *conf)
2768{
2769 struct ath5k_softc *sc = hw->priv;
2770
2771 mutex_lock(&sc->lock);
32bfd35d 2772 if (sc->vif != conf->vif)
fa1c114f
JS		 2773 goto end;
2774
32bfd35d 2775 sc->vif = NULL;
fa1c114f
JS		 2776end:
2777 mutex_unlock(&sc->lock);
2778}
2779
d8ee398d
LR		 2780/*
2781 * TODO: Phy disable/diversity etc
2782 */
fa1c114f
JS		 2783static int
2784ath5k_config(struct ieee80211_hw *hw,
2785 struct ieee80211_conf *conf)
2786{
2787 struct ath5k_softc *sc = hw->priv;
2788
e535c1ac 2789 sc->bintval = conf->beacon_int;
d8ee398d 2790 sc->power_level = conf->power_level;
fa1c114f 2791
d8ee398d 2792 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2793}
2794
2795static int
32bfd35d 2796ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2797 struct ieee80211_if_conf *conf)
2798{
2799 struct ath5k_softc *sc = hw->priv;
2800 struct ath5k_hw *ah = sc->ah;
2801 int ret;
2802
2803 /* Set to a reasonable value. Note that this will
2804 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2805 sc->bintval = 1000;
fa1c114f 2806 mutex_lock(&sc->lock);
32bfd35d 2807 if (sc->vif != vif) {
fa1c114f
JS		 2808 ret = -EIO;
2809 goto unlock;
2810 }
2811 if (conf->bssid) {
2812 /* Cache for later use during resets */
2813 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2814 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2815 * a clean way of letting us retrieve this yet. */
2816 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2817 mmiowb();
fa1c114f 2818 }
9d139c81
JB		 2819
2820 if (conf->changed & IEEE80211_IFCC_BEACON &&
2821 vif->type == IEEE80211_IF_TYPE_IBSS) {
2822 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2823 if (!beacon) {
2824 ret = -ENOMEM;
2825 goto unlock;
2826 }
2827 /* call old handler for now */
2828 ath5k_beacon_update(hw, beacon);
2829 }
2830
fa1c114f
JS		 2831 mutex_unlock(&sc->lock);
2832
2833 return ath5k_reset(hw);
2834unlock:
2835 mutex_unlock(&sc->lock);
2836 return ret;
2837}
2838
2839#define SUPPORTED_FIF_FLAGS \
2840 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2841 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2842 FIF_BCN_PRBRESP_PROMISC
2843/*
2844 * o always accept unicast, broadcast, and multicast traffic
2845 * o multicast traffic for all BSSIDs will be enabled if mac80211
2846 * says it should be
2847 * o maintain current state of phy ofdm or phy cck error reception.
2848 * If the hardware detects any of these type of errors then
2849 * ath5k_hw_get_rx_filter() will pass to us the respective
2850 * hardware filters to be able to receive these type of frames.
2851 * o probe request frames are accepted only when operating in
2852 * hostap, adhoc, or monitor modes
2853 * o enable promiscuous mode according to the interface state
2854 * o accept beacons:
2855 * - when operating in adhoc mode so the 802.11 layer creates
2856 * node table entries for peers,
2857 * - when operating in station mode for collecting rssi data when
2858 * the station is otherwise quiet, or
2859 * - when scanning
2860 */
2861static void ath5k_configure_filter(struct ieee80211_hw *hw,
2862 unsigned int changed_flags,
2863 unsigned int *new_flags,
2864 int mc_count, struct dev_mc_list *mclist)
2865{
2866 struct ath5k_softc *sc = hw->priv;
2867 struct ath5k_hw *ah = sc->ah;
2868 u32 mfilt[2], val, rfilt;
2869 u8 pos;
2870 int i;
2871
2872 mfilt[0] = 0;
2873 mfilt[1] = 0;
2874
2875 /* Only deal with supported flags */
2876 changed_flags &= SUPPORTED_FIF_FLAGS;
2877 *new_flags &= SUPPORTED_FIF_FLAGS;
2878
2879 /* If HW detects any phy or radar errors, leave those filters on.
2880 * Also, always enable Unicast, Broadcasts and Multicast
2881 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2882 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2883 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2884 AR5K_RX_FILTER_MCAST);
2885
2886 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2887 if (*new_flags & FIF_PROMISC_IN_BSS) {
2888 rfilt |= AR5K_RX_FILTER_PROM;
2889 __set_bit(ATH_STAT_PROMISC, sc->status);
2890 }
2891 else
2892 __clear_bit(ATH_STAT_PROMISC, sc->status);
2893 }
2894
2895 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2896 if (*new_flags & FIF_ALLMULTI) {
2897 mfilt[0] = ~0;
2898 mfilt[1] = ~0;
2899 } else {
2900 for (i = 0; i < mc_count; i++) {
2901 if (!mclist)
2902 break;
2903 /* calculate XOR of eight 6-bit values */
533dd1b0 2904 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2905 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2906 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2907 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2908 pos &= 0x3f;
2909 mfilt[pos / 32] |= (1 << (pos % 32));
2910 /* XXX: we might be able to just do this instead,
2911 * but not sure, needs testing, if we do use this we'd
2912 * neet to inform below to not reset the mcast */
2913 /* ath5k_hw_set_mcast_filterindex(ah,
2914 * mclist->dmi_addr[5]); */
2915 mclist = mclist->next;
2916 }
2917 }
2918
2919 /* This is the best we can do */
2920 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2921 rfilt |= AR5K_RX_FILTER_PHYERR;
2922
2923 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2924 * and probes for any BSSID, this needs testing */
2925 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2926 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2927
2928 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2929 * set we should only pass on control frames for this
2930 * station. This needs testing. I believe right now this
2931 * enables *all* control frames, which is OK.. but
2932 * but we should see if we can improve on granularity */
2933 if (*new_flags & FIF_CONTROL)
2934 rfilt |= AR5K_RX_FILTER_CONTROL;
2935
2936 /* Additional settings per mode -- this is per ath5k */
2937
2938 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2939
2940 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2941 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2942 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2943 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2944 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2945 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2946 test_bit(ATH_STAT_PROMISC, sc->status))
2947 rfilt |= AR5K_RX_FILTER_PROM;
2948 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2949 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2950 rfilt |= AR5K_RX_FILTER_BEACON;
2951 }
2952
2953 /* Set filters */
2954 ath5k_hw_set_rx_filter(ah,rfilt);
2955
2956 /* Set multicast bits */
2957 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2958 /* Set the cached hw filter flags, this will alter actually
2959 * be set in HW */
2960 sc->filter_flags = rfilt;
2961}
2962
2963static int
2964ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2965 const u8 *local_addr, const u8 *addr,
2966 struct ieee80211_key_conf *key)
2967{
2968 struct ath5k_softc *sc = hw->priv;
2969 int ret = 0;
2970
2971 switch(key->alg) {
2972 case ALG_WEP:
6844e63a
LR		 2973 /* XXX: fix hardware encryption, its not working. For now
2974 * allow software encryption */
2975 /* break; */
fa1c114f
JS		 2976 case ALG_TKIP:
2977 case ALG_CCMP:
2978 return -EOPNOTSUPP;
2979 default:
2980 WARN_ON(1);
2981 return -EINVAL;
2982 }
2983
2984 mutex_lock(&sc->lock);
2985
2986 switch (cmd) {
2987 case SET_KEY:
2988 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2989 if (ret) {
2990 ATH5K_ERR(sc, "can't set the key\n");
2991 goto unlock;
2992 }
2993 __set_bit(key->keyidx, sc->keymap);
2994 key->hw_key_idx = key->keyidx;
2995 break;
2996 case DISABLE_KEY:
2997 ath5k_hw_reset_key(sc->ah, key->keyidx);
2998 __clear_bit(key->keyidx, sc->keymap);
2999 break;
3000 default:
3001 ret = -EINVAL;
3002 goto unlock;
3003 }
3004
3005unlock:
274c7c36 3006 mmiowb();
fa1c114f
JS		 3007 mutex_unlock(&sc->lock);
3008 return ret;
3009}
3010
3011static int
3012ath5k_get_stats(struct ieee80211_hw *hw,
3013 struct ieee80211_low_level_stats *stats)
3014{
3015 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3016 struct ath5k_hw *ah = sc->ah;
3017
3018 /* Force update */
3019 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3020
3021 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3022
3023 return 0;
3024}
3025
3026static int
3027ath5k_get_tx_stats(struct ieee80211_hw *hw,
3028 struct ieee80211_tx_queue_stats *stats)
3029{
3030 struct ath5k_softc *sc = hw->priv;
3031
3032 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3033
3034 return 0;
3035}
3036
3037static u64
3038ath5k_get_tsf(struct ieee80211_hw *hw)
3039{
3040 struct ath5k_softc *sc = hw->priv;
3041
3042 return ath5k_hw_get_tsf64(sc->ah);
3043}
3044
3045static void
3046ath5k_reset_tsf(struct ieee80211_hw *hw)
3047{
3048 struct ath5k_softc *sc = hw->priv;
3049
9804b98d
BR		 3050 /*
3051 * in IBSS mode we need to update the beacon timers too.
3052 * this will also reset the TSF if we call it with 0
3053 */
3054 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3055 ath5k_beacon_update_timers(sc, 0);
3056 else
3057 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3058}
3059
3060static int
e039fa4a 3061ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3062{
3063 struct ath5k_softc *sc = hw->priv;
3064 int ret;
3065
3066 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3067
3068 mutex_lock(&sc->lock);
3069
3070 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3071 ret = -EIO;
3072 goto end;
3073 }
3074
3075 ath5k_txbuf_free(sc, sc->bbuf);
3076 sc->bbuf->skb = skb;
e039fa4a 3077 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3078 if (ret)
3079 sc->bbuf->skb = NULL;
274c7c36 3080 else {
fa1c114f 3081 ath5k_beacon_config(sc);
274c7c36
JS		 3082 mmiowb();
3083 }
fa1c114f
JS		 3084
3085end:
3086 mutex_unlock(&sc->lock);
3087 return ret;
3088}
3089
Linux kernel - Deliverables
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