Commit | Line | Data |
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f1dc5600 S |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f1dc5600 | 18 | |
cbe61d8a | 19 | static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, |
f1dc5600 S |
20 | u32 reg, u32 mask, |
21 | u32 shift, u32 val) | |
22 | { | |
23 | u32 regVal; | |
24 | ||
25 | regVal = REG_READ(ah, reg) & ~mask; | |
26 | regVal |= (val << shift) & mask; | |
27 | ||
28 | REG_WRITE(ah, reg, regVal); | |
29 | ||
30 | if (ah->ah_config.analog_shiftreg) | |
31 | udelay(100); | |
32 | ||
33 | return; | |
34 | } | |
35 | ||
36 | static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) | |
37 | { | |
38 | ||
39 | if (fbin == AR5416_BCHAN_UNUSED) | |
40 | return fbin; | |
41 | ||
42 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); | |
43 | } | |
44 | ||
45 | static inline int16_t ath9k_hw_interpolate(u16 target, | |
46 | u16 srcLeft, u16 srcRight, | |
47 | int16_t targetLeft, | |
48 | int16_t targetRight) | |
49 | { | |
50 | int16_t rv; | |
51 | ||
52 | if (srcRight == srcLeft) { | |
53 | rv = targetLeft; | |
54 | } else { | |
55 | rv = (int16_t) (((target - srcLeft) * targetRight + | |
56 | (srcRight - target) * targetLeft) / | |
57 | (srcRight - srcLeft)); | |
58 | } | |
59 | return rv; | |
60 | } | |
61 | ||
62 | static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, | |
63 | u16 listSize, u16 *indexL, | |
64 | u16 *indexR) | |
65 | { | |
66 | u16 i; | |
67 | ||
68 | if (target <= pList[0]) { | |
69 | *indexL = *indexR = 0; | |
70 | return true; | |
71 | } | |
72 | if (target >= pList[listSize - 1]) { | |
73 | *indexL = *indexR = (u16) (listSize - 1); | |
74 | return true; | |
75 | } | |
76 | ||
77 | for (i = 0; i < listSize - 1; i++) { | |
78 | if (pList[i] == target) { | |
79 | *indexL = *indexR = i; | |
80 | return true; | |
81 | } | |
82 | if (target < pList[i + 1]) { | |
83 | *indexL = i; | |
84 | *indexR = (u16) (i + 1); | |
85 | return false; | |
86 | } | |
87 | } | |
88 | return false; | |
89 | } | |
90 | ||
cbe61d8a | 91 | static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) |
f1dc5600 | 92 | { |
9dbeb91a GJ |
93 | struct ath_softc *sc = ah->ah_sc; |
94 | ||
95 | return sc->bus_ops->eeprom_read(ah, off, data); | |
f1dc5600 S |
96 | } |
97 | ||
cbe61d8a | 98 | static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) |
f1dc5600 | 99 | { |
e7594072 | 100 | #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) |
cbe61d8a | 101 | struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; |
f1dc5600 | 102 | u16 *eep_data; |
e7594072 SB |
103 | int addr, eep_start_loc = 0; |
104 | ||
105 | eep_start_loc = 64; | |
f1dc5600 S |
106 | |
107 | if (!ath9k_hw_use_flash(ah)) { | |
108 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 109 | "Reading from EEPROM, not flash\n"); |
f1dc5600 S |
110 | } |
111 | ||
e7594072 SB |
112 | eep_data = (u16 *)eep; |
113 | ||
114 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { | |
115 | if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { | |
116 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
117 | "Unable to read eeprom region \n"); | |
118 | return false; | |
119 | } | |
120 | eep_data++; | |
121 | } | |
122 | return true; | |
123 | #undef SIZE_EEPROM_4K | |
124 | } | |
125 | ||
cbe61d8a | 126 | static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah) |
e7594072 SB |
127 | { |
128 | #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) | |
cbe61d8a | 129 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
e7594072 SB |
130 | u16 *eep_data; |
131 | int addr, ar5416_eep_start_loc = 0x100; | |
f1dc5600 S |
132 | |
133 | eep_data = (u16 *)eep; | |
134 | ||
e7594072 | 135 | for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { |
f1dc5600 S |
136 | if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, |
137 | eep_data)) { | |
138 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
e7594072 | 139 | "Unable to read eeprom region\n"); |
f1dc5600 S |
140 | return false; |
141 | } | |
142 | eep_data++; | |
143 | } | |
144 | return true; | |
e7594072 SB |
145 | #undef SIZE_EEPROM_DEF |
146 | } | |
147 | ||
cbe61d8a | 148 | static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = { |
e7594072 SB |
149 | ath9k_hw_fill_def_eeprom, |
150 | ath9k_hw_fill_4k_eeprom | |
151 | }; | |
152 | ||
cbe61d8a | 153 | static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah) |
e7594072 | 154 | { |
cbe61d8a | 155 | return ath9k_fill_eeprom[ah->ah_eep_map](ah); |
f1dc5600 S |
156 | } |
157 | ||
cbe61d8a | 158 | static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) |
f1dc5600 | 159 | { |
e7594072 | 160 | struct ar5416_eeprom_def *eep = |
cbe61d8a | 161 | (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; |
f1dc5600 S |
162 | u16 *eepdata, temp, magic, magic2; |
163 | u32 sum = 0, el; | |
164 | bool need_swap = false; | |
165 | int i, addr, size; | |
166 | ||
e7594072 SB |
167 | if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, |
168 | &magic)) { | |
169 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
170 | "Reading Magic # failed\n"); | |
171 | return false; | |
172 | } | |
173 | ||
f1dc5600 | 174 | if (!ath9k_hw_use_flash(ah)) { |
f1dc5600 | 175 | |
e7594072 SB |
176 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, |
177 | "Read Magic = 0x%04X\n", magic); | |
f1dc5600 S |
178 | |
179 | if (magic != AR5416_EEPROM_MAGIC) { | |
180 | magic2 = swab16(magic); | |
181 | ||
182 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
e7594072 | 183 | size = sizeof(struct ar5416_eeprom_def); |
f1dc5600 | 184 | need_swap = true; |
cbe61d8a | 185 | eepdata = (u16 *) (&ah->ah_eeprom); |
f1dc5600 S |
186 | |
187 | for (addr = 0; addr < size / sizeof(u16); addr++) { | |
188 | temp = swab16(*eepdata); | |
189 | *eepdata = temp; | |
190 | eepdata++; | |
191 | ||
192 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
193 | "0x%04X ", *eepdata); | |
194 | ||
195 | if (((addr + 1) % 6) == 0) | |
196 | DPRINTF(ah->ah_sc, | |
197 | ATH_DBG_EEPROM, "\n"); | |
198 | } | |
199 | } else { | |
200 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
201 | "Invalid EEPROM Magic. " | |
202 | "endianness mismatch.\n"); | |
203 | return -EINVAL; | |
204 | } | |
205 | } | |
206 | } | |
207 | ||
208 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", | |
209 | need_swap ? "True" : "False"); | |
210 | ||
211 | if (need_swap) | |
cbe61d8a | 212 | el = swab16(ah->ah_eeprom.def.baseEepHeader.length); |
f1dc5600 | 213 | else |
cbe61d8a | 214 | el = ah->ah_eeprom.def.baseEepHeader.length; |
f1dc5600 | 215 | |
e7594072 SB |
216 | if (el > sizeof(struct ar5416_eeprom_def)) |
217 | el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); | |
f1dc5600 S |
218 | else |
219 | el = el / sizeof(u16); | |
220 | ||
cbe61d8a | 221 | eepdata = (u16 *)(&ah->ah_eeprom); |
f1dc5600 S |
222 | |
223 | for (i = 0; i < el; i++) | |
224 | sum ^= *eepdata++; | |
225 | ||
226 | if (need_swap) { | |
227 | u32 integer, j; | |
228 | u16 word; | |
229 | ||
230 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
231 | "EEPROM Endianness is not native.. Changing \n"); | |
232 | ||
233 | word = swab16(eep->baseEepHeader.length); | |
234 | eep->baseEepHeader.length = word; | |
235 | ||
236 | word = swab16(eep->baseEepHeader.checksum); | |
237 | eep->baseEepHeader.checksum = word; | |
238 | ||
239 | word = swab16(eep->baseEepHeader.version); | |
240 | eep->baseEepHeader.version = word; | |
241 | ||
242 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
243 | eep->baseEepHeader.regDmn[0] = word; | |
244 | ||
245 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
246 | eep->baseEepHeader.regDmn[1] = word; | |
247 | ||
248 | word = swab16(eep->baseEepHeader.rfSilent); | |
249 | eep->baseEepHeader.rfSilent = word; | |
250 | ||
251 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
252 | eep->baseEepHeader.blueToothOptions = word; | |
253 | ||
254 | word = swab16(eep->baseEepHeader.deviceCap); | |
255 | eep->baseEepHeader.deviceCap = word; | |
256 | ||
257 | for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { | |
258 | struct modal_eep_header *pModal = | |
259 | &eep->modalHeader[j]; | |
260 | integer = swab32(pModal->antCtrlCommon); | |
261 | pModal->antCtrlCommon = integer; | |
262 | ||
263 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
264 | integer = swab32(pModal->antCtrlChain[i]); | |
265 | pModal->antCtrlChain[i] = integer; | |
266 | } | |
267 | ||
268 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | |
269 | word = swab16(pModal->spurChans[i].spurChan); | |
270 | pModal->spurChans[i].spurChan = word; | |
271 | } | |
272 | } | |
273 | } | |
274 | ||
cbe61d8a S |
275 | if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER || |
276 | ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
f1dc5600 S |
277 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, |
278 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | |
cbe61d8a | 279 | sum, ar5416_get_eep_ver(ah)); |
f1dc5600 S |
280 | return -EINVAL; |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
cbe61d8a | 286 | static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) |
e7594072 SB |
287 | { |
288 | #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) | |
e7594072 | 289 | struct ar5416_eeprom_4k *eep = |
cbe61d8a | 290 | (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; |
e7594072 SB |
291 | u16 *eepdata, temp, magic, magic2; |
292 | u32 sum = 0, el; | |
293 | bool need_swap = false; | |
294 | int i, addr; | |
295 | ||
296 | ||
297 | if (!ath9k_hw_use_flash(ah)) { | |
298 | ||
299 | if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, | |
300 | &magic)) { | |
301 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
302 | "Reading Magic # failed\n"); | |
303 | return false; | |
304 | } | |
305 | ||
306 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
307 | "Read Magic = 0x%04X\n", magic); | |
308 | ||
309 | if (magic != AR5416_EEPROM_MAGIC) { | |
310 | magic2 = swab16(magic); | |
311 | ||
312 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
313 | need_swap = true; | |
cbe61d8a | 314 | eepdata = (u16 *) (&ah->ah_eeprom); |
e7594072 SB |
315 | |
316 | for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { | |
317 | temp = swab16(*eepdata); | |
318 | *eepdata = temp; | |
319 | eepdata++; | |
320 | ||
321 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
322 | "0x%04X ", *eepdata); | |
323 | ||
324 | if (((addr + 1) % 6) == 0) | |
325 | DPRINTF(ah->ah_sc, | |
326 | ATH_DBG_EEPROM, "\n"); | |
327 | } | |
328 | } else { | |
329 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
330 | "Invalid EEPROM Magic. " | |
331 | "endianness mismatch.\n"); | |
332 | return -EINVAL; | |
333 | } | |
334 | } | |
335 | } | |
336 | ||
337 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", | |
338 | need_swap ? "True" : "False"); | |
339 | ||
340 | if (need_swap) | |
cbe61d8a | 341 | el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); |
e7594072 | 342 | else |
cbe61d8a | 343 | el = ah->ah_eeprom.map4k.baseEepHeader.length; |
e7594072 SB |
344 | |
345 | if (el > sizeof(struct ar5416_eeprom_def)) | |
346 | el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); | |
347 | else | |
348 | el = el / sizeof(u16); | |
349 | ||
cbe61d8a | 350 | eepdata = (u16 *)(&ah->ah_eeprom); |
e7594072 SB |
351 | |
352 | for (i = 0; i < el; i++) | |
353 | sum ^= *eepdata++; | |
354 | ||
355 | if (need_swap) { | |
356 | u32 integer; | |
357 | u16 word; | |
358 | ||
359 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
360 | "EEPROM Endianness is not native.. Changing \n"); | |
361 | ||
362 | word = swab16(eep->baseEepHeader.length); | |
363 | eep->baseEepHeader.length = word; | |
364 | ||
365 | word = swab16(eep->baseEepHeader.checksum); | |
366 | eep->baseEepHeader.checksum = word; | |
367 | ||
368 | word = swab16(eep->baseEepHeader.version); | |
369 | eep->baseEepHeader.version = word; | |
370 | ||
371 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
372 | eep->baseEepHeader.regDmn[0] = word; | |
373 | ||
374 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
375 | eep->baseEepHeader.regDmn[1] = word; | |
376 | ||
377 | word = swab16(eep->baseEepHeader.rfSilent); | |
378 | eep->baseEepHeader.rfSilent = word; | |
379 | ||
380 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
381 | eep->baseEepHeader.blueToothOptions = word; | |
382 | ||
383 | word = swab16(eep->baseEepHeader.deviceCap); | |
384 | eep->baseEepHeader.deviceCap = word; | |
385 | ||
386 | integer = swab32(eep->modalHeader.antCtrlCommon); | |
387 | eep->modalHeader.antCtrlCommon = integer; | |
388 | ||
389 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
390 | integer = swab32(eep->modalHeader.antCtrlChain[i]); | |
391 | eep->modalHeader.antCtrlChain[i] = integer; | |
392 | } | |
393 | ||
394 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | |
395 | word = swab16(eep->modalHeader.spurChans[i].spurChan); | |
396 | eep->modalHeader.spurChans[i].spurChan = word; | |
397 | } | |
398 | } | |
399 | ||
cbe61d8a S |
400 | if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER || |
401 | ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
e7594072 SB |
402 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, |
403 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | |
cbe61d8a | 404 | sum, ar5416_get_eep4k_ver(ah)); |
e7594072 SB |
405 | return -EINVAL; |
406 | } | |
407 | ||
408 | return 0; | |
409 | #undef EEPROM_4K_SIZE | |
410 | } | |
411 | ||
cbe61d8a | 412 | static int (*ath9k_check_eeprom[]) (struct ath_hw *) = { |
e7594072 SB |
413 | ath9k_hw_check_def_eeprom, |
414 | ath9k_hw_check_4k_eeprom | |
415 | }; | |
416 | ||
cbe61d8a | 417 | static inline int ath9k_hw_check_eeprom(struct ath_hw *ah) |
e7594072 | 418 | { |
cbe61d8a | 419 | return ath9k_check_eeprom[ah->ah_eep_map](ah); |
e7594072 SB |
420 | } |
421 | ||
f1dc5600 S |
422 | static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, |
423 | u8 *pVpdList, u16 numIntercepts, | |
424 | u8 *pRetVpdList) | |
425 | { | |
426 | u16 i, k; | |
427 | u8 currPwr = pwrMin; | |
428 | u16 idxL = 0, idxR = 0; | |
429 | ||
430 | for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { | |
431 | ath9k_hw_get_lower_upper_index(currPwr, pPwrList, | |
432 | numIntercepts, &(idxL), | |
433 | &(idxR)); | |
434 | if (idxR < 1) | |
435 | idxR = 1; | |
436 | if (idxL == numIntercepts - 1) | |
437 | idxL = (u16) (numIntercepts - 2); | |
438 | if (pPwrList[idxL] == pPwrList[idxR]) | |
439 | k = pVpdList[idxL]; | |
440 | else | |
441 | k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + | |
442 | (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / | |
443 | (pPwrList[idxR] - pPwrList[idxL])); | |
444 | pRetVpdList[i] = (u8) k; | |
445 | currPwr += 2; | |
446 | } | |
447 | ||
448 | return true; | |
449 | } | |
450 | ||
cbe61d8a | 451 | static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, |
f1dc5600 | 452 | struct ath9k_channel *chan, |
e7594072 | 453 | struct cal_data_per_freq_4k *pRawDataSet, |
f1dc5600 S |
454 | u8 *bChans, u16 availPiers, |
455 | u16 tPdGainOverlap, int16_t *pMinCalPower, | |
456 | u16 *pPdGainBoundaries, u8 *pPDADCValues, | |
457 | u16 numXpdGains) | |
458 | { | |
e7594072 SB |
459 | #define TMP_VAL_VPD_TABLE \ |
460 | ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); | |
f1dc5600 S |
461 | int i, j, k; |
462 | int16_t ss; | |
463 | u16 idxL = 0, idxR = 0, numPiers; | |
e7594072 | 464 | static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS] |
f1dc5600 | 465 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
e7594072 | 466 | static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS] |
f1dc5600 | 467 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
e7594072 | 468 | static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] |
f1dc5600 S |
469 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; |
470 | ||
471 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | |
e7594072 SB |
472 | u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; |
473 | u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS]; | |
f1dc5600 S |
474 | int16_t vpdStep; |
475 | int16_t tmpVal; | |
476 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | |
477 | bool match; | |
478 | int16_t minDelta = 0; | |
479 | struct chan_centers centers; | |
e7594072 | 480 | #define PD_GAIN_BOUNDARY_DEFAULT 58; |
f1dc5600 S |
481 | |
482 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
483 | ||
484 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | |
485 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) | |
486 | break; | |
487 | } | |
488 | ||
e7594072 SB |
489 | match = ath9k_hw_get_lower_upper_index( |
490 | (u8)FREQ2FBIN(centers.synth_center, | |
491 | IS_CHAN_2GHZ(chan)), bChans, numPiers, | |
492 | &idxL, &idxR); | |
f1dc5600 S |
493 | |
494 | if (match) { | |
495 | for (i = 0; i < numXpdGains; i++) { | |
496 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | |
497 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | |
498 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
499 | pRawDataSet[idxL].pwrPdg[i], | |
500 | pRawDataSet[idxL].vpdPdg[i], | |
e7594072 | 501 | AR5416_EEP4K_PD_GAIN_ICEPTS, |
f1dc5600 S |
502 | vpdTableI[i]); |
503 | } | |
504 | } else { | |
505 | for (i = 0; i < numXpdGains; i++) { | |
506 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | |
507 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | |
508 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | |
509 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | |
510 | ||
511 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | |
512 | ||
513 | maxPwrT4[i] = | |
e7594072 SB |
514 | min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1], |
515 | pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]); | |
f1dc5600 S |
516 | |
517 | ||
518 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
519 | pPwrL, pVpdL, | |
e7594072 | 520 | AR5416_EEP4K_PD_GAIN_ICEPTS, |
f1dc5600 S |
521 | vpdTableL[i]); |
522 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
523 | pPwrR, pVpdR, | |
e7594072 | 524 | AR5416_EEP4K_PD_GAIN_ICEPTS, |
f1dc5600 S |
525 | vpdTableR[i]); |
526 | ||
527 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | |
528 | vpdTableI[i][j] = | |
529 | (u8)(ath9k_hw_interpolate((u16) | |
530 | FREQ2FBIN(centers. | |
531 | synth_center, | |
532 | IS_CHAN_2GHZ | |
533 | (chan)), | |
534 | bChans[idxL], bChans[idxR], | |
535 | vpdTableL[i][j], vpdTableR[i][j])); | |
536 | } | |
537 | } | |
538 | } | |
539 | ||
540 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); | |
541 | ||
542 | k = 0; | |
543 | ||
544 | for (i = 0; i < numXpdGains; i++) { | |
545 | if (i == (numXpdGains - 1)) | |
546 | pPdGainBoundaries[i] = | |
547 | (u16)(maxPwrT4[i] / 2); | |
548 | else | |
549 | pPdGainBoundaries[i] = | |
550 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | |
551 | ||
552 | pPdGainBoundaries[i] = | |
553 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | |
554 | ||
555 | if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { | |
556 | minDelta = pPdGainBoundaries[0] - 23; | |
557 | pPdGainBoundaries[0] = 23; | |
558 | } else { | |
559 | minDelta = 0; | |
560 | } | |
561 | ||
562 | if (i == 0) { | |
563 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
564 | ss = (int16_t)(0 - (minPwrT4[i] / 2)); | |
565 | else | |
566 | ss = 0; | |
567 | } else { | |
568 | ss = (int16_t)((pPdGainBoundaries[i - 1] - | |
569 | (minPwrT4[i] / 2)) - | |
570 | tPdGainOverlap + 1 + minDelta); | |
571 | } | |
572 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | |
573 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
574 | ||
575 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
576 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | |
577 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | |
578 | ss++; | |
579 | } | |
580 | ||
581 | sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | |
582 | tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - | |
583 | (minPwrT4[i] / 2)); | |
584 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | |
585 | tgtIndex : sizeCurrVpdTable; | |
586 | ||
e7594072 | 587 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) |
f1dc5600 | 588 | pPDADCValues[k++] = vpdTableI[i][ss++]; |
f1dc5600 S |
589 | |
590 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | |
591 | vpdTableI[i][sizeCurrVpdTable - 2]); | |
592 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
593 | ||
594 | if (tgtIndex > maxIndex) { | |
595 | while ((ss <= tgtIndex) && | |
596 | (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
e7594072 | 597 | tmpVal = (int16_t) TMP_VAL_VPD_TABLE; |
f1dc5600 S |
598 | pPDADCValues[k++] = (u8)((tmpVal > 255) ? |
599 | 255 : tmpVal); | |
600 | ss++; | |
601 | } | |
602 | } | |
603 | } | |
604 | ||
e7594072 SB |
605 | while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) { |
606 | pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT; | |
f1dc5600 S |
607 | i++; |
608 | } | |
609 | ||
610 | while (k < AR5416_NUM_PDADC_VALUES) { | |
611 | pPDADCValues[k] = pPDADCValues[k - 1]; | |
612 | k++; | |
613 | } | |
614 | ||
615 | return; | |
e7594072 | 616 | #undef TMP_VAL_VPD_TABLE |
f1dc5600 S |
617 | } |
618 | ||
cbe61d8a | 619 | static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, |
e7594072 SB |
620 | struct ath9k_channel *chan, |
621 | struct cal_data_per_freq *pRawDataSet, | |
622 | u8 *bChans, u16 availPiers, | |
623 | u16 tPdGainOverlap, int16_t *pMinCalPower, | |
624 | u16 *pPdGainBoundaries, u8 *pPDADCValues, | |
625 | u16 numXpdGains) | |
f1dc5600 | 626 | { |
e7594072 SB |
627 | int i, j, k; |
628 | int16_t ss; | |
629 | u16 idxL = 0, idxR = 0, numPiers; | |
630 | static u8 vpdTableL[AR5416_NUM_PD_GAINS] | |
631 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
632 | static u8 vpdTableR[AR5416_NUM_PD_GAINS] | |
633 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
634 | static u8 vpdTableI[AR5416_NUM_PD_GAINS] | |
635 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
636 | ||
637 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | |
638 | u8 minPwrT4[AR5416_NUM_PD_GAINS]; | |
639 | u8 maxPwrT4[AR5416_NUM_PD_GAINS]; | |
640 | int16_t vpdStep; | |
641 | int16_t tmpVal; | |
642 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | |
643 | bool match; | |
644 | int16_t minDelta = 0; | |
f1dc5600 | 645 | struct chan_centers centers; |
f1dc5600 S |
646 | |
647 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
f1dc5600 | 648 | |
e7594072 SB |
649 | for (numPiers = 0; numPiers < availPiers; numPiers++) { |
650 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) | |
651 | break; | |
f1dc5600 S |
652 | } |
653 | ||
e7594072 SB |
654 | match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, |
655 | IS_CHAN_2GHZ(chan)), | |
656 | bChans, numPiers, &idxL, &idxR); | |
f1dc5600 | 657 | |
e7594072 SB |
658 | if (match) { |
659 | for (i = 0; i < numXpdGains; i++) { | |
660 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | |
661 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | |
662 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
663 | pRawDataSet[idxL].pwrPdg[i], | |
664 | pRawDataSet[idxL].vpdPdg[i], | |
665 | AR5416_PD_GAIN_ICEPTS, | |
666 | vpdTableI[i]); | |
f1dc5600 | 667 | } |
e7594072 SB |
668 | } else { |
669 | for (i = 0; i < numXpdGains; i++) { | |
670 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | |
671 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | |
672 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | |
673 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | |
f1dc5600 | 674 | |
e7594072 SB |
675 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); |
676 | ||
677 | maxPwrT4[i] = | |
678 | min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], | |
679 | pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); | |
680 | ||
681 | ||
682 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
683 | pPwrL, pVpdL, | |
684 | AR5416_PD_GAIN_ICEPTS, | |
685 | vpdTableL[i]); | |
686 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
687 | pPwrR, pVpdR, | |
688 | AR5416_PD_GAIN_ICEPTS, | |
689 | vpdTableR[i]); | |
690 | ||
691 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | |
692 | vpdTableI[i][j] = | |
693 | (u8)(ath9k_hw_interpolate((u16) | |
694 | FREQ2FBIN(centers. | |
695 | synth_center, | |
696 | IS_CHAN_2GHZ | |
697 | (chan)), | |
698 | bChans[idxL], bChans[idxR], | |
699 | vpdTableL[i][j], vpdTableR[i][j])); | |
700 | } | |
701 | } | |
702 | } | |
703 | ||
704 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); | |
705 | ||
706 | k = 0; | |
707 | ||
708 | for (i = 0; i < numXpdGains; i++) { | |
709 | if (i == (numXpdGains - 1)) | |
710 | pPdGainBoundaries[i] = | |
711 | (u16)(maxPwrT4[i] / 2); | |
712 | else | |
713 | pPdGainBoundaries[i] = | |
714 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | |
715 | ||
716 | pPdGainBoundaries[i] = | |
717 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | |
718 | ||
719 | if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { | |
720 | minDelta = pPdGainBoundaries[0] - 23; | |
721 | pPdGainBoundaries[0] = 23; | |
722 | } else { | |
723 | minDelta = 0; | |
724 | } | |
725 | ||
726 | if (i == 0) { | |
727 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
728 | ss = (int16_t)(0 - (minPwrT4[i] / 2)); | |
729 | else | |
730 | ss = 0; | |
731 | } else { | |
732 | ss = (int16_t)((pPdGainBoundaries[i - 1] - | |
733 | (minPwrT4[i] / 2)) - | |
734 | tPdGainOverlap + 1 + minDelta); | |
735 | } | |
736 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | |
737 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
738 | ||
739 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
740 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | |
741 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | |
742 | ss++; | |
743 | } | |
744 | ||
745 | sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | |
746 | tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - | |
747 | (minPwrT4[i] / 2)); | |
748 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | |
749 | tgtIndex : sizeCurrVpdTable; | |
750 | ||
751 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
752 | pPDADCValues[k++] = vpdTableI[i][ss++]; | |
753 | } | |
754 | ||
755 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | |
756 | vpdTableI[i][sizeCurrVpdTable - 2]); | |
757 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
758 | ||
759 | if (tgtIndex > maxIndex) { | |
760 | while ((ss <= tgtIndex) && | |
761 | (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
762 | tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + | |
763 | (ss - maxIndex + 1) * vpdStep)); | |
764 | pPDADCValues[k++] = (u8)((tmpVal > 255) ? | |
765 | 255 : tmpVal); | |
766 | ss++; | |
767 | } | |
768 | } | |
769 | } | |
770 | ||
771 | while (i < AR5416_PD_GAINS_IN_MASK) { | |
772 | pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; | |
773 | i++; | |
774 | } | |
775 | ||
776 | while (k < AR5416_NUM_PDADC_VALUES) { | |
777 | pPDADCValues[k] = pPDADCValues[k - 1]; | |
778 | k++; | |
779 | } | |
780 | ||
781 | return; | |
782 | } | |
783 | ||
cbe61d8a | 784 | static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, |
e7594072 SB |
785 | struct ath9k_channel *chan, |
786 | struct cal_target_power_leg *powInfo, | |
787 | u16 numChannels, | |
788 | struct cal_target_power_leg *pNewPower, | |
789 | u16 numRates, bool isExtTarget) | |
790 | { | |
791 | struct chan_centers centers; | |
792 | u16 clo, chi; | |
793 | int i; | |
794 | int matchIndex = -1, lowIndex = -1; | |
795 | u16 freq; | |
796 | ||
797 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
798 | freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; | |
799 | ||
800 | if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, | |
801 | IS_CHAN_2GHZ(chan))) { | |
802 | matchIndex = 0; | |
803 | } else { | |
804 | for (i = 0; (i < numChannels) && | |
805 | (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | |
806 | if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
807 | IS_CHAN_2GHZ(chan))) { | |
808 | matchIndex = i; | |
809 | break; | |
810 | } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
811 | IS_CHAN_2GHZ(chan))) && | |
812 | (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, | |
813 | IS_CHAN_2GHZ(chan)))) { | |
814 | lowIndex = i - 1; | |
815 | break; | |
816 | } | |
817 | } | |
818 | if ((matchIndex == -1) && (lowIndex == -1)) | |
819 | matchIndex = i - 1; | |
820 | } | |
821 | ||
822 | if (matchIndex != -1) { | |
823 | *pNewPower = powInfo[matchIndex]; | |
824 | } else { | |
825 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | |
826 | IS_CHAN_2GHZ(chan)); | |
827 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | |
828 | IS_CHAN_2GHZ(chan)); | |
829 | ||
830 | for (i = 0; i < numRates; i++) { | |
831 | pNewPower->tPow2x[i] = | |
832 | (u8)ath9k_hw_interpolate(freq, clo, chi, | |
833 | powInfo[lowIndex].tPow2x[i], | |
834 | powInfo[lowIndex + 1].tPow2x[i]); | |
835 | } | |
836 | } | |
837 | } | |
838 | ||
cbe61d8a | 839 | static void ath9k_hw_get_target_powers(struct ath_hw *ah, |
e7594072 SB |
840 | struct ath9k_channel *chan, |
841 | struct cal_target_power_ht *powInfo, | |
842 | u16 numChannels, | |
843 | struct cal_target_power_ht *pNewPower, | |
844 | u16 numRates, bool isHt40Target) | |
f1dc5600 S |
845 | { |
846 | struct chan_centers centers; | |
847 | u16 clo, chi; | |
848 | int i; | |
849 | int matchIndex = -1, lowIndex = -1; | |
850 | u16 freq; | |
851 | ||
852 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
853 | freq = isHt40Target ? centers.synth_center : centers.ctl_center; | |
854 | ||
855 | if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { | |
856 | matchIndex = 0; | |
857 | } else { | |
858 | for (i = 0; (i < numChannels) && | |
859 | (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | |
860 | if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
861 | IS_CHAN_2GHZ(chan))) { | |
862 | matchIndex = i; | |
863 | break; | |
864 | } else | |
865 | if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
866 | IS_CHAN_2GHZ(chan))) && | |
867 | (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, | |
868 | IS_CHAN_2GHZ(chan)))) { | |
869 | lowIndex = i - 1; | |
870 | break; | |
871 | } | |
872 | } | |
873 | if ((matchIndex == -1) && (lowIndex == -1)) | |
874 | matchIndex = i - 1; | |
875 | } | |
876 | ||
877 | if (matchIndex != -1) { | |
878 | *pNewPower = powInfo[matchIndex]; | |
879 | } else { | |
880 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | |
881 | IS_CHAN_2GHZ(chan)); | |
882 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | |
883 | IS_CHAN_2GHZ(chan)); | |
884 | ||
885 | for (i = 0; i < numRates; i++) { | |
886 | pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, | |
887 | clo, chi, | |
888 | powInfo[lowIndex].tPow2x[i], | |
889 | powInfo[lowIndex + 1].tPow2x[i]); | |
890 | } | |
891 | } | |
892 | } | |
893 | ||
894 | static u16 ath9k_hw_get_max_edge_power(u16 freq, | |
895 | struct cal_ctl_edges *pRdEdgesPower, | |
e7594072 | 896 | bool is2GHz, int num_band_edges) |
f1dc5600 S |
897 | { |
898 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
899 | int i; | |
900 | ||
e7594072 | 901 | for (i = 0; (i < num_band_edges) && |
f1dc5600 S |
902 | (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { |
903 | if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { | |
904 | twiceMaxEdgePower = pRdEdgesPower[i].tPower; | |
905 | break; | |
906 | } else if ((i > 0) && | |
907 | (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, | |
908 | is2GHz))) { | |
909 | if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, | |
910 | is2GHz) < freq && | |
911 | pRdEdgesPower[i - 1].flag) { | |
912 | twiceMaxEdgePower = | |
913 | pRdEdgesPower[i - 1].tPower; | |
914 | } | |
915 | break; | |
916 | } | |
917 | } | |
918 | ||
919 | return twiceMaxEdgePower; | |
920 | } | |
921 | ||
cbe61d8a | 922 | static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, |
e7594072 SB |
923 | struct ath9k_channel *chan, |
924 | int16_t *pTxPowerIndexOffset) | |
f1dc5600 | 925 | { |
cbe61d8a | 926 | struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; |
e7594072 SB |
927 | struct cal_data_per_freq *pRawDataset; |
928 | u8 *pCalBChans = NULL; | |
929 | u16 pdGainOverlap_t2; | |
930 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
931 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; | |
932 | u16 numPiers, i, j; | |
933 | int16_t tMinCalPower; | |
934 | u16 numXpdGain, xpdMask; | |
935 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; | |
936 | u32 reg32, regOffset, regChainOffset; | |
937 | int16_t modalIdx; | |
f1dc5600 | 938 | |
e7594072 SB |
939 | modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; |
940 | xpdMask = pEepData->modalHeader[modalIdx].xpdGain; | |
f1dc5600 S |
941 | |
942 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
943 | AR5416_EEP_MINOR_VER_2) { | |
e7594072 SB |
944 | pdGainOverlap_t2 = |
945 | pEepData->modalHeader[modalIdx].pdGainOverlap; | |
946 | } else { | |
947 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
948 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
f1dc5600 S |
949 | } |
950 | ||
e7594072 SB |
951 | if (IS_CHAN_2GHZ(chan)) { |
952 | pCalBChans = pEepData->calFreqPier2G; | |
953 | numPiers = AR5416_NUM_2G_CAL_PIERS; | |
954 | } else { | |
955 | pCalBChans = pEepData->calFreqPier5G; | |
956 | numPiers = AR5416_NUM_5G_CAL_PIERS; | |
f1dc5600 S |
957 | } |
958 | ||
e7594072 | 959 | numXpdGain = 0; |
f1dc5600 | 960 | |
e7594072 SB |
961 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
962 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
963 | if (numXpdGain >= AR5416_NUM_PD_GAINS) | |
964 | break; | |
965 | xpdGainValues[numXpdGain] = | |
966 | (u16)(AR5416_PD_GAINS_IN_MASK - i); | |
967 | numXpdGain++; | |
968 | } | |
f1dc5600 S |
969 | } |
970 | ||
e7594072 SB |
971 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, |
972 | (numXpdGain - 1) & 0x3); | |
973 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
974 | xpdGainValues[0]); | |
975 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
976 | xpdGainValues[1]); | |
977 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | |
978 | xpdGainValues[2]); | |
f1dc5600 | 979 | |
e7594072 SB |
980 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
981 | if (AR_SREV_5416_V20_OR_LATER(ah) && | |
cbe61d8a | 982 | (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && |
e7594072 SB |
983 | (i != 0)) { |
984 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
985 | } else | |
986 | regChainOffset = i * 0x1000; | |
f1dc5600 | 987 | |
e7594072 SB |
988 | if (pEepData->baseEepHeader.txMask & (1 << i)) { |
989 | if (IS_CHAN_2GHZ(chan)) | |
990 | pRawDataset = pEepData->calPierData2G[i]; | |
991 | else | |
992 | pRawDataset = pEepData->calPierData5G[i]; | |
f1dc5600 | 993 | |
e7594072 SB |
994 | ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, |
995 | pRawDataset, pCalBChans, | |
996 | numPiers, pdGainOverlap_t2, | |
997 | &tMinCalPower, gainBoundaries, | |
998 | pdadcValues, numXpdGain); | |
f1dc5600 | 999 | |
e7594072 SB |
1000 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { |
1001 | REG_WRITE(ah, | |
1002 | AR_PHY_TPCRG5 + regChainOffset, | |
1003 | SM(pdGainOverlap_t2, | |
1004 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
1005 | | SM(gainBoundaries[0], | |
1006 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
1007 | | SM(gainBoundaries[1], | |
1008 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
1009 | | SM(gainBoundaries[2], | |
1010 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
1011 | | SM(gainBoundaries[3], | |
1012 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
1013 | } | |
f1dc5600 | 1014 | |
e7594072 SB |
1015 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; |
1016 | for (j = 0; j < 32; j++) { | |
1017 | reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | | |
1018 | ((pdadcValues[4 * j + 1] & 0xFF) << 8) | | |
1019 | ((pdadcValues[4 * j + 2] & 0xFF) << 16)| | |
1020 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | |
1021 | REG_WRITE(ah, regOffset, reg32); | |
f1dc5600 | 1022 | |
e7594072 SB |
1023 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, |
1024 | "PDADC (%d,%4x): %4.4x %8.8x\n", | |
1025 | i, regChainOffset, regOffset, | |
1026 | reg32); | |
1027 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
1028 | "PDADC: Chain %d | PDADC %3d " | |
1029 | "Value %3d | PDADC %3d Value %3d | " | |
1030 | "PDADC %3d Value %3d | PDADC %3d " | |
1031 | "Value %3d |\n", | |
1032 | i, 4 * j, pdadcValues[4 * j], | |
1033 | 4 * j + 1, pdadcValues[4 * j + 1], | |
1034 | 4 * j + 2, pdadcValues[4 * j + 2], | |
1035 | 4 * j + 3, | |
1036 | pdadcValues[4 * j + 3]); | |
f1dc5600 | 1037 | |
e7594072 SB |
1038 | regOffset += 4; |
1039 | } | |
1040 | } | |
1041 | } | |
f1dc5600 | 1042 | |
e7594072 | 1043 | *pTxPowerIndexOffset = 0; |
f1dc5600 | 1044 | |
e7594072 | 1045 | return true; |
f1dc5600 S |
1046 | } |
1047 | ||
cbe61d8a | 1048 | static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, |
e7594072 SB |
1049 | struct ath9k_channel *chan, |
1050 | int16_t *pTxPowerIndexOffset) | |
f1dc5600 | 1051 | { |
cbe61d8a | 1052 | struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; |
e7594072 SB |
1053 | struct cal_data_per_freq_4k *pRawDataset; |
1054 | u8 *pCalBChans = NULL; | |
1055 | u16 pdGainOverlap_t2; | |
1056 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
1057 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; | |
1058 | u16 numPiers, i, j; | |
1059 | int16_t tMinCalPower; | |
1060 | u16 numXpdGain, xpdMask; | |
1061 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; | |
1062 | u32 reg32, regOffset, regChainOffset; | |
f1dc5600 | 1063 | |
e7594072 | 1064 | xpdMask = pEepData->modalHeader.xpdGain; |
f1dc5600 | 1065 | |
e7594072 SB |
1066 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= |
1067 | AR5416_EEP_MINOR_VER_2) { | |
1068 | pdGainOverlap_t2 = | |
1069 | pEepData->modalHeader.pdGainOverlap; | |
1070 | } else { | |
1071 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
1072 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
1073 | } | |
f1dc5600 | 1074 | |
e7594072 SB |
1075 | pCalBChans = pEepData->calFreqPier2G; |
1076 | numPiers = AR5416_NUM_2G_CAL_PIERS; | |
f1dc5600 | 1077 | |
e7594072 | 1078 | numXpdGain = 0; |
f1dc5600 | 1079 | |
e7594072 SB |
1080 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
1081 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
1082 | if (numXpdGain >= AR5416_NUM_PD_GAINS) | |
1083 | break; | |
1084 | xpdGainValues[numXpdGain] = | |
1085 | (u16)(AR5416_PD_GAINS_IN_MASK - i); | |
1086 | numXpdGain++; | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
1091 | (numXpdGain - 1) & 0x3); | |
1092 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
1093 | xpdGainValues[0]); | |
1094 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
1095 | xpdGainValues[1]); | |
1096 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | |
1097 | xpdGainValues[2]); | |
f1dc5600 | 1098 | |
e7594072 SB |
1099 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { |
1100 | if (AR_SREV_5416_V20_OR_LATER(ah) && | |
cbe61d8a | 1101 | (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && |
e7594072 SB |
1102 | (i != 0)) { |
1103 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
1104 | } else | |
1105 | regChainOffset = i * 0x1000; | |
f1dc5600 | 1106 | |
e7594072 SB |
1107 | if (pEepData->baseEepHeader.txMask & (1 << i)) { |
1108 | pRawDataset = pEepData->calPierData2G[i]; | |
f1dc5600 | 1109 | |
e7594072 SB |
1110 | ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, |
1111 | pRawDataset, pCalBChans, | |
1112 | numPiers, pdGainOverlap_t2, | |
1113 | &tMinCalPower, gainBoundaries, | |
1114 | pdadcValues, numXpdGain); | |
f1dc5600 | 1115 | |
e7594072 SB |
1116 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { |
1117 | REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, | |
1118 | SM(pdGainOverlap_t2, | |
1119 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
1120 | | SM(gainBoundaries[0], | |
1121 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
1122 | | SM(gainBoundaries[1], | |
1123 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
1124 | | SM(gainBoundaries[2], | |
1125 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
1126 | | SM(gainBoundaries[3], | |
1127 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
1128 | } | |
1129 | ||
1130 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; | |
1131 | for (j = 0; j < 32; j++) { | |
1132 | reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | | |
1133 | ((pdadcValues[4 * j + 1] & 0xFF) << 8) | | |
1134 | ((pdadcValues[4 * j + 2] & 0xFF) << 16)| | |
1135 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | |
1136 | REG_WRITE(ah, regOffset, reg32); | |
1137 | ||
1138 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
1139 | "PDADC (%d,%4x): %4.4x %8.8x\n", | |
1140 | i, regChainOffset, regOffset, | |
1141 | reg32); | |
1142 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | |
1143 | "PDADC: Chain %d | " | |
1144 | "PDADC %3d Value %3d | " | |
1145 | "PDADC %3d Value %3d | " | |
1146 | "PDADC %3d Value %3d | " | |
1147 | "PDADC %3d Value %3d |\n", | |
1148 | i, 4 * j, pdadcValues[4 * j], | |
1149 | 4 * j + 1, pdadcValues[4 * j + 1], | |
1150 | 4 * j + 2, pdadcValues[4 * j + 2], | |
1151 | 4 * j + 3, | |
1152 | pdadcValues[4 * j + 3]); | |
1153 | ||
1154 | regOffset += 4; | |
f1dc5600 | 1155 | } |
f1dc5600 S |
1156 | } |
1157 | } | |
1158 | ||
e7594072 SB |
1159 | *pTxPowerIndexOffset = 0; |
1160 | ||
1161 | return true; | |
f1dc5600 S |
1162 | } |
1163 | ||
cbe61d8a | 1164 | static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, |
bf512bc8 HE |
1165 | struct ath9k_channel *chan, |
1166 | int16_t *ratesArray, | |
1167 | u16 cfgCtl, | |
1168 | u16 AntennaReduction, | |
1169 | u16 twiceMaxRegulatoryPower, | |
1170 | u16 powerLimit) | |
f1dc5600 | 1171 | { |
e7594072 SB |
1172 | #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ |
1173 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ | |
1174 | ||
cbe61d8a | 1175 | struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; |
e7594072 | 1176 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
f1dc5600 S |
1177 | static const u16 tpScaleReductionTable[5] = |
1178 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | |
1179 | ||
1180 | int i; | |
e7594072 | 1181 | int16_t twiceLargestAntenna; |
f1dc5600 S |
1182 | struct cal_ctl_data *rep; |
1183 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | |
1184 | 0, { 0, 0, 0, 0} | |
1185 | }; | |
1186 | struct cal_target_power_leg targetPowerOfdmExt = { | |
1187 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
1188 | 0, { 0, 0, 0, 0 } | |
1189 | }; | |
1190 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
1191 | 0, {0, 0, 0, 0} | |
1192 | }; | |
e7594072 | 1193 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; |
f1dc5600 S |
1194 | u16 ctlModesFor11a[] = |
1195 | { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; | |
1196 | u16 ctlModesFor11g[] = | |
1197 | { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, | |
1198 | CTL_2GHT40 | |
1199 | }; | |
1200 | u16 numCtlModes, *pCtlMode, ctlMode, freq; | |
1201 | struct chan_centers centers; | |
1202 | int tx_chainmask; | |
e7594072 | 1203 | u16 twiceMinEdgePower; |
f1dc5600 | 1204 | |
cbe61d8a | 1205 | tx_chainmask = ah->ah_txchainmask; |
f1dc5600 S |
1206 | |
1207 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1208 | ||
1209 | twiceLargestAntenna = max( | |
1210 | pEepData->modalHeader | |
1211 | [IS_CHAN_2GHZ(chan)].antennaGainCh[0], | |
1212 | pEepData->modalHeader | |
1213 | [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); | |
1214 | ||
1215 | twiceLargestAntenna = max((u8)twiceLargestAntenna, | |
1216 | pEepData->modalHeader | |
1217 | [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); | |
1218 | ||
e7594072 SB |
1219 | twiceLargestAntenna = (int16_t)min(AntennaReduction - |
1220 | twiceLargestAntenna, 0); | |
f1dc5600 S |
1221 | |
1222 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
1223 | ||
d6bad496 | 1224 | if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { |
f1dc5600 | 1225 | maxRegAllowedPower -= |
d6bad496 | 1226 | (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); |
f1dc5600 S |
1227 | } |
1228 | ||
1229 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
1230 | ||
1231 | switch (ar5416_get_ntxchains(tx_chainmask)) { | |
1232 | case 1: | |
1233 | break; | |
1234 | case 2: | |
e7594072 | 1235 | scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; |
f1dc5600 S |
1236 | break; |
1237 | case 3: | |
e7594072 | 1238 | scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; |
f1dc5600 S |
1239 | break; |
1240 | } | |
1241 | ||
e7594072 | 1242 | scaledPower = max((u16)0, scaledPower); |
f1dc5600 S |
1243 | |
1244 | if (IS_CHAN_2GHZ(chan)) { | |
1245 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - | |
1246 | SUB_NUM_CTL_MODES_AT_2G_40; | |
1247 | pCtlMode = ctlModesFor11g; | |
1248 | ||
1249 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1250 | pEepData->calTargetPowerCck, | |
1251 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1252 | &targetPowerCck, 4, false); | |
1253 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1254 | pEepData->calTargetPower2G, | |
1255 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1256 | &targetPowerOfdm, 4, false); | |
1257 | ath9k_hw_get_target_powers(ah, chan, | |
1258 | pEepData->calTargetPower2GHT20, | |
1259 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1260 | &targetPowerHt20, 8, false); | |
1261 | ||
1262 | if (IS_CHAN_HT40(chan)) { | |
1263 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
1264 | ath9k_hw_get_target_powers(ah, chan, | |
1265 | pEepData->calTargetPower2GHT40, | |
1266 | AR5416_NUM_2G_40_TARGET_POWERS, | |
1267 | &targetPowerHt40, 8, true); | |
1268 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1269 | pEepData->calTargetPowerCck, | |
1270 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1271 | &targetPowerCckExt, 4, true); | |
1272 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1273 | pEepData->calTargetPower2G, | |
1274 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1275 | &targetPowerOfdmExt, 4, true); | |
1276 | } | |
1277 | } else { | |
1278 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - | |
1279 | SUB_NUM_CTL_MODES_AT_5G_40; | |
1280 | pCtlMode = ctlModesFor11a; | |
1281 | ||
1282 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1283 | pEepData->calTargetPower5G, | |
1284 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1285 | &targetPowerOfdm, 4, false); | |
1286 | ath9k_hw_get_target_powers(ah, chan, | |
1287 | pEepData->calTargetPower5GHT20, | |
1288 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1289 | &targetPowerHt20, 8, false); | |
1290 | ||
1291 | if (IS_CHAN_HT40(chan)) { | |
1292 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | |
1293 | ath9k_hw_get_target_powers(ah, chan, | |
1294 | pEepData->calTargetPower5GHT40, | |
1295 | AR5416_NUM_5G_40_TARGET_POWERS, | |
1296 | &targetPowerHt40, 8, true); | |
1297 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1298 | pEepData->calTargetPower5G, | |
1299 | AR5416_NUM_5G_20_TARGET_POWERS, | |
1300 | &targetPowerOfdmExt, 4, true); | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
1305 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
1306 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
1307 | if (isHt40CtlMode) | |
1308 | freq = centers.synth_center; | |
1309 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
1310 | freq = centers.ext_center; | |
1311 | else | |
1312 | freq = centers.ctl_center; | |
1313 | ||
cbe61d8a | 1314 | if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2) |
f1dc5600 S |
1315 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
1316 | ||
1317 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1318 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " | |
1319 | "EXT_ADDITIVE %d\n", | |
1320 | ctlMode, numCtlModes, isHt40CtlMode, | |
1321 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | |
1322 | ||
1323 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { | |
1324 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1325 | " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " | |
1326 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " | |
1327 | "chan %d\n", | |
1328 | i, cfgCtl, pCtlMode[ctlMode], | |
1329 | pEepData->ctlIndex[i], chan->channel); | |
1330 | ||
1331 | if ((((cfgCtl & ~CTL_MODE_M) | | |
1332 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1333 | pEepData->ctlIndex[i]) || | |
1334 | (((cfgCtl & ~CTL_MODE_M) | | |
1335 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1336 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { | |
1337 | rep = &(pEepData->ctlData[i]); | |
1338 | ||
1339 | twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, | |
1340 | rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], | |
e7594072 | 1341 | IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); |
f1dc5600 S |
1342 | |
1343 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1344 | " MATCH-EE_IDX %d: ch %d is2 %d " | |
1345 | "2xMinEdge %d chainmask %d chains %d\n", | |
1346 | i, freq, IS_CHAN_2GHZ(chan), | |
1347 | twiceMinEdgePower, tx_chainmask, | |
1348 | ar5416_get_ntxchains | |
1349 | (tx_chainmask)); | |
1350 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
1351 | twiceMaxEdgePower = min(twiceMaxEdgePower, | |
1352 | twiceMinEdgePower); | |
1353 | } else { | |
1354 | twiceMaxEdgePower = twiceMinEdgePower; | |
1355 | break; | |
1356 | } | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | minCtlPower = min(twiceMaxEdgePower, scaledPower); | |
1361 | ||
1362 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1363 | " SEL-Min ctlMode %d pCtlMode %d " | |
1364 | "2xMaxEdge %d sP %d minCtlPwr %d\n", | |
1365 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | |
1366 | scaledPower, minCtlPower); | |
1367 | ||
1368 | switch (pCtlMode[ctlMode]) { | |
1369 | case CTL_11B: | |
1370 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { | |
1371 | targetPowerCck.tPow2x[i] = | |
e7594072 | 1372 | min((u16)targetPowerCck.tPow2x[i], |
f1dc5600 S |
1373 | minCtlPower); |
1374 | } | |
1375 | break; | |
1376 | case CTL_11A: | |
1377 | case CTL_11G: | |
1378 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { | |
1379 | targetPowerOfdm.tPow2x[i] = | |
e7594072 | 1380 | min((u16)targetPowerOfdm.tPow2x[i], |
f1dc5600 S |
1381 | minCtlPower); |
1382 | } | |
1383 | break; | |
1384 | case CTL_5GHT20: | |
1385 | case CTL_2GHT20: | |
1386 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { | |
1387 | targetPowerHt20.tPow2x[i] = | |
e7594072 | 1388 | min((u16)targetPowerHt20.tPow2x[i], |
f1dc5600 S |
1389 | minCtlPower); |
1390 | } | |
1391 | break; | |
1392 | case CTL_11B_EXT: | |
e7594072 SB |
1393 | targetPowerCckExt.tPow2x[0] = min((u16) |
1394 | targetPowerCckExt.tPow2x[0], | |
1395 | minCtlPower); | |
f1dc5600 S |
1396 | break; |
1397 | case CTL_11A_EXT: | |
1398 | case CTL_11G_EXT: | |
e7594072 SB |
1399 | targetPowerOfdmExt.tPow2x[0] = min((u16) |
1400 | targetPowerOfdmExt.tPow2x[0], | |
1401 | minCtlPower); | |
f1dc5600 S |
1402 | break; |
1403 | case CTL_5GHT40: | |
1404 | case CTL_2GHT40: | |
1405 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1406 | targetPowerHt40.tPow2x[i] = | |
e7594072 | 1407 | min((u16)targetPowerHt40.tPow2x[i], |
f1dc5600 S |
1408 | minCtlPower); |
1409 | } | |
1410 | break; | |
1411 | default: | |
1412 | break; | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = | |
1417 | ratesArray[rate18mb] = ratesArray[rate24mb] = | |
1418 | targetPowerOfdm.tPow2x[0]; | |
1419 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | |
1420 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
1421 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
1422 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
1423 | ||
1424 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
1425 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
1426 | ||
1427 | if (IS_CHAN_2GHZ(chan)) { | |
1428 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
1429 | ratesArray[rate2s] = ratesArray[rate2l] = | |
1430 | targetPowerCck.tPow2x[1]; | |
1431 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = | |
1432 | targetPowerCck.tPow2x[2]; | |
1433 | ; | |
1434 | ratesArray[rate11s] = ratesArray[rate11l] = | |
1435 | targetPowerCck.tPow2x[3]; | |
1436 | ; | |
1437 | } | |
1438 | if (IS_CHAN_HT40(chan)) { | |
1439 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1440 | ratesArray[rateHt40_0 + i] = | |
1441 | targetPowerHt40.tPow2x[i]; | |
1442 | } | |
1443 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
1444 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
1445 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
1446 | if (IS_CHAN_2GHZ(chan)) { | |
1447 | ratesArray[rateExtCck] = | |
1448 | targetPowerCckExt.tPow2x[0]; | |
1449 | } | |
1450 | } | |
1451 | return true; | |
1452 | } | |
1453 | ||
cbe61d8a | 1454 | static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, |
bf512bc8 HE |
1455 | struct ath9k_channel *chan, |
1456 | int16_t *ratesArray, | |
1457 | u16 cfgCtl, | |
1458 | u16 AntennaReduction, | |
1459 | u16 twiceMaxRegulatoryPower, | |
1460 | u16 powerLimit) | |
f1dc5600 | 1461 | { |
cbe61d8a | 1462 | struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; |
e7594072 SB |
1463 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
1464 | static const u16 tpScaleReductionTable[5] = | |
1465 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | |
f1dc5600 | 1466 | |
e7594072 SB |
1467 | int i; |
1468 | int16_t twiceLargestAntenna; | |
1469 | struct cal_ctl_data_4k *rep; | |
1470 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | |
1471 | 0, { 0, 0, 0, 0} | |
1472 | }; | |
1473 | struct cal_target_power_leg targetPowerOfdmExt = { | |
1474 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
1475 | 0, { 0, 0, 0, 0 } | |
1476 | }; | |
1477 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
1478 | 0, {0, 0, 0, 0} | |
1479 | }; | |
1480 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; | |
1481 | u16 ctlModesFor11g[] = | |
1482 | { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, | |
1483 | CTL_2GHT40 | |
1484 | }; | |
1485 | u16 numCtlModes, *pCtlMode, ctlMode, freq; | |
1486 | struct chan_centers centers; | |
1487 | int tx_chainmask; | |
1488 | u16 twiceMinEdgePower; | |
1489 | ||
cbe61d8a | 1490 | tx_chainmask = ah->ah_txchainmask; |
e7594072 SB |
1491 | |
1492 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
1493 | ||
1494 | twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; | |
1495 | ||
1496 | twiceLargestAntenna = (int16_t)min(AntennaReduction - | |
1497 | twiceLargestAntenna, 0); | |
1498 | ||
1499 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
1500 | ||
d6bad496 | 1501 | if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { |
e7594072 | 1502 | maxRegAllowedPower -= |
d6bad496 | 1503 | (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); |
e7594072 SB |
1504 | } |
1505 | ||
1506 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
1507 | scaledPower = max((u16)0, scaledPower); | |
1508 | ||
1509 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; | |
1510 | pCtlMode = ctlModesFor11g; | |
1511 | ||
1512 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1513 | pEepData->calTargetPowerCck, | |
1514 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1515 | &targetPowerCck, 4, false); | |
1516 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1517 | pEepData->calTargetPower2G, | |
1518 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1519 | &targetPowerOfdm, 4, false); | |
1520 | ath9k_hw_get_target_powers(ah, chan, | |
1521 | pEepData->calTargetPower2GHT20, | |
1522 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1523 | &targetPowerHt20, 8, false); | |
1524 | ||
1525 | if (IS_CHAN_HT40(chan)) { | |
1526 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
1527 | ath9k_hw_get_target_powers(ah, chan, | |
1528 | pEepData->calTargetPower2GHT40, | |
1529 | AR5416_NUM_2G_40_TARGET_POWERS, | |
1530 | &targetPowerHt40, 8, true); | |
1531 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1532 | pEepData->calTargetPowerCck, | |
1533 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
1534 | &targetPowerCckExt, 4, true); | |
1535 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
1536 | pEepData->calTargetPower2G, | |
1537 | AR5416_NUM_2G_20_TARGET_POWERS, | |
1538 | &targetPowerOfdmExt, 4, true); | |
1539 | } | |
1540 | ||
1541 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
1542 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
1543 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
1544 | if (isHt40CtlMode) | |
1545 | freq = centers.synth_center; | |
1546 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
1547 | freq = centers.ext_center; | |
1548 | else | |
1549 | freq = centers.ctl_center; | |
1550 | ||
cbe61d8a S |
1551 | if (ar5416_get_eep_ver(ah) == 14 && |
1552 | ar5416_get_eep_rev(ah) <= 2) | |
e7594072 SB |
1553 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
1554 | ||
1555 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1556 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " | |
1557 | "EXT_ADDITIVE %d\n", | |
1558 | ctlMode, numCtlModes, isHt40CtlMode, | |
1559 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | |
1560 | ||
1561 | for (i = 0; (i < AR5416_NUM_CTLS) && | |
1562 | pEepData->ctlIndex[i]; i++) { | |
1563 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1564 | " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " | |
1565 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " | |
1566 | "chan %d\n", | |
1567 | i, cfgCtl, pCtlMode[ctlMode], | |
1568 | pEepData->ctlIndex[i], chan->channel); | |
1569 | ||
1570 | if ((((cfgCtl & ~CTL_MODE_M) | | |
1571 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1572 | pEepData->ctlIndex[i]) || | |
1573 | (((cfgCtl & ~CTL_MODE_M) | | |
1574 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
1575 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | | |
1576 | SD_NO_CTL))) { | |
1577 | rep = &(pEepData->ctlData[i]); | |
1578 | ||
1579 | twiceMinEdgePower = | |
1580 | ath9k_hw_get_max_edge_power(freq, | |
1581 | rep->ctlEdges[ar5416_get_ntxchains | |
1582 | (tx_chainmask) - 1], | |
1583 | IS_CHAN_2GHZ(chan), | |
1584 | AR5416_EEP4K_NUM_BAND_EDGES); | |
1585 | ||
1586 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1587 | " MATCH-EE_IDX %d: ch %d is2 %d " | |
1588 | "2xMinEdge %d chainmask %d chains %d\n", | |
1589 | i, freq, IS_CHAN_2GHZ(chan), | |
1590 | twiceMinEdgePower, tx_chainmask, | |
1591 | ar5416_get_ntxchains | |
1592 | (tx_chainmask)); | |
1593 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
1594 | twiceMaxEdgePower = | |
1595 | min(twiceMaxEdgePower, | |
1596 | twiceMinEdgePower); | |
1597 | } else { | |
1598 | twiceMaxEdgePower = twiceMinEdgePower; | |
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | |
1605 | ||
1606 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1607 | " SEL-Min ctlMode %d pCtlMode %d " | |
1608 | "2xMaxEdge %d sP %d minCtlPwr %d\n", | |
1609 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | |
1610 | scaledPower, minCtlPower); | |
1611 | ||
1612 | switch (pCtlMode[ctlMode]) { | |
1613 | case CTL_11B: | |
1614 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); | |
1615 | i++) { | |
1616 | targetPowerCck.tPow2x[i] = | |
1617 | min((u16)targetPowerCck.tPow2x[i], | |
1618 | minCtlPower); | |
1619 | } | |
1620 | break; | |
1621 | case CTL_11G: | |
1622 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); | |
1623 | i++) { | |
1624 | targetPowerOfdm.tPow2x[i] = | |
1625 | min((u16)targetPowerOfdm.tPow2x[i], | |
1626 | minCtlPower); | |
1627 | } | |
1628 | break; | |
1629 | case CTL_2GHT20: | |
1630 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); | |
1631 | i++) { | |
1632 | targetPowerHt20.tPow2x[i] = | |
1633 | min((u16)targetPowerHt20.tPow2x[i], | |
1634 | minCtlPower); | |
1635 | } | |
1636 | break; | |
1637 | case CTL_11B_EXT: | |
1638 | targetPowerCckExt.tPow2x[0] = min((u16) | |
1639 | targetPowerCckExt.tPow2x[0], | |
1640 | minCtlPower); | |
1641 | break; | |
1642 | case CTL_11G_EXT: | |
1643 | targetPowerOfdmExt.tPow2x[0] = min((u16) | |
1644 | targetPowerOfdmExt.tPow2x[0], | |
1645 | minCtlPower); | |
1646 | break; | |
1647 | case CTL_2GHT40: | |
1648 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); | |
1649 | i++) { | |
1650 | targetPowerHt40.tPow2x[i] = | |
1651 | min((u16)targetPowerHt40.tPow2x[i], | |
1652 | minCtlPower); | |
1653 | } | |
1654 | break; | |
1655 | default: | |
1656 | break; | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = | |
1661 | ratesArray[rate18mb] = ratesArray[rate24mb] = | |
1662 | targetPowerOfdm.tPow2x[0]; | |
1663 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | |
1664 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
1665 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
1666 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
1667 | ||
1668 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
1669 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
1670 | ||
1671 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
1672 | ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; | |
1673 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; | |
1674 | ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; | |
1675 | ||
1676 | if (IS_CHAN_HT40(chan)) { | |
1677 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1678 | ratesArray[rateHt40_0 + i] = | |
1679 | targetPowerHt40.tPow2x[i]; | |
1680 | } | |
1681 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
1682 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
1683 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
1684 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; | |
1685 | } | |
1686 | return true; | |
1687 | } | |
1688 | ||
cbe61d8a | 1689 | static int ath9k_hw_def_set_txpower(struct ath_hw *ah, |
e7594072 SB |
1690 | struct ath9k_channel *chan, |
1691 | u16 cfgCtl, | |
1692 | u8 twiceAntennaReduction, | |
1693 | u8 twiceMaxRegulatoryPower, | |
1694 | u8 powerLimit) | |
1695 | { | |
cbe61d8a | 1696 | struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; |
e7594072 SB |
1697 | struct modal_eep_header *pModal = |
1698 | &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1699 | int16_t ratesArray[Ar5416RateSize]; | |
1700 | int16_t txPowerIndexOffset = 0; | |
1701 | u8 ht40PowerIncForPdadc = 2; | |
1702 | int i; | |
1703 | ||
1704 | memset(ratesArray, 0, sizeof(ratesArray)); | |
1705 | ||
1706 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1707 | AR5416_EEP_MINOR_VER_2) { | |
1708 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
1709 | } | |
1710 | ||
1711 | if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, | |
1712 | &ratesArray[0], cfgCtl, | |
1713 | twiceAntennaReduction, | |
1714 | twiceMaxRegulatoryPower, | |
1715 | powerLimit)) { | |
1716 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
1717 | "ath9k_hw_set_txpower: unable to set " | |
1718 | "tx power per rate table\n"); | |
1719 | return -EIO; | |
1720 | } | |
1721 | ||
1722 | if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { | |
1723 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
1724 | "ath9k_hw_set_txpower: unable to set power table\n"); | |
1725 | return -EIO; | |
1726 | } | |
1727 | ||
1728 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | |
1729 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
1730 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | |
1731 | ratesArray[i] = AR5416_MAX_RATE_POWER; | |
1732 | } | |
1733 | ||
1734 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1735 | for (i = 0; i < Ar5416RateSize; i++) | |
1736 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; | |
1737 | } | |
1738 | ||
1739 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | |
1740 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
1741 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
1742 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
1743 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
1744 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
1745 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
1746 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
1747 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
1748 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
1749 | ||
1750 | if (IS_CHAN_2GHZ(chan)) { | |
1751 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
1752 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
1753 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
1754 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
1755 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
1756 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
1757 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
1758 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
1759 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
1760 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
1761 | } | |
1762 | ||
1763 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | |
1764 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
1765 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
1766 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
1767 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
1768 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
1769 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
1770 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
1771 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
1772 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
1773 | ||
1774 | if (IS_CHAN_HT40(chan)) { | |
1775 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
1776 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
1777 | ht40PowerIncForPdadc, 24) | |
1778 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
1779 | ht40PowerIncForPdadc, 16) | |
1780 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
1781 | ht40PowerIncForPdadc, 8) | |
1782 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
1783 | ht40PowerIncForPdadc, 0)); | |
1784 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
1785 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
1786 | ht40PowerIncForPdadc, 24) | |
1787 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
1788 | ht40PowerIncForPdadc, 16) | |
1789 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
1790 | ht40PowerIncForPdadc, 8) | |
1791 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
1792 | ht40PowerIncForPdadc, 0)); | |
1793 | ||
1794 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
1795 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
1796 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
1797 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
1798 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
1799 | } | |
1800 | ||
1801 | REG_WRITE(ah, AR_PHY_POWER_TX_SUB, | |
1802 | ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) | |
1803 | | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); | |
1804 | ||
1805 | i = rate6mb; | |
1806 | ||
1807 | if (IS_CHAN_HT40(chan)) | |
1808 | i = rateHt40_0; | |
1809 | else if (IS_CHAN_HT20(chan)) | |
1810 | i = rateHt20_0; | |
1811 | ||
1812 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
d6bad496 | 1813 | ah->regulatory.max_power_level = |
e7594072 SB |
1814 | ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; |
1815 | else | |
d6bad496 | 1816 | ah->regulatory.max_power_level = ratesArray[i]; |
e7594072 SB |
1817 | |
1818 | return 0; | |
1819 | } | |
1820 | ||
cbe61d8a | 1821 | static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, |
e7594072 SB |
1822 | struct ath9k_channel *chan, |
1823 | u16 cfgCtl, | |
1824 | u8 twiceAntennaReduction, | |
1825 | u8 twiceMaxRegulatoryPower, | |
1826 | u8 powerLimit) | |
1827 | { | |
cbe61d8a | 1828 | struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; |
e7594072 SB |
1829 | struct modal_eep_4k_header *pModal = &pEepData->modalHeader; |
1830 | int16_t ratesArray[Ar5416RateSize]; | |
1831 | int16_t txPowerIndexOffset = 0; | |
1832 | u8 ht40PowerIncForPdadc = 2; | |
1833 | int i; | |
1834 | ||
1835 | memset(ratesArray, 0, sizeof(ratesArray)); | |
1836 | ||
1837 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1838 | AR5416_EEP_MINOR_VER_2) { | |
1839 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
1840 | } | |
1841 | ||
1842 | if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, | |
1843 | &ratesArray[0], cfgCtl, | |
1844 | twiceAntennaReduction, | |
1845 | twiceMaxRegulatoryPower, | |
1846 | powerLimit)) { | |
1847 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
1848 | "ath9k_hw_set_txpower: unable to set " | |
1849 | "tx power per rate table\n"); | |
1850 | return -EIO; | |
1851 | } | |
1852 | ||
1853 | if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { | |
1854 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
1855 | "ath9k_hw_set_txpower: unable to set power table\n"); | |
1856 | return -EIO; | |
1857 | } | |
1858 | ||
1859 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | |
1860 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
1861 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | |
1862 | ratesArray[i] = AR5416_MAX_RATE_POWER; | |
1863 | } | |
1864 | ||
1865 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1866 | for (i = 0; i < Ar5416RateSize; i++) | |
1867 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; | |
1868 | } | |
1869 | ||
1870 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | |
1871 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
1872 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
1873 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
1874 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
1875 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
1876 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
1877 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
1878 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
1879 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
1880 | ||
1881 | if (IS_CHAN_2GHZ(chan)) { | |
1882 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
1883 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
1884 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
1885 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
1886 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
1887 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
1888 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
1889 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
1890 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
1891 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
1892 | } | |
1893 | ||
1894 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | |
1895 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
1896 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
1897 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
1898 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
1899 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
1900 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
1901 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
1902 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
1903 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
1904 | ||
1905 | if (IS_CHAN_HT40(chan)) { | |
1906 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
1907 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
1908 | ht40PowerIncForPdadc, 24) | |
1909 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
1910 | ht40PowerIncForPdadc, 16) | |
1911 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
1912 | ht40PowerIncForPdadc, 8) | |
1913 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
1914 | ht40PowerIncForPdadc, 0)); | |
1915 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
1916 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
1917 | ht40PowerIncForPdadc, 24) | |
1918 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
1919 | ht40PowerIncForPdadc, 16) | |
1920 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
1921 | ht40PowerIncForPdadc, 8) | |
1922 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
1923 | ht40PowerIncForPdadc, 0)); | |
1924 | ||
1925 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
1926 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
1927 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
1928 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
1929 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
1930 | } | |
1931 | ||
1932 | i = rate6mb; | |
1933 | ||
1934 | if (IS_CHAN_HT40(chan)) | |
1935 | i = rateHt40_0; | |
1936 | else if (IS_CHAN_HT20(chan)) | |
1937 | i = rateHt20_0; | |
1938 | ||
1939 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
d6bad496 | 1940 | ah->regulatory.max_power_level = |
e7594072 SB |
1941 | ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; |
1942 | else | |
d6bad496 | 1943 | ah->regulatory.max_power_level = ratesArray[i]; |
e7594072 SB |
1944 | |
1945 | return 0; | |
1946 | } | |
1947 | ||
cbe61d8a | 1948 | static int (*ath9k_set_txpower[]) (struct ath_hw *, |
bf512bc8 HE |
1949 | struct ath9k_channel *, |
1950 | u16, u8, u8, u8) = { | |
e7594072 SB |
1951 | ath9k_hw_def_set_txpower, |
1952 | ath9k_hw_4k_set_txpower | |
1953 | }; | |
1954 | ||
cbe61d8a | 1955 | int ath9k_hw_set_txpower(struct ath_hw *ah, |
e7594072 SB |
1956 | struct ath9k_channel *chan, |
1957 | u16 cfgCtl, | |
1958 | u8 twiceAntennaReduction, | |
1959 | u8 twiceMaxRegulatoryPower, | |
1960 | u8 powerLimit) | |
1961 | { | |
cbe61d8a S |
1962 | return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl, |
1963 | twiceAntennaReduction, twiceMaxRegulatoryPower, | |
1964 | powerLimit); | |
e7594072 SB |
1965 | } |
1966 | ||
cbe61d8a | 1967 | static void ath9k_hw_set_def_addac(struct ath_hw *ah, |
e7594072 SB |
1968 | struct ath9k_channel *chan) |
1969 | { | |
1970 | #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) | |
1971 | struct modal_eep_header *pModal; | |
cbe61d8a | 1972 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
e7594072 SB |
1973 | u8 biaslevel; |
1974 | ||
d535a42a | 1975 | if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) |
e7594072 SB |
1976 | return; |
1977 | ||
cbe61d8a | 1978 | if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) |
e7594072 SB |
1979 | return; |
1980 | ||
1981 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1982 | ||
1983 | if (pModal->xpaBiasLvl != 0xff) { | |
1984 | biaslevel = pModal->xpaBiasLvl; | |
1985 | } else { | |
1986 | u16 resetFreqBin, freqBin, freqCount = 0; | |
1987 | struct chan_centers centers; | |
1988 | ||
1989 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
f1dc5600 | 1990 | |
e7594072 SB |
1991 | resetFreqBin = FREQ2FBIN(centers.synth_center, |
1992 | IS_CHAN_2GHZ(chan)); | |
1993 | freqBin = XPA_LVL_FREQ(0) & 0xff; | |
1994 | biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14); | |
f1dc5600 | 1995 | |
e7594072 | 1996 | freqCount++; |
f1dc5600 | 1997 | |
e7594072 SB |
1998 | while (freqCount < 3) { |
1999 | if (XPA_LVL_FREQ(freqCount) == 0x0) | |
f1dc5600 | 2000 | break; |
e7594072 SB |
2001 | |
2002 | freqBin = XPA_LVL_FREQ(freqCount) & 0xff; | |
2003 | if (resetFreqBin >= freqBin) | |
2004 | biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14); | |
2005 | else | |
2006 | break; | |
2007 | freqCount++; | |
f1dc5600 S |
2008 | } |
2009 | } | |
2010 | ||
e7594072 | 2011 | if (IS_CHAN_2GHZ(chan)) { |
cbe61d8a | 2012 | INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, |
e7594072 SB |
2013 | 7, 1) & (~0x18)) | biaslevel << 3; |
2014 | } else { | |
cbe61d8a | 2015 | INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, |
e7594072 SB |
2016 | 6, 1) & (~0xc0)) | biaslevel << 6; |
2017 | } | |
2018 | #undef XPA_LVL_FREQ | |
2019 | } | |
f1dc5600 | 2020 | |
cbe61d8a | 2021 | static void ath9k_hw_set_4k_addac(struct ath_hw *ah, |
e7594072 SB |
2022 | struct ath9k_channel *chan) |
2023 | { | |
2024 | struct modal_eep_4k_header *pModal; | |
cbe61d8a | 2025 | struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; |
e7594072 | 2026 | u8 biaslevel; |
f1dc5600 | 2027 | |
d535a42a | 2028 | if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) |
e7594072 | 2029 | return; |
f1dc5600 | 2030 | |
cbe61d8a | 2031 | if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) |
e7594072 | 2032 | return; |
f1dc5600 | 2033 | |
e7594072 | 2034 | pModal = &eep->modalHeader; |
f1dc5600 | 2035 | |
e7594072 SB |
2036 | if (pModal->xpaBiasLvl != 0xff) { |
2037 | biaslevel = pModal->xpaBiasLvl; | |
cbe61d8a S |
2038 | INI_RA(&ah->ah_iniAddac, 7, 1) = |
2039 | (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; | |
f1dc5600 | 2040 | } |
e7594072 | 2041 | } |
f1dc5600 | 2042 | |
cbe61d8a | 2043 | static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = { |
e7594072 SB |
2044 | ath9k_hw_set_def_addac, |
2045 | ath9k_hw_set_4k_addac | |
2046 | }; | |
f1dc5600 | 2047 | |
cbe61d8a | 2048 | void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) |
e7594072 | 2049 | { |
cbe61d8a | 2050 | ath9k_set_addac[ah->ah_eep_map](ah, chan); |
f1dc5600 S |
2051 | } |
2052 | ||
2053 | /* XXX: Clean me up, make me more legible */ | |
cbe61d8a | 2054 | static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, |
f1dc5600 S |
2055 | struct ath9k_channel *chan) |
2056 | { | |
cb33c412 | 2057 | #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) |
f1dc5600 | 2058 | struct modal_eep_header *pModal; |
cbe61d8a | 2059 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
f1dc5600 S |
2060 | int i, regChainOffset; |
2061 | u8 txRxAttenLocal; | |
f1dc5600 S |
2062 | |
2063 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
2064 | ||
2065 | txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; | |
2066 | ||
81b1e19a VT |
2067 | REG_WRITE(ah, AR_PHY_SWITCH_COM, |
2068 | ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); | |
f1dc5600 S |
2069 | |
2070 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
2071 | if (AR_SREV_9280(ah)) { | |
2072 | if (i >= 2) | |
2073 | break; | |
2074 | } | |
2075 | ||
2076 | if (AR_SREV_5416_V20_OR_LATER(ah) && | |
cbe61d8a | 2077 | (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) |
f1dc5600 S |
2078 | && (i != 0)) |
2079 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
2080 | else | |
2081 | regChainOffset = i * 0x1000; | |
2082 | ||
2083 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | |
2084 | pModal->antCtrlChain[i]); | |
2085 | ||
2086 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | |
2087 | (REG_READ(ah, | |
2088 | AR_PHY_TIMING_CTRL4(0) + | |
2089 | regChainOffset) & | |
2090 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | |
2091 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
2092 | SM(pModal->iqCalICh[i], | |
2093 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
2094 | SM(pModal->iqCalQCh[i], | |
2095 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
2096 | ||
2097 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { | |
cb33c412 | 2098 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { |
f1dc5600 S |
2099 | txRxAttenLocal = pModal->txRxAttenCh[i]; |
2100 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2101 | REG_RMW_FIELD(ah, | |
2102 | AR_PHY_GAIN_2GHZ + | |
2103 | regChainOffset, | |
2104 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
2105 | pModal-> | |
2106 | bswMargin[i]); | |
2107 | REG_RMW_FIELD(ah, | |
2108 | AR_PHY_GAIN_2GHZ + | |
2109 | regChainOffset, | |
2110 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, | |
2111 | pModal-> | |
2112 | bswAtten[i]); | |
2113 | REG_RMW_FIELD(ah, | |
2114 | AR_PHY_GAIN_2GHZ + | |
2115 | regChainOffset, | |
2116 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
2117 | pModal-> | |
2118 | xatten2Margin[i]); | |
2119 | REG_RMW_FIELD(ah, | |
2120 | AR_PHY_GAIN_2GHZ + | |
2121 | regChainOffset, | |
2122 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | |
2123 | pModal-> | |
2124 | xatten2Db[i]); | |
2125 | } else { | |
2126 | REG_WRITE(ah, | |
2127 | AR_PHY_GAIN_2GHZ + | |
2128 | regChainOffset, | |
2129 | (REG_READ(ah, | |
2130 | AR_PHY_GAIN_2GHZ + | |
2131 | regChainOffset) & | |
2132 | ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
2133 | | SM(pModal-> | |
2134 | bswMargin[i], | |
2135 | AR_PHY_GAIN_2GHZ_BSW_MARGIN)); | |
2136 | REG_WRITE(ah, | |
2137 | AR_PHY_GAIN_2GHZ + | |
2138 | regChainOffset, | |
2139 | (REG_READ(ah, | |
2140 | AR_PHY_GAIN_2GHZ + | |
2141 | regChainOffset) & | |
2142 | ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
2143 | | SM(pModal->bswAtten[i], | |
2144 | AR_PHY_GAIN_2GHZ_BSW_ATTEN)); | |
2145 | } | |
2146 | } | |
2147 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2148 | REG_RMW_FIELD(ah, | |
2149 | AR_PHY_RXGAIN + | |
2150 | regChainOffset, | |
2151 | AR9280_PHY_RXGAIN_TXRX_ATTEN, | |
2152 | txRxAttenLocal); | |
2153 | REG_RMW_FIELD(ah, | |
2154 | AR_PHY_RXGAIN + | |
2155 | regChainOffset, | |
2156 | AR9280_PHY_RXGAIN_TXRX_MARGIN, | |
2157 | pModal->rxTxMarginCh[i]); | |
2158 | } else { | |
2159 | REG_WRITE(ah, | |
2160 | AR_PHY_RXGAIN + regChainOffset, | |
2161 | (REG_READ(ah, | |
2162 | AR_PHY_RXGAIN + | |
2163 | regChainOffset) & | |
2164 | ~AR_PHY_RXGAIN_TXRX_ATTEN) | | |
2165 | SM(txRxAttenLocal, | |
2166 | AR_PHY_RXGAIN_TXRX_ATTEN)); | |
2167 | REG_WRITE(ah, | |
2168 | AR_PHY_GAIN_2GHZ + | |
2169 | regChainOffset, | |
2170 | (REG_READ(ah, | |
2171 | AR_PHY_GAIN_2GHZ + | |
2172 | regChainOffset) & | |
2173 | ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | | |
2174 | SM(pModal->rxTxMarginCh[i], | |
2175 | AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); | |
2176 | } | |
2177 | } | |
2178 | } | |
2179 | ||
2180 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2181 | if (IS_CHAN_2GHZ(chan)) { | |
2182 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
2183 | AR_AN_RF2G1_CH0_OB, | |
2184 | AR_AN_RF2G1_CH0_OB_S, | |
2185 | pModal->ob); | |
2186 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
2187 | AR_AN_RF2G1_CH0_DB, | |
2188 | AR_AN_RF2G1_CH0_DB_S, | |
2189 | pModal->db); | |
2190 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
2191 | AR_AN_RF2G1_CH1_OB, | |
2192 | AR_AN_RF2G1_CH1_OB_S, | |
2193 | pModal->ob_ch1); | |
2194 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
2195 | AR_AN_RF2G1_CH1_DB, | |
2196 | AR_AN_RF2G1_CH1_DB_S, | |
2197 | pModal->db_ch1); | |
2198 | } else { | |
2199 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
2200 | AR_AN_RF5G1_CH0_OB5, | |
2201 | AR_AN_RF5G1_CH0_OB5_S, | |
2202 | pModal->ob); | |
2203 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
2204 | AR_AN_RF5G1_CH0_DB5, | |
2205 | AR_AN_RF5G1_CH0_DB5_S, | |
2206 | pModal->db); | |
2207 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
2208 | AR_AN_RF5G1_CH1_OB5, | |
2209 | AR_AN_RF5G1_CH1_OB5_S, | |
2210 | pModal->ob_ch1); | |
2211 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
2212 | AR_AN_RF5G1_CH1_DB5, | |
2213 | AR_AN_RF5G1_CH1_DB5_S, | |
2214 | pModal->db_ch1); | |
2215 | } | |
2216 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
2217 | AR_AN_TOP2_XPABIAS_LVL, | |
2218 | AR_AN_TOP2_XPABIAS_LVL_S, | |
2219 | pModal->xpaBiasLvl); | |
2220 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
2221 | AR_AN_TOP2_LOCALBIAS, | |
2222 | AR_AN_TOP2_LOCALBIAS_S, | |
2223 | pModal->local_bias); | |
2224 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n", | |
2225 | pModal->force_xpaon); | |
2226 | REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, | |
2227 | pModal->force_xpaon); | |
2228 | } | |
2229 | ||
2230 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, | |
2231 | pModal->switchSettling); | |
2232 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
2233 | pModal->adcDesiredSize); | |
2234 | ||
2235 | if (!AR_SREV_9280_10_OR_LATER(ah)) | |
2236 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | |
2237 | AR_PHY_DESIRED_SZ_PGA, | |
2238 | pModal->pgaDesiredSize); | |
2239 | ||
2240 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
2241 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | |
2242 | | SM(pModal->txEndToXpaOff, | |
2243 | AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | |
2244 | | SM(pModal->txFrameToXpaOn, | |
2245 | AR_PHY_RF_CTL4_FRAME_XPAA_ON) | |
2246 | | SM(pModal->txFrameToXpaOn, | |
2247 | AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
2248 | ||
2249 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
2250 | pModal->txEndToRxOn); | |
2251 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2252 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, | |
2253 | pModal->thresh62); | |
2254 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, | |
2255 | AR_PHY_EXT_CCA0_THRESH62, | |
2256 | pModal->thresh62); | |
2257 | } else { | |
2258 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, | |
2259 | pModal->thresh62); | |
2260 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
2261 | AR_PHY_EXT_CCA_THRESH62, | |
2262 | pModal->thresh62); | |
2263 | } | |
2264 | ||
cb33c412 | 2265 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { |
f1dc5600 S |
2266 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, |
2267 | AR_PHY_TX_END_DATA_START, | |
2268 | pModal->txFrameToDataStart); | |
2269 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
2270 | pModal->txFrameToPaOn); | |
2271 | } | |
2272 | ||
cb33c412 | 2273 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { |
f1dc5600 S |
2274 | if (IS_CHAN_HT40(chan)) |
2275 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
2276 | AR_PHY_SETTLING_SWITCH, | |
2277 | pModal->swSettleHt40); | |
2278 | } | |
2279 | ||
cb33c412 SB |
2280 | if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { |
2281 | if (IS_CHAN_HT20(chan)) | |
2282 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, | |
2283 | eep->baseEepHeader.dacLpMode); | |
2284 | else if (eep->baseEepHeader.dacHiPwrMode_5G) | |
2285 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); | |
2286 | else | |
2287 | REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, | |
2288 | eep->baseEepHeader.dacLpMode); | |
2289 | ||
2290 | REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, | |
2291 | pModal->miscBits >> 2); | |
2292 | } | |
2293 | ||
f1dc5600 | 2294 | return true; |
cb33c412 | 2295 | #undef AR5416_VER_MASK |
f1dc5600 S |
2296 | } |
2297 | ||
cbe61d8a | 2298 | static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah, |
e7594072 SB |
2299 | struct ath9k_channel *chan) |
2300 | { | |
2301 | struct modal_eep_4k_header *pModal; | |
cbe61d8a | 2302 | struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; |
e7594072 SB |
2303 | int regChainOffset; |
2304 | u8 txRxAttenLocal; | |
e7594072 SB |
2305 | u8 ob[5], db1[5], db2[5]; |
2306 | u8 ant_div_control1, ant_div_control2; | |
2307 | u32 regVal; | |
2308 | ||
2309 | ||
2310 | pModal = &eep->modalHeader; | |
2311 | ||
2312 | txRxAttenLocal = 23; | |
2313 | ||
81b1e19a VT |
2314 | REG_WRITE(ah, AR_PHY_SWITCH_COM, |
2315 | ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); | |
e7594072 SB |
2316 | |
2317 | regChainOffset = 0; | |
2318 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | |
2319 | pModal->antCtrlChain[0]); | |
2320 | ||
2321 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | |
2322 | (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & | |
2323 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | |
2324 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
2325 | SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
2326 | SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
2327 | ||
2328 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
2329 | AR5416_EEP_MINOR_VER_3) { | |
2330 | txRxAttenLocal = pModal->txRxAttenCh[0]; | |
2331 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
2332 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); | |
2333 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
2334 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); | |
2335 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
2336 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
2337 | pModal->xatten2Margin[0]); | |
2338 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
2339 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); | |
2340 | } | |
2341 | ||
2342 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, | |
2343 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); | |
2344 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, | |
2345 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); | |
2346 | ||
2347 | if (AR_SREV_9285_11(ah)) | |
2348 | REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); | |
2349 | ||
2350 | /* Initialize Ant Diversity settings from EEPROM */ | |
2351 | if (pModal->version == 3) { | |
2352 | ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); | |
2353 | ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); | |
2354 | regVal = REG_READ(ah, 0x99ac); | |
2355 | regVal &= (~(0x7f000000)); | |
2356 | regVal |= ((ant_div_control1 & 0x1) << 24); | |
2357 | regVal |= (((ant_div_control1 >> 1) & 0x1) << 29); | |
2358 | regVal |= (((ant_div_control1 >> 2) & 0x1) << 30); | |
2359 | regVal |= ((ant_div_control2 & 0x3) << 25); | |
2360 | regVal |= (((ant_div_control2 >> 2) & 0x3) << 27); | |
2361 | REG_WRITE(ah, 0x99ac, regVal); | |
2362 | regVal = REG_READ(ah, 0x99ac); | |
2363 | regVal = REG_READ(ah, 0xa208); | |
2364 | regVal &= (~(0x1 << 13)); | |
2365 | regVal |= (((ant_div_control1 >> 3) & 0x1) << 13); | |
2366 | REG_WRITE(ah, 0xa208, regVal); | |
2367 | regVal = REG_READ(ah, 0xa208); | |
2368 | } | |
2369 | ||
2370 | if (pModal->version >= 2) { | |
2371 | ob[0] = (pModal->ob_01 & 0xf); | |
2372 | ob[1] = (pModal->ob_01 >> 4) & 0xf; | |
2373 | ob[2] = (pModal->ob_234 & 0xf); | |
2374 | ob[3] = ((pModal->ob_234 >> 4) & 0xf); | |
2375 | ob[4] = ((pModal->ob_234 >> 8) & 0xf); | |
2376 | ||
2377 | db1[0] = (pModal->db1_01 & 0xf); | |
2378 | db1[1] = ((pModal->db1_01 >> 4) & 0xf); | |
2379 | db1[2] = (pModal->db1_234 & 0xf); | |
2380 | db1[3] = ((pModal->db1_234 >> 4) & 0xf); | |
2381 | db1[4] = ((pModal->db1_234 >> 8) & 0xf); | |
2382 | ||
2383 | db2[0] = (pModal->db2_01 & 0xf); | |
2384 | db2[1] = ((pModal->db2_01 >> 4) & 0xf); | |
2385 | db2[2] = (pModal->db2_234 & 0xf); | |
2386 | db2[3] = ((pModal->db2_234 >> 4) & 0xf); | |
2387 | db2[4] = ((pModal->db2_234 >> 8) & 0xf); | |
2388 | ||
2389 | } else if (pModal->version == 1) { | |
2390 | ||
2391 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
2392 | "EEPROM Model version is set to 1 \n"); | |
2393 | ob[0] = (pModal->ob_01 & 0xf); | |
2394 | ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; | |
2395 | db1[0] = (pModal->db1_01 & 0xf); | |
2396 | db1[1] = db1[2] = db1[3] = | |
2397 | db1[4] = ((pModal->db1_01 >> 4) & 0xf); | |
2398 | db2[0] = (pModal->db2_01 & 0xf); | |
2399 | db2[1] = db2[2] = db2[3] = | |
2400 | db2[4] = ((pModal->db2_01 >> 4) & 0xf); | |
2401 | } else { | |
2402 | int i; | |
2403 | for (i = 0; i < 5; i++) { | |
2404 | ob[i] = pModal->ob_01; | |
2405 | db1[i] = pModal->db1_01; | |
2406 | db2[i] = pModal->db1_01; | |
2407 | } | |
2408 | } | |
2409 | ||
2410 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2411 | AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]); | |
2412 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2413 | AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]); | |
2414 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2415 | AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]); | |
2416 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2417 | AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]); | |
2418 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2419 | AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]); | |
2420 | ||
2421 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2422 | AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]); | |
2423 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2424 | AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]); | |
2425 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, | |
2426 | AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]); | |
2427 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2428 | AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]); | |
2429 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2430 | AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]); | |
2431 | ||
2432 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2433 | AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); | |
2434 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2435 | AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); | |
2436 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2437 | AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); | |
2438 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2439 | AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]); | |
2440 | ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, | |
2441 | AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]); | |
2442 | ||
2443 | ||
2444 | if (AR_SREV_9285_11(ah)) | |
2445 | REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); | |
2446 | ||
2447 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, | |
2448 | pModal->switchSettling); | |
2449 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
2450 | pModal->adcDesiredSize); | |
2451 | ||
2452 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
2453 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | | |
2454 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | | |
2455 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | | |
2456 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
2457 | ||
2458 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
2459 | pModal->txEndToRxOn); | |
2460 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, | |
2461 | pModal->thresh62); | |
2462 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, | |
2463 | pModal->thresh62); | |
2464 | ||
2465 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
2466 | AR5416_EEP_MINOR_VER_2) { | |
2467 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, | |
2468 | pModal->txFrameToDataStart); | |
2469 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
2470 | pModal->txFrameToPaOn); | |
2471 | } | |
2472 | ||
2473 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
2474 | AR5416_EEP_MINOR_VER_3) { | |
2475 | if (IS_CHAN_HT40(chan)) | |
2476 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
2477 | AR_PHY_SETTLING_SWITCH, | |
2478 | pModal->swSettleHt40); | |
2479 | } | |
2480 | ||
2481 | return true; | |
2482 | } | |
2483 | ||
cbe61d8a | 2484 | static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *, |
bf512bc8 | 2485 | struct ath9k_channel *) = { |
e7594072 SB |
2486 | ath9k_hw_eeprom_set_def_board_values, |
2487 | ath9k_hw_eeprom_set_4k_board_values | |
2488 | }; | |
2489 | ||
cbe61d8a | 2490 | bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, |
e7594072 SB |
2491 | struct ath9k_channel *chan) |
2492 | { | |
cbe61d8a | 2493 | return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan); |
e7594072 SB |
2494 | } |
2495 | ||
cbe61d8a | 2496 | static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah, |
81b1e19a | 2497 | struct ath9k_channel *chan) |
f1dc5600 | 2498 | { |
cbe61d8a | 2499 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
f1dc5600 S |
2500 | struct modal_eep_header *pModal = |
2501 | &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
f1dc5600 | 2502 | |
81b1e19a | 2503 | return pModal->antCtrlCommon & 0xFFFF; |
f1dc5600 S |
2504 | } |
2505 | ||
cbe61d8a | 2506 | static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah, |
81b1e19a | 2507 | struct ath9k_channel *chan) |
e7594072 | 2508 | { |
cbe61d8a | 2509 | struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; |
e7594072 SB |
2510 | struct modal_eep_4k_header *pModal = &eep->modalHeader; |
2511 | ||
81b1e19a | 2512 | return pModal->antCtrlCommon & 0xFFFF; |
e7594072 SB |
2513 | } |
2514 | ||
cbe61d8a | 2515 | static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *, |
81b1e19a | 2516 | struct ath9k_channel *) = { |
e7594072 SB |
2517 | ath9k_hw_get_def_eeprom_antenna_cfg, |
2518 | ath9k_hw_get_4k_eeprom_antenna_cfg | |
2519 | }; | |
2520 | ||
cbe61d8a | 2521 | u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, |
81b1e19a | 2522 | struct ath9k_channel *chan) |
e7594072 | 2523 | { |
cbe61d8a | 2524 | return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan); |
e7594072 SB |
2525 | } |
2526 | ||
cbe61d8a | 2527 | static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah, |
bf512bc8 | 2528 | enum ieee80211_band freq_band) |
e7594072 SB |
2529 | { |
2530 | return 1; | |
2531 | } | |
2532 | ||
cbe61d8a | 2533 | static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, |
bf512bc8 | 2534 | enum ieee80211_band freq_band) |
f1dc5600 | 2535 | { |
cbe61d8a | 2536 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
f1dc5600 | 2537 | struct modal_eep_header *pModal = |
2df1bff4 | 2538 | &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); |
f1dc5600 S |
2539 | struct base_eep_header *pBase = &eep->baseEepHeader; |
2540 | u8 num_ant_config; | |
2541 | ||
2542 | num_ant_config = 1; | |
2543 | ||
2544 | if (pBase->version >= 0x0E0D) | |
2545 | if (pModal->useAnt1) | |
2546 | num_ant_config += 1; | |
2547 | ||
2548 | return num_ant_config; | |
2549 | } | |
2550 | ||
cbe61d8a | 2551 | static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *, |
bf512bc8 | 2552 | enum ieee80211_band) = { |
e7594072 SB |
2553 | ath9k_hw_get_def_num_ant_config, |
2554 | ath9k_hw_get_4k_num_ant_config | |
2555 | }; | |
2556 | ||
cbe61d8a | 2557 | u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, |
e7594072 SB |
2558 | enum ieee80211_band freq_band) |
2559 | { | |
cbe61d8a | 2560 | return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band); |
e7594072 SB |
2561 | } |
2562 | ||
cbe61d8a | 2563 | u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) |
f1dc5600 | 2564 | { |
e7594072 | 2565 | #define EEP_MAP4K_SPURCHAN \ |
cbe61d8a | 2566 | (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) |
e7594072 | 2567 | #define EEP_DEF_SPURCHAN \ |
cbe61d8a | 2568 | (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) |
f1dc5600 S |
2569 | u16 spur_val = AR_NO_SPUR; |
2570 | ||
2571 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | |
2572 | "Getting spur idx %d is2Ghz. %d val %x\n", | |
2573 | i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); | |
2574 | ||
2575 | switch (ah->ah_config.spurmode) { | |
2576 | case SPUR_DISABLE: | |
2577 | break; | |
2578 | case SPUR_ENABLE_IOCTL: | |
2579 | spur_val = ah->ah_config.spurchans[i][is2GHz]; | |
2580 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | |
2581 | "Getting spur val from new loc. %d\n", spur_val); | |
2582 | break; | |
2583 | case SPUR_ENABLE_EEPROM: | |
cbe61d8a | 2584 | if (ah->ah_eep_map == EEP_MAP_4KBITS) |
e7594072 SB |
2585 | spur_val = EEP_MAP4K_SPURCHAN; |
2586 | else | |
2587 | spur_val = EEP_DEF_SPURCHAN; | |
f1dc5600 S |
2588 | break; |
2589 | ||
2590 | } | |
2591 | ||
2592 | return spur_val; | |
e7594072 SB |
2593 | #undef EEP_DEF_SPURCHAN |
2594 | #undef EEP_MAP4K_SPURCHAN | |
f1dc5600 S |
2595 | } |
2596 | ||
cbe61d8a | 2597 | static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah, |
e7594072 SB |
2598 | enum eeprom_param param) |
2599 | { | |
cbe61d8a | 2600 | struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; |
e7594072 SB |
2601 | struct modal_eep_4k_header *pModal = &eep->modalHeader; |
2602 | struct base_eep_header_4k *pBase = &eep->baseEepHeader; | |
2603 | ||
2604 | switch (param) { | |
2605 | case EEP_NFTHRESH_2: | |
2606 | return pModal[1].noiseFloorThreshCh[0]; | |
2607 | case AR_EEPROM_MAC(0): | |
2608 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; | |
2609 | case AR_EEPROM_MAC(1): | |
2610 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; | |
2611 | case AR_EEPROM_MAC(2): | |
2612 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; | |
2613 | case EEP_REG_0: | |
2614 | return pBase->regDmn[0]; | |
2615 | case EEP_REG_1: | |
2616 | return pBase->regDmn[1]; | |
2617 | case EEP_OP_CAP: | |
2618 | return pBase->deviceCap; | |
2619 | case EEP_OP_MODE: | |
2620 | return pBase->opCapFlags; | |
2621 | case EEP_RF_SILENT: | |
2622 | return pBase->rfSilent; | |
2623 | case EEP_OB_2: | |
2624 | return pModal->ob_01; | |
2625 | case EEP_DB_2: | |
2626 | return pModal->db1_01; | |
2627 | case EEP_MINOR_REV: | |
2628 | return pBase->version & AR5416_EEP_VER_MINOR_MASK; | |
2629 | case EEP_TX_MASK: | |
2630 | return pBase->txMask; | |
2631 | case EEP_RX_MASK: | |
2632 | return pBase->rxMask; | |
2633 | default: | |
2634 | return 0; | |
2635 | } | |
2636 | } | |
2637 | ||
cbe61d8a | 2638 | static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah, |
e7594072 | 2639 | enum eeprom_param param) |
f1dc5600 | 2640 | { |
cb33c412 | 2641 | #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) |
cbe61d8a | 2642 | struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; |
f1dc5600 S |
2643 | struct modal_eep_header *pModal = eep->modalHeader; |
2644 | struct base_eep_header *pBase = &eep->baseEepHeader; | |
2645 | ||
2646 | switch (param) { | |
2647 | case EEP_NFTHRESH_5: | |
f9bbf431 | 2648 | return pModal[0].noiseFloorThreshCh[0]; |
f1dc5600 | 2649 | case EEP_NFTHRESH_2: |
f9bbf431 | 2650 | return pModal[1].noiseFloorThreshCh[0]; |
f1dc5600 S |
2651 | case AR_EEPROM_MAC(0): |
2652 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; | |
2653 | case AR_EEPROM_MAC(1): | |
2654 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; | |
2655 | case AR_EEPROM_MAC(2): | |
2656 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; | |
2657 | case EEP_REG_0: | |
2658 | return pBase->regDmn[0]; | |
2659 | case EEP_REG_1: | |
2660 | return pBase->regDmn[1]; | |
2661 | case EEP_OP_CAP: | |
2662 | return pBase->deviceCap; | |
2663 | case EEP_OP_MODE: | |
2664 | return pBase->opCapFlags; | |
2665 | case EEP_RF_SILENT: | |
2666 | return pBase->rfSilent; | |
2667 | case EEP_OB_5: | |
2668 | return pModal[0].ob; | |
2669 | case EEP_DB_5: | |
2670 | return pModal[0].db; | |
2671 | case EEP_OB_2: | |
2672 | return pModal[1].ob; | |
2673 | case EEP_DB_2: | |
2674 | return pModal[1].db; | |
2675 | case EEP_MINOR_REV: | |
cb33c412 | 2676 | return AR5416_VER_MASK; |
f1dc5600 S |
2677 | case EEP_TX_MASK: |
2678 | return pBase->txMask; | |
2679 | case EEP_RX_MASK: | |
2680 | return pBase->rxMask; | |
9f804202 SB |
2681 | case EEP_RXGAIN_TYPE: |
2682 | return pBase->rxGainType; | |
2683 | case EEP_TXGAIN_TYPE: | |
2684 | return pBase->txGainType; | |
cb33c412 SB |
2685 | case EEP_DAC_HPWR_5G: |
2686 | if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) | |
2687 | return pBase->dacHiPwrMode_5G; | |
2688 | else | |
2689 | return 0; | |
f1dc5600 S |
2690 | default: |
2691 | return 0; | |
2692 | } | |
cb33c412 | 2693 | #undef AR5416_VER_MASK |
f1dc5600 S |
2694 | } |
2695 | ||
cbe61d8a | 2696 | static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = { |
e7594072 SB |
2697 | ath9k_hw_get_eeprom_def, |
2698 | ath9k_hw_get_eeprom_4k | |
2699 | }; | |
2700 | ||
cbe61d8a | 2701 | u32 ath9k_hw_get_eeprom(struct ath_hw *ah, |
e7594072 SB |
2702 | enum eeprom_param param) |
2703 | { | |
cbe61d8a | 2704 | return ath9k_get_eeprom[ah->ah_eep_map](ah, param); |
e7594072 SB |
2705 | } |
2706 | ||
cbe61d8a | 2707 | int ath9k_hw_eeprom_attach(struct ath_hw *ah) |
f1dc5600 S |
2708 | { |
2709 | int status; | |
2710 | ||
e7594072 | 2711 | if (AR_SREV_9285(ah)) |
cbe61d8a | 2712 | ah->ah_eep_map = EEP_MAP_4KBITS; |
e7594072 | 2713 | else |
cbe61d8a | 2714 | ah->ah_eep_map = EEP_MAP_DEFAULT; |
e7594072 | 2715 | |
f1dc5600 S |
2716 | if (!ath9k_hw_fill_eeprom(ah)) |
2717 | return -EIO; | |
2718 | ||
2719 | status = ath9k_hw_check_eeprom(ah); | |
2720 | ||
2721 | return status; | |
2722 | } |