[deliverable/linux.git] / drivers / net / wireless / ath9k / eeprom.h

/*
 * Copyright (c) 2008 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef EEPROM_H
#define EEPROM_H

#define AH_USE_EEPROM   0x1

#ifdef __BIG_ENDIAN
#define AR5416_EEPROM_MAGIC 0x5aa5
#else
#define AR5416_EEPROM_MAGIC 0xa55a
#endif

#define CTRY_DEBUG   0x1ff
#define	CTRY_DEFAULT 0

#define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
#define AR_EEPROM_EEPCAP_AES_DIS        0x0002
#define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
#define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
#define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
#define AR_EEPROM_EEPCAP_MAXQCU_S       4
#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
#define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
#define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12

#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
#define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800

#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000

#define AR5416_EEPROM_MAGIC_OFFSET  0x0
#define AR5416_EEPROM_S             2
#define AR5416_EEPROM_OFFSET        0x2000
#define AR5416_EEPROM_MAX           0xae0

#define AR5416_EEPROM_START_ADDR \
	(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200

#define SD_NO_CTL               0xE0
#define NO_CTL                  0xff
#define CTL_MODE_M              7
#define CTL_11A                 0
#define CTL_11B                 1
#define CTL_11G                 2
#define CTL_2GHT20              5
#define CTL_5GHT20              6
#define CTL_2GHT40              7
#define CTL_5GHT40              8

#define EXT_ADDITIVE (0x8000)
#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)

#define SUB_NUM_CTL_MODES_AT_5G_40 2
#define SUB_NUM_CTL_MODES_AT_2G_40 3

#define INCREASE_MAXPOW_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
#define INCREASE_MAXPOW_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */

#define AR_EEPROM_MAC(i)	(0x1d+(i))
#define ATH9K_POW_SM(_r, _s)	(((_r) & 0x3f) << (_s))
#define FREQ2FBIN(x, y)		((y) ? ((x) - 2300) : (((x) - 4800) / 5))
#define ath9k_hw_use_flash(_ah)	(!(_ah->ah_flags & AH_USE_EEPROM))

#define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
#define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
#define AR_EEPROM_RFSILENT_POLARITY     0x0002
#define AR_EEPROM_RFSILENT_POLARITY_S   1

#define EEP_RFSILENT_ENABLED        0x0001
#define EEP_RFSILENT_ENABLED_S      0
#define EEP_RFSILENT_POLARITY       0x0002
#define EEP_RFSILENT_POLARITY_S     1
#define EEP_RFSILENT_GPIO_SEL       0x001c
#define EEP_RFSILENT_GPIO_SEL_S     2

#define AR5416_OPFLAGS_11A           0x01
#define AR5416_OPFLAGS_11G           0x02
#define AR5416_OPFLAGS_N_5G_HT40     0x04
#define AR5416_OPFLAGS_N_2G_HT40     0x08
#define AR5416_OPFLAGS_N_5G_HT20     0x10
#define AR5416_OPFLAGS_N_2G_HT20     0x20

#define AR5416_EEP_NO_BACK_VER       0x1
#define AR5416_EEP_VER               0xE
#define AR5416_EEP_VER_MINOR_MASK    0x0FFF
#define AR5416_EEP_MINOR_VER_2       0x2
#define AR5416_EEP_MINOR_VER_3       0x3
#define AR5416_EEP_MINOR_VER_7       0x7
#define AR5416_EEP_MINOR_VER_9       0x9
#define AR5416_EEP_MINOR_VER_16      0x10
#define AR5416_EEP_MINOR_VER_17      0x11
#define AR5416_EEP_MINOR_VER_19      0x13
#define AR5416_EEP_MINOR_VER_20      0x14

#define AR5416_NUM_5G_CAL_PIERS         8
#define AR5416_NUM_2G_CAL_PIERS         4
#define AR5416_NUM_5G_20_TARGET_POWERS  8
#define AR5416_NUM_5G_40_TARGET_POWERS  8
#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
#define AR5416_NUM_2G_20_TARGET_POWERS  4
#define AR5416_NUM_2G_40_TARGET_POWERS  4
#define AR5416_NUM_CTLS                 24
#define AR5416_NUM_BAND_EDGES           8
#define AR5416_NUM_PD_GAINS             4
#define AR5416_PD_GAINS_IN_MASK         4
#define AR5416_PD_GAIN_ICEPTS           5
#define AR5416_EEPROM_MODAL_SPURS       5
#define AR5416_MAX_RATE_POWER           63
#define AR5416_NUM_PDADC_VALUES         128
#define AR5416_BCHAN_UNUSED             0xFF
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
#define AR5416_MAX_CHAINS               3
#define AR5416_PWR_TABLE_OFFSET         -5

/* Rx gain type values */
#define AR5416_EEP_RXGAIN_23DB_BACKOFF     0
#define AR5416_EEP_RXGAIN_13DB_BACKOFF     1
#define AR5416_EEP_RXGAIN_ORIG             2

/* Tx gain type values */
#define AR5416_EEP_TXGAIN_ORIGINAL         0
#define AR5416_EEP_TXGAIN_HIGH_POWER       1

#define AR5416_EEP4K_START_LOC                64
#define AR5416_EEP4K_NUM_2G_CAL_PIERS         3
#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3
#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3
#define AR5416_EEP4K_NUM_CTLS                 12
#define AR5416_EEP4K_NUM_BAND_EDGES           4
#define AR5416_EEP4K_NUM_PD_GAINS             2
#define AR5416_EEP4K_PD_GAINS_IN_MASK         4
#define AR5416_EEP4K_PD_GAIN_ICEPTS           5
#define AR5416_EEP4K_MAX_CHAINS               1

enum eeprom_param {
	EEP_NFTHRESH_5,
	EEP_NFTHRESH_2,
	EEP_MAC_MSW,
	EEP_MAC_MID,
	EEP_MAC_LSW,
	EEP_REG_0,
	EEP_REG_1,
	EEP_OP_CAP,
	EEP_OP_MODE,
	EEP_RF_SILENT,
	EEP_OB_5,
	EEP_DB_5,
	EEP_OB_2,
	EEP_DB_2,
	EEP_MINOR_REV,
	EEP_TX_MASK,
	EEP_RX_MASK,
	EEP_RXGAIN_TYPE,
	EEP_TXGAIN_TYPE,
	EEP_DAC_HPWR_5G,
};

enum ar5416_rates {
	rate6mb, rate9mb, rate12mb, rate18mb,
	rate24mb, rate36mb, rate48mb, rate54mb,
	rate1l, rate2l, rate2s, rate5_5l,
	rate5_5s, rate11l, rate11s, rateXr,
	rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
	rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
	rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
	rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
	rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
	Ar5416RateSize
};

enum ath9k_hal_freq_band {
	ATH9K_HAL_FREQ_BAND_5GHZ = 0,
	ATH9K_HAL_FREQ_BAND_2GHZ = 1
};

struct base_eep_header {
	u16 length;
	u16 checksum;
	u16 version;
	u8 opCapFlags;
	u8 eepMisc;
	u16 regDmn[2];
	u8 macAddr[6];
	u8 rxMask;
	u8 txMask;
	u16 rfSilent;
	u16 blueToothOptions;
	u16 deviceCap;
	u32 binBuildNumber;
	u8 deviceType;
	u8 pwdclkind;
	u8 futureBase_1[2];
	u8 rxGainType;
	u8 dacHiPwrMode_5G;
	u8 futureBase_2;
	u8 dacLpMode;
	u8 txGainType;
	u8 rcChainMask;
	u8 desiredScaleCCK;
	u8 futureBase_3[23];
} __packed;

struct base_eep_header_4k {
	u16 length;
	u16 checksum;
	u16 version;
	u8 opCapFlags;
	u8 eepMisc;
	u16 regDmn[2];
	u8 macAddr[6];
	u8 rxMask;
	u8 txMask;
	u16 rfSilent;
	u16 blueToothOptions;
	u16 deviceCap;
	u32 binBuildNumber;
	u8 deviceType;
	u8 futureBase[1];
} __packed;


struct spur_chan {
	u16 spurChan;
	u8 spurRangeLow;
	u8 spurRangeHigh;
} __packed;

struct modal_eep_header {
	u32 antCtrlChain[AR5416_MAX_CHAINS];
	u32 antCtrlCommon;
	u8 antennaGainCh[AR5416_MAX_CHAINS];
	u8 switchSettling;
	u8 txRxAttenCh[AR5416_MAX_CHAINS];
	u8 rxTxMarginCh[AR5416_MAX_CHAINS];
	u8 adcDesiredSize;
	u8 pgaDesiredSize;
	u8 xlnaGainCh[AR5416_MAX_CHAINS];
	u8 txEndToXpaOff;
	u8 txEndToRxOn;
	u8 txFrameToXpaOn;
	u8 thresh62;
	u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
	u8 xpdGain;
	u8 xpd;
	u8 iqCalICh[AR5416_MAX_CHAINS];
	u8 iqCalQCh[AR5416_MAX_CHAINS];
	u8 pdGainOverlap;
	u8 ob;
	u8 db;
	u8 xpaBiasLvl;
	u8 pwrDecreaseFor2Chain;
	u8 pwrDecreaseFor3Chain;
	u8 txFrameToDataStart;
	u8 txFrameToPaOn;
	u8 ht40PowerIncForPdadc;
	u8 bswAtten[AR5416_MAX_CHAINS];
	u8 bswMargin[AR5416_MAX_CHAINS];
	u8 swSettleHt40;
	u8 xatten2Db[AR5416_MAX_CHAINS];
	u8 xatten2Margin[AR5416_MAX_CHAINS];
	u8 ob_ch1;
	u8 db_ch1;
	u8 useAnt1:1,
	    force_xpaon:1,
	    local_bias:1,
	    femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
	u8 miscBits;
	u16 xpaBiasLvlFreq[3];
	u8 futureModal[6];

	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
} __packed;

struct modal_eep_4k_header {
	u32  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
	u32  antCtrlCommon;
	u8   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
	u8   switchSettling;
	u8   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
	u8   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
	u8   adcDesiredSize;
	u8   pgaDesiredSize;
	u8   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
	u8   txEndToXpaOff;
	u8   txEndToRxOn;
	u8   txFrameToXpaOn;
	u8   thresh62;
	u8   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
	u8   xpdGain;
	u8   xpd;
	u8   iqCalICh[AR5416_EEP4K_MAX_CHAINS];
	u8   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
	u8   pdGainOverlap;
	u8   ob_01;
	u8   db1_01;
	u8   xpaBiasLvl;
	u8   txFrameToDataStart;
	u8   txFrameToPaOn;
	u8   ht40PowerIncForPdadc;
	u8   bswAtten[AR5416_EEP4K_MAX_CHAINS];
	u8   bswMargin[AR5416_EEP4K_MAX_CHAINS];
	u8   swSettleHt40;
	u8   xatten2Db[AR5416_EEP4K_MAX_CHAINS];
	u8   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
	u8   db2_01;
	u8   version;
	u16  ob_234;
	u16  db1_234;
	u16  db2_234;
	u8   futureModal[4];

	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
} __packed;


struct cal_data_per_freq {
	u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
	u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
} __packed;

struct cal_data_per_freq_4k {
	u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
	u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
} __packed;

struct cal_target_power_leg {
	u8 bChannel;
	u8 tPow2x[4];
} __packed;

struct cal_target_power_ht {
	u8 bChannel;
	u8 tPow2x[8];
} __packed;


#ifdef __BIG_ENDIAN_BITFIELD
struct cal_ctl_edges {
	u8 bChannel;
	u8 flag:2, tPower:6;
} __packed;
#else
struct cal_ctl_edges {
	u8 bChannel;
	u8 tPower:6, flag:2;
} __packed;
#endif

struct cal_ctl_data {
	struct cal_ctl_edges
	ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
} __packed;

struct cal_ctl_data_4k {
	struct cal_ctl_edges
	ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
} __packed;

struct ar5416_eeprom_def {
	struct base_eep_header baseEepHeader;
	u8 custData[64];
	struct modal_eep_header modalHeader[2];
	u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
	u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
	struct cal_data_per_freq
	 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
	struct cal_data_per_freq
	 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
	struct cal_target_power_leg
	 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
	struct cal_target_power_ht
	 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
	struct cal_target_power_ht
	 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
	struct cal_target_power_leg
	 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
	struct cal_target_power_leg
	 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
	struct cal_target_power_ht
	 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
	struct cal_target_power_ht
	 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
	u8 ctlIndex[AR5416_NUM_CTLS];
	struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
	u8 padding;
} __packed;

struct ar5416_eeprom_4k {
	struct base_eep_header_4k baseEepHeader;
	u8 custData[20];
	struct modal_eep_4k_header modalHeader;
	u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
	struct cal_data_per_freq_4k
	calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
	struct cal_target_power_leg
	calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
	struct cal_target_power_leg
	calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
	struct cal_target_power_ht
	calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
	struct cal_target_power_ht
	calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
	u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
	struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
	u8 padding;
} __packed;

enum reg_ext_bitmap {
	REG_EXT_JAPAN_MIDBAND = 1,
	REG_EXT_FCC_DFS_HT40 = 2,
	REG_EXT_JAPAN_NONDFS_HT40 = 3,
	REG_EXT_JAPAN_DFS_HT40 = 4
};

struct ath9k_country_entry {
	u16 countryCode;
	u16 regDmnEnum;
	u16 regDmn5G;
	u16 regDmn2G;
	u8 isMultidomain;
	u8 iso[3];
};

enum ath9k_eep_map {
	EEP_MAP_DEFAULT = 0x0,
	EEP_MAP_4KBITS,
	EEP_MAP_MAX
};

struct eeprom_ops {
	int (*check_eeprom)(struct ath_hw *hw);
	u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
	bool (*fill_eeprom)(struct ath_hw *hw);
	int (*get_eeprom_ver)(struct ath_hw *hw);
	int (*get_eeprom_rev)(struct ath_hw *hw);
	u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
	u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
				      struct ath9k_channel *chan);
	bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
	void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
	int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
			   u16 cfgCtl, u8 twiceAntennaReduction,
			   u8 twiceMaxRegulatoryPower, u8 powerLimit);
	u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
};

#define ar5416_get_ntxchains(_txchainmask)			\
	(((_txchainmask >> 2) & 1) +                            \
	 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))

int ath9k_hw_eeprom_attach(struct ath_hw *ah);

#endif /* EEPROM_H */
Commit	Line	Data
394cf0a1 S	1	/*
	2	* Copyright (c) 2008 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef EEPROM_H
	18	#define EEPROM_H
	19
	20	#define AH_USE_EEPROM 0x1
	21
	22	#ifdef __BIG_ENDIAN
	23	#define AR5416_EEPROM_MAGIC 0x5aa5
	24	#else
	25	#define AR5416_EEPROM_MAGIC 0xa55a
	26	#endif
	27
	28	#define CTRY_DEBUG 0x1ff
	29	#define CTRY_DEFAULT 0
	30
	31	#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
	32	#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
	33	#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
	34	#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
	35	#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
	36	#define AR_EEPROM_EEPCAP_MAXQCU_S 4
	37	#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
	38	#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
	39	#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
	40
	41	#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
	42	#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
	43	#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
	44	#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
	45	#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
	46	#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
	47
	48	#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
	49	#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
	50
	51	#define AR5416_EEPROM_MAGIC_OFFSET 0x0
	52	#define AR5416_EEPROM_S 2
	53	#define AR5416_EEPROM_OFFSET 0x2000
	54	#define AR5416_EEPROM_MAX 0xae0
	55
	56	#define AR5416_EEPROM_START_ADDR \
	57	(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
	58
	59	#define SD_NO_CTL 0xE0
	60	#define NO_CTL 0xff
	61	#define CTL_MODE_M 7
	62	#define CTL_11A 0
	63	#define CTL_11B 1
	64	#define CTL_11G 2
65	#define CTL_2GHT20 5
66	#define CTL_5GHT20 6
67	#define CTL_2GHT40 7
68	#define CTL_5GHT40 8
69
70	#define EXT_ADDITIVE (0x8000)
71	#define CTL_11A_EXT (CTL_11A \| EXT_ADDITIVE)
72	#define CTL_11G_EXT (CTL_11G \| EXT_ADDITIVE)
73	#define CTL_11B_EXT (CTL_11B \| EXT_ADDITIVE)
74
75	#define SUB_NUM_CTL_MODES_AT_5G_40 2
76	#define SUB_NUM_CTL_MODES_AT_2G_40 3
77
e421c7b3 S	78	#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10log10(2)2 */
	79	#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10log10(3)2 */
	80
394cf0a1 S	81	#define AR_EEPROM_MAC(i) (0x1d+(i))
	82	#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
	83	#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
	84	#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
	85
	86	#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
	87	#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
	88	#define AR_EEPROM_RFSILENT_POLARITY 0x0002
	89	#define AR_EEPROM_RFSILENT_POLARITY_S 1
	90
	91	#define EEP_RFSILENT_ENABLED 0x0001
	92	#define EEP_RFSILENT_ENABLED_S 0
	93	#define EEP_RFSILENT_POLARITY 0x0002
	94	#define EEP_RFSILENT_POLARITY_S 1
	95	#define EEP_RFSILENT_GPIO_SEL 0x001c
	96	#define EEP_RFSILENT_GPIO_SEL_S 2
	97
	98	#define AR5416_OPFLAGS_11A 0x01
	99	#define AR5416_OPFLAGS_11G 0x02
	100	#define AR5416_OPFLAGS_N_5G_HT40 0x04
	101	#define AR5416_OPFLAGS_N_2G_HT40 0x08
	102	#define AR5416_OPFLAGS_N_5G_HT20 0x10
	103	#define AR5416_OPFLAGS_N_2G_HT20 0x20
	104
	105	#define AR5416_EEP_NO_BACK_VER 0x1
	106	#define AR5416_EEP_VER 0xE
	107	#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
	108	#define AR5416_EEP_MINOR_VER_2 0x2
	109	#define AR5416_EEP_MINOR_VER_3 0x3
	110	#define AR5416_EEP_MINOR_VER_7 0x7
	111	#define AR5416_EEP_MINOR_VER_9 0x9
	112	#define AR5416_EEP_MINOR_VER_16 0x10
	113	#define AR5416_EEP_MINOR_VER_17 0x11
	114	#define AR5416_EEP_MINOR_VER_19 0x13
	115	#define AR5416_EEP_MINOR_VER_20 0x14
	116
	117	#define AR5416_NUM_5G_CAL_PIERS 8
	118	#define AR5416_NUM_2G_CAL_PIERS 4
	119	#define AR5416_NUM_5G_20_TARGET_POWERS 8
	120	#define AR5416_NUM_5G_40_TARGET_POWERS 8
	121	#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
	122	#define AR5416_NUM_2G_20_TARGET_POWERS 4
	123	#define AR5416_NUM_2G_40_TARGET_POWERS 4
	124	#define AR5416_NUM_CTLS 24
	125	#define AR5416_NUM_BAND_EDGES 8
	126	#define AR5416_NUM_PD_GAINS 4
	127	#define AR5416_PD_GAINS_IN_MASK 4
	128	#define AR5416_PD_GAIN_ICEPTS 5
	129	#define AR5416_EEPROM_MODAL_SPURS 5
	130	#define AR5416_MAX_RATE_POWER 63
	131	#define AR5416_NUM_PDADC_VALUES 128
	132	#define AR5416_BCHAN_UNUSED 0xFF
	133	#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
	134	#define AR5416_MAX_CHAINS 3
	135	#define AR5416_PWR_TABLE_OFFSET -5
	136
	137	/* Rx gain type values */
	138	#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
	139	#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
	140	#define AR5416_EEP_RXGAIN_ORIG 2
	141
	142	/* Tx gain type values */
	143	#define AR5416_EEP_TXGAIN_ORIGINAL 0
	144	#define AR5416_EEP_TXGAIN_HIGH_POWER 1
145
146	#define AR5416_EEP4K_START_LOC 64
147	#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
148	#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
149	#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
150	#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
151	#define AR5416_EEP4K_NUM_CTLS 12
152	#define AR5416_EEP4K_NUM_BAND_EDGES 4
153	#define AR5416_EEP4K_NUM_PD_GAINS 2
154	#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
155	#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
156	#define AR5416_EEP4K_MAX_CHAINS 1
157
158	enum eeprom_param {
159	EEP_NFTHRESH_5,
160	EEP_NFTHRESH_2,
161	EEP_MAC_MSW,
162	EEP_MAC_MID,
163	EEP_MAC_LSW,
164	EEP_REG_0,
165	EEP_REG_1,
166	EEP_OP_CAP,
167	EEP_OP_MODE,
168	EEP_RF_SILENT,
169	EEP_OB_5,
170	EEP_DB_5,
171	EEP_OB_2,
172	EEP_DB_2,
173	EEP_MINOR_REV,
174	EEP_TX_MASK,
175	EEP_RX_MASK,
176	EEP_RXGAIN_TYPE,
177	EEP_TXGAIN_TYPE,
178	EEP_DAC_HPWR_5G,
179	};
180
181	enum ar5416_rates {
182	rate6mb, rate9mb, rate12mb, rate18mb,
183	rate24mb, rate36mb, rate48mb, rate54mb,
184	rate1l, rate2l, rate2s, rate5_5l,
185	rate5_5s, rate11l, rate11s, rateXr,
186	rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
187	rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
188	rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
189	rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
190	rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
191	Ar5416RateSize
192	};
193
194	enum ath9k_hal_freq_band {
195	ATH9K_HAL_FREQ_BAND_5GHZ = 0,
196	ATH9K_HAL_FREQ_BAND_2GHZ = 1
197	};
198
199	struct base_eep_header {
200	u16 length;
201	u16 checksum;
202	u16 version;
203	u8 opCapFlags;
204	u8 eepMisc;
205	u16 regDmn[2];
206	u8 macAddr[6];
207	u8 rxMask;
208	u8 txMask;
209	u16 rfSilent;
210	u16 blueToothOptions;
211	u16 deviceCap;
212	u32 binBuildNumber;
213	u8 deviceType;
214	u8 pwdclkind;
215	u8 futureBase_1[2];
216	u8 rxGainType;
217	u8 dacHiPwrMode_5G;
218	u8 futureBase_2;
219	u8 dacLpMode;
220	u8 txGainType;
221	u8 rcChainMask;
222	u8 desiredScaleCCK;
223	u8 futureBase_3[23];
224	} __packed;
225
226	struct base_eep_header_4k {
227	u16 length;
228	u16 checksum;
229	u16 version;
230	u8 opCapFlags;
231	u8 eepMisc;
232	u16 regDmn[2];
233	u8 macAddr[6];
234	u8 rxMask;
235	u8 txMask;
236	u16 rfSilent;
237	u16 blueToothOptions;
238	u16 deviceCap;
239	u32 binBuildNumber;
240	u8 deviceType;
241	u8 futureBase[1];
242	} __packed;
243
244
245	struct spur_chan {
246	u16 spurChan;
247	u8 spurRangeLow;
248	u8 spurRangeHigh;
249	} __packed;
250
251	struct modal_eep_header {
252	u32 antCtrlChain[AR5416_MAX_CHAINS];
253	u32 antCtrlCommon;
254	u8 antennaGainCh[AR5416_MAX_CHAINS];
255	u8 switchSettling;
256	u8 txRxAttenCh[AR5416_MAX_CHAINS];
257	u8 rxTxMarginCh[AR5416_MAX_CHAINS];
258	u8 adcDesiredSize;
259	u8 pgaDesiredSize;
260	u8 xlnaGainCh[AR5416_MAX_CHAINS];
261	u8 txEndToXpaOff;
262	u8 txEndToRxOn;
263	u8 txFrameToXpaOn;
264	u8 thresh62;
265	u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
266	u8 xpdGain;
267	u8 xpd;
268	u8 iqCalICh[AR5416_MAX_CHAINS];
269	u8 iqCalQCh[AR5416_MAX_CHAINS];
270	u8 pdGainOverlap;
271	u8 ob;
272	u8 db;
273	u8 xpaBiasLvl;
274	u8 pwrDecreaseFor2Chain;
275	u8 pwrDecreaseFor3Chain;
276	u8 txFrameToDataStart;
277	u8 txFrameToPaOn;
278	u8 ht40PowerIncForPdadc;
279	u8 bswAtten[AR5416_MAX_CHAINS];
280	u8 bswMargin[AR5416_MAX_CHAINS];
281	u8 swSettleHt40;
282	u8 xatten2Db[AR5416_MAX_CHAINS];
283	u8 xatten2Margin[AR5416_MAX_CHAINS];
284	u8 ob_ch1;
285	u8 db_ch1;
286	u8 useAnt1:1,
287	force_xpaon:1,
288	local_bias:1,
289	femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
290	u8 miscBits;
291	u16 xpaBiasLvlFreq[3];
292	u8 futureModal[6];
293
294	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
295	} __packed;
296
297	struct modal_eep_4k_header {
298	u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
299	u32 antCtrlCommon;
300	u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
301	u8 switchSettling;
302	u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
303	u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
304	u8 adcDesiredSize;
305	u8 pgaDesiredSize;
306	u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
307	u8 txEndToXpaOff;
308	u8 txEndToRxOn;
309	u8 txFrameToXpaOn;
310	u8 thresh62;
311	u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
312	u8 xpdGain;
313	u8 xpd;
314	u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
315	u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
316	u8 pdGainOverlap;
317	u8 ob_01;
318	u8 db1_01;
319	u8 xpaBiasLvl;
320	u8 txFrameToDataStart;
321	u8 txFrameToPaOn;
322	u8 ht40PowerIncForPdadc;
323	u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
324	u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
325	u8 swSettleHt40;
326	u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
327	u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
328	u8 db2_01;
329	u8 version;
330	u16 ob_234;
331	u16 db1_234;
332	u16 db2_234;
333	u8 futureModal[4];
334
335	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
336	} __packed;
337
338
339	struct cal_data_per_freq {
340	u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
341	u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
342	} __packed;
343
344	struct cal_data_per_freq_4k {
345	u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
346	u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
347	} __packed;
348
349	struct cal_target_power_leg {
350	u8 bChannel;
351	u8 tPow2x[4];
352	} __packed;
353
354	struct cal_target_power_ht {
355	u8 bChannel;
356	u8 tPow2x[8];
357	} __packed;
358
359
360	#ifdef __BIG_ENDIAN_BITFIELD
361	struct cal_ctl_edges {
362	u8 bChannel;
363	u8 flag:2, tPower:6;
364	} __packed;
365	#else
366	struct cal_ctl_edges {
367	u8 bChannel;
368	u8 tPower:6, flag:2;
369	} __packed;
370	#endif
371
372	struct cal_ctl_data {
373	struct cal_ctl_edges
374	ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
375	} __packed;
376
377	struct cal_ctl_data_4k {
378	struct cal_ctl_edges
379	ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
380	} __packed;
381
382	struct ar5416_eeprom_def {
383	struct base_eep_header baseEepHeader;
384	u8 custData[64];
385	struct modal_eep_header modalHeader[2];
386	u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
387	u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
388	struct cal_data_per_freq
389	calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
390	struct cal_data_per_freq
391	calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
392	struct cal_target_power_leg
393	calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
394	struct cal_target_power_ht
395	calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
396	struct cal_target_power_ht
397	calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
398	struct cal_target_power_leg
399	calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
400	struct cal_target_power_leg
401	calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
402	struct cal_target_power_ht
403	calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
404	struct cal_target_power_ht
405	calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
406	u8 ctlIndex[AR5416_NUM_CTLS];
407	struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
408	u8 padding;
409	} __packed;
410
411	struct ar5416_eeprom_4k {
412	struct base_eep_header_4k baseEepHeader;
413	u8 custData[20];
414	struct modal_eep_4k_header modalHeader;
415	u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
416	struct cal_data_per_freq_4k
417	calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
418	struct cal_target_power_leg
419	calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
420	struct cal_target_power_leg
421	calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
422	struct cal_target_power_ht
423	calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
424	struct cal_target_power_ht
425	calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
426	u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
427	struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
428	u8 padding;
429	} __packed;
430
431	enum reg_ext_bitmap {
432	REG_EXT_JAPAN_MIDBAND = 1,
433	REG_EXT_FCC_DFS_HT40 = 2,
434	REG_EXT_JAPAN_NONDFS_HT40 = 3,
435	REG_EXT_JAPAN_DFS_HT40 = 4
436	};
437
438	struct ath9k_country_entry {
439	u16 countryCode;
440	u16 regDmnEnum;
441	u16 regDmn5G;
442	u16 regDmn2G;
443	u8 isMultidomain;
444	u8 iso[3];
445	};
446
2660b81a	447	enum ath9k_eep_map {
394cf0a1 S	448	EEP_MAP_DEFAULT = 0x0,
	449	EEP_MAP_4KBITS,
	450	EEP_MAP_MAX
	451	};
	452
e153789d S	453	struct eeprom_ops {
	454	int (check_eeprom)(struct ath_hw hw);
	455	u32 (get_eeprom)(struct ath_hw hw, enum eeprom_param param);
	456	bool (fill_eeprom)(struct ath_hw hw);
	457	int (get_eeprom_ver)(struct ath_hw hw);
	458	int (get_eeprom_rev)(struct ath_hw hw);
	459	u8 (get_num_ant_config)(struct ath_hw hw, enum ieee80211_band band);
	460	u16 (get_eeprom_antenna_cfg)(struct ath_hw hw,
	461	struct ath9k_channel *chan);
	462	bool (set_board_values)(struct ath_hw hw, struct ath9k_channel *chan);
	463	void (set_addac)(struct ath_hw hw, struct ath9k_channel *chan);
	464	int (set_txpower)(struct ath_hw hw, struct ath9k_channel *chan,
	465	u16 cfgCtl, u8 twiceAntennaReduction,
	466	u8 twiceMaxRegulatoryPower, u8 powerLimit);
	467	u16 (get_spur_channel)(struct ath_hw ah, u16 i, bool is2GHz);
	468	};
	469
394cf0a1	470	#define ar5416_get_ntxchains(_txchainmask) \
f74df6fb	471	(((_txchainmask >> 2) & 1) + \
394cf0a1 S	472	((_txchainmask >> 1) & 1) + (_txchainmask & 1))
394cf0a1 S	473
cbe61d8a	474	int ath9k_hw_eeprom_attach(struct ath_hw *ah);
394cf0a1 S	475
394cf0a1 S	476	#endif /* EEPROM_H */