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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
b481de9c ZY |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 12 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
13 | * published by the Free Software Foundation. |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
b481de9c ZY |
27 | * |
28 | * Contact Information: | |
759ef89f | 29 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
8b4139dc | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
b481de9c ZY |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | *****************************************************************************/ | |
64 | ||
65 | #ifndef __iwl_prph_h__ | |
66 | #define __iwl_prph_h__ | |
67 | ||
e3851447 BC |
68 | /* |
69 | * Registers in this file are internal, not PCI bus memory mapped. | |
70 | * Driver accesses these via HBUS_TARG_PRPH_* registers. | |
71 | */ | |
b481de9c ZY |
72 | #define PRPH_BASE (0x00000) |
73 | #define PRPH_END (0xFFFFF) | |
74 | ||
75 | /* APMG (power management) constants */ | |
76 | #define APMG_BASE (PRPH_BASE + 0x3000) | |
77 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) | |
78 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) | |
79 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) | |
80 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) | |
81 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) | |
82 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) | |
83 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) | |
84 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) | |
02c06e4a WYG |
85 | #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) |
86 | #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) | |
b481de9c | 87 | |
50619ac9 | 88 | #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
b481de9c ZY |
89 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
90 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) | |
91 | ||
4c43e0d0 TW |
92 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
93 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | |
94 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | |
95 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | |
4c43e0d0 | 96 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
02c06e4a WYG |
97 | #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
98 | #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) | |
b481de9c | 99 | |
a812cba9 AB |
100 | #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200) |
101 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) | |
b7aaeae4 | 102 | #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000) |
b481de9c | 103 | |
889b1696 EG |
104 | #define APMG_RTC_INT_STT_RFKILL (0x10000000) |
105 | ||
99cd4714 JB |
106 | /* Device system time */ |
107 | #define DEVICE_SYSTEM_TIME_REG 0xA0206C | |
108 | ||
119663c3 AB |
109 | /* Device NMI register */ |
110 | #define DEVICE_SET_NMI_REG 0x00a01c30 | |
66396583 EG |
111 | #define DEVICE_SET_NMI_VAL_HW BIT(0) |
112 | #define DEVICE_SET_NMI_VAL_DRV BIT(7) | |
5dd9c68a EG |
113 | #define DEVICE_SET_NMI_8000_REG 0x00a01c24 |
114 | #define DEVICE_SET_NMI_8000_VAL 0x1000000 | |
119663c3 | 115 | |
a812cba9 AB |
116 | /* Shared registers (0x0..0x3ff, via target indirect or periphery */ |
117 | #define SHR_BASE 0x00a10000 | |
118 | ||
119 | /* Shared GP1 register */ | |
120 | #define SHR_APMG_GP1_REG 0x01dc | |
121 | #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG) | |
122 | #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004 | |
123 | #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000 | |
124 | ||
125 | /* Shared DL_CFG register */ | |
126 | #define SHR_APMG_DL_CFG_REG 0x01c4 | |
127 | #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG) | |
128 | #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0 | |
129 | #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080 | |
130 | #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100 | |
131 | ||
132 | /* Shared APMG_XTAL_CFG register */ | |
133 | #define SHR_APMG_XTAL_CFG_REG 0x1c0 | |
134 | #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000 | |
135 | ||
e12ba844 EH |
136 | /* |
137 | * Device reset for family 8000 | |
138 | * write to bit 24 in order to reset the CPU | |
139 | */ | |
140 | #define RELEASE_CPU_RESET (0x300C) | |
141 | #define RELEASE_CPU_RESET_BIT BIT(24) | |
142 | ||
9ee718aa EL |
143 | /***************************************************************************** |
144 | * 7000/3000 series SHR DTS addresses * | |
145 | *****************************************************************************/ | |
146 | ||
147 | #define SHR_MISC_WFM_DTS_EN (0x00a10024) | |
148 | #define DTSC_CFG_MODE (0x00a10604) | |
149 | #define DTSC_VREF_AVG (0x00a10648) | |
150 | #define DTSC_VREF5_AVG (0x00a1064c) | |
151 | #define DTSC_CFG_MODE_PERIODIC (0x2) | |
152 | #define DTSC_PTAT_AVG (0x00a10650) | |
153 | ||
154 | ||
038669e4 EG |
155 | /** |
156 | * Tx Scheduler | |
157 | * | |
a96a27f9 | 158 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
038669e4 EG |
159 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
160 | * host DRAM. It steers each frame's Tx command (which contains the frame | |
161 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the | |
162 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, | |
163 | * but one DMA channel may take input from several queues. | |
164 | * | |
8ff84a2c | 165 | * Tx DMA FIFOs have dedicated purposes. |
038669e4 | 166 | * |
edc1a3a0 | 167 | * For 5000 series and up, they are used differently |
68198865 JB |
168 | * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): |
169 | * | |
170 | * 0 -- EDCA BK (background) frames, lowest priority | |
171 | * 1 -- EDCA BE (best effort) frames, normal priority | |
172 | * 2 -- EDCA VI (video) frames, higher priority | |
173 | * 3 -- EDCA VO (voice) and management frames, highest priority | |
edc1a3a0 JB |
174 | * 4 -- unused |
175 | * 5 -- unused | |
176 | * 6 -- unused | |
68198865 JB |
177 | * 7 -- Commands |
178 | * | |
038669e4 | 179 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
68198865 JB |
180 | * In addition, driver can map the remaining queues to Tx DMA/FIFO |
181 | * channels 0-3 to support 11n aggregation via EDCA DMA channels. | |
038669e4 EG |
182 | * |
183 | * The driver sets up each queue to work in one of two modes: | |
184 | * | |
185 | * 1) Scheduler-Ack, in which the scheduler automatically supports a | |
186 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue | |
187 | * contains TFDs for a unique combination of Recipient Address (RA) | |
188 | * and Traffic Identifier (TID), that is, traffic of a given | |
189 | * Quality-Of-Service (QOS) priority, destined for a single station. | |
190 | * | |
191 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of | |
192 | * each frame within the BA window, including whether it's been transmitted, | |
193 | * and whether it's been acknowledged by the receiving station. The device | |
194 | * automatically processes block-acks received from the receiving STA, | |
195 | * and reschedules un-acked frames to be retransmitted (successful | |
196 | * Tx completion may end up being out-of-order). | |
197 | * | |
198 | * The driver must maintain the queue's Byte Count table in host DRAM | |
8ff84a2c | 199 | * for this mode. |
038669e4 EG |
200 | * This mode does not support fragmentation. |
201 | * | |
202 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. | |
203 | * The device may automatically retry Tx, but will retry only one frame | |
204 | * at a time, until receiving ACK from receiving station, or reaching | |
205 | * retry limit and giving up. | |
206 | * | |
13bb9483 | 207 | * The command queue (#4/#9) must use this mode! |
038669e4 EG |
208 | * This mode does not require use of the Byte Count table in host DRAM. |
209 | * | |
210 | * Driver controls scheduler operation via 3 means: | |
211 | * 1) Scheduler registers | |
8ff84a2c | 212 | * 2) Shared scheduler data base in internal SRAM |
038669e4 EG |
213 | * 3) Shared data in host DRAM |
214 | * | |
215 | * Initialization: | |
216 | * | |
217 | * When loading, driver should allocate memory for: | |
218 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. | |
219 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory | |
220 | * (1024 bytes for each queue). | |
221 | * | |
222 | * After receiving "Alive" response from uCode, driver must initialize | |
13bb9483 | 223 | * the scheduler (especially for queue #4/#9, the command queue, otherwise |
038669e4 EG |
224 | * the driver can't issue commands!): |
225 | */ | |
f86af7ba | 226 | #define SCD_MEM_LOWER_BOUND (0x0000) |
038669e4 EG |
227 | |
228 | /** | |
229 | * Max Tx window size is the max number of contiguous TFDs that the scheduler | |
230 | * can keep track of at one time when creating block-ack chains of frames. | |
231 | * Note that "64" matches the number of ack bits in a block-ack packet. | |
038669e4 EG |
232 | */ |
233 | #define SCD_WIN_SIZE 64 | |
234 | #define SCD_FRAME_LIMIT 64 | |
235 | ||
b3c2ce13 EG |
236 | #define SCD_TXFIFO_POS_TID (0) |
237 | #define SCD_TXFIFO_POS_RA (4) | |
238 | #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) | |
038669e4 | 239 | |
f4388adc | 240 | /* agn SCD */ |
b3c2ce13 EG |
241 | #define SCD_QUEUE_STTS_REG_POS_TXF (0) |
242 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) | |
243 | #define SCD_QUEUE_STTS_REG_POS_WSL (4) | |
244 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) | |
cde5b487 | 245 | #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) |
b3c2ce13 EG |
246 | |
247 | #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) | |
248 | #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) | |
249 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) | |
250 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) | |
251 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) | |
252 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) | |
253 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) | |
254 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
cb6bb128 | 255 | #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) |
f4388adc | 256 | |
f86af7ba | 257 | /* Context Data */ |
b3c2ce13 EG |
258 | #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) |
259 | #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) | |
f86af7ba WYG |
260 | |
261 | /* Tx status */ | |
b3c2ce13 EG |
262 | #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) |
263 | #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) | |
f86af7ba WYG |
264 | |
265 | /* Translation Data */ | |
b3c2ce13 EG |
266 | #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) |
267 | #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) | |
f4388adc | 268 | |
b3c2ce13 EG |
269 | #define SCD_CONTEXT_QUEUE_OFFSET(x)\ |
270 | (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) | |
f4388adc | 271 | |
986ea6c9 EG |
272 | #define SCD_TX_STTS_QUEUE_OFFSET(x)\ |
273 | (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) | |
274 | ||
b3c2ce13 EG |
275 | #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ |
276 | ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) | |
f4388adc | 277 | |
b3c2ce13 EG |
278 | #define SCD_BASE (PRPH_BASE + 0xa02c00) |
279 | ||
280 | #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) | |
281 | #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) | |
282 | #define SCD_AIT (SCD_BASE + 0x0c) | |
283 | #define SCD_TXFACT (SCD_BASE + 0x10) | |
284 | #define SCD_ACTIVE (SCD_BASE + 0x14) | |
b3c2ce13 | 285 | #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) |
d012d04e | 286 | #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) |
b3c2ce13 EG |
287 | #define SCD_AGGR_SEL (SCD_BASE + 0x248) |
288 | #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) | |
cb6bb128 | 289 | #define SCD_GP_CTRL (SCD_BASE + 0x1a8) |
002a9e26 | 290 | #define SCD_EN_CTRL (SCD_BASE + 0x254) |
5ef4acd5 | 291 | |
038669e4 EG |
292 | /*********************** END TX SCHEDULER *************************************/ |
293 | ||
2d93aee1 EG |
294 | /* Oscillator clock */ |
295 | #define OSC_CLK (0xa04068) | |
296 | #define OSC_CLK_FORCE_CONTROL (0x8) | |
297 | ||
dcab8ecd | 298 | #define FH_UCODE_LOAD_STATUS (0x1AF0) |
189fa2fa EH |
299 | #define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70) |
300 | enum secure_load_status_reg { | |
301 | LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, | |
302 | LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, | |
303 | LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, | |
304 | LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, | |
305 | LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, | |
306 | }; | |
307 | ||
308 | #define LMPM_SECURE_INSPECTOR_CODE_ADDR (0x1E38) | |
309 | #define LMPM_SECURE_INSPECTOR_DATA_ADDR (0x1E3C) | |
310 | #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) | |
311 | #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) | |
312 | ||
313 | #define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE (0x400000) | |
314 | #define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE (0x402000) | |
dcab8ecd EH |
315 | #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) |
316 | #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) | |
189fa2fa | 317 | |
7b445f35 EG |
318 | /* Rx FIFO */ |
319 | #define RXF_SIZE_ADDR (0xa00c88) | |
04fd2c28 LK |
320 | #define RXF_RD_D_SPACE (0xa00c40) |
321 | #define RXF_RD_WR_PTR (0xa00c50) | |
322 | #define RXF_RD_RD_PTR (0xa00c54) | |
323 | #define RXF_RD_FENCE_PTR (0xa00c4c) | |
324 | #define RXF_SET_FENCE_MODE (0xa00c14) | |
325 | #define RXF_LD_WR2FENCE (0xa00c1c) | |
326 | #define RXF_FIFO_RD_FENCE_INC (0xa00c68) | |
7b445f35 EG |
327 | #define RXF_SIZE_BYTE_CND_POS (7) |
328 | #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS) | |
04fd2c28 | 329 | #define RXF_DIFF_FROM_PREV (0x200) |
7b445f35 EG |
330 | |
331 | #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10) | |
332 | #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c) | |
333 | ||
04fd2c28 LK |
334 | /* Tx FIFO */ |
335 | #define TXF_FIFO_ITEM_CNT (0xa00438) | |
336 | #define TXF_WR_PTR (0xa00414) | |
337 | #define TXF_RD_PTR (0xa00410) | |
338 | #define TXF_FENCE_PTR (0xa00418) | |
339 | #define TXF_LOCK_FENCE (0xa00424) | |
340 | #define TXF_LARC_NUM (0xa0043c) | |
341 | #define TXF_READ_MODIFY_DATA (0xa00448) | |
342 | #define TXF_READ_MODIFY_ADDR (0xa0044c) | |
343 | ||
c2d20201 | 344 | /* FW monitor */ |
8c23f95c | 345 | #define MON_BUFF_SAMPLE_CTL (0xa03c00) |
c2d20201 EG |
346 | #define MON_BUFF_BASE_ADDR (0xa03c3c) |
347 | #define MON_BUFF_END_ADDR (0xa03c40) | |
348 | #define MON_BUFF_WRPTR (0xa03c44) | |
349 | #define MON_BUFF_CYCLE_CNT (0xa03c48) | |
350 | ||
cc79ef66 LK |
351 | #define MON_DMARB_RD_CTL_ADDR (0xa03c60) |
352 | #define MON_DMARB_RD_DATA_ADDR (0xa03c5c) | |
353 | ||
8c23f95c | 354 | #define DBGC_IN_SAMPLE (0xa03c00) |
8c23f95c | 355 | |
8ba2d7a1 EH |
356 | /* enable the ID buf for read */ |
357 | #define WFPM_PS_CTL_CLR 0xA0300C | |
358 | #define WFMP_MAC_ADDR_0 0xA03080 | |
359 | #define WFMP_MAC_ADDR_1 0xA03084 | |
360 | #define LMPM_PMG_EN 0xA01CEC | |
361 | #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078 | |
362 | #define RFIC_REG_RD 0xAD0470 | |
7a42baa6 EH |
363 | #define WFPM_CTRL_REG 0xA03030 |
364 | enum { | |
365 | ENABLE_WFPM = BIT(31), | |
16bc119b | 366 | WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, |
7a42baa6 EH |
367 | }; |
368 | ||
369 | #define AUX_MISC_REG 0xA200B0 | |
370 | enum { | |
371 | HW_STEP_LOCATION_BITS = 24, | |
372 | }; | |
8ba2d7a1 | 373 | |
16bc119b EH |
374 | #define AUX_MISC_MASTER1_EN 0xA20818 |
375 | enum aux_misc_master1_en { | |
376 | AUX_MISC_MASTER1_EN_SBE_MSK = 0x1, | |
377 | }; | |
378 | ||
379 | #define AUX_MISC_MASTER1_SMPHR_STATUS 0xA20800 | |
380 | #define RSA_ENABLE 0xA24B08 | |
381 | #define PREG_AUX_BUS_WPROT_0 0xA04CC0 | |
382 | ||
fe45773b AN |
383 | /* FW chicken bits */ |
384 | #define LMPM_CHICK 0xA01FF8 | |
385 | enum { | |
386 | LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), | |
387 | }; | |
388 | ||
b481de9c | 389 | #endif /* __iwl_prph_h__ */ |