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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
4e318262 | 8 | * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
4e318262 | 33 | * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. |
c85eb619 EG |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
a42a1844 EG |
63 | #include <linux/pci.h> |
64 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 65 | #include <linux/interrupt.h> |
87e5666c | 66 | #include <linux/debugfs.h> |
6d8f6eeb EG |
67 | #include <linux/bitops.h> |
68 | #include <linux/gfp.h> | |
e6bb4c9c | 69 | |
c85eb619 | 70 | #include "iwl-trans.h" |
c17d0681 | 71 | #include "iwl-trans-pcie-int.h" |
522376d2 EG |
72 | #include "iwl-csr.h" |
73 | #include "iwl-prph.h" | |
48f20d35 | 74 | #include "iwl-shared.h" |
522376d2 | 75 | #include "iwl-eeprom.h" |
7a10e3e4 | 76 | #include "iwl-agn-hw.h" |
c85eb619 | 77 | |
5a878bf6 | 78 | static int iwl_trans_rx_alloc(struct iwl_trans *trans) |
c85eb619 | 79 | { |
5a878bf6 EG |
80 | struct iwl_trans_pcie *trans_pcie = |
81 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
82 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
83 | struct device *dev = bus(trans)->dev; | |
c85eb619 | 84 | |
5a878bf6 | 85 | memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq)); |
c85eb619 EG |
86 | |
87 | spin_lock_init(&rxq->lock); | |
c85eb619 EG |
88 | |
89 | if (WARN_ON(rxq->bd || rxq->rb_stts)) | |
90 | return -EINVAL; | |
91 | ||
92 | /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */ | |
84c816da DH |
93 | rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
94 | &rxq->bd_dma, GFP_KERNEL); | |
c85eb619 EG |
95 | if (!rxq->bd) |
96 | goto err_bd; | |
c85eb619 EG |
97 | |
98 | /*Allocate the driver's pointer to receive buffer status */ | |
84c816da DH |
99 | rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts), |
100 | &rxq->rb_stts_dma, GFP_KERNEL); | |
c85eb619 EG |
101 | if (!rxq->rb_stts) |
102 | goto err_rb_stts; | |
c85eb619 EG |
103 | |
104 | return 0; | |
105 | ||
106 | err_rb_stts: | |
a0f6b0a2 EG |
107 | dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE, |
108 | rxq->bd, rxq->bd_dma); | |
c85eb619 EG |
109 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); |
110 | rxq->bd = NULL; | |
111 | err_bd: | |
112 | return -ENOMEM; | |
113 | } | |
114 | ||
5a878bf6 | 115 | static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans) |
c85eb619 | 116 | { |
5a878bf6 EG |
117 | struct iwl_trans_pcie *trans_pcie = |
118 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
119 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
a0f6b0a2 | 120 | int i; |
c85eb619 EG |
121 | |
122 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
123 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
124 | /* In the reset function, these buffers may have been allocated | |
125 | * to an SKB, so we need to unmap and free potential storage */ | |
126 | if (rxq->pool[i].page != NULL) { | |
5a878bf6 EG |
127 | dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma, |
128 | PAGE_SIZE << hw_params(trans).rx_page_order, | |
c85eb619 | 129 | DMA_FROM_DEVICE); |
790428b6 EG |
130 | __free_pages(rxq->pool[i].page, |
131 | hw_params(trans).rx_page_order); | |
c85eb619 EG |
132 | rxq->pool[i].page = NULL; |
133 | } | |
134 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
135 | } | |
a0f6b0a2 EG |
136 | } |
137 | ||
fd656935 | 138 | static void iwl_trans_rx_hw_init(struct iwl_trans *trans, |
ab697a9f EG |
139 | struct iwl_rx_queue *rxq) |
140 | { | |
141 | u32 rb_size; | |
142 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ | |
c17d0681 | 143 | u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */ |
ab697a9f EG |
144 | |
145 | if (iwlagn_mod_params.amsdu_size_8K) | |
146 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
147 | else | |
148 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
149 | ||
150 | /* Stop Rx DMA */ | |
83ed9015 | 151 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
ab697a9f EG |
152 | |
153 | /* Reset driver's Rx queue write index */ | |
83ed9015 | 154 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
ab697a9f EG |
155 | |
156 | /* Tell device where to find RBD circular buffer in DRAM */ | |
83ed9015 | 157 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
ab697a9f EG |
158 | (u32)(rxq->bd_dma >> 8)); |
159 | ||
160 | /* Tell device where in DRAM to update its Rx status */ | |
83ed9015 | 161 | iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG, |
ab697a9f EG |
162 | rxq->rb_stts_dma >> 4); |
163 | ||
164 | /* Enable Rx DMA | |
165 | * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in | |
166 | * the credit mechanism in 5000 HW RX FIFO | |
167 | * Direct rx interrupts to hosts | |
168 | * Rx buffer size 4 or 8k | |
169 | * RB timeout 0x10 | |
170 | * 256 RBDs | |
171 | */ | |
83ed9015 | 172 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, |
ab697a9f EG |
173 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
174 | FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | | |
175 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
176 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | |
177 | rb_size| | |
178 | (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| | |
179 | (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
180 | ||
181 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
83ed9015 | 182 | iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); |
ab697a9f EG |
183 | } |
184 | ||
5a878bf6 | 185 | static int iwl_rx_init(struct iwl_trans *trans) |
a0f6b0a2 | 186 | { |
5a878bf6 EG |
187 | struct iwl_trans_pcie *trans_pcie = |
188 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
189 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
190 | ||
a0f6b0a2 EG |
191 | int i, err; |
192 | unsigned long flags; | |
193 | ||
194 | if (!rxq->bd) { | |
5a878bf6 | 195 | err = iwl_trans_rx_alloc(trans); |
a0f6b0a2 EG |
196 | if (err) |
197 | return err; | |
198 | } | |
199 | ||
200 | spin_lock_irqsave(&rxq->lock, flags); | |
201 | INIT_LIST_HEAD(&rxq->rx_free); | |
202 | INIT_LIST_HEAD(&rxq->rx_used); | |
203 | ||
5a878bf6 | 204 | iwl_trans_rxq_free_rx_bufs(trans); |
c85eb619 EG |
205 | |
206 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
207 | rxq->queue[i] = NULL; | |
208 | ||
209 | /* Set us so that we have processed and used all buffers, but have | |
210 | * not restocked the Rx queue with fresh buffers */ | |
211 | rxq->read = rxq->write = 0; | |
212 | rxq->write_actual = 0; | |
213 | rxq->free_count = 0; | |
214 | spin_unlock_irqrestore(&rxq->lock, flags); | |
215 | ||
5a878bf6 | 216 | iwlagn_rx_replenish(trans); |
ab697a9f | 217 | |
fd656935 | 218 | iwl_trans_rx_hw_init(trans, rxq); |
ab697a9f | 219 | |
5a878bf6 | 220 | spin_lock_irqsave(&trans->shrd->lock, flags); |
ab697a9f | 221 | rxq->need_update = 1; |
5a878bf6 EG |
222 | iwl_rx_queue_update_write_ptr(trans, rxq); |
223 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
ab697a9f | 224 | |
c85eb619 EG |
225 | return 0; |
226 | } | |
227 | ||
5a878bf6 | 228 | static void iwl_trans_pcie_rx_free(struct iwl_trans *trans) |
a0f6b0a2 | 229 | { |
5a878bf6 EG |
230 | struct iwl_trans_pcie *trans_pcie = |
231 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
232 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
233 | ||
a0f6b0a2 EG |
234 | unsigned long flags; |
235 | ||
236 | /*if rxq->bd is NULL, it means that nothing has been allocated, | |
237 | * exit now */ | |
238 | if (!rxq->bd) { | |
5a878bf6 | 239 | IWL_DEBUG_INFO(trans, "Free NULL rx context\n"); |
a0f6b0a2 EG |
240 | return; |
241 | } | |
242 | ||
243 | spin_lock_irqsave(&rxq->lock, flags); | |
5a878bf6 | 244 | iwl_trans_rxq_free_rx_bufs(trans); |
a0f6b0a2 EG |
245 | spin_unlock_irqrestore(&rxq->lock, flags); |
246 | ||
5a878bf6 | 247 | dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE, |
a0f6b0a2 EG |
248 | rxq->bd, rxq->bd_dma); |
249 | memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma)); | |
250 | rxq->bd = NULL; | |
251 | ||
252 | if (rxq->rb_stts) | |
5a878bf6 | 253 | dma_free_coherent(bus(trans)->dev, |
a0f6b0a2 EG |
254 | sizeof(struct iwl_rb_status), |
255 | rxq->rb_stts, rxq->rb_stts_dma); | |
256 | else | |
5a878bf6 | 257 | IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n"); |
a0f6b0a2 EG |
258 | memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma)); |
259 | rxq->rb_stts = NULL; | |
260 | } | |
261 | ||
6d8f6eeb | 262 | static int iwl_trans_rx_stop(struct iwl_trans *trans) |
c2c52e8b EG |
263 | { |
264 | ||
265 | /* stop Rx DMA */ | |
83ed9015 EG |
266 | iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
267 | return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG, | |
c2c52e8b EG |
268 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
269 | } | |
270 | ||
6d8f6eeb | 271 | static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans, |
02aca585 EG |
272 | struct iwl_dma_ptr *ptr, size_t size) |
273 | { | |
274 | if (WARN_ON(ptr->addr)) | |
275 | return -EINVAL; | |
276 | ||
6d8f6eeb | 277 | ptr->addr = dma_alloc_coherent(bus(trans)->dev, size, |
02aca585 EG |
278 | &ptr->dma, GFP_KERNEL); |
279 | if (!ptr->addr) | |
280 | return -ENOMEM; | |
281 | ptr->size = size; | |
282 | return 0; | |
283 | } | |
284 | ||
6d8f6eeb | 285 | static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans, |
1359ca4f EG |
286 | struct iwl_dma_ptr *ptr) |
287 | { | |
288 | if (unlikely(!ptr->addr)) | |
289 | return; | |
290 | ||
6d8f6eeb | 291 | dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma); |
1359ca4f EG |
292 | memset(ptr, 0, sizeof(*ptr)); |
293 | } | |
294 | ||
6d8f6eeb EG |
295 | static int iwl_trans_txq_alloc(struct iwl_trans *trans, |
296 | struct iwl_tx_queue *txq, int slots_num, | |
297 | u32 txq_id) | |
02aca585 | 298 | { |
ab9e212e | 299 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; |
02aca585 EG |
300 | int i; |
301 | ||
2c452297 | 302 | if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds)) |
02aca585 EG |
303 | return -EINVAL; |
304 | ||
1359ca4f EG |
305 | txq->q.n_window = slots_num; |
306 | ||
7f90dce1 EG |
307 | txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL); |
308 | txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL); | |
02aca585 EG |
309 | |
310 | if (!txq->meta || !txq->cmd) | |
311 | goto error; | |
312 | ||
dfa2bdba EG |
313 | if (txq_id == trans->shrd->cmd_queue) |
314 | for (i = 0; i < slots_num; i++) { | |
315 | txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd), | |
316 | GFP_KERNEL); | |
317 | if (!txq->cmd[i]) | |
318 | goto error; | |
319 | } | |
02aca585 EG |
320 | |
321 | /* Alloc driver data array and TFD circular buffer */ | |
322 | /* Driver private data, only for Tx (not command) queues, | |
323 | * not shared with device. */ | |
6d8f6eeb | 324 | if (txq_id != trans->shrd->cmd_queue) { |
7f90dce1 EG |
325 | txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]), |
326 | GFP_KERNEL); | |
2c452297 | 327 | if (!txq->skbs) { |
6d8f6eeb | 328 | IWL_ERR(trans, "kmalloc for auxiliary BD " |
02aca585 EG |
329 | "structures failed\n"); |
330 | goto error; | |
331 | } | |
332 | } else { | |
2c452297 | 333 | txq->skbs = NULL; |
02aca585 EG |
334 | } |
335 | ||
336 | /* Circular buffer of transmit frame descriptors (TFDs), | |
337 | * shared with device */ | |
6d8f6eeb EG |
338 | txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz, |
339 | &txq->q.dma_addr, GFP_KERNEL); | |
02aca585 | 340 | if (!txq->tfds) { |
6d8f6eeb | 341 | IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz); |
02aca585 EG |
342 | goto error; |
343 | } | |
344 | txq->q.id = txq_id; | |
345 | ||
346 | return 0; | |
347 | error: | |
2c452297 EG |
348 | kfree(txq->skbs); |
349 | txq->skbs = NULL; | |
02aca585 EG |
350 | /* since txq->cmd has been zeroed, |
351 | * all non allocated cmd[i] will be NULL */ | |
dfa2bdba | 352 | if (txq->cmd && txq_id == trans->shrd->cmd_queue) |
02aca585 EG |
353 | for (i = 0; i < slots_num; i++) |
354 | kfree(txq->cmd[i]); | |
355 | kfree(txq->meta); | |
356 | kfree(txq->cmd); | |
357 | txq->meta = NULL; | |
358 | txq->cmd = NULL; | |
359 | ||
360 | return -ENOMEM; | |
361 | ||
362 | } | |
363 | ||
6d8f6eeb | 364 | static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq, |
02aca585 EG |
365 | int slots_num, u32 txq_id) |
366 | { | |
367 | int ret; | |
368 | ||
369 | txq->need_update = 0; | |
370 | memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num); | |
371 | ||
372 | /* | |
373 | * For the default queues 0-3, set up the swq_id | |
374 | * already -- all others need to get one later | |
375 | * (if they need one at all). | |
376 | */ | |
377 | if (txq_id < 4) | |
378 | iwl_set_swq_id(txq, txq_id, txq_id); | |
379 | ||
380 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
381 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
382 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
383 | ||
384 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
6d8f6eeb | 385 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, |
02aca585 EG |
386 | txq_id); |
387 | if (ret) | |
388 | return ret; | |
389 | ||
390 | /* | |
391 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
392 | * given Tx queue, and enable the DMA channel used for that queue. | |
393 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
83ed9015 | 394 | iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id), |
02aca585 EG |
395 | txq->q.dma_addr >> 8); |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
c170b867 EG |
400 | /** |
401 | * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
402 | */ | |
6d8f6eeb | 403 | static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id) |
c170b867 | 404 | { |
8ad71bef EG |
405 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
406 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
c170b867 | 407 | struct iwl_queue *q = &txq->q; |
39644e9a | 408 | enum dma_data_direction dma_dir; |
984ecb92 | 409 | unsigned long flags; |
cda4ee3f | 410 | spinlock_t *lock; |
c170b867 EG |
411 | |
412 | if (!q->n_bd) | |
413 | return; | |
414 | ||
39644e9a EG |
415 | /* In the command queue, all the TBs are mapped as BIDI |
416 | * so unmap them as such. | |
417 | */ | |
cda4ee3f | 418 | if (txq_id == trans->shrd->cmd_queue) { |
39644e9a | 419 | dma_dir = DMA_BIDIRECTIONAL; |
cda4ee3f EG |
420 | lock = &trans->hcmd_lock; |
421 | } else { | |
39644e9a | 422 | dma_dir = DMA_TO_DEVICE; |
cda4ee3f EG |
423 | lock = &trans->shrd->sta_lock; |
424 | } | |
39644e9a | 425 | |
cda4ee3f | 426 | spin_lock_irqsave(lock, flags); |
c170b867 EG |
427 | while (q->write_ptr != q->read_ptr) { |
428 | /* The read_ptr needs to bound by q->n_window */ | |
39644e9a EG |
429 | iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr), |
430 | dma_dir); | |
c170b867 EG |
431 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
432 | } | |
cda4ee3f | 433 | spin_unlock_irqrestore(lock, flags); |
c170b867 EG |
434 | } |
435 | ||
1359ca4f EG |
436 | /** |
437 | * iwl_tx_queue_free - Deallocate DMA queue. | |
438 | * @txq: Transmit queue to deallocate. | |
439 | * | |
440 | * Empty queue by removing and destroying all BD's. | |
441 | * Free all buffers. | |
442 | * 0-fill, but do not free "txq" descriptor structure. | |
443 | */ | |
6d8f6eeb | 444 | static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id) |
1359ca4f | 445 | { |
8ad71bef EG |
446 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
447 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
6d8f6eeb | 448 | struct device *dev = bus(trans)->dev; |
1359ca4f EG |
449 | int i; |
450 | if (WARN_ON(!txq)) | |
451 | return; | |
452 | ||
6d8f6eeb | 453 | iwl_tx_queue_unmap(trans, txq_id); |
1359ca4f EG |
454 | |
455 | /* De-alloc array of command/tx buffers */ | |
dfa2bdba EG |
456 | |
457 | if (txq_id == trans->shrd->cmd_queue) | |
458 | for (i = 0; i < txq->q.n_window; i++) | |
459 | kfree(txq->cmd[i]); | |
1359ca4f EG |
460 | |
461 | /* De-alloc circular buffer of TFDs */ | |
462 | if (txq->q.n_bd) { | |
ab9e212e | 463 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * |
1359ca4f EG |
464 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
465 | memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr)); | |
466 | } | |
467 | ||
468 | /* De-alloc array of per-TFD driver data */ | |
2c452297 EG |
469 | kfree(txq->skbs); |
470 | txq->skbs = NULL; | |
1359ca4f EG |
471 | |
472 | /* deallocate arrays */ | |
473 | kfree(txq->cmd); | |
474 | kfree(txq->meta); | |
475 | txq->cmd = NULL; | |
476 | txq->meta = NULL; | |
477 | ||
478 | /* 0-fill queue descriptor structure */ | |
479 | memset(txq, 0, sizeof(*txq)); | |
480 | } | |
481 | ||
482 | /** | |
483 | * iwl_trans_tx_free - Free TXQ Context | |
484 | * | |
485 | * Destroy all TX DMA queues and structures | |
486 | */ | |
6d8f6eeb | 487 | static void iwl_trans_pcie_tx_free(struct iwl_trans *trans) |
1359ca4f EG |
488 | { |
489 | int txq_id; | |
8ad71bef | 490 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1359ca4f EG |
491 | |
492 | /* Tx queues */ | |
8ad71bef | 493 | if (trans_pcie->txq) { |
d6189124 | 494 | for (txq_id = 0; |
6d8f6eeb EG |
495 | txq_id < hw_params(trans).max_txq_num; txq_id++) |
496 | iwl_tx_queue_free(trans, txq_id); | |
1359ca4f EG |
497 | } |
498 | ||
8ad71bef EG |
499 | kfree(trans_pcie->txq); |
500 | trans_pcie->txq = NULL; | |
1359ca4f | 501 | |
9d6b2cb1 | 502 | iwlagn_free_dma_ptr(trans, &trans_pcie->kw); |
1359ca4f | 503 | |
6d8f6eeb | 504 | iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); |
1359ca4f EG |
505 | } |
506 | ||
02aca585 EG |
507 | /** |
508 | * iwl_trans_tx_alloc - allocate TX context | |
509 | * Allocate all Tx DMA structures and initialize them | |
510 | * | |
511 | * @param priv | |
512 | * @return error code | |
513 | */ | |
6d8f6eeb | 514 | static int iwl_trans_tx_alloc(struct iwl_trans *trans) |
02aca585 EG |
515 | { |
516 | int ret; | |
517 | int txq_id, slots_num; | |
8ad71bef | 518 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 519 | |
fd656935 | 520 | u16 scd_bc_tbls_size = hw_params(trans).max_txq_num * |
ab9e212e EG |
521 | sizeof(struct iwlagn_scd_bc_tbl); |
522 | ||
02aca585 EG |
523 | /*It is not allowed to alloc twice, so warn when this happens. |
524 | * We cannot rely on the previous allocation, so free and fail */ | |
8ad71bef | 525 | if (WARN_ON(trans_pcie->txq)) { |
02aca585 EG |
526 | ret = -EINVAL; |
527 | goto error; | |
528 | } | |
529 | ||
6d8f6eeb | 530 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, |
ab9e212e | 531 | scd_bc_tbls_size); |
02aca585 | 532 | if (ret) { |
6d8f6eeb | 533 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); |
02aca585 EG |
534 | goto error; |
535 | } | |
536 | ||
537 | /* Alloc keep-warm buffer */ | |
9d6b2cb1 | 538 | ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); |
02aca585 | 539 | if (ret) { |
6d8f6eeb | 540 | IWL_ERR(trans, "Keep Warm allocation failed\n"); |
02aca585 EG |
541 | goto error; |
542 | } | |
543 | ||
7f90dce1 EG |
544 | trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num, |
545 | sizeof(struct iwl_tx_queue), GFP_KERNEL); | |
8ad71bef | 546 | if (!trans_pcie->txq) { |
6d8f6eeb | 547 | IWL_ERR(trans, "Not enough memory for txq\n"); |
02aca585 EG |
548 | ret = ENOMEM; |
549 | goto error; | |
550 | } | |
551 | ||
552 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
553 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
554 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 555 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
556 | ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id], |
557 | slots_num, txq_id); | |
02aca585 | 558 | if (ret) { |
6d8f6eeb | 559 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); |
02aca585 EG |
560 | goto error; |
561 | } | |
562 | } | |
563 | ||
564 | return 0; | |
565 | ||
566 | error: | |
ae2c30bf | 567 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
568 | |
569 | return ret; | |
570 | } | |
6d8f6eeb | 571 | static int iwl_tx_init(struct iwl_trans *trans) |
02aca585 EG |
572 | { |
573 | int ret; | |
574 | int txq_id, slots_num; | |
575 | unsigned long flags; | |
576 | bool alloc = false; | |
8ad71bef | 577 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
02aca585 | 578 | |
8ad71bef | 579 | if (!trans_pcie->txq) { |
6d8f6eeb | 580 | ret = iwl_trans_tx_alloc(trans); |
02aca585 EG |
581 | if (ret) |
582 | goto error; | |
583 | alloc = true; | |
584 | } | |
585 | ||
6d8f6eeb | 586 | spin_lock_irqsave(&trans->shrd->lock, flags); |
02aca585 EG |
587 | |
588 | /* Turn off all Tx DMA fifos */ | |
83ed9015 | 589 | iwl_write_prph(bus(trans), SCD_TXFACT, 0); |
02aca585 EG |
590 | |
591 | /* Tell NIC where to find the "keep warm" buffer */ | |
83ed9015 EG |
592 | iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG, |
593 | trans_pcie->kw.dma >> 4); | |
02aca585 | 594 | |
6d8f6eeb | 595 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
02aca585 EG |
596 | |
597 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
6d8f6eeb EG |
598 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) { |
599 | slots_num = (txq_id == trans->shrd->cmd_queue) ? | |
02aca585 | 600 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
8ad71bef EG |
601 | ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id], |
602 | slots_num, txq_id); | |
02aca585 | 603 | if (ret) { |
6d8f6eeb | 604 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); |
02aca585 EG |
605 | goto error; |
606 | } | |
607 | } | |
608 | ||
609 | return 0; | |
610 | error: | |
611 | /*Upon error, free only if we allocated something */ | |
612 | if (alloc) | |
ae2c30bf | 613 | iwl_trans_pcie_tx_free(trans); |
02aca585 EG |
614 | return ret; |
615 | } | |
616 | ||
3e10caeb | 617 | static void iwl_set_pwr_vmain(struct iwl_trans *trans) |
392f8b78 EG |
618 | { |
619 | /* | |
620 | * (for documentation purposes) | |
621 | * to set power to V_AUX, do: | |
622 | ||
623 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | |
83ed9015 | 624 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
392f8b78 EG |
625 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
626 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
627 | */ | |
628 | ||
83ed9015 | 629 | iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG, |
392f8b78 EG |
630 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
631 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
632 | } | |
633 | ||
6d8f6eeb | 634 | static int iwl_nic_init(struct iwl_trans *trans) |
392f8b78 EG |
635 | { |
636 | unsigned long flags; | |
637 | ||
638 | /* nic_init */ | |
6d8f6eeb | 639 | spin_lock_irqsave(&trans->shrd->lock, flags); |
3e10caeb | 640 | iwl_apm_init(priv(trans)); |
392f8b78 EG |
641 | |
642 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ | |
83ed9015 EG |
643 | iwl_write8(bus(trans), CSR_INT_COALESCING, |
644 | IWL_HOST_INT_CALIB_TIMEOUT_DEF); | |
392f8b78 | 645 | |
6d8f6eeb | 646 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
392f8b78 | 647 | |
3e10caeb | 648 | iwl_set_pwr_vmain(trans); |
392f8b78 | 649 | |
7a10e3e4 | 650 | iwl_nic_config(priv(trans)); |
392f8b78 | 651 | |
a5916977 | 652 | #ifndef CONFIG_IWLWIFI_IDI |
392f8b78 | 653 | /* Allocate the RX queue, or reset if it is already allocated */ |
6d8f6eeb | 654 | iwl_rx_init(trans); |
a5916977 | 655 | #endif |
392f8b78 EG |
656 | |
657 | /* Allocate or reset and init all Tx and Command queues */ | |
6d8f6eeb | 658 | if (iwl_tx_init(trans)) |
392f8b78 EG |
659 | return -ENOMEM; |
660 | ||
fd656935 | 661 | if (hw_params(trans).shadow_reg_enable) { |
392f8b78 | 662 | /* enable shadow regs in HW */ |
83ed9015 | 663 | iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL, |
392f8b78 EG |
664 | 0x800FFFFF); |
665 | } | |
666 | ||
6d8f6eeb | 667 | set_bit(STATUS_INIT, &trans->shrd->status); |
392f8b78 EG |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
672 | #define HW_READY_TIMEOUT (50) | |
673 | ||
674 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
6d8f6eeb | 675 | static int iwl_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
676 | { |
677 | int ret; | |
678 | ||
83ed9015 | 679 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
680 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
681 | ||
682 | /* See if we got it */ | |
83ed9015 | 683 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
684 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
685 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
686 | HW_READY_TIMEOUT); | |
687 | ||
6d8f6eeb | 688 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
689 | return ret; |
690 | } | |
691 | ||
692 | /* Note: returns standard 0/-ERROR code */ | |
6d8f6eeb | 693 | static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
694 | { |
695 | int ret; | |
696 | ||
6d8f6eeb | 697 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 698 | |
6d8f6eeb | 699 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
700 | if (ret >= 0) |
701 | return 0; | |
702 | ||
703 | /* If HW is not ready, prepare the conditions to check again */ | |
83ed9015 | 704 | iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
705 | CSR_HW_IF_CONFIG_REG_PREPARE); |
706 | ||
83ed9015 | 707 | ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG, |
392f8b78 EG |
708 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
709 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
710 | ||
711 | if (ret < 0) | |
712 | return ret; | |
713 | ||
714 | /* HW should be ready by now, check again. */ | |
6d8f6eeb | 715 | ret = iwl_set_hw_ready(trans); |
392f8b78 EG |
716 | if (ret >= 0) |
717 | return 0; | |
718 | return ret; | |
719 | } | |
720 | ||
e13c0c59 EG |
721 | #define IWL_AC_UNSET -1 |
722 | ||
723 | struct queue_to_fifo_ac { | |
724 | s8 fifo, ac; | |
725 | }; | |
726 | ||
727 | static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = { | |
728 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
729 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
730 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
731 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
732 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
733 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
734 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
735 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
736 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
737 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
738 | { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, }, | |
739 | }; | |
740 | ||
741 | static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = { | |
742 | { IWL_TX_FIFO_VO, IEEE80211_AC_VO, }, | |
743 | { IWL_TX_FIFO_VI, IEEE80211_AC_VI, }, | |
744 | { IWL_TX_FIFO_BE, IEEE80211_AC_BE, }, | |
745 | { IWL_TX_FIFO_BK, IEEE80211_AC_BK, }, | |
746 | { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, }, | |
747 | { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, }, | |
748 | { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, }, | |
749 | { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, }, | |
750 | { IWL_TX_FIFO_BE_IPAN, 2, }, | |
751 | { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, }, | |
752 | { IWL_TX_FIFO_AUX, IWL_AC_UNSET, }, | |
753 | }; | |
754 | ||
755 | static const u8 iwlagn_bss_ac_to_fifo[] = { | |
756 | IWL_TX_FIFO_VO, | |
757 | IWL_TX_FIFO_VI, | |
758 | IWL_TX_FIFO_BE, | |
759 | IWL_TX_FIFO_BK, | |
760 | }; | |
761 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
762 | 0, 1, 2, 3, | |
763 | }; | |
764 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
765 | IWL_TX_FIFO_VO_IPAN, | |
766 | IWL_TX_FIFO_VI_IPAN, | |
767 | IWL_TX_FIFO_BE_IPAN, | |
768 | IWL_TX_FIFO_BK_IPAN, | |
769 | }; | |
770 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
771 | 7, 6, 5, 4, | |
772 | }; | |
773 | ||
6d8f6eeb | 774 | static int iwl_trans_pcie_start_device(struct iwl_trans *trans) |
392f8b78 EG |
775 | { |
776 | int ret; | |
e13c0c59 EG |
777 | struct iwl_trans_pcie *trans_pcie = |
778 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
392f8b78 | 779 | |
c91bd124 | 780 | trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER; |
e13c0c59 EG |
781 | trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue; |
782 | trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue; | |
783 | ||
784 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo; | |
785 | trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo; | |
786 | ||
787 | trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0; | |
788 | trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE; | |
392f8b78 | 789 | |
c91bd124 | 790 | if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) && |
6d8f6eeb EG |
791 | iwl_trans_pcie_prepare_card_hw(trans)) { |
792 | IWL_WARN(trans, "Exit HW not ready\n"); | |
392f8b78 EG |
793 | return -EIO; |
794 | } | |
795 | ||
796 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
83ed9015 | 797 | if (iwl_read32(bus(trans), CSR_GP_CNTRL) & |
392f8b78 | 798 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
6d8f6eeb | 799 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
392f8b78 | 800 | else |
6d8f6eeb | 801 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); |
392f8b78 | 802 | |
6d8f6eeb | 803 | if (iwl_is_rfkill(trans->shrd)) { |
3e10caeb | 804 | iwl_set_hw_rfkill_state(priv(trans), true); |
6d8f6eeb | 805 | iwl_enable_interrupts(trans); |
392f8b78 EG |
806 | return -ERFKILL; |
807 | } | |
808 | ||
83ed9015 | 809 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
392f8b78 | 810 | |
6d8f6eeb | 811 | ret = iwl_nic_init(trans); |
392f8b78 | 812 | if (ret) { |
6d8f6eeb | 813 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
814 | return ret; |
815 | } | |
816 | ||
817 | /* make sure rfkill handshake bits are cleared */ | |
83ed9015 EG |
818 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
819 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
820 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
821 | ||
822 | /* clear (again), then enable host interrupts */ | |
83ed9015 | 823 | iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 824 | iwl_enable_interrupts(trans); |
392f8b78 EG |
825 | |
826 | /* really make sure rfkill handshake bits are cleared */ | |
83ed9015 EG |
827 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
828 | iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 EG |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
b3c2ce13 EG |
833 | /* |
834 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
10b15e6f | 835 | * must be called under priv->shrd->lock and mac access |
b3c2ce13 | 836 | */ |
6d8f6eeb | 837 | static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) |
b3c2ce13 | 838 | { |
83ed9015 | 839 | iwl_write_prph(bus(trans), SCD_TXFACT, mask); |
b3c2ce13 EG |
840 | } |
841 | ||
ed6a3803 | 842 | static void iwl_tx_start(struct iwl_trans *trans) |
b3c2ce13 EG |
843 | { |
844 | const struct queue_to_fifo_ac *queue_to_fifo; | |
105183b1 EG |
845 | struct iwl_trans_pcie *trans_pcie = |
846 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
b3c2ce13 EG |
847 | u32 a; |
848 | unsigned long flags; | |
849 | int i, chan; | |
850 | u32 reg_val; | |
851 | ||
105183b1 | 852 | spin_lock_irqsave(&trans->shrd->lock, flags); |
b3c2ce13 | 853 | |
83ed9015 EG |
854 | trans_pcie->scd_base_addr = |
855 | iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR); | |
105183b1 | 856 | a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; |
b3c2ce13 | 857 | /* reset conext data memory */ |
105183b1 | 858 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
b3c2ce13 | 859 | a += 4) |
83ed9015 | 860 | iwl_write_targ_mem(bus(trans), a, 0); |
b3c2ce13 | 861 | /* reset tx status memory */ |
105183b1 | 862 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
b3c2ce13 | 863 | a += 4) |
83ed9015 | 864 | iwl_write_targ_mem(bus(trans), a, 0); |
105183b1 | 865 | for (; a < trans_pcie->scd_base_addr + |
c91bd124 | 866 | SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num); |
d6189124 | 867 | a += 4) |
83ed9015 | 868 | iwl_write_targ_mem(bus(trans), a, 0); |
b3c2ce13 | 869 | |
83ed9015 | 870 | iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR, |
105183b1 | 871 | trans_pcie->scd_bc_tbls.dma >> 10); |
b3c2ce13 EG |
872 | |
873 | /* Enable DMA channel */ | |
874 | for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) | |
83ed9015 | 875 | iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
b3c2ce13 EG |
876 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
877 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
878 | ||
879 | /* Update FH chicken bits */ | |
83ed9015 EG |
880 | reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG); |
881 | iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG, | |
b3c2ce13 EG |
882 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
883 | ||
83ed9015 | 884 | iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL, |
c91bd124 | 885 | SCD_QUEUECHAIN_SEL_ALL(trans)); |
83ed9015 | 886 | iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0); |
b3c2ce13 EG |
887 | |
888 | /* initiate the queues */ | |
c91bd124 | 889 | for (i = 0; i < hw_params(trans).max_txq_num; i++) { |
83ed9015 EG |
890 | iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0); |
891 | iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8)); | |
892 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + | |
b3c2ce13 | 893 | SCD_CONTEXT_QUEUE_OFFSET(i), 0); |
83ed9015 | 894 | iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr + |
b3c2ce13 EG |
895 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
896 | sizeof(u32), | |
897 | ((SCD_WIN_SIZE << | |
898 | SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
899 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
900 | ((SCD_FRAME_LIMIT << | |
901 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
902 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
903 | } | |
904 | ||
83ed9015 | 905 | iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK, |
105183b1 | 906 | IWL_MASK(0, hw_params(trans).max_txq_num)); |
b3c2ce13 EG |
907 | |
908 | /* Activate all Tx DMA/FIFO channels */ | |
6d8f6eeb | 909 | iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7)); |
b3c2ce13 EG |
910 | |
911 | /* map queues to FIFOs */ | |
7a10e3e4 | 912 | if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
b3c2ce13 EG |
913 | queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo; |
914 | else | |
915 | queue_to_fifo = iwlagn_default_queue_to_tx_fifo; | |
916 | ||
6d8f6eeb | 917 | iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0); |
b3c2ce13 EG |
918 | |
919 | /* make sure all queue are not stopped */ | |
8ad71bef EG |
920 | memset(&trans_pcie->queue_stopped[0], 0, |
921 | sizeof(trans_pcie->queue_stopped)); | |
b3c2ce13 | 922 | for (i = 0; i < 4; i++) |
8ad71bef | 923 | atomic_set(&trans_pcie->queue_stop_count[i], 0); |
b3c2ce13 EG |
924 | |
925 | /* reset to 0 to enable all the queue first */ | |
8ad71bef | 926 | trans_pcie->txq_ctx_active_msk = 0; |
b3c2ce13 | 927 | |
effcea16 | 928 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) < |
72c04ce0 | 929 | IWLAGN_FIRST_AMPDU_QUEUE); |
effcea16 | 930 | BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) < |
72c04ce0 | 931 | IWLAGN_FIRST_AMPDU_QUEUE); |
b3c2ce13 | 932 | |
72c04ce0 | 933 | for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) { |
b3c2ce13 EG |
934 | int fifo = queue_to_fifo[i].fifo; |
935 | int ac = queue_to_fifo[i].ac; | |
936 | ||
8ad71bef | 937 | iwl_txq_ctx_activate(trans_pcie, i); |
b3c2ce13 EG |
938 | |
939 | if (fifo == IWL_TX_FIFO_UNUSED) | |
940 | continue; | |
941 | ||
942 | if (ac != IWL_AC_UNSET) | |
8ad71bef EG |
943 | iwl_set_swq_id(&trans_pcie->txq[i], ac, i); |
944 | iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], | |
945 | fifo, 0); | |
b3c2ce13 EG |
946 | } |
947 | ||
6d8f6eeb | 948 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
b3c2ce13 EG |
949 | |
950 | /* Enable L1-Active */ | |
83ed9015 | 951 | iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG, |
b3c2ce13 EG |
952 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
953 | } | |
954 | ||
ed6a3803 EG |
955 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) |
956 | { | |
957 | iwl_reset_ict(trans); | |
958 | iwl_tx_start(trans); | |
959 | } | |
960 | ||
c170b867 EG |
961 | /** |
962 | * iwlagn_txq_ctx_stop - Stop all Tx DMA channels | |
963 | */ | |
6d8f6eeb | 964 | static int iwl_trans_tx_stop(struct iwl_trans *trans) |
c170b867 EG |
965 | { |
966 | int ch, txq_id; | |
967 | unsigned long flags; | |
8ad71bef | 968 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
c170b867 EG |
969 | |
970 | /* Turn off all Tx DMA fifos */ | |
6d8f6eeb | 971 | spin_lock_irqsave(&trans->shrd->lock, flags); |
c170b867 | 972 | |
6d8f6eeb | 973 | iwl_trans_txq_set_sched(trans, 0); |
c170b867 EG |
974 | |
975 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
02f6f659 | 976 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { |
83ed9015 | 977 | iwl_write_direct32(bus(trans), |
6d8f6eeb | 978 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
83ed9015 | 979 | if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG, |
c170b867 EG |
980 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
981 | 1000)) | |
6d8f6eeb | 982 | IWL_ERR(trans, "Failing on timeout while stopping" |
c170b867 | 983 | " DMA channel %d [0x%08x]", ch, |
83ed9015 | 984 | iwl_read_direct32(bus(trans), |
6d8f6eeb | 985 | FH_TSSR_TX_STATUS_REG)); |
c170b867 | 986 | } |
6d8f6eeb | 987 | spin_unlock_irqrestore(&trans->shrd->lock, flags); |
c170b867 | 988 | |
8ad71bef | 989 | if (!trans_pcie->txq) { |
6d8f6eeb | 990 | IWL_WARN(trans, "Stopping tx queues that aren't allocated..."); |
c170b867 EG |
991 | return 0; |
992 | } | |
993 | ||
994 | /* Unmap DMA from host system and free skb's */ | |
6d8f6eeb EG |
995 | for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) |
996 | iwl_tx_queue_unmap(trans, txq_id); | |
c170b867 EG |
997 | |
998 | return 0; | |
999 | } | |
1000 | ||
43e58856 | 1001 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) |
ae2c30bf EG |
1002 | { |
1003 | unsigned long flags; | |
43e58856 | 1004 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
ae2c30bf | 1005 | |
43e58856 | 1006 | /* tell the device to stop sending interrupts */ |
ae2c30bf EG |
1007 | spin_lock_irqsave(&trans->shrd->lock, flags); |
1008 | iwl_disable_interrupts(trans); | |
1009 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1010 | ||
ab6cf8e8 | 1011 | /* device going down, Stop using ICT table */ |
6d8f6eeb | 1012 | iwl_disable_ict(trans); |
ab6cf8e8 EG |
1013 | |
1014 | /* | |
1015 | * If a HW restart happens during firmware loading, | |
1016 | * then the firmware loading might call this function | |
1017 | * and later it might be called again due to the | |
1018 | * restart. So don't process again if the device is | |
1019 | * already dead. | |
1020 | */ | |
6d8f6eeb EG |
1021 | if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) { |
1022 | iwl_trans_tx_stop(trans); | |
a5916977 | 1023 | #ifndef CONFIG_IWLWIFI_IDI |
6d8f6eeb | 1024 | iwl_trans_rx_stop(trans); |
a5916977 | 1025 | #endif |
ab6cf8e8 | 1026 | /* Power-down device's busmaster DMA clocks */ |
83ed9015 | 1027 | iwl_write_prph(bus(trans), APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1028 | APMG_CLK_VAL_DMA_CLK_RQT); |
1029 | udelay(5); | |
1030 | } | |
1031 | ||
1032 | /* Make sure (redundant) we've released our request to stay awake */ | |
83ed9015 | 1033 | iwl_clear_bit(bus(trans), CSR_GP_CNTRL, |
6d8f6eeb | 1034 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1035 | |
1036 | /* Stop the device, and put it in low power state */ | |
6d8f6eeb | 1037 | iwl_apm_stop(priv(trans)); |
43e58856 EG |
1038 | |
1039 | /* Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1040 | * Clean again the interrupt here | |
1041 | */ | |
1042 | spin_lock_irqsave(&trans->shrd->lock, flags); | |
1043 | iwl_disable_interrupts(trans); | |
1044 | spin_unlock_irqrestore(&trans->shrd->lock, flags); | |
1045 | ||
1046 | /* wait to make sure we flush pending tasklet*/ | |
a42a1844 | 1047 | synchronize_irq(trans->irq); |
43e58856 EG |
1048 | tasklet_kill(&trans_pcie->irq_tasklet); |
1049 | ||
1050 | /* stop and reset the on-board processor */ | |
1051 | iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
ab6cf8e8 EG |
1052 | } |
1053 | ||
e13c0c59 | 1054 | static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
14991a9d | 1055 | struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx, |
34b5321e | 1056 | u8 sta_id, u8 tid) |
47c1b496 | 1057 | { |
e13c0c59 EG |
1058 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1059 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1060 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
132f98c2 | 1061 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload; |
47c1b496 | 1062 | struct iwl_cmd_meta *out_meta; |
e13c0c59 EG |
1063 | struct iwl_tx_queue *txq; |
1064 | struct iwl_queue *q; | |
47c1b496 EG |
1065 | |
1066 | dma_addr_t phys_addr = 0; | |
1067 | dma_addr_t txcmd_phys; | |
1068 | dma_addr_t scratch_phys; | |
1069 | u16 len, firstlen, secondlen; | |
1070 | u8 wait_write_ptr = 0; | |
e13c0c59 | 1071 | u8 txq_id; |
e13c0c59 EG |
1072 | bool is_agg = false; |
1073 | __le16 fc = hdr->frame_control; | |
47c1b496 | 1074 | u8 hdr_len = ieee80211_hdrlen(fc); |
631b84c5 | 1075 | u16 __maybe_unused wifi_seq; |
47c1b496 | 1076 | |
e13c0c59 EG |
1077 | /* |
1078 | * Send this frame after DTIM -- there's a special queue | |
1079 | * reserved for this for contexts that support AP mode. | |
1080 | */ | |
1081 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { | |
1082 | txq_id = trans_pcie->mcast_queue[ctx]; | |
1083 | ||
1084 | /* | |
1085 | * The microcode will clear the more data | |
1086 | * bit in the last frame it transmits. | |
1087 | */ | |
1088 | hdr->frame_control |= | |
1089 | cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1090 | } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) | |
1091 | txq_id = IWL_AUX_QUEUE; | |
1092 | else | |
1093 | txq_id = | |
1094 | trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)]; | |
1095 | ||
97756fb1 EG |
1096 | /* aggregation is on for this <sta,tid> */ |
1097 | if (info->flags & IEEE80211_TX_CTL_AMPDU) { | |
1098 | WARN_ON(tid >= IWL_MAX_TID_COUNT); | |
1099 | txq_id = trans_pcie->agg_txq[sta_id][tid]; | |
1100 | is_agg = true; | |
e13c0c59 EG |
1101 | } |
1102 | ||
8ad71bef | 1103 | txq = &trans_pcie->txq[txq_id]; |
e13c0c59 EG |
1104 | q = &txq->q; |
1105 | ||
631b84c5 EG |
1106 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1107 | * sequence number. This is a HW requirements to help the SCD to parse | |
1108 | * the BA. | |
1109 | * Check here that the packets are in the right place on the ring. | |
1110 | */ | |
1111 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1112 | wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); | |
1113 | WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr), | |
1114 | "Q: %d WiFi Seq %d tfdNum %d", | |
1115 | txq_id, wifi_seq, q->write_ptr); | |
1116 | #endif | |
1117 | ||
47c1b496 | 1118 | /* Set up driver data for this TFD */ |
2c452297 | 1119 | txq->skbs[q->write_ptr] = skb; |
dfa2bdba EG |
1120 | txq->cmd[q->write_ptr] = dev_cmd; |
1121 | ||
1122 | dev_cmd->hdr.cmd = REPLY_TX; | |
1123 | dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1124 | INDEX_TO_SEQ(q->write_ptr))); | |
47c1b496 EG |
1125 | |
1126 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1127 | out_meta = &txq->meta[q->write_ptr]; | |
1128 | ||
1129 | /* | |
1130 | * Use the first empty entry in this queue's command buffer array | |
1131 | * to contain the Tx command and MAC header concatenated together | |
1132 | * (payload data will be in another buffer). | |
1133 | * Size of this varies, due to varying MAC header length. | |
1134 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1135 | * of the MAC header (device reads on dword boundaries). | |
1136 | * We'll tell device about this padding later. | |
1137 | */ | |
1138 | len = sizeof(struct iwl_tx_cmd) + | |
1139 | sizeof(struct iwl_cmd_header) + hdr_len; | |
1140 | firstlen = (len + 3) & ~3; | |
1141 | ||
1142 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1143 | if (firstlen != len) | |
1144 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1145 | ||
1146 | /* Physical address of this Tx command's header (not MAC header!), | |
1147 | * within command buffer array. */ | |
e13c0c59 | 1148 | txcmd_phys = dma_map_single(bus(trans)->dev, |
47c1b496 EG |
1149 | &dev_cmd->hdr, firstlen, |
1150 | DMA_BIDIRECTIONAL); | |
e13c0c59 | 1151 | if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys))) |
47c1b496 EG |
1152 | return -1; |
1153 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); | |
1154 | dma_unmap_len_set(out_meta, len, firstlen); | |
1155 | ||
1156 | if (!ieee80211_has_morefrags(fc)) { | |
1157 | txq->need_update = 1; | |
1158 | } else { | |
1159 | wait_write_ptr = 1; | |
1160 | txq->need_update = 0; | |
1161 | } | |
1162 | ||
1163 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1164 | * if any (802.11 null frames have no payload). */ | |
1165 | secondlen = skb->len - hdr_len; | |
1166 | if (secondlen > 0) { | |
e13c0c59 | 1167 | phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len, |
47c1b496 | 1168 | secondlen, DMA_TO_DEVICE); |
e13c0c59 EG |
1169 | if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) { |
1170 | dma_unmap_single(bus(trans)->dev, | |
47c1b496 EG |
1171 | dma_unmap_addr(out_meta, mapping), |
1172 | dma_unmap_len(out_meta, len), | |
1173 | DMA_BIDIRECTIONAL); | |
1174 | return -1; | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | /* Attach buffers to TFD */ | |
e13c0c59 | 1179 | iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1); |
47c1b496 | 1180 | if (secondlen > 0) |
e13c0c59 | 1181 | iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr, |
47c1b496 EG |
1182 | secondlen, 0); |
1183 | ||
1184 | scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + | |
1185 | offsetof(struct iwl_tx_cmd, scratch); | |
1186 | ||
1187 | /* take back ownership of DMA buffer to enable update */ | |
e13c0c59 | 1188 | dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1189 | DMA_BIDIRECTIONAL); |
1190 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1191 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1192 | ||
e13c0c59 | 1193 | IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n", |
47c1b496 | 1194 | le16_to_cpu(dev_cmd->hdr.sequence)); |
e13c0c59 EG |
1195 | IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
1196 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); | |
1197 | iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); | |
47c1b496 EG |
1198 | |
1199 | /* Set up entry for this TFD in Tx byte-count array */ | |
96f1f05a | 1200 | iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); |
47c1b496 | 1201 | |
e13c0c59 | 1202 | dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen, |
47c1b496 EG |
1203 | DMA_BIDIRECTIONAL); |
1204 | ||
e13c0c59 | 1205 | trace_iwlwifi_dev_tx(priv(trans), |
47c1b496 EG |
1206 | &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr], |
1207 | sizeof(struct iwl_tfd), | |
1208 | &dev_cmd->hdr, firstlen, | |
1209 | skb->data + hdr_len, secondlen); | |
1210 | ||
1211 | /* Tell device the write index *just past* this latest filled TFD */ | |
1212 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
e13c0c59 EG |
1213 | iwl_txq_update_write_ptr(trans, txq); |
1214 | ||
47c1b496 EG |
1215 | /* |
1216 | * At this point the frame is "transmitted" successfully | |
1217 | * and we will get a TX status notification eventually, | |
1218 | * regardless of the value of ret. "ret" only indicates | |
1219 | * whether or not we should update the write pointer. | |
1220 | */ | |
a0eaad71 | 1221 | if (iwl_queue_space(q) < q->high_mark) { |
47c1b496 EG |
1222 | if (wait_write_ptr) { |
1223 | txq->need_update = 1; | |
e13c0c59 | 1224 | iwl_txq_update_write_ptr(trans, txq); |
47c1b496 | 1225 | } else { |
81a3de1c | 1226 | iwl_stop_queue(trans, txq, "Queue is full"); |
47c1b496 EG |
1227 | } |
1228 | } | |
1229 | return 0; | |
1230 | } | |
1231 | ||
6d8f6eeb | 1232 | static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans) |
56d90f4c EG |
1233 | { |
1234 | /* Remove all resets to allow NIC to operate */ | |
83ed9015 | 1235 | iwl_write32(bus(trans), CSR_RESET, 0); |
56d90f4c EG |
1236 | } |
1237 | ||
e6bb4c9c EG |
1238 | static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) |
1239 | { | |
5a878bf6 EG |
1240 | struct iwl_trans_pcie *trans_pcie = |
1241 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
e6bb4c9c EG |
1242 | int err; |
1243 | ||
0c325769 EG |
1244 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
1245 | ||
1246 | tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long)) | |
1247 | iwl_irq_tasklet, (unsigned long)trans); | |
e6bb4c9c | 1248 | |
0c325769 | 1249 | iwl_alloc_isr_ict(trans); |
e6bb4c9c | 1250 | |
a42a1844 | 1251 | err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED, |
0c325769 | 1252 | DRV_NAME, trans); |
e6bb4c9c | 1253 | if (err) { |
a42a1844 | 1254 | IWL_ERR(trans, "Error allocating IRQ %d\n", trans->irq); |
0c325769 | 1255 | iwl_free_isr_ict(trans); |
e6bb4c9c EG |
1256 | return err; |
1257 | } | |
1258 | ||
5a878bf6 | 1259 | INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish); |
e6bb4c9c EG |
1260 | return 0; |
1261 | } | |
1262 | ||
76bc10fc | 1263 | static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid, |
464021ff EG |
1264 | int txq_id, int ssn, u32 status, |
1265 | struct sk_buff_head *skbs) | |
1266 | { | |
8ad71bef EG |
1267 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1268 | struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id]; | |
a0eaad71 EG |
1269 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
1270 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
464021ff | 1271 | int freed = 0; |
a0eaad71 | 1272 | |
8ad71bef EG |
1273 | txq->time_stamp = jiffies; |
1274 | ||
76bc10fc EG |
1275 | if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE && |
1276 | txq_id != trans_pcie->agg_txq[sta_id][tid])) { | |
1277 | /* | |
1278 | * FIXME: this is a uCode bug which need to be addressed, | |
1279 | * log the information and return for now. | |
1280 | * Since it is can possibly happen very often and in order | |
1281 | * not to fill the syslog, don't use IWL_ERR or IWL_WARN | |
1282 | */ | |
1283 | IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, " | |
1284 | "agg_txq[sta_id[tid] %d", txq_id, | |
1285 | trans_pcie->agg_txq[sta_id][tid]); | |
1286 | return 1; | |
a0eaad71 EG |
1287 | } |
1288 | ||
1289 | if (txq->q.read_ptr != tfd_num) { | |
1daf04b8 EG |
1290 | IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n", |
1291 | txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr, | |
1292 | tfd_num, ssn); | |
464021ff | 1293 | freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs); |
1ba42da4 EG |
1294 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
1295 | (!txq->sched_retry || | |
1296 | status != TX_STATUS_FAIL_PASSIVE_NO_RX)) | |
81a3de1c | 1297 | iwl_wake_queue(trans, txq, "Packets reclaimed"); |
a0eaad71 | 1298 | } |
76bc10fc | 1299 | return 0; |
a0eaad71 EG |
1300 | } |
1301 | ||
6d8f6eeb | 1302 | static void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1303 | { |
a42a1844 EG |
1304 | struct iwl_trans_pcie *trans_pcie = |
1305 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1306 | ||
45c30dba | 1307 | iwl_calib_free_results(trans); |
ae2c30bf | 1308 | iwl_trans_pcie_tx_free(trans); |
a5916977 | 1309 | #ifndef CONFIG_IWLWIFI_IDI |
ae2c30bf | 1310 | iwl_trans_pcie_rx_free(trans); |
a5916977 | 1311 | #endif |
a42a1844 | 1312 | free_irq(trans->irq, trans); |
6d8f6eeb | 1313 | iwl_free_isr_ict(trans); |
a42a1844 EG |
1314 | |
1315 | pci_disable_msi(trans_pcie->pci_dev); | |
1316 | pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base); | |
1317 | pci_release_regions(trans_pcie->pci_dev); | |
1318 | pci_disable_device(trans_pcie->pci_dev); | |
1319 | ||
6d8f6eeb EG |
1320 | trans->shrd->trans = NULL; |
1321 | kfree(trans); | |
34c1b7ba EG |
1322 | } |
1323 | ||
c01a4047 | 1324 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1325 | static int iwl_trans_pcie_suspend(struct iwl_trans *trans) |
1326 | { | |
1327 | /* | |
1328 | * This function is called when system goes into suspend state | |
ade4c649 WYG |
1329 | * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend |
1330 | * function first but since iwlagn_mac_stop() has no knowledge of | |
1331 | * who the caller is, | |
57210f7c EG |
1332 | * it will not call apm_ops.stop() to stop the DMA operation. |
1333 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
1334 | * | |
1335 | * But of course ... if we have configured WoWLAN then we did other | |
1336 | * things already :-) | |
1337 | */ | |
d36120c6 | 1338 | if (!trans->shrd->wowlan) { |
57210f7c | 1339 | iwl_apm_stop(priv(trans)); |
d36120c6 JB |
1340 | } else { |
1341 | iwl_disable_interrupts(trans); | |
1342 | iwl_clear_bit(bus(trans), CSR_GP_CNTRL, | |
1343 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1344 | } | |
57210f7c EG |
1345 | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static int iwl_trans_pcie_resume(struct iwl_trans *trans) | |
1350 | { | |
1351 | bool hw_rfkill = false; | |
1352 | ||
0c325769 | 1353 | iwl_enable_interrupts(trans); |
57210f7c | 1354 | |
83ed9015 | 1355 | if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) & |
57210f7c EG |
1356 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1357 | hw_rfkill = true; | |
1358 | ||
1359 | if (hw_rfkill) | |
1360 | set_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1361 | else | |
1362 | clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); | |
1363 | ||
3e10caeb | 1364 | iwl_set_hw_rfkill_state(priv(trans), hw_rfkill); |
57210f7c EG |
1365 | |
1366 | return 0; | |
1367 | } | |
c01a4047 | 1368 | #endif /* CONFIG_PM_SLEEP */ |
57210f7c | 1369 | |
e13c0c59 | 1370 | static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans, |
81a3de1c EG |
1371 | enum iwl_rxon_context_id ctx, |
1372 | const char *msg) | |
e13c0c59 EG |
1373 | { |
1374 | u8 ac, txq_id; | |
1375 | struct iwl_trans_pcie *trans_pcie = | |
1376 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1377 | ||
1378 | for (ac = 0; ac < AC_NUM; ac++) { | |
1379 | txq_id = trans_pcie->ac_to_queue[ctx][ac]; | |
81a3de1c | 1380 | IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n", |
e13c0c59 | 1381 | ac, |
8ad71bef | 1382 | (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0) |
e13c0c59 | 1383 | ? "stopped" : "awake"); |
81a3de1c | 1384 | iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg); |
e13c0c59 EG |
1385 | } |
1386 | } | |
1387 | ||
81a3de1c EG |
1388 | static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id, |
1389 | const char *msg) | |
e20d4341 | 1390 | { |
8ad71bef EG |
1391 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1392 | ||
81a3de1c | 1393 | iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg); |
e20d4341 EG |
1394 | } |
1395 | ||
5f178cd2 EG |
1396 | #define IWL_FLUSH_WAIT_MS 2000 |
1397 | ||
1398 | static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans) | |
1399 | { | |
8ad71bef | 1400 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
5f178cd2 EG |
1401 | struct iwl_tx_queue *txq; |
1402 | struct iwl_queue *q; | |
1403 | int cnt; | |
1404 | unsigned long now = jiffies; | |
1405 | int ret = 0; | |
1406 | ||
1407 | /* waiting for all the tx frames complete might take a while */ | |
1408 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { | |
1409 | if (cnt == trans->shrd->cmd_queue) | |
1410 | continue; | |
8ad71bef | 1411 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 EG |
1412 | q = &txq->q; |
1413 | while (q->read_ptr != q->write_ptr && !time_after(jiffies, | |
1414 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) | |
1415 | msleep(1); | |
1416 | ||
1417 | if (q->read_ptr != q->write_ptr) { | |
1418 | IWL_ERR(trans, "fail to flush all tx fifo queues\n"); | |
1419 | ret = -ETIMEDOUT; | |
1420 | break; | |
1421 | } | |
1422 | } | |
1423 | return ret; | |
1424 | } | |
1425 | ||
f22be624 EG |
1426 | /* |
1427 | * On every watchdog tick we check (latest) time stamp. If it does not | |
1428 | * change during timeout period and queue is not empty we reset firmware. | |
1429 | */ | |
1430 | static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt) | |
1431 | { | |
8ad71bef EG |
1432 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1433 | struct iwl_tx_queue *txq = &trans_pcie->txq[cnt]; | |
f22be624 EG |
1434 | struct iwl_queue *q = &txq->q; |
1435 | unsigned long timeout; | |
1436 | ||
1437 | if (q->read_ptr == q->write_ptr) { | |
1438 | txq->time_stamp = jiffies; | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | timeout = txq->time_stamp + | |
1443 | msecs_to_jiffies(hw_params(trans).wd_timeout); | |
1444 | ||
1445 | if (time_after(jiffies, timeout)) { | |
1446 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id, | |
1447 | hw_params(trans).wd_timeout); | |
08d1700d | 1448 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
05f8a09f | 1449 | q->read_ptr, q->write_ptr); |
08d1700d EG |
1450 | IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n", |
1451 | iwl_read_prph(bus(trans), SCD_QUEUE_RDPTR(cnt)) | |
1452 | & (TFD_QUEUE_SIZE_MAX - 1), | |
1453 | iwl_read_prph(bus(trans), SCD_QUEUE_WRPTR(cnt))); | |
f22be624 EG |
1454 | return 1; |
1455 | } | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
ff620849 EG |
1460 | static const char *get_fh_string(int cmd) |
1461 | { | |
1462 | switch (cmd) { | |
1463 | IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); | |
1464 | IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1465 | IWL_CMD(FH_RSCSR_CHNL0_WPTR); | |
1466 | IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); | |
1467 | IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); | |
1468 | IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); | |
1469 | IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1470 | IWL_CMD(FH_TSSR_TX_STATUS_REG); | |
1471 | IWL_CMD(FH_TSSR_TX_ERROR_REG); | |
1472 | default: | |
1473 | return "UNKNOWN"; | |
1474 | } | |
1475 | } | |
1476 | ||
1477 | int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display) | |
1478 | { | |
1479 | int i; | |
1480 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1481 | int pos = 0; | |
1482 | size_t bufsz = 0; | |
1483 | #endif | |
1484 | static const u32 fh_tbl[] = { | |
1485 | FH_RSCSR_CHNL0_STTS_WPTR_REG, | |
1486 | FH_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1487 | FH_RSCSR_CHNL0_WPTR, | |
1488 | FH_MEM_RCSR_CHNL0_CONFIG_REG, | |
1489 | FH_MEM_RSSR_SHARED_CTRL_REG, | |
1490 | FH_MEM_RSSR_RX_STATUS_REG, | |
1491 | FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1492 | FH_TSSR_TX_STATUS_REG, | |
1493 | FH_TSSR_TX_ERROR_REG | |
1494 | }; | |
1495 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1496 | if (display) { | |
1497 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1498 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1499 | if (!*buf) | |
1500 | return -ENOMEM; | |
1501 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1502 | "FH register values:\n"); | |
1503 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1504 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1505 | " %34s: 0X%08x\n", | |
1506 | get_fh_string(fh_tbl[i]), | |
1507 | iwl_read_direct32(bus(trans), fh_tbl[i])); | |
1508 | } | |
1509 | return pos; | |
1510 | } | |
1511 | #endif | |
1512 | IWL_ERR(trans, "FH register values:\n"); | |
1513 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | |
1514 | IWL_ERR(trans, " %34s: 0X%08x\n", | |
1515 | get_fh_string(fh_tbl[i]), | |
1516 | iwl_read_direct32(bus(trans), fh_tbl[i])); | |
1517 | } | |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | static const char *get_csr_string(int cmd) | |
1522 | { | |
1523 | switch (cmd) { | |
1524 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1525 | IWL_CMD(CSR_INT_COALESCING); | |
1526 | IWL_CMD(CSR_INT); | |
1527 | IWL_CMD(CSR_INT_MASK); | |
1528 | IWL_CMD(CSR_FH_INT_STATUS); | |
1529 | IWL_CMD(CSR_GPIO_IN); | |
1530 | IWL_CMD(CSR_RESET); | |
1531 | IWL_CMD(CSR_GP_CNTRL); | |
1532 | IWL_CMD(CSR_HW_REV); | |
1533 | IWL_CMD(CSR_EEPROM_REG); | |
1534 | IWL_CMD(CSR_EEPROM_GP); | |
1535 | IWL_CMD(CSR_OTP_GP_REG); | |
1536 | IWL_CMD(CSR_GIO_REG); | |
1537 | IWL_CMD(CSR_GP_UCODE_REG); | |
1538 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1539 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1540 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1541 | IWL_CMD(CSR_LED_REG); | |
1542 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1543 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1544 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1545 | IWL_CMD(CSR_HW_REV_WA_REG); | |
1546 | IWL_CMD(CSR_DBG_HPET_MEM_REG); | |
1547 | default: | |
1548 | return "UNKNOWN"; | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | void iwl_dump_csr(struct iwl_trans *trans) | |
1553 | { | |
1554 | int i; | |
1555 | static const u32 csr_tbl[] = { | |
1556 | CSR_HW_IF_CONFIG_REG, | |
1557 | CSR_INT_COALESCING, | |
1558 | CSR_INT, | |
1559 | CSR_INT_MASK, | |
1560 | CSR_FH_INT_STATUS, | |
1561 | CSR_GPIO_IN, | |
1562 | CSR_RESET, | |
1563 | CSR_GP_CNTRL, | |
1564 | CSR_HW_REV, | |
1565 | CSR_EEPROM_REG, | |
1566 | CSR_EEPROM_GP, | |
1567 | CSR_OTP_GP_REG, | |
1568 | CSR_GIO_REG, | |
1569 | CSR_GP_UCODE_REG, | |
1570 | CSR_GP_DRIVER_REG, | |
1571 | CSR_UCODE_DRV_GP1, | |
1572 | CSR_UCODE_DRV_GP2, | |
1573 | CSR_LED_REG, | |
1574 | CSR_DRAM_INT_TBL_REG, | |
1575 | CSR_GIO_CHICKEN_BITS, | |
1576 | CSR_ANA_PLL_CFG, | |
1577 | CSR_HW_REV_WA_REG, | |
1578 | CSR_DBG_HPET_MEM_REG | |
1579 | }; | |
1580 | IWL_ERR(trans, "CSR values:\n"); | |
1581 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1582 | "CSR_INT_PERIODIC_REG)\n"); | |
1583 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1584 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1585 | get_csr_string(csr_tbl[i]), | |
1586 | iwl_read32(bus(trans), csr_tbl[i])); | |
1587 | } | |
1588 | } | |
1589 | ||
87e5666c EG |
1590 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1591 | /* create and remove of files */ | |
1592 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1593 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c EG |
1594 | &iwl_dbgfs_##name##_ops)) \ |
1595 | return -ENOMEM; \ | |
1596 | } while (0) | |
1597 | ||
1598 | /* file operation */ | |
1599 | #define DEBUGFS_READ_FUNC(name) \ | |
1600 | static ssize_t iwl_dbgfs_##name##_read(struct file *file, \ | |
1601 | char __user *user_buf, \ | |
1602 | size_t count, loff_t *ppos); | |
1603 | ||
1604 | #define DEBUGFS_WRITE_FUNC(name) \ | |
1605 | static ssize_t iwl_dbgfs_##name##_write(struct file *file, \ | |
1606 | const char __user *user_buf, \ | |
1607 | size_t count, loff_t *ppos); | |
1608 | ||
1609 | ||
1610 | static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file) | |
1611 | { | |
1612 | file->private_data = inode->i_private; | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | #define DEBUGFS_READ_FILE_OPS(name) \ | |
1617 | DEBUGFS_READ_FUNC(name); \ | |
1618 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1619 | .read = iwl_dbgfs_##name##_read, \ | |
1620 | .open = iwl_dbgfs_open_file_generic, \ | |
1621 | .llseek = generic_file_llseek, \ | |
1622 | }; | |
1623 | ||
16db88ba EG |
1624 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
1625 | DEBUGFS_WRITE_FUNC(name); \ | |
1626 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1627 | .write = iwl_dbgfs_##name##_write, \ | |
1628 | .open = iwl_dbgfs_open_file_generic, \ | |
1629 | .llseek = generic_file_llseek, \ | |
1630 | }; | |
1631 | ||
87e5666c EG |
1632 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
1633 | DEBUGFS_READ_FUNC(name); \ | |
1634 | DEBUGFS_WRITE_FUNC(name); \ | |
1635 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ | |
1636 | .write = iwl_dbgfs_##name##_write, \ | |
1637 | .read = iwl_dbgfs_##name##_read, \ | |
1638 | .open = iwl_dbgfs_open_file_generic, \ | |
1639 | .llseek = generic_file_llseek, \ | |
1640 | }; | |
1641 | ||
87e5666c EG |
1642 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
1643 | char __user *user_buf, | |
8ad71bef EG |
1644 | size_t count, loff_t *ppos) |
1645 | { | |
5a878bf6 | 1646 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1647 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
87e5666c EG |
1648 | struct iwl_tx_queue *txq; |
1649 | struct iwl_queue *q; | |
1650 | char *buf; | |
1651 | int pos = 0; | |
1652 | int cnt; | |
1653 | int ret; | |
fd656935 | 1654 | const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num; |
87e5666c | 1655 | |
8ad71bef | 1656 | if (!trans_pcie->txq) { |
3e10caeb | 1657 | IWL_ERR(trans, "txq not ready\n"); |
87e5666c EG |
1658 | return -EAGAIN; |
1659 | } | |
1660 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1661 | if (!buf) | |
1662 | return -ENOMEM; | |
1663 | ||
5a878bf6 | 1664 | for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) { |
8ad71bef | 1665 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1666 | q = &txq->q; |
1667 | pos += scnprintf(buf + pos, bufsz - pos, | |
1668 | "hwq %.2d: read=%u write=%u stop=%d" | |
1669 | " swq_id=%#.2x (ac %d/hwq %d)\n", | |
1670 | cnt, q->read_ptr, q->write_ptr, | |
8ad71bef | 1671 | !!test_bit(cnt, trans_pcie->queue_stopped), |
87e5666c EG |
1672 | txq->swq_id, txq->swq_id & 3, |
1673 | (txq->swq_id >> 2) & 0x1f); | |
1674 | if (cnt >= 4) | |
1675 | continue; | |
1676 | /* for the ACs, display the stop count too */ | |
1677 | pos += scnprintf(buf + pos, bufsz - pos, | |
8ad71bef EG |
1678 | " stop-count: %d\n", |
1679 | atomic_read(&trans_pcie->queue_stop_count[cnt])); | |
87e5666c EG |
1680 | } |
1681 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1682 | kfree(buf); | |
1683 | return ret; | |
1684 | } | |
1685 | ||
1686 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
1687 | char __user *user_buf, | |
1688 | size_t count, loff_t *ppos) { | |
5a878bf6 EG |
1689 | struct iwl_trans *trans = file->private_data; |
1690 | struct iwl_trans_pcie *trans_pcie = | |
1691 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1692 | struct iwl_rx_queue *rxq = &trans_pcie->rxq; | |
87e5666c EG |
1693 | char buf[256]; |
1694 | int pos = 0; | |
1695 | const size_t bufsz = sizeof(buf); | |
1696 | ||
1697 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1698 | rxq->read); | |
1699 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1700 | rxq->write); | |
1701 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", | |
1702 | rxq->free_count); | |
1703 | if (rxq->rb_stts) { | |
1704 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1705 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1706 | } else { | |
1707 | pos += scnprintf(buf + pos, bufsz - pos, | |
1708 | "closed_rb_num: Not Allocated\n"); | |
1709 | } | |
1710 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1711 | } | |
1712 | ||
7ff94706 EG |
1713 | static ssize_t iwl_dbgfs_log_event_read(struct file *file, |
1714 | char __user *user_buf, | |
1715 | size_t count, loff_t *ppos) | |
1716 | { | |
1717 | struct iwl_trans *trans = file->private_data; | |
1718 | char *buf; | |
1719 | int pos = 0; | |
1720 | ssize_t ret = -ENOMEM; | |
1721 | ||
6bb78847 | 1722 | ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true); |
7ff94706 EG |
1723 | if (buf) { |
1724 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1725 | kfree(buf); | |
1726 | } | |
1727 | return ret; | |
1728 | } | |
1729 | ||
1730 | static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |
1731 | const char __user *user_buf, | |
1732 | size_t count, loff_t *ppos) | |
1733 | { | |
1734 | struct iwl_trans *trans = file->private_data; | |
1735 | u32 event_log_flag; | |
1736 | char buf[8]; | |
1737 | int buf_size; | |
1738 | ||
1739 | memset(buf, 0, sizeof(buf)); | |
1740 | buf_size = min(count, sizeof(buf) - 1); | |
1741 | if (copy_from_user(buf, user_buf, buf_size)) | |
1742 | return -EFAULT; | |
1743 | if (sscanf(buf, "%d", &event_log_flag) != 1) | |
1744 | return -EFAULT; | |
1745 | if (event_log_flag == 1) | |
6bb78847 | 1746 | iwl_dump_nic_event_log(trans, true, NULL, false); |
7ff94706 EG |
1747 | |
1748 | return count; | |
1749 | } | |
1750 | ||
1f7b6172 EG |
1751 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1752 | char __user *user_buf, | |
1753 | size_t count, loff_t *ppos) { | |
1754 | ||
1755 | struct iwl_trans *trans = file->private_data; | |
1756 | struct iwl_trans_pcie *trans_pcie = | |
1757 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1758 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1759 | ||
1760 | int pos = 0; | |
1761 | char *buf; | |
1762 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1763 | ssize_t ret; | |
1764 | ||
1765 | buf = kzalloc(bufsz, GFP_KERNEL); | |
1766 | if (!buf) { | |
1767 | IWL_ERR(trans, "Can not allocate Buffer\n"); | |
1768 | return -ENOMEM; | |
1769 | } | |
1770 | ||
1771 | pos += scnprintf(buf + pos, bufsz - pos, | |
1772 | "Interrupt Statistics Report:\n"); | |
1773 | ||
1774 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1775 | isr_stats->hw); | |
1776 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1777 | isr_stats->sw); | |
1778 | if (isr_stats->sw || isr_stats->hw) { | |
1779 | pos += scnprintf(buf + pos, bufsz - pos, | |
1780 | "\tLast Restarting Code: 0x%X\n", | |
1781 | isr_stats->err_code); | |
1782 | } | |
1783 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1784 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1785 | isr_stats->sch); | |
1786 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1787 | isr_stats->alive); | |
1788 | #endif | |
1789 | pos += scnprintf(buf + pos, bufsz - pos, | |
1790 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1791 | ||
1792 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1793 | isr_stats->ctkill); | |
1794 | ||
1795 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1796 | isr_stats->wakeup); | |
1797 | ||
1798 | pos += scnprintf(buf + pos, bufsz - pos, | |
1799 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1800 | ||
1801 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1802 | isr_stats->tx); | |
1803 | ||
1804 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1805 | isr_stats->unhandled); | |
1806 | ||
1807 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1808 | kfree(buf); | |
1809 | return ret; | |
1810 | } | |
1811 | ||
1812 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1813 | const char __user *user_buf, | |
1814 | size_t count, loff_t *ppos) | |
1815 | { | |
1816 | struct iwl_trans *trans = file->private_data; | |
1817 | struct iwl_trans_pcie *trans_pcie = | |
1818 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
1819 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; | |
1820 | ||
1821 | char buf[8]; | |
1822 | int buf_size; | |
1823 | u32 reset_flag; | |
1824 | ||
1825 | memset(buf, 0, sizeof(buf)); | |
1826 | buf_size = min(count, sizeof(buf) - 1); | |
1827 | if (copy_from_user(buf, user_buf, buf_size)) | |
1828 | return -EFAULT; | |
1829 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1830 | return -EFAULT; | |
1831 | if (reset_flag == 0) | |
1832 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1833 | ||
1834 | return count; | |
1835 | } | |
1836 | ||
16db88ba EG |
1837 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
1838 | const char __user *user_buf, | |
1839 | size_t count, loff_t *ppos) | |
1840 | { | |
1841 | struct iwl_trans *trans = file->private_data; | |
1842 | char buf[8]; | |
1843 | int buf_size; | |
1844 | int csr; | |
1845 | ||
1846 | memset(buf, 0, sizeof(buf)); | |
1847 | buf_size = min(count, sizeof(buf) - 1); | |
1848 | if (copy_from_user(buf, user_buf, buf_size)) | |
1849 | return -EFAULT; | |
1850 | if (sscanf(buf, "%d", &csr) != 1) | |
1851 | return -EFAULT; | |
1852 | ||
1853 | iwl_dump_csr(trans); | |
1854 | ||
1855 | return count; | |
1856 | } | |
1857 | ||
16db88ba EG |
1858 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
1859 | char __user *user_buf, | |
1860 | size_t count, loff_t *ppos) | |
1861 | { | |
1862 | struct iwl_trans *trans = file->private_data; | |
1863 | char *buf; | |
1864 | int pos = 0; | |
1865 | ssize_t ret = -EFAULT; | |
1866 | ||
1867 | ret = pos = iwl_dump_fh(trans, &buf, true); | |
1868 | if (buf) { | |
1869 | ret = simple_read_from_buffer(user_buf, | |
1870 | count, ppos, buf, pos); | |
1871 | kfree(buf); | |
1872 | } | |
1873 | ||
1874 | return ret; | |
1875 | } | |
1876 | ||
7ff94706 | 1877 | DEBUGFS_READ_WRITE_FILE_OPS(log_event); |
1f7b6172 | 1878 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1879 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1880 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1881 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1882 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1883 | |
1884 | /* | |
1885 | * Create the debugfs files and directories | |
1886 | * | |
1887 | */ | |
1888 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1889 | struct dentry *dir) | |
1890 | { | |
87e5666c EG |
1891 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1892 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
7ff94706 | 1893 | DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR); |
1f7b6172 | 1894 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1895 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1896 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c EG |
1897 | return 0; |
1898 | } | |
1899 | #else | |
1900 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
1901 | struct dentry *dir) | |
1902 | { return 0; } | |
1903 | ||
1904 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
1905 | ||
e6bb4c9c | 1906 | const struct iwl_trans_ops trans_ops_pcie = { |
e6bb4c9c | 1907 | .request_irq = iwl_trans_pcie_request_irq, |
ed6a3803 | 1908 | .fw_alive = iwl_trans_pcie_fw_alive, |
e6bb4c9c EG |
1909 | .start_device = iwl_trans_pcie_start_device, |
1910 | .prepare_card_hw = iwl_trans_pcie_prepare_card_hw, | |
1911 | .stop_device = iwl_trans_pcie_stop_device, | |
48d42c42 | 1912 | |
e13c0c59 | 1913 | .wake_any_queue = iwl_trans_pcie_wake_any_queue, |
48d42c42 | 1914 | |
e6bb4c9c | 1915 | .send_cmd = iwl_trans_pcie_send_cmd, |
c85eb619 | 1916 | |
e6bb4c9c | 1917 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 1918 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 1919 | |
7f01d567 | 1920 | .tx_agg_disable = iwl_trans_pcie_tx_agg_disable, |
288712a6 | 1921 | .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc, |
c91bd124 | 1922 | .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, |
34c1b7ba | 1923 | |
e6bb4c9c | 1924 | .kick_nic = iwl_trans_pcie_kick_nic, |
1e89cbac | 1925 | |
e6bb4c9c | 1926 | .free = iwl_trans_pcie_free, |
e20d4341 | 1927 | .stop_queue = iwl_trans_pcie_stop_queue, |
87e5666c EG |
1928 | |
1929 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, | |
5f178cd2 EG |
1930 | |
1931 | .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty, | |
f22be624 | 1932 | .check_stuck_queue = iwl_trans_pcie_check_stuck_queue, |
5f178cd2 | 1933 | |
c01a4047 | 1934 | #ifdef CONFIG_PM_SLEEP |
57210f7c EG |
1935 | .suspend = iwl_trans_pcie_suspend, |
1936 | .resume = iwl_trans_pcie_resume, | |
c01a4047 | 1937 | #endif |
e6bb4c9c | 1938 | }; |
a42a1844 EG |
1939 | |
1940 | /* TODO: remove this hack - will be possible when all the io{write/read} ops | |
1941 | * will be done through the transport | |
1942 | */ | |
1943 | struct iwl_pci_bus { | |
1944 | /* basic pci-network driver stuff */ | |
1945 | struct pci_dev *pci_dev; | |
1946 | ||
1947 | /* pci hardware address support */ | |
1948 | void __iomem *hw_base; | |
1949 | }; | |
1950 | ||
1951 | #define IWL_BUS_GET_PCI_BUS(_iwl_bus) \ | |
1952 | ((struct iwl_pci_bus *) ((_iwl_bus)->bus_specific)) | |
1953 | ||
1954 | /* PCI registers */ | |
1955 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
1956 | ||
1957 | struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd, | |
1958 | struct pci_dev *pdev, | |
1959 | const struct pci_device_id *ent) | |
1960 | { | |
1961 | struct iwl_pci_bus *iwl_pci_bus = IWL_BUS_GET_PCI_BUS(shrd->bus); | |
1962 | struct iwl_trans_pcie *trans_pcie; | |
1963 | struct iwl_trans *trans; | |
1964 | u16 pci_cmd; | |
1965 | int err; | |
1966 | ||
1967 | trans = kzalloc(sizeof(struct iwl_trans) + | |
1968 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); | |
1969 | ||
1970 | if (WARN_ON(!trans)) | |
1971 | return NULL; | |
1972 | ||
1973 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1974 | ||
1975 | trans->ops = &trans_ops_pcie; | |
1976 | trans->shrd = shrd; | |
1977 | trans_pcie->trans = trans; | |
1978 | spin_lock_init(&trans->hcmd_lock); | |
1979 | ||
1980 | /* W/A - seems to solve weird behavior. We need to remove this if we | |
1981 | * don't want to stay in L1 all the time. This wastes a lot of power */ | |
1982 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
1983 | PCIE_LINK_STATE_CLKPM); | |
1984 | ||
1985 | if (pci_enable_device(pdev)) { | |
1986 | err = -ENODEV; | |
1987 | goto out_no_pci; | |
1988 | } | |
1989 | ||
1990 | pci_set_master(pdev); | |
1991 | ||
1992 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1993 | if (!err) | |
1994 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
1995 | if (err) { | |
1996 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1997 | if (!err) | |
1998 | err = pci_set_consistent_dma_mask(pdev, | |
1999 | DMA_BIT_MASK(32)); | |
2000 | /* both attempts failed: */ | |
2001 | if (err) { | |
2002 | dev_printk(KERN_ERR, &pdev->dev, | |
2003 | "No suitable DMA available.\n"); | |
2004 | goto out_pci_disable_device; | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | err = pci_request_regions(pdev, DRV_NAME); | |
2009 | if (err) { | |
2010 | dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed"); | |
2011 | goto out_pci_disable_device; | |
2012 | } | |
2013 | ||
2014 | trans_pcie->hw_base = pci_iomap(pdev, 0, 0); | |
2015 | if (!trans_pcie->hw_base) { | |
2016 | dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed"); | |
2017 | err = -ENODEV; | |
2018 | goto out_pci_release_regions; | |
2019 | } | |
2020 | ||
2021 | /* TODO: remove this hack */ | |
2022 | iwl_pci_bus->hw_base = trans_pcie->hw_base; | |
2023 | ||
2024 | dev_printk(KERN_INFO, &pdev->dev, | |
2025 | "pci_resource_len = 0x%08llx\n", | |
2026 | (unsigned long long) pci_resource_len(pdev, 0)); | |
2027 | dev_printk(KERN_INFO, &pdev->dev, | |
2028 | "pci_resource_base = %p\n", trans_pcie->hw_base); | |
2029 | ||
2030 | dev_printk(KERN_INFO, &pdev->dev, | |
2031 | "HW Revision ID = 0x%X\n", pdev->revision); | |
2032 | ||
2033 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2034 | * PCI Tx retries from interfering with C3 CPU state */ | |
2035 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2036 | ||
2037 | err = pci_enable_msi(pdev); | |
2038 | if (err) | |
2039 | dev_printk(KERN_ERR, &pdev->dev, | |
2040 | "pci_enable_msi failed(0X%x)", err); | |
2041 | ||
2042 | trans->dev = &pdev->dev; | |
2043 | trans->irq = pdev->irq; | |
2044 | trans_pcie->pci_dev = pdev; | |
2045 | ||
2046 | /* TODO: Move this away, not needed if not MSI */ | |
2047 | /* enable rfkill interrupt: hw bug w/a */ | |
2048 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2049 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2050 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2051 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2052 | } | |
2053 | ||
2054 | return trans; | |
2055 | ||
2056 | out_pci_release_regions: | |
2057 | pci_release_regions(pdev); | |
2058 | out_pci_disable_device: | |
2059 | pci_disable_device(pdev); | |
2060 | out_no_pci: | |
2061 | kfree(trans); | |
2062 | return NULL; | |
2063 | } | |
2064 |