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iwlwifi: mvm: don't set AP STA to EINVAL
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
CommitLineData
c85eb619
EG		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
c85eb619
EG		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
410dc5aa 25 * in the file called COPYING.
c85eb619
EG		 26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
51368bf7 33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
c85eb619
EG		 34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
a42a1844
EG		 63#include <linux/pci.h>
64#include <linux/pci-aspm.h>
e6bb4c9c 65#include <linux/interrupt.h>
87e5666c 66#include <linux/debugfs.h>
cf614297 67#include <linux/sched.h>
6d8f6eeb
EG		 68#include <linux/bitops.h>
69#include <linux/gfp.h>
e6bb4c9c 70
82575102 71#include "iwl-drv.h"
c85eb619 72#include "iwl-trans.h"
522376d2
EG		 73#include "iwl-csr.h"
74#include "iwl-prph.h"
7a10e3e4 75#include "iwl-agn-hw.h"
6468a01a 76#include "internal.h"
0439bb62 77
a812cba9
AB		 78static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
79{
80 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
81 ((reg & 0x0000ffff) | (2 << 28)));
82 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
83}
84
85static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
86{
87 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
88 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
89 ((reg & 0x0000ffff) | (3 << 28)));
90}
91
ddaf5a5b 92static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
392f8b78 93{
ddaf5a5b
JB		 94 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
95 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
96 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
97 ~APMG_PS_CTRL_MSK_PWR_SRC);
98 else
99 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
100 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
101 ~APMG_PS_CTRL_MSK_PWR_SRC);
392f8b78
EG		 102}
103
af634bee
EG		 104/* PCI registers */
105#define PCI_CFG_RETRY_TIMEOUT 0x041
af634bee 106
7afe3705 107static void iwl_pcie_apm_config(struct iwl_trans *trans)
af634bee 108{
20d3b647 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
7afe3705 110 u16 lctl;
af634bee 111
af634bee
EG		 112 /*
113 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
114 * Check if BIOS (or OS) enabled L1-ASPM on this device.
115 * If so (likely), disable L0S, so device moves directly L0->L1;
116 * costs negligible amount of power savings.
117 * If not (unlikely), enable L0S, so there is at least some
118 * power savings, even without L1.
119 */
7afe3705 120 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
438a0f0a 121 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
af634bee
EG		 122 /* L1-ASPM enabled; disable(!) L0S */
123 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
6a4b09f8 124 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
af634bee
EG		 125 } else {
126 /* L1-ASPM disabled; enable(!) L0S */
127 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
6a4b09f8 128 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
af634bee 129 }
438a0f0a 130 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
af634bee
EG		 131}
132
a6c684ee
EG		 133/*
134 * Start up NIC's basic functionality after it has been reset
7afe3705 135 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
a6c684ee
EG		 136 * NOTE: This does not load uCode nor start the embedded processor
137 */
7afe3705 138static int iwl_pcie_apm_init(struct iwl_trans *trans)
a6c684ee
EG		 139{
140 int ret = 0;
141 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
142
143 /*
144 * Use "set_bit" below rather than "write", to preserve any hardware
145 * bits already set by default after reset.
146 */
147
148 /* Disable L0S exit timer (platform NMI Work/Around) */
e4a9f8ce
EH		 149 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
150 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
151 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
a6c684ee
EG		 152
153 /*
154 * Disable L0s without affecting L1;
155 * don't wait for ICH L0s (ICH bug W/A)
156 */
157 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
20d3b647 158 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
a6c684ee
EG		 159
160 /* Set FH wait threshold to maximum (HW error during stress W/A) */
161 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
162
163 /*
164 * Enable HAP INTA (interrupt from management bus) to
165 * wake device's PCI Express link L1a -> L0s
166 */
167 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 168 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
a6c684ee 169
7afe3705 170 iwl_pcie_apm_config(trans);
a6c684ee
EG		 171
172 /* Configure analog phase-lock-loop before activating to D0A */
035f7ff2 173 if (trans->cfg->base_params->pll_cfg_val)
a6c684ee 174 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
035f7ff2 175 trans->cfg->base_params->pll_cfg_val);
a6c684ee
EG		 176
177 /*
178 * Set "initialization complete" bit to move adapter from
179 * D0U* --> D0A* (powered-up active) state.
180 */
181 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
182
183 /*
184 * Wait for clock stabilization; once stabilized, access to
185 * device-internal resources is supported, e.g. iwl_write_prph()
186 * and accesses to uCode SRAM.
187 */
188 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
20d3b647
JB		 189 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
190 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
a6c684ee
EG		 191 if (ret < 0) {
192 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
193 goto out;
194 }
195
2d93aee1
EG		 196 if (trans->cfg->host_interrupt_operation_mode) {
197 /*
198 * This is a bit of an abuse - This is needed for 7260 / 3160
199 * only check host_interrupt_operation_mode even if this is
200 * not related to host_interrupt_operation_mode.
201 *
202 * Enable the oscillator to count wake up time for L1 exit. This
203 * consumes slightly more power (100uA) - but allows to be sure
204 * that we wake up from L1 on time.
205 *
206 * This looks weird: read twice the same register, discard the
207 * value, set a bit, and yet again, read that same register
208 * just to discard the value. But that's the way the hardware
209 * seems to like it.
210 */
211 iwl_read_prph(trans, OSC_CLK);
212 iwl_read_prph(trans, OSC_CLK);
213 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
214 iwl_read_prph(trans, OSC_CLK);
215 iwl_read_prph(trans, OSC_CLK);
216 }
217
a6c684ee
EG		 218 /*
219 * Enable DMA clock and wait for it to stabilize.
220 *
3073d8c0
EH		 221 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
222 * bits do not disable clocks. This preserves any hardware
223 * bits already set by default in "CLK_CTRL_REG" after reset.
a6c684ee 224 */
3073d8c0
EH		 225 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
226 iwl_write_prph(trans, APMG_CLK_EN_REG,
227 APMG_CLK_VAL_DMA_CLK_RQT);
228 udelay(20);
229
230 /* Disable L1-Active */
231 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
232 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
233
234 /* Clear the interrupt in APMG if the NIC is in RFKILL */
235 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
236 APMG_RTC_INT_STT_RFKILL);
237 }
889b1696 238
eb7ff77e 239 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
a6c684ee
EG		 240
241out:
242 return ret;
243}
244
a812cba9
AB		 245/*
246 * Enable LP XTAL to avoid HW bug where device may consume much power if
247 * FW is not loaded after device reset. LP XTAL is disabled by default
248 * after device HW reset. Do it only if XTAL is fed by internal source.
249 * Configure device's "persistence" mode to avoid resetting XTAL again when
250 * SHRD_HW_RST occurs in S3.
251 */
252static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
253{
254 int ret;
255 u32 apmg_gp1_reg;
256 u32 apmg_xtal_cfg_reg;
257 u32 dl_cfg_reg;
258
259 /* Force XTAL ON */
260 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
261 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
262
263 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
264 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
265
266 udelay(10);
267
268 /*
269 * Set "initialization complete" bit to move adapter from
270 * D0U* --> D0A* (powered-up active) state.
271 */
272 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
273
274 /*
275 * Wait for clock stabilization; once stabilized, access to
276 * device-internal resources is possible.
277 */
278 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
279 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
280 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
281 25000);
282 if (WARN_ON(ret < 0)) {
283 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
284 /* Release XTAL ON request */
285 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
286 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
287 return;
288 }
289
290 /*
291 * Clear "disable persistence" to avoid LP XTAL resetting when
292 * SHRD_HW_RST is applied in S3.
293 */
294 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
295 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
296
297 /*
298 * Force APMG XTAL to be active to prevent its disabling by HW
299 * caused by APMG idle state.
300 */
301 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
302 SHR_APMG_XTAL_CFG_REG);
303 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
304 apmg_xtal_cfg_reg |
305 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
306
307 /*
308 * Reset entire device again - do controller reset (results in
309 * SHRD_HW_RST). Turn MAC off before proceeding.
310 */
311 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
312
313 udelay(10);
314
315 /* Enable LP XTAL by indirect access through CSR */
316 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
317 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
318 SHR_APMG_GP1_WF_XTAL_LP_EN |
319 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
320
321 /* Clear delay line clock power up */
322 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
323 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
324 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
325
326 /*
327 * Enable persistence mode to avoid LP XTAL resetting when
328 * SHRD_HW_RST is applied in S3.
329 */
330 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
331 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
332
333 /*
334 * Clear "initialization complete" bit to move adapter from
335 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
336 */
337 iwl_clear_bit(trans, CSR_GP_CNTRL,
338 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
339
340 /* Activates XTAL resources monitor */
341 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
342 CSR_MONITOR_XTAL_RESOURCES);
343
344 /* Release XTAL ON request */
345 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
346 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
347 udelay(10);
348
349 /* Release APMG XTAL */
350 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
351 apmg_xtal_cfg_reg &
352 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
353}
354
7afe3705 355static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
cc56feb2
EG		 356{
357 int ret = 0;
358
359 /* stop device's busmaster DMA activity */
360 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
361
362 ret = iwl_poll_bit(trans, CSR_RESET,
20d3b647
JB		 363 CSR_RESET_REG_FLAG_MASTER_DISABLED,
364 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
cc56feb2
EG		 365 if (ret)
366 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
367
368 IWL_DEBUG_INFO(trans, "stop master\n");
369
370 return ret;
371}
372
7afe3705 373static void iwl_pcie_apm_stop(struct iwl_trans *trans)
cc56feb2
EG		 374{
375 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
376
eb7ff77e 377 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
cc56feb2
EG		 378
379 /* Stop device's DMA activity */
7afe3705 380 iwl_pcie_apm_stop_master(trans);
cc56feb2 381
a812cba9
AB		 382 if (trans->cfg->lp_xtal_workaround) {
383 iwl_pcie_apm_lp_xtal_enable(trans);
384 return;
385 }
386
cc56feb2
EG		 387 /* Reset the entire device */
388 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
389
390 udelay(10);
391
392 /*
393 * Clear "initialization complete" bit to move adapter from
394 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
395 */
396 iwl_clear_bit(trans, CSR_GP_CNTRL,
397 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
398}
399
7afe3705 400static int iwl_pcie_nic_init(struct iwl_trans *trans)
392f8b78 401{
7b11488f 402 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
392f8b78
EG		 403
404 /* nic_init */
7b70bd63 405 spin_lock(&trans_pcie->irq_lock);
7afe3705 406 iwl_pcie_apm_init(trans);
392f8b78 407
7b70bd63 408 spin_unlock(&trans_pcie->irq_lock);
392f8b78 409
3073d8c0
EH		 410 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
411 iwl_pcie_set_pwr(trans, false);
392f8b78 412
ecdb975c 413 iwl_op_mode_nic_config(trans->op_mode);
392f8b78
EG		 414
415 /* Allocate the RX queue, or reset if it is already allocated */
9805c446 416 iwl_pcie_rx_init(trans);
392f8b78
EG		 417
418 /* Allocate or reset and init all Tx and Command queues */
f02831be 419 if (iwl_pcie_tx_init(trans))
392f8b78
EG		 420 return -ENOMEM;
421
035f7ff2 422 if (trans->cfg->base_params->shadow_reg_enable) {
392f8b78 423 /* enable shadow regs in HW */
20d3b647 424 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
d38069d1 425 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
392f8b78
EG		 426 }
427
392f8b78
EG		 428 return 0;
429}
430
431#define HW_READY_TIMEOUT (50)
432
433/* Note: returns poll_bit return value, which is >= 0 if success */
7afe3705 434static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
392f8b78
EG		 435{
436 int ret;
437
1042db2a 438 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 439 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
392f8b78
EG		 440
441 /* See if we got it */
1042db2a 442 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647
JB		 443 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
444 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
445 HW_READY_TIMEOUT);
392f8b78 446
6d8f6eeb 447 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
392f8b78
EG		 448 return ret;
449}
450
451/* Note: returns standard 0/-ERROR code */
7afe3705 452static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
392f8b78
EG		 453{
454 int ret;
289e5501 455 int t = 0;
392f8b78 456
6d8f6eeb 457 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
392f8b78 458
7afe3705 459 ret = iwl_pcie_set_hw_ready(trans);
ebb7678d 460 /* If the card is ready, exit 0 */
392f8b78
EG		 461 if (ret >= 0)
462 return 0;
463
464 /* If HW is not ready, prepare the conditions to check again */
1042db2a 465 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
20d3b647 466 CSR_HW_IF_CONFIG_REG_PREPARE);
392f8b78 467
289e5501 468 do {
7afe3705 469 ret = iwl_pcie_set_hw_ready(trans);
289e5501
EG		 470 if (ret >= 0)
471 return 0;
392f8b78 472
289e5501
EG		 473 usleep_range(200, 1000);
474 t += 200;
475 } while (t < 150000);
392f8b78 476
392f8b78
EG		 477 return ret;
478}
479
cf614297
EG		 480/*
481 * ucode
482 */
7afe3705 483static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
83f84d7b 484 dma_addr_t phy_addr, u32 byte_cnt)
cf614297 485{
13df1aab 486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
cf614297
EG		 487 int ret;
488
13df1aab 489 trans_pcie->ucode_write_complete = false;
cf614297
EG		 490
491 iwl_write_direct32(trans,
20d3b647
JB		 492 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
493 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
cf614297
EG		 494
495 iwl_write_direct32(trans,
20d3b647
JB		 496 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
497 dst_addr);
cf614297
EG		 498
499 iwl_write_direct32(trans,
83f84d7b
JB		 500 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
501 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
cf614297
EG		 502
503 iwl_write_direct32(trans,
20d3b647
JB		 504 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
505 (iwl_get_dma_hi_addr(phy_addr)
506 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
cf614297
EG		 507
508 iwl_write_direct32(trans,
20d3b647
JB		 509 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
510 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
511 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
512 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
cf614297
EG		 513
514 iwl_write_direct32(trans,
20d3b647
JB		 515 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
516 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
517 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
518 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
cf614297 519
13df1aab
JB		 520 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
521 trans_pcie->ucode_write_complete, 5 * HZ);
cf614297 522 if (!ret) {
83f84d7b 523 IWL_ERR(trans, "Failed to load firmware chunk!\n");
cf614297
EG		 524 return -ETIMEDOUT;
525 }
526
527 return 0;
528}
529
7afe3705 530static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
83f84d7b 531 const struct fw_desc *section)
cf614297 532{
83f84d7b
JB		 533 u8 *v_addr;
534 dma_addr_t p_addr;
c571573a 535 u32 offset, chunk_sz = section->len;
cf614297
EG		 536 int ret = 0;
537
83f84d7b
JB		 538 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
539 section_num);
540
c571573a
EG		 541 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
542 GFP_KERNEL | __GFP_NOWARN);
543 if (!v_addr) {
544 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
545 chunk_sz = PAGE_SIZE;
546 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
547 &p_addr, GFP_KERNEL);
548 if (!v_addr)
549 return -ENOMEM;
550 }
83f84d7b 551
c571573a 552 for (offset = 0; offset < section->len; offset += chunk_sz) {
83f84d7b
JB		 553 u32 copy_size;
554
c571573a 555 copy_size = min_t(u32, chunk_sz, section->len - offset);
cf614297 556
83f84d7b 557 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
7afe3705
EG		 558 ret = iwl_pcie_load_firmware_chunk(trans,
559 section->offset + offset,
560 p_addr, copy_size);
83f84d7b
JB		 561 if (ret) {
562 IWL_ERR(trans,
563 "Could not load the [%d] uCode section\n",
564 section_num);
565 break;
6dfa8d01 566 }
83f84d7b
JB		 567 }
568
c571573a 569 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
83f84d7b
JB		 570 return ret;
571}
572
189fa2fa
EH		 573static int iwl_pcie_load_cpu_secured_sections(struct iwl_trans *trans,
574 const struct fw_img *image,
034846cf
EH		 575 int cpu,
576 int *first_ucode_section)
e2d6f4e7
EH		 577{
578 int shift_param;
189fa2fa 579 int i, ret = 0;
034846cf 580 u32 last_read_idx = 0;
e2d6f4e7
EH		 581
582 if (cpu == 1) {
583 shift_param = 0;
034846cf 584 *first_ucode_section = 0;
e2d6f4e7
EH		 585 } else {
586 shift_param = 16;
034846cf 587 (*first_ucode_section)++;
e2d6f4e7
EH		 588 }
589
034846cf
EH		 590 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
591 last_read_idx = i;
592
593 if (!image->sec[i].data ||
594 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
595 IWL_DEBUG_FW(trans,
596 "Break since Data not valid or Empty section, sec = %d\n",
597 i);
189fa2fa 598 break;
034846cf
EH		 599 }
600
601 if (i == (*first_ucode_section) + 1)
189fa2fa
EH		 602 /* set CPU to started */
603 iwl_set_bits_prph(trans,
604 CSR_UCODE_LOAD_STATUS_ADDR,
605 LMPM_CPU_HDRS_LOADING_COMPLETED
606 << shift_param);
e2d6f4e7 607
189fa2fa
EH		 608 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
609 if (ret)
610 return ret;
e2d6f4e7 611 }
189fa2fa
EH		 612 /* image loading complete */
613 iwl_set_bits_prph(trans,
614 CSR_UCODE_LOAD_STATUS_ADDR,
615 LMPM_CPU_UCODE_LOADING_COMPLETED << shift_param);
e2d6f4e7 616
034846cf
EH		 617 *first_ucode_section = last_read_idx;
618
189fa2fa
EH		 619 return 0;
620}
e2d6f4e7 621
189fa2fa
EH		 622static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
623 const struct fw_img *image,
034846cf
EH		 624 int cpu,
625 int *first_ucode_section)
189fa2fa
EH		 626{
627 int shift_param;
189fa2fa 628 int i, ret = 0;
034846cf 629 u32 last_read_idx = 0;
189fa2fa
EH		 630
631 if (cpu == 1) {
632 shift_param = 0;
034846cf 633 *first_ucode_section = 0;
189fa2fa
EH		 634 } else {
635 shift_param = 16;
034846cf 636 (*first_ucode_section)++;
189fa2fa
EH		 637 }
638
034846cf
EH		 639 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
640 last_read_idx = i;
641
642 if (!image->sec[i].data ||
643 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
644 IWL_DEBUG_FW(trans,
645 "Break since Data not valid or Empty section, sec = %d\n",
646 i);
189fa2fa 647 break;
034846cf
EH		 648 }
649
189fa2fa
EH		 650 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
651 if (ret)
652 return ret;
e2d6f4e7
EH		 653 }
654
189fa2fa
EH		 655 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
656 iwl_set_bits_prph(trans,
657 CSR_UCODE_LOAD_STATUS_ADDR,
658 (LMPM_CPU_UCODE_LOADING_COMPLETED |
659 LMPM_CPU_HDRS_LOADING_COMPLETED |
660 LMPM_CPU_UCODE_LOADING_STARTED) <<
661 shift_param);
662
034846cf
EH		 663 *first_ucode_section = last_read_idx;
664
e2d6f4e7
EH		 665 return 0;
666}
667
7afe3705 668static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
0692fe41 669 const struct fw_img *image)
cf614297 670{
189fa2fa 671 int ret = 0;
034846cf 672 int first_ucode_section;
cf614297 673
e2d6f4e7
EH		 674 IWL_DEBUG_FW(trans,
675 "working with %s image\n",
676 image->is_secure ? "Secured" : "Non Secured");
677 IWL_DEBUG_FW(trans,
678 "working with %s CPU\n",
679 image->is_dual_cpus ? "Dual" : "Single");
680
681 /* configure the ucode to be ready to get the secured image */
682 if (image->is_secure) {
683 /* set secure boot inspector addresses */
189fa2fa
EH		 684 iwl_write_prph(trans,
685 LMPM_SECURE_INSPECTOR_CODE_ADDR,
686 LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE);
e2d6f4e7 687
189fa2fa
EH		 688 iwl_write_prph(trans,
689 LMPM_SECURE_INSPECTOR_DATA_ADDR,
690 LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE);
e2d6f4e7 691
189fa2fa
EH		 692 /* set CPU1 header address */
693 iwl_write_prph(trans,
694 LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR,
695 LMPM_SECURE_CPU1_HDR_MEM_SPACE);
696
697 /* load to FW the binary Secured sections of CPU1 */
034846cf
EH		 698 ret = iwl_pcie_load_cpu_secured_sections(trans, image, 1,
699 &first_ucode_section);
2d1c0044
JB		 700 if (ret)
701 return ret;
cf614297 702
189fa2fa
EH		 703 } else {
704 /* load to FW the binary Non secured sections of CPU1 */
034846cf
EH		 705 ret = iwl_pcie_load_cpu_sections(trans, image, 1,
706 &first_ucode_section);
e2d6f4e7
EH		 707 if (ret)
708 return ret;
e2d6f4e7
EH		 709 }
710
711 if (image->is_dual_cpus) {
189fa2fa
EH		 712 /* set CPU2 header address */
713 iwl_write_prph(trans,
714 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
715 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
e2d6f4e7 716
189fa2fa
EH		 717 /* load to FW the binary sections of CPU2 */
718 if (image->is_secure)
034846cf
EH		 719 ret = iwl_pcie_load_cpu_secured_sections(
720 trans, image, 2,
721 &first_ucode_section);
189fa2fa 722 else
034846cf
EH		 723 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
724 &first_ucode_section);
189fa2fa
EH		 725 if (ret)
726 return ret;
e2d6f4e7 727 }
cf614297 728
e12ba844
EH		 729 /* release CPU reset */
730 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
731 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
732 else
733 iwl_write32(trans, CSR_RESET, 0);
734
189fa2fa
EH		 735 if (image->is_secure) {
736 /* wait for image verification to complete */
737 ret = iwl_poll_prph_bit(trans,
738 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR,
739 LMPM_SECURE_BOOT_STATUS_SUCCESS,
740 LMPM_SECURE_BOOT_STATUS_SUCCESS,
741 LMPM_SECURE_TIME_OUT);
742
743 if (ret < 0) {
744 IWL_ERR(trans, "Time out on secure boot process\n");
745 return ret;
746 }
747 }
748
cf614297
EG		 749 return 0;
750}
751
0692fe41 752static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
6ae02f3e 753 const struct fw_img *fw, bool run_in_rfkill)
392f8b78
EG		 754{
755 int ret;
c9eec95c 756 bool hw_rfkill;
392f8b78 757
496bab39 758 /* This may fail if AMT took ownership of the device */
7afe3705 759 if (iwl_pcie_prepare_card_hw(trans)) {
6d8f6eeb 760 IWL_WARN(trans, "Exit HW not ready\n");
392f8b78
EG		 761 return -EIO;
762 }
763
8c46bb70
EG		 764 iwl_enable_rfkill_int(trans);
765
392f8b78 766 /* If platform's RF_KILL switch is NOT set to KILL */
8d425517 767 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 768 if (hw_rfkill)
eb7ff77e 769 set_bit(STATUS_RFKILL, &trans->status);
4620020b 770 else
eb7ff77e 771 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 772 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
6ae02f3e 773 if (hw_rfkill && !run_in_rfkill)
392f8b78 774 return -ERFKILL;
392f8b78 775
1042db2a 776 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
392f8b78 777
7afe3705 778 ret = iwl_pcie_nic_init(trans);
392f8b78 779 if (ret) {
6d8f6eeb 780 IWL_ERR(trans, "Unable to init nic\n");
392f8b78
EG		 781 return ret;
782 }
783
784 /* make sure rfkill handshake bits are cleared */
1042db2a
EG		 785 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
786 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
392f8b78
EG		 787 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
788
789 /* clear (again), then enable host interrupts */
1042db2a 790 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
6d8f6eeb 791 iwl_enable_interrupts(trans);
392f8b78
EG		 792
793 /* really make sure rfkill handshake bits are cleared */
1042db2a
EG		 794 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
795 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
392f8b78 796
cf614297 797 /* Load the given image to the HW */
7afe3705 798 return iwl_pcie_load_given_ucode(trans, fw);
b3c2ce13
EG		 799}
800
adca1235 801static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
ed6a3803 802{
990aa6d7 803 iwl_pcie_reset_ict(trans);
f02831be 804 iwl_pcie_tx_start(trans, scd_addr);
c170b867
EG		 805}
806
43e58856 807static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
ae2c30bf 808{
43e58856 809 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3dc3374f
EG		 810 bool hw_rfkill, was_hw_rfkill;
811
812 was_hw_rfkill = iwl_is_rfkill_set(trans);
ae2c30bf 813
43e58856 814 /* tell the device to stop sending interrupts */
7b70bd63 815 spin_lock(&trans_pcie->irq_lock);
ae2c30bf 816 iwl_disable_interrupts(trans);
7b70bd63 817 spin_unlock(&trans_pcie->irq_lock);
ae2c30bf 818
ab6cf8e8 819 /* device going down, Stop using ICT table */
990aa6d7 820 iwl_pcie_disable_ict(trans);
ab6cf8e8
EG		 821
822 /*
823 * If a HW restart happens during firmware loading,
824 * then the firmware loading might call this function
825 * and later it might be called again due to the
826 * restart. So don't process again if the device is
827 * already dead.
828 */
eb7ff77e 829 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
f02831be 830 iwl_pcie_tx_stop(trans);
9805c446 831 iwl_pcie_rx_stop(trans);
6379103e 832
ab6cf8e8 833 /* Power-down device's busmaster DMA clocks */
1042db2a 834 iwl_write_prph(trans, APMG_CLK_DIS_REG,
ab6cf8e8
EG		 835 APMG_CLK_VAL_DMA_CLK_RQT);
836 udelay(5);
837 }
838
839 /* Make sure (redundant) we've released our request to stay awake */
1042db2a 840 iwl_clear_bit(trans, CSR_GP_CNTRL,
20d3b647 841 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ab6cf8e8
EG		 842
843 /* Stop the device, and put it in low power state */
7afe3705 844 iwl_pcie_apm_stop(trans);
43e58856
EG		 845
846 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
847 * Clean again the interrupt here
848 */
7b70bd63 849 spin_lock(&trans_pcie->irq_lock);
43e58856 850 iwl_disable_interrupts(trans);
7b70bd63 851 spin_unlock(&trans_pcie->irq_lock);
43e58856 852
43e58856 853 /* stop and reset the on-board processor */
1042db2a 854 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
74fda971
DF		 855
856 /* clear all status bits */
eb7ff77e
AN		 857 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
858 clear_bit(STATUS_INT_ENABLED, &trans->status);
859 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
860 clear_bit(STATUS_TPOWER_PMI, &trans->status);
861 clear_bit(STATUS_RFKILL, &trans->status);
a4082843
AN		 862
863 /*
864 * Even if we stop the HW, we still want the RF kill
865 * interrupt
866 */
867 iwl_enable_rfkill_int(trans);
868
869 /*
870 * Check again since the RF kill state may have changed while
871 * all the interrupts were disabled, in this case we couldn't
872 * receive the RF kill interrupt and update the state in the
873 * op_mode.
3dc3374f
EG		 874 * Don't call the op_mode if the rkfill state hasn't changed.
875 * This allows the op_mode to call stop_device from the rfkill
876 * notification without endless recursion. Under very rare
877 * circumstances, we might have a small recursion if the rfkill
878 * state changed exactly now while we were called from stop_device.
879 * This is very unlikely but can happen and is supported.
a4082843
AN		 880 */
881 hw_rfkill = iwl_is_rfkill_set(trans);
882 if (hw_rfkill)
eb7ff77e 883 set_bit(STATUS_RFKILL, &trans->status);
a4082843 884 else
eb7ff77e 885 clear_bit(STATUS_RFKILL, &trans->status);
3dc3374f 886 if (hw_rfkill != was_hw_rfkill)
14cfca71
JB		 887 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
888}
889
890void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
891{
892 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
893 iwl_trans_pcie_stop_device(trans);
ab6cf8e8
EG		 894}
895
debff618 896static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
2dd4f9f7 897{
2dd4f9f7 898 iwl_disable_interrupts(trans);
debff618
JB		 899
900 /*
901 * in testing mode, the host stays awake and the
902 * hardware won't be reset (not even partially)
903 */
904 if (test)
905 return;
906
ddaf5a5b
JB		 907 iwl_pcie_disable_ict(trans);
908
2dd4f9f7
JB		 909 iwl_clear_bit(trans, CSR_GP_CNTRL,
910 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ddaf5a5b
JB		 911 iwl_clear_bit(trans, CSR_GP_CNTRL,
912 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
913
914 /*
915 * reset TX queues -- some of their registers reset during S3
916 * so if we don't reset everything here the D3 image would try
917 * to execute some invalid memory upon resume
918 */
919 iwl_trans_pcie_tx_reset(trans);
920
921 iwl_pcie_set_pwr(trans, true);
922}
923
924static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
debff618
JB		 925 enum iwl_d3_status *status,
926 bool test)
ddaf5a5b
JB		 927{
928 u32 val;
929 int ret;
930
debff618
JB		 931 if (test) {
932 iwl_enable_interrupts(trans);
933 *status = IWL_D3_STATUS_ALIVE;
934 return 0;
935 }
936
ddaf5a5b
JB		 937 iwl_pcie_set_pwr(trans, false);
938
939 val = iwl_read32(trans, CSR_RESET);
940 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
941 *status = IWL_D3_STATUS_RESET;
942 return 0;
943 }
944
945 /*
946 * Also enables interrupts - none will happen as the device doesn't
947 * know we're waking it up, only when the opmode actually tells it
948 * after this call.
949 */
950 iwl_pcie_reset_ict(trans);
951
952 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
953 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
954
955 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
956 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
957 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
958 25000);
959 if (ret) {
960 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
961 return ret;
962 }
963
964 iwl_trans_pcie_tx_reset(trans);
965
966 ret = iwl_pcie_rx_init(trans);
967 if (ret) {
968 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
969 return ret;
970 }
971
ddaf5a5b
JB		 972 *status = IWL_D3_STATUS_ALIVE;
973 return 0;
2dd4f9f7
JB		 974}
975
57a1dc89 976static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
e6bb4c9c 977{
c9eec95c 978 bool hw_rfkill;
a8b691e6 979 int err;
e6bb4c9c 980
7afe3705 981 err = iwl_pcie_prepare_card_hw(trans);
ebb7678d 982 if (err) {
d6f1c316 983 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
a8b691e6 984 return err;
ebb7678d 985 }
a6c684ee 986
2997494f 987 /* Reset the entire device */
ce836c76 988 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
2997494f
EG		 989
990 usleep_range(10, 15);
991
7afe3705 992 iwl_pcie_apm_init(trans);
a6c684ee 993
226c02ca
EG		 994 /* From now on, the op_mode will be kept updated about RF kill state */
995 iwl_enable_rfkill_int(trans);
996
8d425517 997 hw_rfkill = iwl_is_rfkill_set(trans);
4620020b 998 if (hw_rfkill)
eb7ff77e 999 set_bit(STATUS_RFKILL, &trans->status);
4620020b 1000 else
eb7ff77e 1001 clear_bit(STATUS_RFKILL, &trans->status);
14cfca71 1002 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
d48e2074 1003
a8b691e6 1004 return 0;
e6bb4c9c
EG		 1005}
1006
a4082843 1007static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
cc56feb2 1008{
20d3b647 1009 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
d23f78e6 1010
a4082843 1011 /* disable interrupts - don't enable HW RF kill interrupt */
7b70bd63 1012 spin_lock(&trans_pcie->irq_lock);
ee7d737c 1013 iwl_disable_interrupts(trans);
7b70bd63 1014 spin_unlock(&trans_pcie->irq_lock);
ee7d737c 1015
7afe3705 1016 iwl_pcie_apm_stop(trans);
cc56feb2 1017
7b70bd63 1018 spin_lock(&trans_pcie->irq_lock);
218733cf 1019 iwl_disable_interrupts(trans);
7b70bd63 1020 spin_unlock(&trans_pcie->irq_lock);
1df06bdc 1021
8d96bb61 1022 iwl_pcie_disable_ict(trans);
cc56feb2
EG		 1023}
1024
03905495
EG		 1025static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1026{
05f5b97e 1027 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1028}
1029
1030static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1031{
05f5b97e 1032 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1033}
1034
1035static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1036{
05f5b97e 1037 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
03905495
EG		 1038}
1039
6a06b6c1
EG		 1040static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1041{
f9477c17
AP		 1042 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1043 ((reg & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1044 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1045}
1046
1047static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1048 u32 val)
1049{
1050 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
f9477c17 1051 ((addr & 0x000FFFFF) | (3 << 24)));
6a06b6c1
EG		 1052 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1053}
1054
f14d6b39
JB		 1055static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1056{
1057 WARN_ON(1);
1058 return 0;
1059}
1060
c6f600fc 1061static void iwl_trans_pcie_configure(struct iwl_trans *trans,
9eae88fa 1062 const struct iwl_trans_config *trans_cfg)
c6f600fc
MV		 1063{
1064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1065
1066 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
b04db9ac 1067 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
d663ee73
JB		 1068 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1069 trans_pcie->n_no_reclaim_cmds = 0;
1070 else
1071 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1072 if (trans_pcie->n_no_reclaim_cmds)
1073 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1074 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
9eae88fa 1075
b2cf410c
JB		 1076 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1077 if (trans_pcie->rx_buf_size_8k)
1078 trans_pcie->rx_page_order = get_order(8 * 1024);
1079 else
1080 trans_pcie->rx_page_order = get_order(4 * 1024);
7c5ba4a8
JB		 1081
1082 trans_pcie->wd_timeout =
1083 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
d9fb6465
JB		 1084
1085 trans_pcie->command_names = trans_cfg->command_names;
046db346 1086 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
f14d6b39
JB		 1087
1088 /* Initialize NAPI here - it should be before registering to mac80211
1089 * in the opmode but after the HW struct is allocated.
1090 * As this function may be called again in some corner cases don't
1091 * do anything if NAPI was already initialized.
1092 */
1093 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1094 init_dummy_netdev(&trans_pcie->napi_dev);
1095 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1096 &trans_pcie->napi_dev,
1097 iwl_pcie_dummy_napi_poll, 64);
1098 }
c6f600fc
MV		 1099}
1100
d1ff5253 1101void iwl_trans_pcie_free(struct iwl_trans *trans)
34c1b7ba 1102{
20d3b647 1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
a42a1844 1104
0aa86df6 1105 synchronize_irq(trans_pcie->pci_dev->irq);
0aa86df6 1106
f02831be 1107 iwl_pcie_tx_free(trans);
9805c446 1108 iwl_pcie_rx_free(trans);
6379103e 1109
a8b691e6
JB		 1110 free_irq(trans_pcie->pci_dev->irq, trans);
1111 iwl_pcie_free_ict(trans);
a42a1844
EG		 1112
1113 pci_disable_msi(trans_pcie->pci_dev);
05f5b97e 1114 iounmap(trans_pcie->hw_base);
a42a1844
EG		 1115 pci_release_regions(trans_pcie->pci_dev);
1116 pci_disable_device(trans_pcie->pci_dev);
59c647b6 1117 kmem_cache_destroy(trans->dev_cmd_pool);
a42a1844 1118
f14d6b39
JB		 1119 if (trans_pcie->napi.poll)
1120 netif_napi_del(&trans_pcie->napi);
1121
6d8f6eeb 1122 kfree(trans);
34c1b7ba
EG		 1123}
1124
47107e84
DF		 1125static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1126{
47107e84 1127 if (state)
eb7ff77e 1128 set_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84 1129 else
eb7ff77e 1130 clear_bit(STATUS_TPOWER_PMI, &trans->status);
47107e84
DF		 1131}
1132
e56b04ef
LE		 1133static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1134 unsigned long *flags)
7a65d170
EG		 1135{
1136 int ret;
cfb4e624
JB		 1137 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1138
1139 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
7a65d170 1140
b9439491
EG		 1141 if (trans_pcie->cmd_in_flight)
1142 goto out;
1143
7a65d170 1144 /* this bit wakes up the NIC */
e139dc4a
LE		 1145 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1146 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1147
1148 /*
1149 * These bits say the device is running, and should keep running for
1150 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1151 * but they do not indicate that embedded SRAM is restored yet;
1152 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1153 * to/from host DRAM when sleeping/waking for power-saving.
1154 * Each direction takes approximately 1/4 millisecond; with this
1155 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1156 * series of register accesses are expected (e.g. reading Event Log),
1157 * to keep device from sleeping.
1158 *
1159 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1160 * SRAM is okay/restored. We don't check that here because this call
1161 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1162 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1163 *
1164 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1165 * and do not save/restore SRAM when power cycling.
1166 */
1167 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1168 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1169 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1170 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1171 if (unlikely(ret < 0)) {
1172 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1173 if (!silent) {
1174 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1175 WARN_ONCE(1,
1176 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1177 val);
cfb4e624 1178 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1179 return false;
1180 }
1181 }
1182
b9439491 1183out:
e56b04ef
LE		 1184 /*
1185 * Fool sparse by faking we release the lock - sparse will
1186 * track nic_access anyway.
1187 */
cfb4e624 1188 __release(&trans_pcie->reg_lock);
7a65d170
EG		 1189 return true;
1190}
1191
e56b04ef
LE		 1192static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1193 unsigned long *flags)
7a65d170 1194{
cfb4e624 1195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e56b04ef 1196
cfb4e624 1197 lockdep_assert_held(&trans_pcie->reg_lock);
e56b04ef
LE		 1198
1199 /*
1200 * Fool sparse by faking we acquiring the lock - sparse will
1201 * track nic_access anyway.
1202 */
cfb4e624 1203 __acquire(&trans_pcie->reg_lock);
e56b04ef 1204
b9439491
EG		 1205 if (trans_pcie->cmd_in_flight)
1206 goto out;
1207
e139dc4a
LE		 1208 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1209 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
7a65d170
EG		 1210 /*
1211 * Above we read the CSR_GP_CNTRL register, which will flush
1212 * any previous writes, but we need the write that clears the
1213 * MAC_ACCESS_REQ bit to be performed before any other writes
1214 * scheduled on different CPUs (after we drop reg_lock).
1215 */
1216 mmiowb();
b9439491 1217out:
cfb4e624 1218 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
7a65d170
EG		 1219}
1220
4fd442db
EG		 1221static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1222 void *buf, int dwords)
1223{
1224 unsigned long flags;
1225 int offs, ret = 0;
1226 u32 *vals = buf;
1227
e56b04ef 1228 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1229 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1230 for (offs = 0; offs < dwords; offs++)
1231 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
e56b04ef 1232 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1233 } else {
1234 ret = -EBUSY;
1235 }
4fd442db
EG		 1236 return ret;
1237}
1238
1239static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
bf0fd5da 1240 const void *buf, int dwords)
4fd442db
EG		 1241{
1242 unsigned long flags;
1243 int offs, ret = 0;
bf0fd5da 1244 const u32 *vals = buf;
4fd442db 1245
e56b04ef 1246 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
4fd442db
EG		 1247 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1248 for (offs = 0; offs < dwords; offs++)
01387ffd
EG		 1249 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1250 vals ? vals[offs] : 0);
e56b04ef 1251 iwl_trans_release_nic_access(trans, &flags);
4fd442db
EG		 1252 } else {
1253 ret = -EBUSY;
1254 }
4fd442db
EG		 1255 return ret;
1256}
7a65d170 1257
5f178cd2
EG		 1258#define IWL_FLUSH_WAIT_MS 2000
1259
990aa6d7 1260static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
5f178cd2 1261{
8ad71bef 1262 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1263 struct iwl_txq *txq;
5f178cd2
EG		 1264 struct iwl_queue *q;
1265 int cnt;
1266 unsigned long now = jiffies;
1c3fea82
EG		 1267 u32 scd_sram_addr;
1268 u8 buf[16];
5f178cd2
EG		 1269 int ret = 0;
1270
1271 /* waiting for all the tx frames complete might take a while */
035f7ff2 1272 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
9ba1947a 1273 if (cnt == trans_pcie->cmd_queue)
5f178cd2 1274 continue;
8ad71bef 1275 txq = &trans_pcie->txq[cnt];
5f178cd2
EG		 1276 q = &txq->q;
1277 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1278 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1279 msleep(1);
1280
1281 if (q->read_ptr != q->write_ptr) {
1c3fea82
EG		 1282 IWL_ERR(trans,
1283 "fail to flush all tx fifo queues Q %d\n", cnt);
5f178cd2
EG		 1284 ret = -ETIMEDOUT;
1285 break;
1286 }
1287 }
1c3fea82
EG		 1288
1289 if (!ret)
1290 return 0;
1291
1292 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1293 txq->q.read_ptr, txq->q.write_ptr);
1294
1295 scd_sram_addr = trans_pcie->scd_base_addr +
1296 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1297 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1298
1299 iwl_print_hex_error(trans, buf, sizeof(buf));
1300
1301 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1302 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1303 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1304
1305 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1306 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1307 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1308 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1309 u32 tbl_dw =
1310 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1311 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1312
1313 if (cnt & 0x1)
1314 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1315 else
1316 tbl_dw = tbl_dw & 0x0000FFFF;
1317
1318 IWL_ERR(trans,
1319 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1320 cnt, active ? "" : "in", fifo, tbl_dw,
1321 iwl_read_prph(trans,
1322 SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1323 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1324 }
1325
5f178cd2
EG		 1326 return ret;
1327}
1328
e139dc4a
LE		 1329static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1330 u32 mask, u32 value)
1331{
e56b04ef 1332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
e139dc4a
LE		 1333 unsigned long flags;
1334
e56b04ef 1335 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
e139dc4a 1336 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
e56b04ef 1337 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
e139dc4a
LE		 1338}
1339
ff620849
EG		 1340static const char *get_csr_string(int cmd)
1341{
d9fb6465 1342#define IWL_CMD(x) case x: return #x
ff620849
EG		 1343 switch (cmd) {
1344 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1345 IWL_CMD(CSR_INT_COALESCING);
1346 IWL_CMD(CSR_INT);
1347 IWL_CMD(CSR_INT_MASK);
1348 IWL_CMD(CSR_FH_INT_STATUS);
1349 IWL_CMD(CSR_GPIO_IN);
1350 IWL_CMD(CSR_RESET);
1351 IWL_CMD(CSR_GP_CNTRL);
1352 IWL_CMD(CSR_HW_REV);
1353 IWL_CMD(CSR_EEPROM_REG);
1354 IWL_CMD(CSR_EEPROM_GP);
1355 IWL_CMD(CSR_OTP_GP_REG);
1356 IWL_CMD(CSR_GIO_REG);
1357 IWL_CMD(CSR_GP_UCODE_REG);
1358 IWL_CMD(CSR_GP_DRIVER_REG);
1359 IWL_CMD(CSR_UCODE_DRV_GP1);
1360 IWL_CMD(CSR_UCODE_DRV_GP2);
1361 IWL_CMD(CSR_LED_REG);
1362 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1363 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1364 IWL_CMD(CSR_ANA_PLL_CFG);
1365 IWL_CMD(CSR_HW_REV_WA_REG);
a812cba9 1366 IWL_CMD(CSR_MONITOR_STATUS_REG);
ff620849
EG		 1367 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1368 default:
1369 return "UNKNOWN";
1370 }
d9fb6465 1371#undef IWL_CMD
ff620849
EG		 1372}
1373
990aa6d7 1374void iwl_pcie_dump_csr(struct iwl_trans *trans)
ff620849
EG		 1375{
1376 int i;
1377 static const u32 csr_tbl[] = {
1378 CSR_HW_IF_CONFIG_REG,
1379 CSR_INT_COALESCING,
1380 CSR_INT,
1381 CSR_INT_MASK,
1382 CSR_FH_INT_STATUS,
1383 CSR_GPIO_IN,
1384 CSR_RESET,
1385 CSR_GP_CNTRL,
1386 CSR_HW_REV,
1387 CSR_EEPROM_REG,
1388 CSR_EEPROM_GP,
1389 CSR_OTP_GP_REG,
1390 CSR_GIO_REG,
1391 CSR_GP_UCODE_REG,
1392 CSR_GP_DRIVER_REG,
1393 CSR_UCODE_DRV_GP1,
1394 CSR_UCODE_DRV_GP2,
1395 CSR_LED_REG,
1396 CSR_DRAM_INT_TBL_REG,
1397 CSR_GIO_CHICKEN_BITS,
1398 CSR_ANA_PLL_CFG,
a812cba9 1399 CSR_MONITOR_STATUS_REG,
ff620849
EG		 1400 CSR_HW_REV_WA_REG,
1401 CSR_DBG_HPET_MEM_REG
1402 };
1403 IWL_ERR(trans, "CSR values:\n");
1404 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1405 "CSR_INT_PERIODIC_REG)\n");
1406 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1407 IWL_ERR(trans, " %25s: 0X%08x\n",
1408 get_csr_string(csr_tbl[i]),
1042db2a 1409 iwl_read32(trans, csr_tbl[i]));
ff620849
EG		 1410 }
1411}
1412
87e5666c
EG		 1413#ifdef CONFIG_IWLWIFI_DEBUGFS
1414/* create and remove of files */
1415#define DEBUGFS_ADD_FILE(name, parent, mode) do { \
5a878bf6 1416 if (!debugfs_create_file(#name, mode, parent, trans, \
87e5666c 1417 &iwl_dbgfs_##name##_ops)) \
9da987ac 1418 goto err; \
87e5666c
EG		 1419} while (0)
1420
1421/* file operation */
87e5666c 1422#define DEBUGFS_READ_FILE_OPS(name) \
87e5666c
EG		 1423static const struct file_operations iwl_dbgfs_##name##_ops = { \
1424 .read = iwl_dbgfs_##name##_read, \
234e3405 1425 .open = simple_open, \
87e5666c
EG		 1426 .llseek = generic_file_llseek, \
1427};
1428
16db88ba 1429#define DEBUGFS_WRITE_FILE_OPS(name) \
16db88ba
EG		 1430static const struct file_operations iwl_dbgfs_##name##_ops = { \
1431 .write = iwl_dbgfs_##name##_write, \
234e3405 1432 .open = simple_open, \
16db88ba
EG		 1433 .llseek = generic_file_llseek, \
1434};
1435
87e5666c 1436#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
87e5666c
EG		 1437static const struct file_operations iwl_dbgfs_##name##_ops = { \
1438 .write = iwl_dbgfs_##name##_write, \
1439 .read = iwl_dbgfs_##name##_read, \
234e3405 1440 .open = simple_open, \
87e5666c
EG		 1441 .llseek = generic_file_llseek, \
1442};
1443
87e5666c 1444static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
20d3b647
JB		 1445 char __user *user_buf,
1446 size_t count, loff_t *ppos)
8ad71bef 1447{
5a878bf6 1448 struct iwl_trans *trans = file->private_data;
8ad71bef 1449 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1450 struct iwl_txq *txq;
87e5666c
EG		 1451 struct iwl_queue *q;
1452 char *buf;
1453 int pos = 0;
1454 int cnt;
1455 int ret;
1745e440
WYG		 1456 size_t bufsz;
1457
035f7ff2 1458 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
87e5666c 1459
f9e75447 1460 if (!trans_pcie->txq)
87e5666c 1461 return -EAGAIN;
f9e75447 1462
87e5666c
EG		 1463 buf = kzalloc(bufsz, GFP_KERNEL);
1464 if (!buf)
1465 return -ENOMEM;
1466
035f7ff2 1467 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
8ad71bef 1468 txq = &trans_pcie->txq[cnt];
87e5666c
EG		 1469 q = &txq->q;
1470 pos += scnprintf(buf + pos, bufsz - pos,
9eae88fa 1471 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
87e5666c 1472 cnt, q->read_ptr, q->write_ptr,
9eae88fa
JB		 1473 !!test_bit(cnt, trans_pcie->queue_used),
1474 !!test_bit(cnt, trans_pcie->queue_stopped));
87e5666c
EG		 1475 }
1476 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1477 kfree(buf);
1478 return ret;
1479}
1480
1481static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
20d3b647
JB		 1482 char __user *user_buf,
1483 size_t count, loff_t *ppos)
1484{
5a878bf6 1485 struct iwl_trans *trans = file->private_data;
20d3b647 1486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
990aa6d7 1487 struct iwl_rxq *rxq = &trans_pcie->rxq;
87e5666c
EG		 1488 char buf[256];
1489 int pos = 0;
1490 const size_t bufsz = sizeof(buf);
1491
1492 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1493 rxq->read);
1494 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1495 rxq->write);
1496 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1497 rxq->free_count);
1498 if (rxq->rb_stts) {
1499 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1500 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1501 } else {
1502 pos += scnprintf(buf + pos, bufsz - pos,
1503 "closed_rb_num: Not Allocated\n");
1504 }
1505 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1506}
1507
1f7b6172
EG		 1508static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1509 char __user *user_buf,
20d3b647
JB		 1510 size_t count, loff_t *ppos)
1511{
1f7b6172 1512 struct iwl_trans *trans = file->private_data;
20d3b647 1513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1514 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1515
1516 int pos = 0;
1517 char *buf;
1518 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1519 ssize_t ret;
1520
1521 buf = kzalloc(bufsz, GFP_KERNEL);
f9e75447 1522 if (!buf)
1f7b6172 1523 return -ENOMEM;
1f7b6172
EG		 1524
1525 pos += scnprintf(buf + pos, bufsz - pos,
1526 "Interrupt Statistics Report:\n");
1527
1528 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1529 isr_stats->hw);
1530 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1531 isr_stats->sw);
1532 if (isr_stats->sw || isr_stats->hw) {
1533 pos += scnprintf(buf + pos, bufsz - pos,
1534 "\tLast Restarting Code: 0x%X\n",
1535 isr_stats->err_code);
1536 }
1537#ifdef CONFIG_IWLWIFI_DEBUG
1538 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1539 isr_stats->sch);
1540 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1541 isr_stats->alive);
1542#endif
1543 pos += scnprintf(buf + pos, bufsz - pos,
1544 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1545
1546 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1547 isr_stats->ctkill);
1548
1549 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1550 isr_stats->wakeup);
1551
1552 pos += scnprintf(buf + pos, bufsz - pos,
1553 "Rx command responses:\t\t %u\n", isr_stats->rx);
1554
1555 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1556 isr_stats->tx);
1557
1558 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1559 isr_stats->unhandled);
1560
1561 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1562 kfree(buf);
1563 return ret;
1564}
1565
1566static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1567 const char __user *user_buf,
1568 size_t count, loff_t *ppos)
1569{
1570 struct iwl_trans *trans = file->private_data;
20d3b647 1571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1f7b6172
EG		 1572 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1573
1574 char buf[8];
1575 int buf_size;
1576 u32 reset_flag;
1577
1578 memset(buf, 0, sizeof(buf));
1579 buf_size = min(count, sizeof(buf) - 1);
1580 if (copy_from_user(buf, user_buf, buf_size))
1581 return -EFAULT;
1582 if (sscanf(buf, "%x", &reset_flag) != 1)
1583 return -EFAULT;
1584 if (reset_flag == 0)
1585 memset(isr_stats, 0, sizeof(*isr_stats));
1586
1587 return count;
1588}
1589
16db88ba 1590static ssize_t iwl_dbgfs_csr_write(struct file *file,
20d3b647
JB		 1591 const char __user *user_buf,
1592 size_t count, loff_t *ppos)
16db88ba
EG		 1593{
1594 struct iwl_trans *trans = file->private_data;
1595 char buf[8];
1596 int buf_size;
1597 int csr;
1598
1599 memset(buf, 0, sizeof(buf));
1600 buf_size = min(count, sizeof(buf) - 1);
1601 if (copy_from_user(buf, user_buf, buf_size))
1602 return -EFAULT;
1603 if (sscanf(buf, "%d", &csr) != 1)
1604 return -EFAULT;
1605
990aa6d7 1606 iwl_pcie_dump_csr(trans);
16db88ba
EG		 1607
1608 return count;
1609}
1610
16db88ba 1611static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
20d3b647
JB		 1612 char __user *user_buf,
1613 size_t count, loff_t *ppos)
16db88ba
EG		 1614{
1615 struct iwl_trans *trans = file->private_data;
94543a8d 1616 char *buf = NULL;
56c2477f 1617 ssize_t ret;
16db88ba 1618
56c2477f
JB		 1619 ret = iwl_dump_fh(trans, &buf);
1620 if (ret < 0)
1621 return ret;
1622 if (!buf)
1623 return -EINVAL;
1624 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1625 kfree(buf);
16db88ba
EG		 1626 return ret;
1627}
1628
1f7b6172 1629DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
16db88ba 1630DEBUGFS_READ_FILE_OPS(fh_reg);
87e5666c
EG		 1631DEBUGFS_READ_FILE_OPS(rx_queue);
1632DEBUGFS_READ_FILE_OPS(tx_queue);
16db88ba 1633DEBUGFS_WRITE_FILE_OPS(csr);
87e5666c
EG		 1634
1635/*
1636 * Create the debugfs files and directories
1637 *
1638 */
1639static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647 1640 struct dentry *dir)
87e5666c 1641{
87e5666c
EG		 1642 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1643 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1f7b6172 1644 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
16db88ba
EG		 1645 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1646 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
87e5666c 1647 return 0;
9da987ac
MV		 1648
1649err:
1650 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1651 return -ENOMEM;
87e5666c
EG		 1652}
1653#else
1654static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
20d3b647
JB		 1655 struct dentry *dir)
1656{
1657 return 0;
1658}
87e5666c
EG		 1659#endif /*CONFIG_IWLWIFI_DEBUGFS */
1660
d1ff5253 1661static const struct iwl_trans_ops trans_ops_pcie = {
57a1dc89 1662 .start_hw = iwl_trans_pcie_start_hw,
a4082843 1663 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
ed6a3803 1664 .fw_alive = iwl_trans_pcie_fw_alive,
cf614297 1665 .start_fw = iwl_trans_pcie_start_fw,
e6bb4c9c 1666 .stop_device = iwl_trans_pcie_stop_device,
48d42c42 1667
ddaf5a5b
JB		 1668 .d3_suspend = iwl_trans_pcie_d3_suspend,
1669 .d3_resume = iwl_trans_pcie_d3_resume,
2dd4f9f7 1670
f02831be 1671 .send_cmd = iwl_trans_pcie_send_hcmd,
c85eb619 1672
e6bb4c9c 1673 .tx = iwl_trans_pcie_tx,
a0eaad71 1674 .reclaim = iwl_trans_pcie_reclaim,
34c1b7ba 1675
d0624be6 1676 .txq_disable = iwl_trans_pcie_txq_disable,
4beaf6c2 1677 .txq_enable = iwl_trans_pcie_txq_enable,
34c1b7ba 1678
87e5666c 1679 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
5f178cd2 1680
990aa6d7 1681 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
5f178cd2 1682
03905495
EG		 1683 .write8 = iwl_trans_pcie_write8,
1684 .write32 = iwl_trans_pcie_write32,
1685 .read32 = iwl_trans_pcie_read32,
6a06b6c1
EG		 1686 .read_prph = iwl_trans_pcie_read_prph,
1687 .write_prph = iwl_trans_pcie_write_prph,
4fd442db
EG		 1688 .read_mem = iwl_trans_pcie_read_mem,
1689 .write_mem = iwl_trans_pcie_write_mem,
c6f600fc 1690 .configure = iwl_trans_pcie_configure,
47107e84 1691 .set_pmi = iwl_trans_pcie_set_pmi,
7a65d170 1692 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
e139dc4a
LE		 1693 .release_nic_access = iwl_trans_pcie_release_nic_access,
1694 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
e6bb4c9c 1695};
a42a1844 1696
87ce05a2 1697struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
035f7ff2
EG		 1698 const struct pci_device_id *ent,
1699 const struct iwl_cfg *cfg)
a42a1844 1700{
a42a1844
EG		 1701 struct iwl_trans_pcie *trans_pcie;
1702 struct iwl_trans *trans;
1703 u16 pci_cmd;
1704 int err;
1705
1706 trans = kzalloc(sizeof(struct iwl_trans) +
20d3b647 1707 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
6965a354
LC		 1708 if (!trans) {
1709 err = -ENOMEM;
1710 goto out;
1711 }
a42a1844
EG		 1712
1713 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1714
1715 trans->ops = &trans_ops_pcie;
035f7ff2 1716 trans->cfg = cfg;
2bfb5092 1717 trans_lockdep_init(trans);
a42a1844 1718 trans_pcie->trans = trans;
7b11488f 1719 spin_lock_init(&trans_pcie->irq_lock);
e56b04ef 1720 spin_lock_init(&trans_pcie->reg_lock);
13df1aab 1721 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
a42a1844 1722
d819c6cf
JB		 1723 err = pci_enable_device(pdev);
1724 if (err)
1725 goto out_no_pci;
1726
f2532b04
EG		 1727 if (!cfg->base_params->pcie_l1_allowed) {
1728 /*
1729 * W/A - seems to solve weird behavior. We need to remove this
1730 * if we don't want to stay in L1 all the time. This wastes a
1731 * lot of power.
1732 */
1733 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1734 PCIE_LINK_STATE_L1 |
1735 PCIE_LINK_STATE_CLKPM);
1736 }
a42a1844 1737
a42a1844
EG		 1738 pci_set_master(pdev);
1739
1740 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1741 if (!err)
1742 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1743 if (err) {
1744 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1745 if (!err)
1746 err = pci_set_consistent_dma_mask(pdev,
20d3b647 1747 DMA_BIT_MASK(32));
a42a1844
EG		 1748 /* both attempts failed: */
1749 if (err) {
6a4b09f8 1750 dev_err(&pdev->dev, "No suitable DMA available\n");
a42a1844
EG		 1751 goto out_pci_disable_device;
1752 }
1753 }
1754
1755 err = pci_request_regions(pdev, DRV_NAME);
1756 if (err) {
6a4b09f8 1757 dev_err(&pdev->dev, "pci_request_regions failed\n");
a42a1844
EG		 1758 goto out_pci_disable_device;
1759 }
1760
05f5b97e 1761 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
a42a1844 1762 if (!trans_pcie->hw_base) {
6a4b09f8 1763 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
a42a1844
EG		 1764 err = -ENODEV;
1765 goto out_pci_release_regions;
1766 }
1767
a42a1844
EG		 1768 /* We disable the RETRY_TIMEOUT register (0x41) to keep
1769 * PCI Tx retries from interfering with C3 CPU state */
1770 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1771
1772 err = pci_enable_msi(pdev);
9f904b38 1773 if (err) {
6a4b09f8 1774 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
9f904b38
EG		 1775 /* enable rfkill interrupt: hw bug w/a */
1776 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1777 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1778 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1779 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1780 }
1781 }
a42a1844
EG		 1782
1783 trans->dev = &pdev->dev;
a42a1844 1784 trans_pcie->pci_dev = pdev;
08079a49 1785 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
99673ee5 1786 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
9ca85961
EG		 1787 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1788 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
a42a1844 1789
69a10b29 1790 /* Initialize the wait queue for commands */
f946b529 1791 init_waitqueue_head(&trans_pcie->wait_command_queue);
69a10b29 1792
3ec45882
JB		 1793 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1794 "iwl_cmd_pool:%s", dev_name(trans->dev));
59c647b6
EG		 1795
1796 trans->dev_cmd_headroom = 0;
1797 trans->dev_cmd_pool =
3ec45882 1798 kmem_cache_create(trans->dev_cmd_pool_name,
59c647b6
EG		 1799 sizeof(struct iwl_device_cmd)
1800 + trans->dev_cmd_headroom,
1801 sizeof(void *),
1802 SLAB_HWCACHE_ALIGN,
1803 NULL);
1804
6965a354
LC		 1805 if (!trans->dev_cmd_pool) {
1806 err = -ENOMEM;
59c647b6 1807 goto out_pci_disable_msi;
6965a354 1808 }
59c647b6 1809
a8b691e6
JB		 1810 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1811
a8b691e6
JB		 1812 if (iwl_pcie_alloc_ict(trans))
1813 goto out_free_cmd_pool;
1814
85bf9da1 1815 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
6965a354
LC		 1816 iwl_pcie_irq_handler,
1817 IRQF_SHARED, DRV_NAME, trans);
1818 if (err) {
a8b691e6
JB		 1819 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1820 goto out_free_ict;
1821 }
1822
a42a1844
EG		 1823 return trans;
1824
a8b691e6
JB		 1825out_free_ict:
1826 iwl_pcie_free_ict(trans);
1827out_free_cmd_pool:
1828 kmem_cache_destroy(trans->dev_cmd_pool);
59c647b6
EG		 1829out_pci_disable_msi:
1830 pci_disable_msi(pdev);
a42a1844
EG		 1831out_pci_release_regions:
1832 pci_release_regions(pdev);
1833out_pci_disable_device:
1834 pci_disable_device(pdev);
1835out_no_pci:
1836 kfree(trans);
6965a354
LC		 1837out:
1838 return ERR_PTR(err);
a42a1844 1839}
Linux kernel - Deliverables
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