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c85eb619 EG |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
553452e5 LK |
8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
c85eb619 EG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
c85eb619 EG |
27 | * |
28 | * Contact Information: | |
29 | * Intel Linux Wireless <ilw@linux.intel.com> | |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
553452e5 LK |
34 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
35 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH | |
c85eb619 EG |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
a42a1844 EG |
65 | #include <linux/pci.h> |
66 | #include <linux/pci-aspm.h> | |
e6bb4c9c | 67 | #include <linux/interrupt.h> |
87e5666c | 68 | #include <linux/debugfs.h> |
cf614297 | 69 | #include <linux/sched.h> |
6d8f6eeb EG |
70 | #include <linux/bitops.h> |
71 | #include <linux/gfp.h> | |
48eb7b34 | 72 | #include <linux/vmalloc.h> |
e6bb4c9c | 73 | |
82575102 | 74 | #include "iwl-drv.h" |
c85eb619 | 75 | #include "iwl-trans.h" |
522376d2 EG |
76 | #include "iwl-csr.h" |
77 | #include "iwl-prph.h" | |
cb6bb128 | 78 | #include "iwl-scd.h" |
7a10e3e4 | 79 | #include "iwl-agn-hw.h" |
4d075007 | 80 | #include "iwl-fw-error-dump.h" |
6468a01a | 81 | #include "internal.h" |
06d51e0d | 82 | #include "iwl-fh.h" |
0439bb62 | 83 | |
fe45773b AN |
84 | /* extended range in FW SRAM */ |
85 | #define IWL_FW_MEM_EXTENDED_START 0x40000 | |
86 | #define IWL_FW_MEM_EXTENDED_END 0x57FFF | |
87 | ||
c2d20201 EG |
88 | static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) |
89 | { | |
90 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
91 | ||
92 | if (!trans_pcie->fw_mon_page) | |
93 | return; | |
94 | ||
95 | dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, | |
96 | trans_pcie->fw_mon_size, DMA_FROM_DEVICE); | |
97 | __free_pages(trans_pcie->fw_mon_page, | |
98 | get_order(trans_pcie->fw_mon_size)); | |
99 | trans_pcie->fw_mon_page = NULL; | |
100 | trans_pcie->fw_mon_phys = 0; | |
101 | trans_pcie->fw_mon_size = 0; | |
102 | } | |
103 | ||
104 | static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans) | |
105 | { | |
106 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
553452e5 | 107 | struct page *page = NULL; |
c2d20201 EG |
108 | dma_addr_t phys; |
109 | u32 size; | |
110 | u8 power; | |
111 | ||
112 | if (trans_pcie->fw_mon_page) { | |
113 | dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, | |
114 | trans_pcie->fw_mon_size, | |
115 | DMA_FROM_DEVICE); | |
116 | return; | |
117 | } | |
118 | ||
119 | phys = 0; | |
120 | for (power = 26; power >= 11; power--) { | |
121 | int order; | |
122 | ||
123 | size = BIT(power); | |
124 | order = get_order(size); | |
125 | page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, | |
126 | order); | |
127 | if (!page) | |
128 | continue; | |
129 | ||
130 | phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, | |
131 | DMA_FROM_DEVICE); | |
132 | if (dma_mapping_error(trans->dev, phys)) { | |
133 | __free_pages(page, order); | |
553452e5 | 134 | page = NULL; |
c2d20201 EG |
135 | continue; |
136 | } | |
137 | IWL_INFO(trans, | |
138 | "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", | |
139 | size, order); | |
140 | break; | |
141 | } | |
142 | ||
40a76905 | 143 | if (WARN_ON_ONCE(!page)) |
c2d20201 EG |
144 | return; |
145 | ||
146 | trans_pcie->fw_mon_page = page; | |
147 | trans_pcie->fw_mon_phys = phys; | |
148 | trans_pcie->fw_mon_size = size; | |
149 | } | |
150 | ||
a812cba9 AB |
151 | static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) |
152 | { | |
153 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
154 | ((reg & 0x0000ffff) | (2 << 28))); | |
155 | return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); | |
156 | } | |
157 | ||
158 | static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) | |
159 | { | |
160 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); | |
161 | iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, | |
162 | ((reg & 0x0000ffff) | (3 << 28))); | |
163 | } | |
164 | ||
ddaf5a5b | 165 | static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) |
392f8b78 | 166 | { |
ddaf5a5b JB |
167 | if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) |
168 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
169 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
170 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
171 | else | |
172 | iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, | |
173 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
174 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
392f8b78 EG |
175 | } |
176 | ||
af634bee EG |
177 | /* PCI registers */ |
178 | #define PCI_CFG_RETRY_TIMEOUT 0x041 | |
af634bee | 179 | |
7afe3705 | 180 | static void iwl_pcie_apm_config(struct iwl_trans *trans) |
af634bee | 181 | { |
20d3b647 | 182 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
7afe3705 | 183 | u16 lctl; |
9180ac50 | 184 | u16 cap; |
af634bee | 185 | |
af634bee EG |
186 | /* |
187 | * HW bug W/A for instability in PCIe bus L0S->L1 transition. | |
188 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
189 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
190 | * costs negligible amount of power savings. | |
191 | * If not (unlikely), enable L0S, so there is at least some | |
192 | * power savings, even without L1. | |
193 | */ | |
7afe3705 | 194 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); |
9180ac50 | 195 | if (lctl & PCI_EXP_LNKCTL_ASPM_L1) |
af634bee | 196 | iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
9180ac50 | 197 | else |
af634bee | 198 | iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
438a0f0a | 199 | trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); |
9180ac50 EG |
200 | |
201 | pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); | |
202 | trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; | |
203 | dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", | |
204 | (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", | |
205 | trans->ltr_enabled ? "En" : "Dis"); | |
af634bee EG |
206 | } |
207 | ||
a6c684ee EG |
208 | /* |
209 | * Start up NIC's basic functionality after it has been reset | |
7afe3705 | 210 | * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) |
a6c684ee EG |
211 | * NOTE: This does not load uCode nor start the embedded processor |
212 | */ | |
7afe3705 | 213 | static int iwl_pcie_apm_init(struct iwl_trans *trans) |
a6c684ee EG |
214 | { |
215 | int ret = 0; | |
216 | IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); | |
217 | ||
218 | /* | |
219 | * Use "set_bit" below rather than "write", to preserve any hardware | |
220 | * bits already set by default after reset. | |
221 | */ | |
222 | ||
223 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
e4a9f8ce EH |
224 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
225 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
226 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
a6c684ee EG |
227 | |
228 | /* | |
229 | * Disable L0s without affecting L1; | |
230 | * don't wait for ICH L0s (ICH bug W/A) | |
231 | */ | |
232 | iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, | |
20d3b647 | 233 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
a6c684ee EG |
234 | |
235 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
236 | iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
237 | ||
238 | /* | |
239 | * Enable HAP INTA (interrupt from management bus) to | |
240 | * wake device's PCI Express link L1a -> L0s | |
241 | */ | |
242 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
20d3b647 | 243 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
a6c684ee | 244 | |
7afe3705 | 245 | iwl_pcie_apm_config(trans); |
a6c684ee EG |
246 | |
247 | /* Configure analog phase-lock-loop before activating to D0A */ | |
035f7ff2 | 248 | if (trans->cfg->base_params->pll_cfg_val) |
a6c684ee | 249 | iwl_set_bit(trans, CSR_ANA_PLL_CFG, |
035f7ff2 | 250 | trans->cfg->base_params->pll_cfg_val); |
a6c684ee EG |
251 | |
252 | /* | |
253 | * Set "initialization complete" bit to move adapter from | |
254 | * D0U* --> D0A* (powered-up active) state. | |
255 | */ | |
256 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
257 | ||
258 | /* | |
259 | * Wait for clock stabilization; once stabilized, access to | |
260 | * device-internal resources is supported, e.g. iwl_write_prph() | |
261 | * and accesses to uCode SRAM. | |
262 | */ | |
263 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
20d3b647 JB |
264 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
265 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
a6c684ee EG |
266 | if (ret < 0) { |
267 | IWL_DEBUG_INFO(trans, "Failed to init the card\n"); | |
268 | goto out; | |
269 | } | |
270 | ||
2d93aee1 EG |
271 | if (trans->cfg->host_interrupt_operation_mode) { |
272 | /* | |
273 | * This is a bit of an abuse - This is needed for 7260 / 3160 | |
274 | * only check host_interrupt_operation_mode even if this is | |
275 | * not related to host_interrupt_operation_mode. | |
276 | * | |
277 | * Enable the oscillator to count wake up time for L1 exit. This | |
278 | * consumes slightly more power (100uA) - but allows to be sure | |
279 | * that we wake up from L1 on time. | |
280 | * | |
281 | * This looks weird: read twice the same register, discard the | |
282 | * value, set a bit, and yet again, read that same register | |
283 | * just to discard the value. But that's the way the hardware | |
284 | * seems to like it. | |
285 | */ | |
286 | iwl_read_prph(trans, OSC_CLK); | |
287 | iwl_read_prph(trans, OSC_CLK); | |
288 | iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); | |
289 | iwl_read_prph(trans, OSC_CLK); | |
290 | iwl_read_prph(trans, OSC_CLK); | |
291 | } | |
292 | ||
a6c684ee EG |
293 | /* |
294 | * Enable DMA clock and wait for it to stabilize. | |
295 | * | |
3073d8c0 EH |
296 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" |
297 | * bits do not disable clocks. This preserves any hardware | |
298 | * bits already set by default in "CLK_CTRL_REG" after reset. | |
a6c684ee | 299 | */ |
3073d8c0 EH |
300 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) { |
301 | iwl_write_prph(trans, APMG_CLK_EN_REG, | |
302 | APMG_CLK_VAL_DMA_CLK_RQT); | |
303 | udelay(20); | |
304 | ||
305 | /* Disable L1-Active */ | |
306 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
307 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
308 | ||
309 | /* Clear the interrupt in APMG if the NIC is in RFKILL */ | |
310 | iwl_write_prph(trans, APMG_RTC_INT_STT_REG, | |
311 | APMG_RTC_INT_STT_RFKILL); | |
312 | } | |
889b1696 | 313 | |
eb7ff77e | 314 | set_bit(STATUS_DEVICE_ENABLED, &trans->status); |
a6c684ee EG |
315 | |
316 | out: | |
317 | return ret; | |
318 | } | |
319 | ||
a812cba9 AB |
320 | /* |
321 | * Enable LP XTAL to avoid HW bug where device may consume much power if | |
322 | * FW is not loaded after device reset. LP XTAL is disabled by default | |
323 | * after device HW reset. Do it only if XTAL is fed by internal source. | |
324 | * Configure device's "persistence" mode to avoid resetting XTAL again when | |
325 | * SHRD_HW_RST occurs in S3. | |
326 | */ | |
327 | static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) | |
328 | { | |
329 | int ret; | |
330 | u32 apmg_gp1_reg; | |
331 | u32 apmg_xtal_cfg_reg; | |
332 | u32 dl_cfg_reg; | |
333 | ||
334 | /* Force XTAL ON */ | |
335 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, | |
336 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
337 | ||
338 | /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ | |
339 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
340 | ||
341 | udelay(10); | |
342 | ||
343 | /* | |
344 | * Set "initialization complete" bit to move adapter from | |
345 | * D0U* --> D0A* (powered-up active) state. | |
346 | */ | |
347 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
348 | ||
349 | /* | |
350 | * Wait for clock stabilization; once stabilized, access to | |
351 | * device-internal resources is possible. | |
352 | */ | |
353 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
354 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
355 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
356 | 25000); | |
357 | if (WARN_ON(ret < 0)) { | |
358 | IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); | |
359 | /* Release XTAL ON request */ | |
360 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
361 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
362 | return; | |
363 | } | |
364 | ||
365 | /* | |
366 | * Clear "disable persistence" to avoid LP XTAL resetting when | |
367 | * SHRD_HW_RST is applied in S3. | |
368 | */ | |
369 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
370 | APMG_PCIDEV_STT_VAL_PERSIST_DIS); | |
371 | ||
372 | /* | |
373 | * Force APMG XTAL to be active to prevent its disabling by HW | |
374 | * caused by APMG idle state. | |
375 | */ | |
376 | apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, | |
377 | SHR_APMG_XTAL_CFG_REG); | |
378 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
379 | apmg_xtal_cfg_reg | | |
380 | SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
381 | ||
382 | /* | |
383 | * Reset entire device again - do controller reset (results in | |
384 | * SHRD_HW_RST). Turn MAC off before proceeding. | |
385 | */ | |
386 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
387 | ||
388 | udelay(10); | |
389 | ||
390 | /* Enable LP XTAL by indirect access through CSR */ | |
391 | apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); | |
392 | iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | | |
393 | SHR_APMG_GP1_WF_XTAL_LP_EN | | |
394 | SHR_APMG_GP1_CHICKEN_BIT_SELECT); | |
395 | ||
396 | /* Clear delay line clock power up */ | |
397 | dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); | |
398 | iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & | |
399 | ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); | |
400 | ||
401 | /* | |
402 | * Enable persistence mode to avoid LP XTAL resetting when | |
403 | * SHRD_HW_RST is applied in S3. | |
404 | */ | |
405 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
406 | CSR_HW_IF_CONFIG_REG_PERSIST_MODE); | |
407 | ||
408 | /* | |
409 | * Clear "initialization complete" bit to move adapter from | |
410 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
411 | */ | |
412 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
413 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
414 | ||
415 | /* Activates XTAL resources monitor */ | |
416 | __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, | |
417 | CSR_MONITOR_XTAL_RESOURCES); | |
418 | ||
419 | /* Release XTAL ON request */ | |
420 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, | |
421 | CSR_GP_CNTRL_REG_FLAG_XTAL_ON); | |
422 | udelay(10); | |
423 | ||
424 | /* Release APMG XTAL */ | |
425 | iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, | |
426 | apmg_xtal_cfg_reg & | |
427 | ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); | |
428 | } | |
429 | ||
7afe3705 | 430 | static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) |
cc56feb2 EG |
431 | { |
432 | int ret = 0; | |
433 | ||
434 | /* stop device's busmaster DMA activity */ | |
435 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
436 | ||
437 | ret = iwl_poll_bit(trans, CSR_RESET, | |
20d3b647 JB |
438 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
439 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
7f2ac8fb | 440 | if (ret < 0) |
cc56feb2 EG |
441 | IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); |
442 | ||
443 | IWL_DEBUG_INFO(trans, "stop master\n"); | |
444 | ||
445 | return ret; | |
446 | } | |
447 | ||
b7aaeae4 | 448 | static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) |
cc56feb2 EG |
449 | { |
450 | IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); | |
451 | ||
b7aaeae4 EG |
452 | if (op_mode_leave) { |
453 | if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) | |
454 | iwl_pcie_apm_init(trans); | |
455 | ||
456 | /* inform ME that we are leaving */ | |
457 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) | |
458 | iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
459 | APMG_PCIDEV_STT_VAL_WAKE_ME); | |
460 | else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) | |
461 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
462 | CSR_HW_IF_CONFIG_REG_PREPARE | | |
463 | CSR_HW_IF_CONFIG_REG_ENABLE_PME); | |
464 | mdelay(5); | |
465 | } | |
466 | ||
eb7ff77e | 467 | clear_bit(STATUS_DEVICE_ENABLED, &trans->status); |
cc56feb2 EG |
468 | |
469 | /* Stop device's DMA activity */ | |
7afe3705 | 470 | iwl_pcie_apm_stop_master(trans); |
cc56feb2 | 471 | |
a812cba9 AB |
472 | if (trans->cfg->lp_xtal_workaround) { |
473 | iwl_pcie_apm_lp_xtal_enable(trans); | |
474 | return; | |
475 | } | |
476 | ||
cc56feb2 EG |
477 | /* Reset the entire device */ |
478 | iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
479 | ||
480 | udelay(10); | |
481 | ||
482 | /* | |
483 | * Clear "initialization complete" bit to move adapter from | |
484 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
485 | */ | |
486 | iwl_clear_bit(trans, CSR_GP_CNTRL, | |
487 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
488 | } | |
489 | ||
7afe3705 | 490 | static int iwl_pcie_nic_init(struct iwl_trans *trans) |
392f8b78 | 491 | { |
7b11488f | 492 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
392f8b78 EG |
493 | |
494 | /* nic_init */ | |
7b70bd63 | 495 | spin_lock(&trans_pcie->irq_lock); |
7afe3705 | 496 | iwl_pcie_apm_init(trans); |
392f8b78 | 497 | |
7b70bd63 | 498 | spin_unlock(&trans_pcie->irq_lock); |
392f8b78 | 499 | |
3073d8c0 EH |
500 | if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) |
501 | iwl_pcie_set_pwr(trans, false); | |
392f8b78 | 502 | |
ecdb975c | 503 | iwl_op_mode_nic_config(trans->op_mode); |
392f8b78 EG |
504 | |
505 | /* Allocate the RX queue, or reset if it is already allocated */ | |
9805c446 | 506 | iwl_pcie_rx_init(trans); |
392f8b78 EG |
507 | |
508 | /* Allocate or reset and init all Tx and Command queues */ | |
f02831be | 509 | if (iwl_pcie_tx_init(trans)) |
392f8b78 EG |
510 | return -ENOMEM; |
511 | ||
035f7ff2 | 512 | if (trans->cfg->base_params->shadow_reg_enable) { |
392f8b78 | 513 | /* enable shadow regs in HW */ |
20d3b647 | 514 | iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); |
d38069d1 | 515 | IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); |
392f8b78 EG |
516 | } |
517 | ||
392f8b78 EG |
518 | return 0; |
519 | } | |
520 | ||
521 | #define HW_READY_TIMEOUT (50) | |
522 | ||
523 | /* Note: returns poll_bit return value, which is >= 0 if success */ | |
7afe3705 | 524 | static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) |
392f8b78 EG |
525 | { |
526 | int ret; | |
527 | ||
1042db2a | 528 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 | 529 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
392f8b78 EG |
530 | |
531 | /* See if we got it */ | |
1042db2a | 532 | ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, |
20d3b647 JB |
533 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
534 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
535 | HW_READY_TIMEOUT); | |
392f8b78 | 536 | |
6a08f514 EG |
537 | if (ret >= 0) |
538 | iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); | |
539 | ||
6d8f6eeb | 540 | IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); |
392f8b78 EG |
541 | return ret; |
542 | } | |
543 | ||
544 | /* Note: returns standard 0/-ERROR code */ | |
7afe3705 | 545 | static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) |
392f8b78 EG |
546 | { |
547 | int ret; | |
289e5501 | 548 | int t = 0; |
501fd989 | 549 | int iter; |
392f8b78 | 550 | |
6d8f6eeb | 551 | IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); |
392f8b78 | 552 | |
7afe3705 | 553 | ret = iwl_pcie_set_hw_ready(trans); |
ebb7678d | 554 | /* If the card is ready, exit 0 */ |
392f8b78 EG |
555 | if (ret >= 0) |
556 | return 0; | |
557 | ||
501fd989 EG |
558 | for (iter = 0; iter < 10; iter++) { |
559 | /* If HW is not ready, prepare the conditions to check again */ | |
560 | iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, | |
561 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
562 | ||
563 | do { | |
564 | ret = iwl_pcie_set_hw_ready(trans); | |
565 | if (ret >= 0) | |
566 | return 0; | |
392f8b78 | 567 | |
501fd989 EG |
568 | usleep_range(200, 1000); |
569 | t += 200; | |
570 | } while (t < 150000); | |
571 | msleep(25); | |
572 | } | |
392f8b78 | 573 | |
7f2ac8fb | 574 | IWL_ERR(trans, "Couldn't prepare the card\n"); |
392f8b78 | 575 | |
392f8b78 EG |
576 | return ret; |
577 | } | |
578 | ||
cf614297 EG |
579 | /* |
580 | * ucode | |
581 | */ | |
7afe3705 | 582 | static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, |
83f84d7b | 583 | dma_addr_t phy_addr, u32 byte_cnt) |
cf614297 | 584 | { |
13df1aab | 585 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
cf614297 EG |
586 | int ret; |
587 | ||
13df1aab | 588 | trans_pcie->ucode_write_complete = false; |
cf614297 EG |
589 | |
590 | iwl_write_direct32(trans, | |
20d3b647 JB |
591 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
592 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
cf614297 EG |
593 | |
594 | iwl_write_direct32(trans, | |
20d3b647 JB |
595 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), |
596 | dst_addr); | |
cf614297 EG |
597 | |
598 | iwl_write_direct32(trans, | |
83f84d7b JB |
599 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), |
600 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
cf614297 EG |
601 | |
602 | iwl_write_direct32(trans, | |
20d3b647 JB |
603 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
604 | (iwl_get_dma_hi_addr(phy_addr) | |
605 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
cf614297 EG |
606 | |
607 | iwl_write_direct32(trans, | |
20d3b647 JB |
608 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), |
609 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
610 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
611 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
cf614297 EG |
612 | |
613 | iwl_write_direct32(trans, | |
20d3b647 JB |
614 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
615 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
616 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | | |
617 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
cf614297 | 618 | |
13df1aab JB |
619 | ret = wait_event_timeout(trans_pcie->ucode_write_waitq, |
620 | trans_pcie->ucode_write_complete, 5 * HZ); | |
cf614297 | 621 | if (!ret) { |
83f84d7b | 622 | IWL_ERR(trans, "Failed to load firmware chunk!\n"); |
cf614297 EG |
623 | return -ETIMEDOUT; |
624 | } | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
7afe3705 | 629 | static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, |
83f84d7b | 630 | const struct fw_desc *section) |
cf614297 | 631 | { |
83f84d7b JB |
632 | u8 *v_addr; |
633 | dma_addr_t p_addr; | |
baa21e83 | 634 | u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); |
cf614297 EG |
635 | int ret = 0; |
636 | ||
83f84d7b JB |
637 | IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", |
638 | section_num); | |
639 | ||
c571573a EG |
640 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, |
641 | GFP_KERNEL | __GFP_NOWARN); | |
642 | if (!v_addr) { | |
643 | IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); | |
644 | chunk_sz = PAGE_SIZE; | |
645 | v_addr = dma_alloc_coherent(trans->dev, chunk_sz, | |
646 | &p_addr, GFP_KERNEL); | |
647 | if (!v_addr) | |
648 | return -ENOMEM; | |
649 | } | |
83f84d7b | 650 | |
c571573a | 651 | for (offset = 0; offset < section->len; offset += chunk_sz) { |
fe45773b AN |
652 | u32 copy_size, dst_addr; |
653 | bool extended_addr = false; | |
83f84d7b | 654 | |
c571573a | 655 | copy_size = min_t(u32, chunk_sz, section->len - offset); |
fe45773b AN |
656 | dst_addr = section->offset + offset; |
657 | ||
658 | if (dst_addr >= IWL_FW_MEM_EXTENDED_START && | |
659 | dst_addr <= IWL_FW_MEM_EXTENDED_END) | |
660 | extended_addr = true; | |
661 | ||
662 | if (extended_addr) | |
663 | iwl_set_bits_prph(trans, LMPM_CHICK, | |
664 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
cf614297 | 665 | |
83f84d7b | 666 | memcpy(v_addr, (u8 *)section->data + offset, copy_size); |
fe45773b AN |
667 | ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, |
668 | copy_size); | |
669 | ||
670 | if (extended_addr) | |
671 | iwl_clear_bits_prph(trans, LMPM_CHICK, | |
672 | LMPM_CHICK_EXTENDED_ADDR_SPACE); | |
673 | ||
83f84d7b JB |
674 | if (ret) { |
675 | IWL_ERR(trans, | |
676 | "Could not load the [%d] uCode section\n", | |
677 | section_num); | |
678 | break; | |
6dfa8d01 | 679 | } |
83f84d7b JB |
680 | } |
681 | ||
c571573a | 682 | dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); |
83f84d7b JB |
683 | return ret; |
684 | } | |
685 | ||
16bc119b EH |
686 | /* |
687 | * Driver Takes the ownership on secure machine before FW load | |
688 | * and prevent race with the BT load. | |
689 | * W/A for ROM bug. (should be remove in the next Si step) | |
690 | */ | |
691 | static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) | |
692 | { | |
693 | u32 val, loop = 1000; | |
694 | ||
1e167071 EH |
695 | /* |
696 | * Check the RSA semaphore is accessible. | |
697 | * If the HW isn't locked and the rsa semaphore isn't accessible, | |
698 | * we are in trouble. | |
699 | */ | |
16bc119b EH |
700 | val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); |
701 | if (val & (BIT(1) | BIT(17))) { | |
1e167071 EH |
702 | IWL_INFO(trans, |
703 | "can't access the RSA semaphore it is write protected\n"); | |
16bc119b EH |
704 | return 0; |
705 | } | |
706 | ||
707 | /* take ownership on the AUX IF */ | |
708 | iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); | |
709 | iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); | |
710 | ||
711 | do { | |
712 | iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); | |
713 | val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); | |
714 | if (val == 0x1) { | |
715 | iwl_write_prph(trans, RSA_ENABLE, 0); | |
716 | return 0; | |
717 | } | |
718 | ||
719 | udelay(10); | |
720 | loop--; | |
721 | } while (loop > 0); | |
722 | ||
723 | IWL_ERR(trans, "Failed to take ownership on secure machine\n"); | |
724 | return -EIO; | |
725 | } | |
726 | ||
5dd9c68a EG |
727 | static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, |
728 | const struct fw_img *image, | |
729 | int cpu, | |
730 | int *first_ucode_section) | |
e2d6f4e7 EH |
731 | { |
732 | int shift_param; | |
dcab8ecd EH |
733 | int i, ret = 0, sec_num = 0x1; |
734 | u32 val, last_read_idx = 0; | |
e2d6f4e7 EH |
735 | |
736 | if (cpu == 1) { | |
737 | shift_param = 0; | |
034846cf | 738 | *first_ucode_section = 0; |
e2d6f4e7 EH |
739 | } else { |
740 | shift_param = 16; | |
034846cf | 741 | (*first_ucode_section)++; |
e2d6f4e7 EH |
742 | } |
743 | ||
034846cf EH |
744 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
745 | last_read_idx = i; | |
746 | ||
747 | if (!image->sec[i].data || | |
748 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) { | |
749 | IWL_DEBUG_FW(trans, | |
750 | "Break since Data not valid or Empty section, sec = %d\n", | |
751 | i); | |
189fa2fa | 752 | break; |
034846cf EH |
753 | } |
754 | ||
189fa2fa EH |
755 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
756 | if (ret) | |
757 | return ret; | |
dcab8ecd EH |
758 | |
759 | /* Notify the ucode of the loaded section number and status */ | |
760 | val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); | |
761 | val = val | (sec_num << shift_param); | |
762 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); | |
763 | sec_num = (sec_num << 1) | 0x1; | |
e2d6f4e7 EH |
764 | } |
765 | ||
034846cf EH |
766 | *first_ucode_section = last_read_idx; |
767 | ||
afb88917 EH |
768 | if (cpu == 1) |
769 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); | |
770 | else | |
771 | iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); | |
772 | ||
189fa2fa EH |
773 | return 0; |
774 | } | |
e2d6f4e7 | 775 | |
189fa2fa EH |
776 | static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, |
777 | const struct fw_img *image, | |
034846cf EH |
778 | int cpu, |
779 | int *first_ucode_section) | |
189fa2fa EH |
780 | { |
781 | int shift_param; | |
189fa2fa | 782 | int i, ret = 0; |
034846cf | 783 | u32 last_read_idx = 0; |
189fa2fa EH |
784 | |
785 | if (cpu == 1) { | |
786 | shift_param = 0; | |
034846cf | 787 | *first_ucode_section = 0; |
189fa2fa EH |
788 | } else { |
789 | shift_param = 16; | |
034846cf | 790 | (*first_ucode_section)++; |
189fa2fa EH |
791 | } |
792 | ||
034846cf EH |
793 | for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { |
794 | last_read_idx = i; | |
795 | ||
796 | if (!image->sec[i].data || | |
797 | image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) { | |
798 | IWL_DEBUG_FW(trans, | |
799 | "Break since Data not valid or Empty section, sec = %d\n", | |
800 | i); | |
189fa2fa | 801 | break; |
034846cf EH |
802 | } |
803 | ||
189fa2fa EH |
804 | ret = iwl_pcie_load_section(trans, i, &image->sec[i]); |
805 | if (ret) | |
806 | return ret; | |
e2d6f4e7 EH |
807 | } |
808 | ||
189fa2fa EH |
809 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
810 | iwl_set_bits_prph(trans, | |
811 | CSR_UCODE_LOAD_STATUS_ADDR, | |
812 | (LMPM_CPU_UCODE_LOADING_COMPLETED | | |
813 | LMPM_CPU_HDRS_LOADING_COMPLETED | | |
814 | LMPM_CPU_UCODE_LOADING_STARTED) << | |
815 | shift_param); | |
816 | ||
034846cf EH |
817 | *first_ucode_section = last_read_idx; |
818 | ||
e2d6f4e7 EH |
819 | return 0; |
820 | } | |
821 | ||
09e350f7 LK |
822 | static void iwl_pcie_apply_destination(struct iwl_trans *trans) |
823 | { | |
824 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
825 | const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; | |
826 | int i; | |
827 | ||
828 | if (dest->version) | |
829 | IWL_ERR(trans, | |
830 | "DBG DEST version is %d - expect issues\n", | |
831 | dest->version); | |
832 | ||
833 | IWL_INFO(trans, "Applying debug destination %s\n", | |
834 | get_fw_dbg_mode_string(dest->monitor_mode)); | |
835 | ||
836 | if (dest->monitor_mode == EXTERNAL_MODE) | |
837 | iwl_pcie_alloc_fw_monitor(trans); | |
838 | else | |
839 | IWL_WARN(trans, "PCI should have external buffer debug\n"); | |
840 | ||
841 | for (i = 0; i < trans->dbg_dest_reg_num; i++) { | |
842 | u32 addr = le32_to_cpu(dest->reg_ops[i].addr); | |
843 | u32 val = le32_to_cpu(dest->reg_ops[i].val); | |
844 | ||
845 | switch (dest->reg_ops[i].op) { | |
846 | case CSR_ASSIGN: | |
847 | iwl_write32(trans, addr, val); | |
848 | break; | |
849 | case CSR_SETBIT: | |
850 | iwl_set_bit(trans, addr, BIT(val)); | |
851 | break; | |
852 | case CSR_CLEARBIT: | |
853 | iwl_clear_bit(trans, addr, BIT(val)); | |
854 | break; | |
855 | case PRPH_ASSIGN: | |
856 | iwl_write_prph(trans, addr, val); | |
857 | break; | |
858 | case PRPH_SETBIT: | |
859 | iwl_set_bits_prph(trans, addr, BIT(val)); | |
860 | break; | |
861 | case PRPH_CLEARBIT: | |
862 | iwl_clear_bits_prph(trans, addr, BIT(val)); | |
863 | break; | |
864 | default: | |
865 | IWL_ERR(trans, "FW debug - unknown OP %d\n", | |
866 | dest->reg_ops[i].op); | |
867 | break; | |
868 | } | |
869 | } | |
870 | ||
871 | if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { | |
872 | iwl_write_prph(trans, le32_to_cpu(dest->base_reg), | |
873 | trans_pcie->fw_mon_phys >> dest->base_shift); | |
874 | iwl_write_prph(trans, le32_to_cpu(dest->end_reg), | |
875 | (trans_pcie->fw_mon_phys + | |
876 | trans_pcie->fw_mon_size) >> dest->end_shift); | |
877 | } | |
878 | } | |
879 | ||
7afe3705 | 880 | static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, |
0692fe41 | 881 | const struct fw_img *image) |
cf614297 | 882 | { |
c2d20201 | 883 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
189fa2fa | 884 | int ret = 0; |
034846cf | 885 | int first_ucode_section; |
cf614297 | 886 | |
dcab8ecd | 887 | IWL_DEBUG_FW(trans, "working with %s CPU\n", |
e2d6f4e7 EH |
888 | image->is_dual_cpus ? "Dual" : "Single"); |
889 | ||
dcab8ecd EH |
890 | /* load to FW the binary non secured sections of CPU1 */ |
891 | ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); | |
892 | if (ret) | |
893 | return ret; | |
e2d6f4e7 EH |
894 | |
895 | if (image->is_dual_cpus) { | |
189fa2fa EH |
896 | /* set CPU2 header address */ |
897 | iwl_write_prph(trans, | |
898 | LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, | |
899 | LMPM_SECURE_CPU2_HDR_MEM_SPACE); | |
e2d6f4e7 | 900 | |
189fa2fa | 901 | /* load to FW the binary sections of CPU2 */ |
dcab8ecd EH |
902 | ret = iwl_pcie_load_cpu_sections(trans, image, 2, |
903 | &first_ucode_section); | |
189fa2fa EH |
904 | if (ret) |
905 | return ret; | |
e2d6f4e7 | 906 | } |
cf614297 | 907 | |
c2d20201 EG |
908 | /* supported for 7000 only for the moment */ |
909 | if (iwlwifi_mod_params.fw_monitor && | |
910 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { | |
911 | iwl_pcie_alloc_fw_monitor(trans); | |
912 | ||
913 | if (trans_pcie->fw_mon_size) { | |
914 | iwl_write_prph(trans, MON_BUFF_BASE_ADDR, | |
915 | trans_pcie->fw_mon_phys >> 4); | |
916 | iwl_write_prph(trans, MON_BUFF_END_ADDR, | |
917 | (trans_pcie->fw_mon_phys + | |
918 | trans_pcie->fw_mon_size) >> 4); | |
919 | } | |
09e350f7 LK |
920 | } else if (trans->dbg_dest_tlv) { |
921 | iwl_pcie_apply_destination(trans); | |
c2d20201 EG |
922 | } |
923 | ||
e12ba844 | 924 | /* release CPU reset */ |
5dd9c68a | 925 | iwl_write32(trans, CSR_RESET, 0); |
e12ba844 | 926 | |
dcab8ecd EH |
927 | return 0; |
928 | } | |
189fa2fa | 929 | |
5dd9c68a EG |
930 | static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, |
931 | const struct fw_img *image) | |
dcab8ecd EH |
932 | { |
933 | int ret = 0; | |
934 | int first_ucode_section; | |
dcab8ecd EH |
935 | |
936 | IWL_DEBUG_FW(trans, "working with %s CPU\n", | |
937 | image->is_dual_cpus ? "Dual" : "Single"); | |
938 | ||
a2227ce2 EG |
939 | if (trans->dbg_dest_tlv) |
940 | iwl_pcie_apply_destination(trans); | |
941 | ||
16bc119b EH |
942 | /* TODO: remove in the next Si step */ |
943 | ret = iwl_pcie_rsa_race_bug_wa(trans); | |
944 | if (ret) | |
945 | return ret; | |
946 | ||
dcab8ecd EH |
947 | /* configure the ucode to be ready to get the secured image */ |
948 | /* release CPU reset */ | |
949 | iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); | |
950 | ||
951 | /* load to FW the binary Secured sections of CPU1 */ | |
5dd9c68a EG |
952 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, |
953 | &first_ucode_section); | |
dcab8ecd EH |
954 | if (ret) |
955 | return ret; | |
956 | ||
957 | /* load to FW the binary sections of CPU2 */ | |
5dd9c68a EG |
958 | ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2, |
959 | &first_ucode_section); | |
dcab8ecd EH |
960 | if (ret) |
961 | return ret; | |
962 | ||
cf614297 EG |
963 | return 0; |
964 | } | |
965 | ||
0692fe41 | 966 | static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, |
6ae02f3e | 967 | const struct fw_img *fw, bool run_in_rfkill) |
392f8b78 EG |
968 | { |
969 | int ret; | |
c9eec95c | 970 | bool hw_rfkill; |
392f8b78 | 971 | |
496bab39 | 972 | /* This may fail if AMT took ownership of the device */ |
7afe3705 | 973 | if (iwl_pcie_prepare_card_hw(trans)) { |
6d8f6eeb | 974 | IWL_WARN(trans, "Exit HW not ready\n"); |
392f8b78 EG |
975 | return -EIO; |
976 | } | |
977 | ||
8c46bb70 EG |
978 | iwl_enable_rfkill_int(trans); |
979 | ||
392f8b78 | 980 | /* If platform's RF_KILL switch is NOT set to KILL */ |
8d425517 | 981 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 982 | if (hw_rfkill) |
eb7ff77e | 983 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 984 | else |
eb7ff77e | 985 | clear_bit(STATUS_RFKILL, &trans->status); |
14cfca71 | 986 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
6ae02f3e | 987 | if (hw_rfkill && !run_in_rfkill) |
392f8b78 | 988 | return -ERFKILL; |
392f8b78 | 989 | |
1042db2a | 990 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
392f8b78 | 991 | |
7afe3705 | 992 | ret = iwl_pcie_nic_init(trans); |
392f8b78 | 993 | if (ret) { |
6d8f6eeb | 994 | IWL_ERR(trans, "Unable to init nic\n"); |
392f8b78 EG |
995 | return ret; |
996 | } | |
997 | ||
998 | /* make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
999 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1000 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, | |
392f8b78 EG |
1001 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1002 | ||
1003 | /* clear (again), then enable host interrupts */ | |
1042db2a | 1004 | iwl_write32(trans, CSR_INT, 0xFFFFFFFF); |
6d8f6eeb | 1005 | iwl_enable_interrupts(trans); |
392f8b78 EG |
1006 | |
1007 | /* really make sure rfkill handshake bits are cleared */ | |
1042db2a EG |
1008 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1009 | iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
392f8b78 | 1010 | |
cf614297 | 1011 | /* Load the given image to the HW */ |
5dd9c68a EG |
1012 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1013 | return iwl_pcie_load_given_ucode_8000(trans, fw); | |
dcab8ecd EH |
1014 | else |
1015 | return iwl_pcie_load_given_ucode(trans, fw); | |
b3c2ce13 EG |
1016 | } |
1017 | ||
adca1235 | 1018 | static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) |
ed6a3803 | 1019 | { |
990aa6d7 | 1020 | iwl_pcie_reset_ict(trans); |
f02831be | 1021 | iwl_pcie_tx_start(trans, scd_addr); |
c170b867 EG |
1022 | } |
1023 | ||
8d193ca2 | 1024 | static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) |
ae2c30bf | 1025 | { |
43e58856 | 1026 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
3dc3374f EG |
1027 | bool hw_rfkill, was_hw_rfkill; |
1028 | ||
1029 | was_hw_rfkill = iwl_is_rfkill_set(trans); | |
ae2c30bf | 1030 | |
43e58856 | 1031 | /* tell the device to stop sending interrupts */ |
7b70bd63 | 1032 | spin_lock(&trans_pcie->irq_lock); |
ae2c30bf | 1033 | iwl_disable_interrupts(trans); |
7b70bd63 | 1034 | spin_unlock(&trans_pcie->irq_lock); |
ae2c30bf | 1035 | |
ab6cf8e8 | 1036 | /* device going down, Stop using ICT table */ |
990aa6d7 | 1037 | iwl_pcie_disable_ict(trans); |
ab6cf8e8 EG |
1038 | |
1039 | /* | |
1040 | * If a HW restart happens during firmware loading, | |
1041 | * then the firmware loading might call this function | |
1042 | * and later it might be called again due to the | |
1043 | * restart. So don't process again if the device is | |
1044 | * already dead. | |
1045 | */ | |
31b8b343 EG |
1046 | if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { |
1047 | IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n"); | |
f02831be | 1048 | iwl_pcie_tx_stop(trans); |
9805c446 | 1049 | iwl_pcie_rx_stop(trans); |
6379103e | 1050 | |
ab6cf8e8 | 1051 | /* Power-down device's busmaster DMA clocks */ |
1042db2a | 1052 | iwl_write_prph(trans, APMG_CLK_DIS_REG, |
ab6cf8e8 EG |
1053 | APMG_CLK_VAL_DMA_CLK_RQT); |
1054 | udelay(5); | |
1055 | } | |
1056 | ||
1057 | /* Make sure (redundant) we've released our request to stay awake */ | |
1042db2a | 1058 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
20d3b647 | 1059 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
ab6cf8e8 EG |
1060 | |
1061 | /* Stop the device, and put it in low power state */ | |
b7aaeae4 | 1062 | iwl_pcie_apm_stop(trans, false); |
43e58856 | 1063 | |
03d6c3b0 EG |
1064 | /* stop and reset the on-board processor */ |
1065 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
1066 | udelay(20); | |
1067 | ||
1068 | /* | |
1069 | * Upon stop, the APM issues an interrupt if HW RF kill is set. | |
1070 | * This is a bug in certain verions of the hardware. | |
1071 | * Certain devices also keep sending HW RF kill interrupt all | |
1072 | * the time, unless the interrupt is ACKed even if the interrupt | |
1073 | * should be masked. Re-ACK all the interrupts here. | |
43e58856 | 1074 | */ |
7b70bd63 | 1075 | spin_lock(&trans_pcie->irq_lock); |
43e58856 | 1076 | iwl_disable_interrupts(trans); |
7b70bd63 | 1077 | spin_unlock(&trans_pcie->irq_lock); |
43e58856 | 1078 | |
74fda971 DF |
1079 | |
1080 | /* clear all status bits */ | |
eb7ff77e AN |
1081 | clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); |
1082 | clear_bit(STATUS_INT_ENABLED, &trans->status); | |
eb7ff77e AN |
1083 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
1084 | clear_bit(STATUS_RFKILL, &trans->status); | |
a4082843 AN |
1085 | |
1086 | /* | |
1087 | * Even if we stop the HW, we still want the RF kill | |
1088 | * interrupt | |
1089 | */ | |
1090 | iwl_enable_rfkill_int(trans); | |
1091 | ||
1092 | /* | |
1093 | * Check again since the RF kill state may have changed while | |
1094 | * all the interrupts were disabled, in this case we couldn't | |
1095 | * receive the RF kill interrupt and update the state in the | |
1096 | * op_mode. | |
3dc3374f EG |
1097 | * Don't call the op_mode if the rkfill state hasn't changed. |
1098 | * This allows the op_mode to call stop_device from the rfkill | |
1099 | * notification without endless recursion. Under very rare | |
1100 | * circumstances, we might have a small recursion if the rfkill | |
1101 | * state changed exactly now while we were called from stop_device. | |
1102 | * This is very unlikely but can happen and is supported. | |
a4082843 AN |
1103 | */ |
1104 | hw_rfkill = iwl_is_rfkill_set(trans); | |
1105 | if (hw_rfkill) | |
eb7ff77e | 1106 | set_bit(STATUS_RFKILL, &trans->status); |
a4082843 | 1107 | else |
eb7ff77e | 1108 | clear_bit(STATUS_RFKILL, &trans->status); |
3dc3374f | 1109 | if (hw_rfkill != was_hw_rfkill) |
14cfca71 | 1110 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
655e5cf0 EG |
1111 | |
1112 | /* re-take ownership to prevent other users from stealing the deivce */ | |
1113 | iwl_pcie_prepare_card_hw(trans); | |
14cfca71 JB |
1114 | } |
1115 | ||
1116 | void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) | |
1117 | { | |
1118 | if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) | |
8d193ca2 | 1119 | iwl_trans_pcie_stop_device(trans, true); |
ab6cf8e8 EG |
1120 | } |
1121 | ||
debff618 | 1122 | static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) |
2dd4f9f7 | 1123 | { |
2dd4f9f7 | 1124 | iwl_disable_interrupts(trans); |
debff618 JB |
1125 | |
1126 | /* | |
1127 | * in testing mode, the host stays awake and the | |
1128 | * hardware won't be reset (not even partially) | |
1129 | */ | |
1130 | if (test) | |
1131 | return; | |
1132 | ||
ddaf5a5b JB |
1133 | iwl_pcie_disable_ict(trans); |
1134 | ||
2dd4f9f7 JB |
1135 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1136 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
ddaf5a5b JB |
1137 | iwl_clear_bit(trans, CSR_GP_CNTRL, |
1138 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1139 | ||
1140 | /* | |
1141 | * reset TX queues -- some of their registers reset during S3 | |
1142 | * so if we don't reset everything here the D3 image would try | |
1143 | * to execute some invalid memory upon resume | |
1144 | */ | |
1145 | iwl_trans_pcie_tx_reset(trans); | |
1146 | ||
1147 | iwl_pcie_set_pwr(trans, true); | |
1148 | } | |
1149 | ||
1150 | static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, | |
debff618 JB |
1151 | enum iwl_d3_status *status, |
1152 | bool test) | |
ddaf5a5b JB |
1153 | { |
1154 | u32 val; | |
1155 | int ret; | |
1156 | ||
debff618 JB |
1157 | if (test) { |
1158 | iwl_enable_interrupts(trans); | |
1159 | *status = IWL_D3_STATUS_ALIVE; | |
1160 | return 0; | |
1161 | } | |
1162 | ||
ddaf5a5b JB |
1163 | /* |
1164 | * Also enables interrupts - none will happen as the device doesn't | |
1165 | * know we're waking it up, only when the opmode actually tells it | |
1166 | * after this call. | |
1167 | */ | |
1168 | iwl_pcie_reset_ict(trans); | |
1169 | ||
1170 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
1171 | iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1172 | ||
01e58a28 EG |
1173 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1174 | udelay(2); | |
1175 | ||
ddaf5a5b JB |
1176 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, |
1177 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1178 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
1179 | 25000); | |
7f2ac8fb | 1180 | if (ret < 0) { |
ddaf5a5b JB |
1181 | IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); |
1182 | return ret; | |
1183 | } | |
1184 | ||
a3ead656 EG |
1185 | iwl_pcie_set_pwr(trans, false); |
1186 | ||
ddaf5a5b JB |
1187 | iwl_trans_pcie_tx_reset(trans); |
1188 | ||
1189 | ret = iwl_pcie_rx_init(trans); | |
1190 | if (ret) { | |
1191 | IWL_ERR(trans, "Failed to resume the device (RX reset)\n"); | |
1192 | return ret; | |
1193 | } | |
1194 | ||
a3ead656 EG |
1195 | val = iwl_read32(trans, CSR_RESET); |
1196 | if (val & CSR_RESET_REG_FLAG_NEVO_RESET) | |
1197 | *status = IWL_D3_STATUS_RESET; | |
1198 | else | |
1199 | *status = IWL_D3_STATUS_ALIVE; | |
1200 | ||
ddaf5a5b | 1201 | return 0; |
2dd4f9f7 JB |
1202 | } |
1203 | ||
8d193ca2 | 1204 | static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) |
e6bb4c9c | 1205 | { |
c9eec95c | 1206 | bool hw_rfkill; |
a8b691e6 | 1207 | int err; |
e6bb4c9c | 1208 | |
7afe3705 | 1209 | err = iwl_pcie_prepare_card_hw(trans); |
ebb7678d | 1210 | if (err) { |
d6f1c316 | 1211 | IWL_ERR(trans, "Error while preparing HW: %d\n", err); |
a8b691e6 | 1212 | return err; |
ebb7678d | 1213 | } |
a6c684ee | 1214 | |
2997494f | 1215 | /* Reset the entire device */ |
ce836c76 | 1216 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
2997494f EG |
1217 | |
1218 | usleep_range(10, 15); | |
1219 | ||
7afe3705 | 1220 | iwl_pcie_apm_init(trans); |
a6c684ee | 1221 | |
226c02ca EG |
1222 | /* From now on, the op_mode will be kept updated about RF kill state */ |
1223 | iwl_enable_rfkill_int(trans); | |
1224 | ||
8d425517 | 1225 | hw_rfkill = iwl_is_rfkill_set(trans); |
4620020b | 1226 | if (hw_rfkill) |
eb7ff77e | 1227 | set_bit(STATUS_RFKILL, &trans->status); |
4620020b | 1228 | else |
eb7ff77e | 1229 | clear_bit(STATUS_RFKILL, &trans->status); |
14cfca71 | 1230 | iwl_trans_pcie_rf_kill(trans, hw_rfkill); |
d48e2074 | 1231 | |
a8b691e6 | 1232 | return 0; |
e6bb4c9c EG |
1233 | } |
1234 | ||
a4082843 | 1235 | static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) |
cc56feb2 | 1236 | { |
20d3b647 | 1237 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
d23f78e6 | 1238 | |
a4082843 | 1239 | /* disable interrupts - don't enable HW RF kill interrupt */ |
7b70bd63 | 1240 | spin_lock(&trans_pcie->irq_lock); |
ee7d737c | 1241 | iwl_disable_interrupts(trans); |
7b70bd63 | 1242 | spin_unlock(&trans_pcie->irq_lock); |
ee7d737c | 1243 | |
b7aaeae4 | 1244 | iwl_pcie_apm_stop(trans, true); |
cc56feb2 | 1245 | |
7b70bd63 | 1246 | spin_lock(&trans_pcie->irq_lock); |
218733cf | 1247 | iwl_disable_interrupts(trans); |
7b70bd63 | 1248 | spin_unlock(&trans_pcie->irq_lock); |
1df06bdc | 1249 | |
8d96bb61 | 1250 | iwl_pcie_disable_ict(trans); |
cc56feb2 EG |
1251 | } |
1252 | ||
03905495 EG |
1253 | static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) |
1254 | { | |
05f5b97e | 1255 | writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1256 | } |
1257 | ||
1258 | static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) | |
1259 | { | |
05f5b97e | 1260 | writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1261 | } |
1262 | ||
1263 | static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) | |
1264 | { | |
05f5b97e | 1265 | return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); |
03905495 EG |
1266 | } |
1267 | ||
6a06b6c1 EG |
1268 | static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) |
1269 | { | |
f9477c17 AP |
1270 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, |
1271 | ((reg & 0x000FFFFF) | (3 << 24))); | |
6a06b6c1 EG |
1272 | return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); |
1273 | } | |
1274 | ||
1275 | static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, | |
1276 | u32 val) | |
1277 | { | |
1278 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, | |
f9477c17 | 1279 | ((addr & 0x000FFFFF) | (3 << 24))); |
6a06b6c1 EG |
1280 | iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); |
1281 | } | |
1282 | ||
f14d6b39 JB |
1283 | static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) |
1284 | { | |
1285 | WARN_ON(1); | |
1286 | return 0; | |
1287 | } | |
1288 | ||
c6f600fc | 1289 | static void iwl_trans_pcie_configure(struct iwl_trans *trans, |
9eae88fa | 1290 | const struct iwl_trans_config *trans_cfg) |
c6f600fc MV |
1291 | { |
1292 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1293 | ||
1294 | trans_pcie->cmd_queue = trans_cfg->cmd_queue; | |
b04db9ac | 1295 | trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; |
4cf677fd | 1296 | trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; |
d663ee73 JB |
1297 | if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) |
1298 | trans_pcie->n_no_reclaim_cmds = 0; | |
1299 | else | |
1300 | trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; | |
1301 | if (trans_pcie->n_no_reclaim_cmds) | |
1302 | memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, | |
1303 | trans_pcie->n_no_reclaim_cmds * sizeof(u8)); | |
9eae88fa | 1304 | |
b2cf410c JB |
1305 | trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k; |
1306 | if (trans_pcie->rx_buf_size_8k) | |
1307 | trans_pcie->rx_page_order = get_order(8 * 1024); | |
1308 | else | |
1309 | trans_pcie->rx_page_order = get_order(4 * 1024); | |
7c5ba4a8 | 1310 | |
d9fb6465 | 1311 | trans_pcie->command_names = trans_cfg->command_names; |
046db346 | 1312 | trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; |
3a736bcb | 1313 | trans_pcie->scd_set_active = trans_cfg->scd_set_active; |
f14d6b39 | 1314 | |
483f3ab1 EP |
1315 | /* init ref_count to 1 (should be cleared when ucode is loaded) */ |
1316 | trans_pcie->ref_count = 1; | |
1317 | ||
f14d6b39 JB |
1318 | /* Initialize NAPI here - it should be before registering to mac80211 |
1319 | * in the opmode but after the HW struct is allocated. | |
1320 | * As this function may be called again in some corner cases don't | |
1321 | * do anything if NAPI was already initialized. | |
1322 | */ | |
1323 | if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) { | |
1324 | init_dummy_netdev(&trans_pcie->napi_dev); | |
1325 | iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi, | |
1326 | &trans_pcie->napi_dev, | |
1327 | iwl_pcie_dummy_napi_poll, 64); | |
1328 | } | |
c6f600fc MV |
1329 | } |
1330 | ||
d1ff5253 | 1331 | void iwl_trans_pcie_free(struct iwl_trans *trans) |
34c1b7ba | 1332 | { |
20d3b647 | 1333 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
a42a1844 | 1334 | |
0aa86df6 | 1335 | synchronize_irq(trans_pcie->pci_dev->irq); |
0aa86df6 | 1336 | |
f02831be | 1337 | iwl_pcie_tx_free(trans); |
9805c446 | 1338 | iwl_pcie_rx_free(trans); |
6379103e | 1339 | |
a8b691e6 JB |
1340 | free_irq(trans_pcie->pci_dev->irq, trans); |
1341 | iwl_pcie_free_ict(trans); | |
a42a1844 EG |
1342 | |
1343 | pci_disable_msi(trans_pcie->pci_dev); | |
05f5b97e | 1344 | iounmap(trans_pcie->hw_base); |
a42a1844 EG |
1345 | pci_release_regions(trans_pcie->pci_dev); |
1346 | pci_disable_device(trans_pcie->pci_dev); | |
59c647b6 | 1347 | kmem_cache_destroy(trans->dev_cmd_pool); |
a42a1844 | 1348 | |
f14d6b39 JB |
1349 | if (trans_pcie->napi.poll) |
1350 | netif_napi_del(&trans_pcie->napi); | |
1351 | ||
c2d20201 EG |
1352 | iwl_pcie_free_fw_monitor(trans); |
1353 | ||
6d8f6eeb | 1354 | kfree(trans); |
34c1b7ba EG |
1355 | } |
1356 | ||
47107e84 DF |
1357 | static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) |
1358 | { | |
47107e84 | 1359 | if (state) |
eb7ff77e | 1360 | set_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 | 1361 | else |
eb7ff77e | 1362 | clear_bit(STATUS_TPOWER_PMI, &trans->status); |
47107e84 DF |
1363 | } |
1364 | ||
e56b04ef LE |
1365 | static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent, |
1366 | unsigned long *flags) | |
7a65d170 EG |
1367 | { |
1368 | int ret; | |
cfb4e624 JB |
1369 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1370 | ||
1371 | spin_lock_irqsave(&trans_pcie->reg_lock, *flags); | |
7a65d170 | 1372 | |
b9439491 EG |
1373 | if (trans_pcie->cmd_in_flight) |
1374 | goto out; | |
1375 | ||
7a65d170 | 1376 | /* this bit wakes up the NIC */ |
e139dc4a LE |
1377 | __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, |
1378 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
01e58a28 EG |
1379 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) |
1380 | udelay(2); | |
7a65d170 EG |
1381 | |
1382 | /* | |
1383 | * These bits say the device is running, and should keep running for | |
1384 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | |
1385 | * but they do not indicate that embedded SRAM is restored yet; | |
1386 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | |
1387 | * to/from host DRAM when sleeping/waking for power-saving. | |
1388 | * Each direction takes approximately 1/4 millisecond; with this | |
1389 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | |
1390 | * series of register accesses are expected (e.g. reading Event Log), | |
1391 | * to keep device from sleeping. | |
1392 | * | |
1393 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | |
1394 | * SRAM is okay/restored. We don't check that here because this call | |
1395 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | |
1396 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | |
1397 | * | |
1398 | * 5000 series and later (including 1000 series) have non-volatile SRAM, | |
1399 | * and do not save/restore SRAM when power cycling. | |
1400 | */ | |
1401 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
1402 | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | |
1403 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | |
1404 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | |
1405 | if (unlikely(ret < 0)) { | |
1406 | iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | |
1407 | if (!silent) { | |
1408 | u32 val = iwl_read32(trans, CSR_GP_CNTRL); | |
1409 | WARN_ONCE(1, | |
1410 | "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", | |
1411 | val); | |
cfb4e624 | 1412 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1413 | return false; |
1414 | } | |
1415 | } | |
1416 | ||
b9439491 | 1417 | out: |
e56b04ef LE |
1418 | /* |
1419 | * Fool sparse by faking we release the lock - sparse will | |
1420 | * track nic_access anyway. | |
1421 | */ | |
cfb4e624 | 1422 | __release(&trans_pcie->reg_lock); |
7a65d170 EG |
1423 | return true; |
1424 | } | |
1425 | ||
e56b04ef LE |
1426 | static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, |
1427 | unsigned long *flags) | |
7a65d170 | 1428 | { |
cfb4e624 | 1429 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e56b04ef | 1430 | |
cfb4e624 | 1431 | lockdep_assert_held(&trans_pcie->reg_lock); |
e56b04ef LE |
1432 | |
1433 | /* | |
1434 | * Fool sparse by faking we acquiring the lock - sparse will | |
1435 | * track nic_access anyway. | |
1436 | */ | |
cfb4e624 | 1437 | __acquire(&trans_pcie->reg_lock); |
e56b04ef | 1438 | |
b9439491 EG |
1439 | if (trans_pcie->cmd_in_flight) |
1440 | goto out; | |
1441 | ||
e139dc4a LE |
1442 | __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, |
1443 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
7a65d170 EG |
1444 | /* |
1445 | * Above we read the CSR_GP_CNTRL register, which will flush | |
1446 | * any previous writes, but we need the write that clears the | |
1447 | * MAC_ACCESS_REQ bit to be performed before any other writes | |
1448 | * scheduled on different CPUs (after we drop reg_lock). | |
1449 | */ | |
1450 | mmiowb(); | |
b9439491 | 1451 | out: |
cfb4e624 | 1452 | spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); |
7a65d170 EG |
1453 | } |
1454 | ||
4fd442db EG |
1455 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, |
1456 | void *buf, int dwords) | |
1457 | { | |
1458 | unsigned long flags; | |
1459 | int offs, ret = 0; | |
1460 | u32 *vals = buf; | |
1461 | ||
e56b04ef | 1462 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1463 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); |
1464 | for (offs = 0; offs < dwords; offs++) | |
1465 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | |
e56b04ef | 1466 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1467 | } else { |
1468 | ret = -EBUSY; | |
1469 | } | |
4fd442db EG |
1470 | return ret; |
1471 | } | |
1472 | ||
1473 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | |
bf0fd5da | 1474 | const void *buf, int dwords) |
4fd442db EG |
1475 | { |
1476 | unsigned long flags; | |
1477 | int offs, ret = 0; | |
bf0fd5da | 1478 | const u32 *vals = buf; |
4fd442db | 1479 | |
e56b04ef | 1480 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { |
4fd442db EG |
1481 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); |
1482 | for (offs = 0; offs < dwords; offs++) | |
01387ffd EG |
1483 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, |
1484 | vals ? vals[offs] : 0); | |
e56b04ef | 1485 | iwl_trans_release_nic_access(trans, &flags); |
4fd442db EG |
1486 | } else { |
1487 | ret = -EBUSY; | |
1488 | } | |
4fd442db EG |
1489 | return ret; |
1490 | } | |
7a65d170 | 1491 | |
e0b8d405 EG |
1492 | static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, |
1493 | unsigned long txqs, | |
1494 | bool freeze) | |
1495 | { | |
1496 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1497 | int queue; | |
1498 | ||
1499 | for_each_set_bit(queue, &txqs, BITS_PER_LONG) { | |
1500 | struct iwl_txq *txq = &trans_pcie->txq[queue]; | |
1501 | unsigned long now; | |
1502 | ||
1503 | spin_lock_bh(&txq->lock); | |
1504 | ||
1505 | now = jiffies; | |
1506 | ||
1507 | if (txq->frozen == freeze) | |
1508 | goto next_queue; | |
1509 | ||
1510 | IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", | |
1511 | freeze ? "Freezing" : "Waking", queue); | |
1512 | ||
1513 | txq->frozen = freeze; | |
1514 | ||
1515 | if (txq->q.read_ptr == txq->q.write_ptr) | |
1516 | goto next_queue; | |
1517 | ||
1518 | if (freeze) { | |
1519 | if (unlikely(time_after(now, | |
1520 | txq->stuck_timer.expires))) { | |
1521 | /* | |
1522 | * The timer should have fired, maybe it is | |
1523 | * spinning right now on the lock. | |
1524 | */ | |
1525 | goto next_queue; | |
1526 | } | |
1527 | /* remember how long until the timer fires */ | |
1528 | txq->frozen_expiry_remainder = | |
1529 | txq->stuck_timer.expires - now; | |
1530 | del_timer(&txq->stuck_timer); | |
1531 | goto next_queue; | |
1532 | } | |
1533 | ||
1534 | /* | |
1535 | * Wake a non-empty queue -> arm timer with the | |
1536 | * remainder before it froze | |
1537 | */ | |
1538 | mod_timer(&txq->stuck_timer, | |
1539 | now + txq->frozen_expiry_remainder); | |
1540 | ||
1541 | next_queue: | |
1542 | spin_unlock_bh(&txq->lock); | |
1543 | } | |
1544 | } | |
1545 | ||
5f178cd2 EG |
1546 | #define IWL_FLUSH_WAIT_MS 2000 |
1547 | ||
3cafdbe6 | 1548 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) |
5f178cd2 | 1549 | { |
8ad71bef | 1550 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1551 | struct iwl_txq *txq; |
5f178cd2 EG |
1552 | struct iwl_queue *q; |
1553 | int cnt; | |
1554 | unsigned long now = jiffies; | |
1c3fea82 EG |
1555 | u32 scd_sram_addr; |
1556 | u8 buf[16]; | |
5f178cd2 EG |
1557 | int ret = 0; |
1558 | ||
1559 | /* waiting for all the tx frames complete might take a while */ | |
035f7ff2 | 1560 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
fa1a91fd EG |
1561 | u8 wr_ptr; |
1562 | ||
9ba1947a | 1563 | if (cnt == trans_pcie->cmd_queue) |
5f178cd2 | 1564 | continue; |
3cafdbe6 EG |
1565 | if (!test_bit(cnt, trans_pcie->queue_used)) |
1566 | continue; | |
1567 | if (!(BIT(cnt) & txq_bm)) | |
1568 | continue; | |
748fa67c EG |
1569 | |
1570 | IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); | |
8ad71bef | 1571 | txq = &trans_pcie->txq[cnt]; |
5f178cd2 | 1572 | q = &txq->q; |
fa1a91fd EG |
1573 | wr_ptr = ACCESS_ONCE(q->write_ptr); |
1574 | ||
1575 | while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && | |
1576 | !time_after(jiffies, | |
1577 | now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { | |
1578 | u8 write_ptr = ACCESS_ONCE(q->write_ptr); | |
1579 | ||
1580 | if (WARN_ONCE(wr_ptr != write_ptr, | |
1581 | "WR pointer moved while flushing %d -> %d\n", | |
1582 | wr_ptr, write_ptr)) | |
1583 | return -ETIMEDOUT; | |
5f178cd2 | 1584 | msleep(1); |
fa1a91fd | 1585 | } |
5f178cd2 EG |
1586 | |
1587 | if (q->read_ptr != q->write_ptr) { | |
1c3fea82 EG |
1588 | IWL_ERR(trans, |
1589 | "fail to flush all tx fifo queues Q %d\n", cnt); | |
5f178cd2 EG |
1590 | ret = -ETIMEDOUT; |
1591 | break; | |
1592 | } | |
748fa67c | 1593 | IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); |
5f178cd2 | 1594 | } |
1c3fea82 EG |
1595 | |
1596 | if (!ret) | |
1597 | return 0; | |
1598 | ||
1599 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
1600 | txq->q.read_ptr, txq->q.write_ptr); | |
1601 | ||
1602 | scd_sram_addr = trans_pcie->scd_base_addr + | |
1603 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
1604 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | |
1605 | ||
1606 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
1607 | ||
1608 | for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) | |
1609 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, | |
1610 | iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); | |
1611 | ||
1612 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { | |
1613 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); | |
1614 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
1615 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
1616 | u32 tbl_dw = | |
1617 | iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + | |
1618 | SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); | |
1619 | ||
1620 | if (cnt & 0x1) | |
1621 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
1622 | else | |
1623 | tbl_dw = tbl_dw & 0x0000FFFF; | |
1624 | ||
1625 | IWL_ERR(trans, | |
1626 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
1627 | cnt, active ? "" : "in", fifo, tbl_dw, | |
83f32a4b JB |
1628 | iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & |
1629 | (TFD_QUEUE_SIZE_MAX - 1), | |
1c3fea82 EG |
1630 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
1631 | } | |
1632 | ||
5f178cd2 EG |
1633 | return ret; |
1634 | } | |
1635 | ||
e139dc4a LE |
1636 | static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, |
1637 | u32 mask, u32 value) | |
1638 | { | |
e56b04ef | 1639 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
e139dc4a LE |
1640 | unsigned long flags; |
1641 | ||
e56b04ef | 1642 | spin_lock_irqsave(&trans_pcie->reg_lock, flags); |
e139dc4a | 1643 | __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); |
e56b04ef | 1644 | spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); |
e139dc4a LE |
1645 | } |
1646 | ||
7616f334 EP |
1647 | void iwl_trans_pcie_ref(struct iwl_trans *trans) |
1648 | { | |
1649 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1650 | unsigned long flags; | |
1651 | ||
1652 | if (iwlwifi_mod_params.d0i3_disable) | |
1653 | return; | |
1654 | ||
1655 | spin_lock_irqsave(&trans_pcie->ref_lock, flags); | |
1656 | IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); | |
1657 | trans_pcie->ref_count++; | |
1658 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1659 | } | |
1660 | ||
1661 | void iwl_trans_pcie_unref(struct iwl_trans *trans) | |
1662 | { | |
1663 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
1664 | unsigned long flags; | |
1665 | ||
1666 | if (iwlwifi_mod_params.d0i3_disable) | |
1667 | return; | |
1668 | ||
1669 | spin_lock_irqsave(&trans_pcie->ref_lock, flags); | |
1670 | IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); | |
1671 | if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) { | |
1672 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1673 | return; | |
1674 | } | |
1675 | trans_pcie->ref_count--; | |
1676 | spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); | |
1677 | } | |
1678 | ||
ff620849 EG |
1679 | static const char *get_csr_string(int cmd) |
1680 | { | |
d9fb6465 | 1681 | #define IWL_CMD(x) case x: return #x |
ff620849 EG |
1682 | switch (cmd) { |
1683 | IWL_CMD(CSR_HW_IF_CONFIG_REG); | |
1684 | IWL_CMD(CSR_INT_COALESCING); | |
1685 | IWL_CMD(CSR_INT); | |
1686 | IWL_CMD(CSR_INT_MASK); | |
1687 | IWL_CMD(CSR_FH_INT_STATUS); | |
1688 | IWL_CMD(CSR_GPIO_IN); | |
1689 | IWL_CMD(CSR_RESET); | |
1690 | IWL_CMD(CSR_GP_CNTRL); | |
1691 | IWL_CMD(CSR_HW_REV); | |
1692 | IWL_CMD(CSR_EEPROM_REG); | |
1693 | IWL_CMD(CSR_EEPROM_GP); | |
1694 | IWL_CMD(CSR_OTP_GP_REG); | |
1695 | IWL_CMD(CSR_GIO_REG); | |
1696 | IWL_CMD(CSR_GP_UCODE_REG); | |
1697 | IWL_CMD(CSR_GP_DRIVER_REG); | |
1698 | IWL_CMD(CSR_UCODE_DRV_GP1); | |
1699 | IWL_CMD(CSR_UCODE_DRV_GP2); | |
1700 | IWL_CMD(CSR_LED_REG); | |
1701 | IWL_CMD(CSR_DRAM_INT_TBL_REG); | |
1702 | IWL_CMD(CSR_GIO_CHICKEN_BITS); | |
1703 | IWL_CMD(CSR_ANA_PLL_CFG); | |
1704 | IWL_CMD(CSR_HW_REV_WA_REG); | |
a812cba9 | 1705 | IWL_CMD(CSR_MONITOR_STATUS_REG); |
ff620849 EG |
1706 | IWL_CMD(CSR_DBG_HPET_MEM_REG); |
1707 | default: | |
1708 | return "UNKNOWN"; | |
1709 | } | |
d9fb6465 | 1710 | #undef IWL_CMD |
ff620849 EG |
1711 | } |
1712 | ||
990aa6d7 | 1713 | void iwl_pcie_dump_csr(struct iwl_trans *trans) |
ff620849 EG |
1714 | { |
1715 | int i; | |
1716 | static const u32 csr_tbl[] = { | |
1717 | CSR_HW_IF_CONFIG_REG, | |
1718 | CSR_INT_COALESCING, | |
1719 | CSR_INT, | |
1720 | CSR_INT_MASK, | |
1721 | CSR_FH_INT_STATUS, | |
1722 | CSR_GPIO_IN, | |
1723 | CSR_RESET, | |
1724 | CSR_GP_CNTRL, | |
1725 | CSR_HW_REV, | |
1726 | CSR_EEPROM_REG, | |
1727 | CSR_EEPROM_GP, | |
1728 | CSR_OTP_GP_REG, | |
1729 | CSR_GIO_REG, | |
1730 | CSR_GP_UCODE_REG, | |
1731 | CSR_GP_DRIVER_REG, | |
1732 | CSR_UCODE_DRV_GP1, | |
1733 | CSR_UCODE_DRV_GP2, | |
1734 | CSR_LED_REG, | |
1735 | CSR_DRAM_INT_TBL_REG, | |
1736 | CSR_GIO_CHICKEN_BITS, | |
1737 | CSR_ANA_PLL_CFG, | |
a812cba9 | 1738 | CSR_MONITOR_STATUS_REG, |
ff620849 EG |
1739 | CSR_HW_REV_WA_REG, |
1740 | CSR_DBG_HPET_MEM_REG | |
1741 | }; | |
1742 | IWL_ERR(trans, "CSR values:\n"); | |
1743 | IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " | |
1744 | "CSR_INT_PERIODIC_REG)\n"); | |
1745 | for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { | |
1746 | IWL_ERR(trans, " %25s: 0X%08x\n", | |
1747 | get_csr_string(csr_tbl[i]), | |
1042db2a | 1748 | iwl_read32(trans, csr_tbl[i])); |
ff620849 EG |
1749 | } |
1750 | } | |
1751 | ||
87e5666c EG |
1752 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1753 | /* create and remove of files */ | |
1754 | #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ | |
5a878bf6 | 1755 | if (!debugfs_create_file(#name, mode, parent, trans, \ |
87e5666c | 1756 | &iwl_dbgfs_##name##_ops)) \ |
9da987ac | 1757 | goto err; \ |
87e5666c EG |
1758 | } while (0) |
1759 | ||
1760 | /* file operation */ | |
87e5666c | 1761 | #define DEBUGFS_READ_FILE_OPS(name) \ |
87e5666c EG |
1762 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1763 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1764 | .open = simple_open, \ |
87e5666c EG |
1765 | .llseek = generic_file_llseek, \ |
1766 | }; | |
1767 | ||
16db88ba | 1768 | #define DEBUGFS_WRITE_FILE_OPS(name) \ |
16db88ba EG |
1769 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1770 | .write = iwl_dbgfs_##name##_write, \ | |
234e3405 | 1771 | .open = simple_open, \ |
16db88ba EG |
1772 | .llseek = generic_file_llseek, \ |
1773 | }; | |
1774 | ||
87e5666c | 1775 | #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ |
87e5666c EG |
1776 | static const struct file_operations iwl_dbgfs_##name##_ops = { \ |
1777 | .write = iwl_dbgfs_##name##_write, \ | |
1778 | .read = iwl_dbgfs_##name##_read, \ | |
234e3405 | 1779 | .open = simple_open, \ |
87e5666c EG |
1780 | .llseek = generic_file_llseek, \ |
1781 | }; | |
1782 | ||
87e5666c | 1783 | static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, |
20d3b647 JB |
1784 | char __user *user_buf, |
1785 | size_t count, loff_t *ppos) | |
8ad71bef | 1786 | { |
5a878bf6 | 1787 | struct iwl_trans *trans = file->private_data; |
8ad71bef | 1788 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1789 | struct iwl_txq *txq; |
87e5666c EG |
1790 | struct iwl_queue *q; |
1791 | char *buf; | |
1792 | int pos = 0; | |
1793 | int cnt; | |
1794 | int ret; | |
1745e440 WYG |
1795 | size_t bufsz; |
1796 | ||
e0b8d405 | 1797 | bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; |
87e5666c | 1798 | |
f9e75447 | 1799 | if (!trans_pcie->txq) |
87e5666c | 1800 | return -EAGAIN; |
f9e75447 | 1801 | |
87e5666c EG |
1802 | buf = kzalloc(bufsz, GFP_KERNEL); |
1803 | if (!buf) | |
1804 | return -ENOMEM; | |
1805 | ||
035f7ff2 | 1806 | for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
8ad71bef | 1807 | txq = &trans_pcie->txq[cnt]; |
87e5666c EG |
1808 | q = &txq->q; |
1809 | pos += scnprintf(buf + pos, bufsz - pos, | |
e0b8d405 | 1810 | "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", |
87e5666c | 1811 | cnt, q->read_ptr, q->write_ptr, |
9eae88fa | 1812 | !!test_bit(cnt, trans_pcie->queue_used), |
f40faf62 | 1813 | !!test_bit(cnt, trans_pcie->queue_stopped), |
e0b8d405 | 1814 | txq->need_update, txq->frozen, |
f40faf62 | 1815 | (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); |
87e5666c EG |
1816 | } |
1817 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1818 | kfree(buf); | |
1819 | return ret; | |
1820 | } | |
1821 | ||
1822 | static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, | |
20d3b647 JB |
1823 | char __user *user_buf, |
1824 | size_t count, loff_t *ppos) | |
1825 | { | |
5a878bf6 | 1826 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1827 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1828 | struct iwl_rxq *rxq = &trans_pcie->rxq; |
87e5666c EG |
1829 | char buf[256]; |
1830 | int pos = 0; | |
1831 | const size_t bufsz = sizeof(buf); | |
1832 | ||
1833 | pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", | |
1834 | rxq->read); | |
1835 | pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", | |
1836 | rxq->write); | |
f40faf62 AL |
1837 | pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n", |
1838 | rxq->write_actual); | |
1839 | pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n", | |
1840 | rxq->need_update); | |
87e5666c EG |
1841 | pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", |
1842 | rxq->free_count); | |
1843 | if (rxq->rb_stts) { | |
1844 | pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", | |
1845 | le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); | |
1846 | } else { | |
1847 | pos += scnprintf(buf + pos, bufsz - pos, | |
1848 | "closed_rb_num: Not Allocated\n"); | |
1849 | } | |
1850 | return simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1851 | } | |
1852 | ||
1f7b6172 EG |
1853 | static ssize_t iwl_dbgfs_interrupt_read(struct file *file, |
1854 | char __user *user_buf, | |
20d3b647 JB |
1855 | size_t count, loff_t *ppos) |
1856 | { | |
1f7b6172 | 1857 | struct iwl_trans *trans = file->private_data; |
20d3b647 | 1858 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1859 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1860 | ||
1861 | int pos = 0; | |
1862 | char *buf; | |
1863 | int bufsz = 24 * 64; /* 24 items * 64 char per item */ | |
1864 | ssize_t ret; | |
1865 | ||
1866 | buf = kzalloc(bufsz, GFP_KERNEL); | |
f9e75447 | 1867 | if (!buf) |
1f7b6172 | 1868 | return -ENOMEM; |
1f7b6172 EG |
1869 | |
1870 | pos += scnprintf(buf + pos, bufsz - pos, | |
1871 | "Interrupt Statistics Report:\n"); | |
1872 | ||
1873 | pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", | |
1874 | isr_stats->hw); | |
1875 | pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", | |
1876 | isr_stats->sw); | |
1877 | if (isr_stats->sw || isr_stats->hw) { | |
1878 | pos += scnprintf(buf + pos, bufsz - pos, | |
1879 | "\tLast Restarting Code: 0x%X\n", | |
1880 | isr_stats->err_code); | |
1881 | } | |
1882 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1883 | pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", | |
1884 | isr_stats->sch); | |
1885 | pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", | |
1886 | isr_stats->alive); | |
1887 | #endif | |
1888 | pos += scnprintf(buf + pos, bufsz - pos, | |
1889 | "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); | |
1890 | ||
1891 | pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", | |
1892 | isr_stats->ctkill); | |
1893 | ||
1894 | pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", | |
1895 | isr_stats->wakeup); | |
1896 | ||
1897 | pos += scnprintf(buf + pos, bufsz - pos, | |
1898 | "Rx command responses:\t\t %u\n", isr_stats->rx); | |
1899 | ||
1900 | pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", | |
1901 | isr_stats->tx); | |
1902 | ||
1903 | pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", | |
1904 | isr_stats->unhandled); | |
1905 | ||
1906 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); | |
1907 | kfree(buf); | |
1908 | return ret; | |
1909 | } | |
1910 | ||
1911 | static ssize_t iwl_dbgfs_interrupt_write(struct file *file, | |
1912 | const char __user *user_buf, | |
1913 | size_t count, loff_t *ppos) | |
1914 | { | |
1915 | struct iwl_trans *trans = file->private_data; | |
20d3b647 | 1916 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1f7b6172 EG |
1917 | struct isr_statistics *isr_stats = &trans_pcie->isr_stats; |
1918 | ||
1919 | char buf[8]; | |
1920 | int buf_size; | |
1921 | u32 reset_flag; | |
1922 | ||
1923 | memset(buf, 0, sizeof(buf)); | |
1924 | buf_size = min(count, sizeof(buf) - 1); | |
1925 | if (copy_from_user(buf, user_buf, buf_size)) | |
1926 | return -EFAULT; | |
1927 | if (sscanf(buf, "%x", &reset_flag) != 1) | |
1928 | return -EFAULT; | |
1929 | if (reset_flag == 0) | |
1930 | memset(isr_stats, 0, sizeof(*isr_stats)); | |
1931 | ||
1932 | return count; | |
1933 | } | |
1934 | ||
16db88ba | 1935 | static ssize_t iwl_dbgfs_csr_write(struct file *file, |
20d3b647 JB |
1936 | const char __user *user_buf, |
1937 | size_t count, loff_t *ppos) | |
16db88ba EG |
1938 | { |
1939 | struct iwl_trans *trans = file->private_data; | |
1940 | char buf[8]; | |
1941 | int buf_size; | |
1942 | int csr; | |
1943 | ||
1944 | memset(buf, 0, sizeof(buf)); | |
1945 | buf_size = min(count, sizeof(buf) - 1); | |
1946 | if (copy_from_user(buf, user_buf, buf_size)) | |
1947 | return -EFAULT; | |
1948 | if (sscanf(buf, "%d", &csr) != 1) | |
1949 | return -EFAULT; | |
1950 | ||
990aa6d7 | 1951 | iwl_pcie_dump_csr(trans); |
16db88ba EG |
1952 | |
1953 | return count; | |
1954 | } | |
1955 | ||
16db88ba | 1956 | static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, |
20d3b647 JB |
1957 | char __user *user_buf, |
1958 | size_t count, loff_t *ppos) | |
16db88ba EG |
1959 | { |
1960 | struct iwl_trans *trans = file->private_data; | |
94543a8d | 1961 | char *buf = NULL; |
56c2477f | 1962 | ssize_t ret; |
16db88ba | 1963 | |
56c2477f JB |
1964 | ret = iwl_dump_fh(trans, &buf); |
1965 | if (ret < 0) | |
1966 | return ret; | |
1967 | if (!buf) | |
1968 | return -EINVAL; | |
1969 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); | |
1970 | kfree(buf); | |
16db88ba EG |
1971 | return ret; |
1972 | } | |
1973 | ||
1f7b6172 | 1974 | DEBUGFS_READ_WRITE_FILE_OPS(interrupt); |
16db88ba | 1975 | DEBUGFS_READ_FILE_OPS(fh_reg); |
87e5666c EG |
1976 | DEBUGFS_READ_FILE_OPS(rx_queue); |
1977 | DEBUGFS_READ_FILE_OPS(tx_queue); | |
16db88ba | 1978 | DEBUGFS_WRITE_FILE_OPS(csr); |
87e5666c EG |
1979 | |
1980 | /* | |
1981 | * Create the debugfs files and directories | |
1982 | * | |
1983 | */ | |
1984 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
20d3b647 | 1985 | struct dentry *dir) |
87e5666c | 1986 | { |
87e5666c EG |
1987 | DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); |
1988 | DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); | |
1f7b6172 | 1989 | DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); |
16db88ba EG |
1990 | DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); |
1991 | DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); | |
87e5666c | 1992 | return 0; |
9da987ac MV |
1993 | |
1994 | err: | |
1995 | IWL_ERR(trans, "failed to create the trans debugfs entry\n"); | |
1996 | return -ENOMEM; | |
87e5666c | 1997 | } |
aadede6e JB |
1998 | #else |
1999 | static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans, | |
2000 | struct dentry *dir) | |
2001 | { | |
2002 | return 0; | |
2003 | } | |
2004 | #endif /*CONFIG_IWLWIFI_DEBUGFS */ | |
4d075007 JB |
2005 | |
2006 | static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) | |
2007 | { | |
2008 | u32 cmdlen = 0; | |
2009 | int i; | |
2010 | ||
2011 | for (i = 0; i < IWL_NUM_OF_TBS; i++) | |
2012 | cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); | |
2013 | ||
2014 | return cmdlen; | |
2015 | } | |
2016 | ||
67c65f2c EG |
2017 | static const struct { |
2018 | u32 start, end; | |
2019 | } iwl_prph_dump_addr[] = { | |
2020 | { .start = 0x00a00000, .end = 0x00a00000 }, | |
2021 | { .start = 0x00a0000c, .end = 0x00a00024 }, | |
2022 | { .start = 0x00a0002c, .end = 0x00a0003c }, | |
2023 | { .start = 0x00a00410, .end = 0x00a00418 }, | |
2024 | { .start = 0x00a00420, .end = 0x00a00420 }, | |
2025 | { .start = 0x00a00428, .end = 0x00a00428 }, | |
2026 | { .start = 0x00a00430, .end = 0x00a0043c }, | |
2027 | { .start = 0x00a00444, .end = 0x00a00444 }, | |
2028 | { .start = 0x00a004c0, .end = 0x00a004cc }, | |
2029 | { .start = 0x00a004d8, .end = 0x00a004d8 }, | |
2030 | { .start = 0x00a004e0, .end = 0x00a004f0 }, | |
2031 | { .start = 0x00a00840, .end = 0x00a00840 }, | |
2032 | { .start = 0x00a00850, .end = 0x00a00858 }, | |
2033 | { .start = 0x00a01004, .end = 0x00a01008 }, | |
2034 | { .start = 0x00a01010, .end = 0x00a01010 }, | |
2035 | { .start = 0x00a01018, .end = 0x00a01018 }, | |
2036 | { .start = 0x00a01024, .end = 0x00a01024 }, | |
2037 | { .start = 0x00a0102c, .end = 0x00a01034 }, | |
2038 | { .start = 0x00a0103c, .end = 0x00a01040 }, | |
2039 | { .start = 0x00a01048, .end = 0x00a01094 }, | |
2040 | { .start = 0x00a01c00, .end = 0x00a01c20 }, | |
2041 | { .start = 0x00a01c58, .end = 0x00a01c58 }, | |
2042 | { .start = 0x00a01c7c, .end = 0x00a01c7c }, | |
2043 | { .start = 0x00a01c28, .end = 0x00a01c54 }, | |
2044 | { .start = 0x00a01c5c, .end = 0x00a01c5c }, | |
6a65bd53 | 2045 | { .start = 0x00a01c60, .end = 0x00a01cdc }, |
67c65f2c EG |
2046 | { .start = 0x00a01ce0, .end = 0x00a01d0c }, |
2047 | { .start = 0x00a01d18, .end = 0x00a01d20 }, | |
2048 | { .start = 0x00a01d2c, .end = 0x00a01d30 }, | |
2049 | { .start = 0x00a01d40, .end = 0x00a01d5c }, | |
2050 | { .start = 0x00a01d80, .end = 0x00a01d80 }, | |
6a65bd53 EG |
2051 | { .start = 0x00a01d98, .end = 0x00a01d9c }, |
2052 | { .start = 0x00a01da8, .end = 0x00a01da8 }, | |
2053 | { .start = 0x00a01db8, .end = 0x00a01df4 }, | |
67c65f2c EG |
2054 | { .start = 0x00a01dc0, .end = 0x00a01dfc }, |
2055 | { .start = 0x00a01e00, .end = 0x00a01e2c }, | |
2056 | { .start = 0x00a01e40, .end = 0x00a01e60 }, | |
6a65bd53 EG |
2057 | { .start = 0x00a01e68, .end = 0x00a01e6c }, |
2058 | { .start = 0x00a01e74, .end = 0x00a01e74 }, | |
67c65f2c EG |
2059 | { .start = 0x00a01e84, .end = 0x00a01e90 }, |
2060 | { .start = 0x00a01e9c, .end = 0x00a01ec4 }, | |
6a65bd53 EG |
2061 | { .start = 0x00a01ed0, .end = 0x00a01ee0 }, |
2062 | { .start = 0x00a01f00, .end = 0x00a01f1c }, | |
2063 | { .start = 0x00a01f44, .end = 0x00a01ffc }, | |
67c65f2c EG |
2064 | { .start = 0x00a02000, .end = 0x00a02048 }, |
2065 | { .start = 0x00a02068, .end = 0x00a020f0 }, | |
2066 | { .start = 0x00a02100, .end = 0x00a02118 }, | |
2067 | { .start = 0x00a02140, .end = 0x00a0214c }, | |
2068 | { .start = 0x00a02168, .end = 0x00a0218c }, | |
2069 | { .start = 0x00a021c0, .end = 0x00a021c0 }, | |
2070 | { .start = 0x00a02400, .end = 0x00a02410 }, | |
2071 | { .start = 0x00a02418, .end = 0x00a02420 }, | |
2072 | { .start = 0x00a02428, .end = 0x00a0242c }, | |
2073 | { .start = 0x00a02434, .end = 0x00a02434 }, | |
2074 | { .start = 0x00a02440, .end = 0x00a02460 }, | |
2075 | { .start = 0x00a02468, .end = 0x00a024b0 }, | |
2076 | { .start = 0x00a024c8, .end = 0x00a024cc }, | |
2077 | { .start = 0x00a02500, .end = 0x00a02504 }, | |
2078 | { .start = 0x00a0250c, .end = 0x00a02510 }, | |
2079 | { .start = 0x00a02540, .end = 0x00a02554 }, | |
2080 | { .start = 0x00a02580, .end = 0x00a025f4 }, | |
2081 | { .start = 0x00a02600, .end = 0x00a0260c }, | |
2082 | { .start = 0x00a02648, .end = 0x00a02650 }, | |
2083 | { .start = 0x00a02680, .end = 0x00a02680 }, | |
2084 | { .start = 0x00a026c0, .end = 0x00a026d0 }, | |
2085 | { .start = 0x00a02700, .end = 0x00a0270c }, | |
2086 | { .start = 0x00a02804, .end = 0x00a02804 }, | |
2087 | { .start = 0x00a02818, .end = 0x00a0281c }, | |
2088 | { .start = 0x00a02c00, .end = 0x00a02db4 }, | |
2089 | { .start = 0x00a02df4, .end = 0x00a02fb0 }, | |
2090 | { .start = 0x00a03000, .end = 0x00a03014 }, | |
2091 | { .start = 0x00a0301c, .end = 0x00a0302c }, | |
2092 | { .start = 0x00a03034, .end = 0x00a03038 }, | |
2093 | { .start = 0x00a03040, .end = 0x00a03048 }, | |
2094 | { .start = 0x00a03060, .end = 0x00a03068 }, | |
2095 | { .start = 0x00a03070, .end = 0x00a03074 }, | |
2096 | { .start = 0x00a0307c, .end = 0x00a0307c }, | |
2097 | { .start = 0x00a03080, .end = 0x00a03084 }, | |
2098 | { .start = 0x00a0308c, .end = 0x00a03090 }, | |
2099 | { .start = 0x00a03098, .end = 0x00a03098 }, | |
2100 | { .start = 0x00a030a0, .end = 0x00a030a0 }, | |
2101 | { .start = 0x00a030a8, .end = 0x00a030b4 }, | |
2102 | { .start = 0x00a030bc, .end = 0x00a030bc }, | |
2103 | { .start = 0x00a030c0, .end = 0x00a0312c }, | |
2104 | { .start = 0x00a03c00, .end = 0x00a03c5c }, | |
2105 | { .start = 0x00a04400, .end = 0x00a04454 }, | |
2106 | { .start = 0x00a04460, .end = 0x00a04474 }, | |
2107 | { .start = 0x00a044c0, .end = 0x00a044ec }, | |
2108 | { .start = 0x00a04500, .end = 0x00a04504 }, | |
2109 | { .start = 0x00a04510, .end = 0x00a04538 }, | |
2110 | { .start = 0x00a04540, .end = 0x00a04548 }, | |
2111 | { .start = 0x00a04560, .end = 0x00a0457c }, | |
2112 | { .start = 0x00a04590, .end = 0x00a04598 }, | |
2113 | { .start = 0x00a045c0, .end = 0x00a045f4 }, | |
2114 | }; | |
2115 | ||
2116 | static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans, | |
2117 | struct iwl_fw_error_dump_data **data) | |
2118 | { | |
2119 | struct iwl_fw_error_dump_prph *prph; | |
2120 | unsigned long flags; | |
2121 | u32 prph_len = 0, i; | |
2122 | ||
2123 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
2124 | return 0; | |
2125 | ||
2126 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { | |
2127 | /* The range includes both boundaries */ | |
2128 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
2129 | iwl_prph_dump_addr[i].start + 4; | |
2130 | int reg; | |
2131 | __le32 *val; | |
2132 | ||
87dd634a | 2133 | prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk; |
67c65f2c EG |
2134 | |
2135 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); | |
2136 | (*data)->len = cpu_to_le32(sizeof(*prph) + | |
2137 | num_bytes_in_chunk); | |
2138 | prph = (void *)(*data)->data; | |
2139 | prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); | |
2140 | val = (void *)prph->data; | |
2141 | ||
2142 | for (reg = iwl_prph_dump_addr[i].start; | |
2143 | reg <= iwl_prph_dump_addr[i].end; | |
2144 | reg += 4) | |
2145 | *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, | |
2146 | reg)); | |
2147 | *data = iwl_fw_error_next_data(*data); | |
2148 | } | |
2149 | ||
2150 | iwl_trans_release_nic_access(trans, &flags); | |
2151 | ||
2152 | return prph_len; | |
2153 | } | |
2154 | ||
473ad712 EG |
2155 | #define IWL_CSR_TO_DUMP (0x250) |
2156 | ||
2157 | static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, | |
2158 | struct iwl_fw_error_dump_data **data) | |
2159 | { | |
2160 | u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; | |
2161 | __le32 *val; | |
2162 | int i; | |
2163 | ||
2164 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); | |
2165 | (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); | |
2166 | val = (void *)(*data)->data; | |
2167 | ||
2168 | for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) | |
2169 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2170 | ||
2171 | *data = iwl_fw_error_next_data(*data); | |
2172 | ||
2173 | return csr_len; | |
2174 | } | |
2175 | ||
06d51e0d LK |
2176 | static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, |
2177 | struct iwl_fw_error_dump_data **data) | |
2178 | { | |
2179 | u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; | |
2180 | unsigned long flags; | |
2181 | __le32 *val; | |
2182 | int i; | |
2183 | ||
2184 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
2185 | return 0; | |
2186 | ||
2187 | (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); | |
2188 | (*data)->len = cpu_to_le32(fh_regs_len); | |
2189 | val = (void *)(*data)->data; | |
2190 | ||
2191 | for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) | |
2192 | *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); | |
2193 | ||
2194 | iwl_trans_release_nic_access(trans, &flags); | |
2195 | ||
2196 | *data = iwl_fw_error_next_data(*data); | |
2197 | ||
2198 | return sizeof(**data) + fh_regs_len; | |
2199 | } | |
2200 | ||
cc79ef66 LK |
2201 | static u32 |
2202 | iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, | |
2203 | struct iwl_fw_error_dump_fw_mon *fw_mon_data, | |
2204 | u32 monitor_len) | |
2205 | { | |
2206 | u32 buf_size_in_dwords = (monitor_len >> 2); | |
2207 | u32 *buffer = (u32 *)fw_mon_data->data; | |
2208 | unsigned long flags; | |
2209 | u32 i; | |
2210 | ||
2211 | if (!iwl_trans_grab_nic_access(trans, false, &flags)) | |
2212 | return 0; | |
2213 | ||
2214 | __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1); | |
2215 | for (i = 0; i < buf_size_in_dwords; i++) | |
2216 | buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR); | |
2217 | __iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0); | |
2218 | ||
2219 | iwl_trans_release_nic_access(trans, &flags); | |
2220 | ||
2221 | return monitor_len; | |
2222 | } | |
2223 | ||
48eb7b34 EG |
2224 | static |
2225 | struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans) | |
4d075007 JB |
2226 | { |
2227 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2228 | struct iwl_fw_error_dump_data *data; | |
2229 | struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; | |
2230 | struct iwl_fw_error_dump_txcmd *txcmd; | |
48eb7b34 | 2231 | struct iwl_trans_dump_data *dump_data; |
4d075007 | 2232 | u32 len; |
99684ae3 | 2233 | u32 monitor_len; |
4d075007 JB |
2234 | int i, ptr; |
2235 | ||
473ad712 EG |
2236 | /* transport dump header */ |
2237 | len = sizeof(*dump_data); | |
2238 | ||
2239 | /* host commands */ | |
2240 | len += sizeof(*data) + | |
c2d20201 EG |
2241 | cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); |
2242 | ||
473ad712 EG |
2243 | /* CSR registers */ |
2244 | len += sizeof(*data) + IWL_CSR_TO_DUMP; | |
2245 | ||
2246 | /* PRPH registers */ | |
67c65f2c EG |
2247 | for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) { |
2248 | /* The range includes both boundaries */ | |
2249 | int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - | |
2250 | iwl_prph_dump_addr[i].start + 4; | |
2251 | ||
2252 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) + | |
2253 | num_bytes_in_chunk; | |
2254 | } | |
2255 | ||
06d51e0d LK |
2256 | /* FH registers */ |
2257 | len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); | |
2258 | ||
473ad712 | 2259 | /* FW monitor */ |
99684ae3 | 2260 | if (trans_pcie->fw_mon_page) { |
c544e9c4 | 2261 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + |
99684ae3 LK |
2262 | trans_pcie->fw_mon_size; |
2263 | monitor_len = trans_pcie->fw_mon_size; | |
2264 | } else if (trans->dbg_dest_tlv) { | |
2265 | u32 base, end; | |
2266 | ||
2267 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2268 | end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); | |
2269 | ||
2270 | base = iwl_read_prph(trans, base) << | |
2271 | trans->dbg_dest_tlv->base_shift; | |
2272 | end = iwl_read_prph(trans, end) << | |
2273 | trans->dbg_dest_tlv->end_shift; | |
2274 | ||
2275 | /* Make "end" point to the actual end */ | |
cc79ef66 LK |
2276 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || |
2277 | trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) | |
99684ae3 LK |
2278 | end += (1 << trans->dbg_dest_tlv->end_shift); |
2279 | monitor_len = end - base; | |
2280 | len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + | |
2281 | monitor_len; | |
2282 | } else { | |
2283 | monitor_len = 0; | |
2284 | } | |
c2d20201 | 2285 | |
48eb7b34 EG |
2286 | dump_data = vzalloc(len); |
2287 | if (!dump_data) | |
2288 | return NULL; | |
4d075007 JB |
2289 | |
2290 | len = 0; | |
48eb7b34 | 2291 | data = (void *)dump_data->data; |
4d075007 JB |
2292 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); |
2293 | txcmd = (void *)data->data; | |
2294 | spin_lock_bh(&cmdq->lock); | |
2295 | ptr = cmdq->q.write_ptr; | |
2296 | for (i = 0; i < cmdq->q.n_window; i++) { | |
2297 | u8 idx = get_cmd_index(&cmdq->q, ptr); | |
2298 | u32 caplen, cmdlen; | |
2299 | ||
2300 | cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); | |
2301 | caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); | |
2302 | ||
2303 | if (cmdlen) { | |
2304 | len += sizeof(*txcmd) + caplen; | |
2305 | txcmd->cmdlen = cpu_to_le32(cmdlen); | |
2306 | txcmd->caplen = cpu_to_le32(caplen); | |
2307 | memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); | |
2308 | txcmd = (void *)((u8 *)txcmd->data + caplen); | |
2309 | } | |
2310 | ||
2311 | ptr = iwl_queue_dec_wrap(ptr); | |
2312 | } | |
2313 | spin_unlock_bh(&cmdq->lock); | |
2314 | ||
2315 | data->len = cpu_to_le32(len); | |
c2d20201 | 2316 | len += sizeof(*data); |
67c65f2c EG |
2317 | data = iwl_fw_error_next_data(data); |
2318 | ||
2319 | len += iwl_trans_pcie_dump_prph(trans, &data); | |
473ad712 | 2320 | len += iwl_trans_pcie_dump_csr(trans, &data); |
06d51e0d | 2321 | len += iwl_trans_pcie_fh_regs_dump(trans, &data); |
67c65f2c | 2322 | /* data is already pointing to the next section */ |
c2d20201 | 2323 | |
99684ae3 LK |
2324 | if ((trans_pcie->fw_mon_page && |
2325 | trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || | |
2326 | trans->dbg_dest_tlv) { | |
c544e9c4 | 2327 | struct iwl_fw_error_dump_fw_mon *fw_mon_data; |
99684ae3 LK |
2328 | u32 base, write_ptr, wrap_cnt; |
2329 | ||
2330 | /* If there was a dest TLV - use the values from there */ | |
2331 | if (trans->dbg_dest_tlv) { | |
2332 | write_ptr = | |
2333 | le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); | |
2334 | wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); | |
2335 | base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); | |
2336 | } else { | |
2337 | base = MON_BUFF_BASE_ADDR; | |
2338 | write_ptr = MON_BUFF_WRPTR; | |
2339 | wrap_cnt = MON_BUFF_CYCLE_CNT; | |
2340 | } | |
c2d20201 | 2341 | |
c2d20201 | 2342 | data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); |
c2d20201 EG |
2343 | fw_mon_data = (void *)data->data; |
2344 | fw_mon_data->fw_mon_wr_ptr = | |
99684ae3 | 2345 | cpu_to_le32(iwl_read_prph(trans, write_ptr)); |
c2d20201 | 2346 | fw_mon_data->fw_mon_cycle_cnt = |
99684ae3 | 2347 | cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); |
c2d20201 | 2348 | fw_mon_data->fw_mon_base_ptr = |
99684ae3 LK |
2349 | cpu_to_le32(iwl_read_prph(trans, base)); |
2350 | ||
2351 | len += sizeof(*data) + sizeof(*fw_mon_data); | |
2352 | if (trans_pcie->fw_mon_page) { | |
99684ae3 LK |
2353 | /* |
2354 | * The firmware is now asserted, it won't write anything | |
2355 | * to the buffer. CPU can take ownership to fetch the | |
2356 | * data. The buffer will be handed back to the device | |
2357 | * before the firmware will be restarted. | |
2358 | */ | |
2359 | dma_sync_single_for_cpu(trans->dev, | |
2360 | trans_pcie->fw_mon_phys, | |
2361 | trans_pcie->fw_mon_size, | |
2362 | DMA_FROM_DEVICE); | |
2363 | memcpy(fw_mon_data->data, | |
2364 | page_address(trans_pcie->fw_mon_page), | |
2365 | trans_pcie->fw_mon_size); | |
2366 | ||
cc79ef66 LK |
2367 | monitor_len = trans_pcie->fw_mon_size; |
2368 | } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { | |
99684ae3 LK |
2369 | /* |
2370 | * Update pointers to reflect actual values after | |
2371 | * shifting | |
2372 | */ | |
2373 | base = iwl_read_prph(trans, base) << | |
2374 | trans->dbg_dest_tlv->base_shift; | |
2375 | iwl_trans_read_mem(trans, base, fw_mon_data->data, | |
2376 | monitor_len / sizeof(u32)); | |
cc79ef66 LK |
2377 | } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { |
2378 | monitor_len = | |
2379 | iwl_trans_pci_dump_marbh_monitor(trans, | |
2380 | fw_mon_data, | |
2381 | monitor_len); | |
2382 | } else { | |
2383 | /* Didn't match anything - output no monitor data */ | |
2384 | monitor_len = 0; | |
99684ae3 | 2385 | } |
cc79ef66 LK |
2386 | |
2387 | len += monitor_len; | |
2388 | data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); | |
c2d20201 EG |
2389 | } |
2390 | ||
48eb7b34 EG |
2391 | dump_data->len = len; |
2392 | ||
2393 | return dump_data; | |
4d075007 | 2394 | } |
87e5666c | 2395 | |
d1ff5253 | 2396 | static const struct iwl_trans_ops trans_ops_pcie = { |
57a1dc89 | 2397 | .start_hw = iwl_trans_pcie_start_hw, |
a4082843 | 2398 | .op_mode_leave = iwl_trans_pcie_op_mode_leave, |
ed6a3803 | 2399 | .fw_alive = iwl_trans_pcie_fw_alive, |
cf614297 | 2400 | .start_fw = iwl_trans_pcie_start_fw, |
e6bb4c9c | 2401 | .stop_device = iwl_trans_pcie_stop_device, |
48d42c42 | 2402 | |
ddaf5a5b JB |
2403 | .d3_suspend = iwl_trans_pcie_d3_suspend, |
2404 | .d3_resume = iwl_trans_pcie_d3_resume, | |
2dd4f9f7 | 2405 | |
f02831be | 2406 | .send_cmd = iwl_trans_pcie_send_hcmd, |
c85eb619 | 2407 | |
e6bb4c9c | 2408 | .tx = iwl_trans_pcie_tx, |
a0eaad71 | 2409 | .reclaim = iwl_trans_pcie_reclaim, |
34c1b7ba | 2410 | |
d0624be6 | 2411 | .txq_disable = iwl_trans_pcie_txq_disable, |
4beaf6c2 | 2412 | .txq_enable = iwl_trans_pcie_txq_enable, |
34c1b7ba | 2413 | |
87e5666c | 2414 | .dbgfs_register = iwl_trans_pcie_dbgfs_register, |
5f178cd2 | 2415 | |
990aa6d7 | 2416 | .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, |
e0b8d405 | 2417 | .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, |
5f178cd2 | 2418 | |
03905495 EG |
2419 | .write8 = iwl_trans_pcie_write8, |
2420 | .write32 = iwl_trans_pcie_write32, | |
2421 | .read32 = iwl_trans_pcie_read32, | |
6a06b6c1 EG |
2422 | .read_prph = iwl_trans_pcie_read_prph, |
2423 | .write_prph = iwl_trans_pcie_write_prph, | |
4fd442db EG |
2424 | .read_mem = iwl_trans_pcie_read_mem, |
2425 | .write_mem = iwl_trans_pcie_write_mem, | |
c6f600fc | 2426 | .configure = iwl_trans_pcie_configure, |
47107e84 | 2427 | .set_pmi = iwl_trans_pcie_set_pmi, |
7a65d170 | 2428 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
e139dc4a LE |
2429 | .release_nic_access = iwl_trans_pcie_release_nic_access, |
2430 | .set_bits_mask = iwl_trans_pcie_set_bits_mask, | |
4d075007 | 2431 | |
7616f334 EP |
2432 | .ref = iwl_trans_pcie_ref, |
2433 | .unref = iwl_trans_pcie_unref, | |
2434 | ||
4d075007 | 2435 | .dump_data = iwl_trans_pcie_dump_data, |
e6bb4c9c | 2436 | }; |
a42a1844 | 2437 | |
87ce05a2 | 2438 | struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, |
035f7ff2 EG |
2439 | const struct pci_device_id *ent, |
2440 | const struct iwl_cfg *cfg) | |
a42a1844 | 2441 | { |
a42a1844 EG |
2442 | struct iwl_trans_pcie *trans_pcie; |
2443 | struct iwl_trans *trans; | |
2444 | u16 pci_cmd; | |
2445 | int err; | |
2446 | ||
2447 | trans = kzalloc(sizeof(struct iwl_trans) + | |
20d3b647 | 2448 | sizeof(struct iwl_trans_pcie), GFP_KERNEL); |
6965a354 LC |
2449 | if (!trans) { |
2450 | err = -ENOMEM; | |
2451 | goto out; | |
2452 | } | |
a42a1844 EG |
2453 | |
2454 | trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
2455 | ||
2456 | trans->ops = &trans_ops_pcie; | |
035f7ff2 | 2457 | trans->cfg = cfg; |
2bfb5092 | 2458 | trans_lockdep_init(trans); |
a42a1844 | 2459 | trans_pcie->trans = trans; |
7b11488f | 2460 | spin_lock_init(&trans_pcie->irq_lock); |
e56b04ef | 2461 | spin_lock_init(&trans_pcie->reg_lock); |
dad33ecf | 2462 | spin_lock_init(&trans_pcie->ref_lock); |
13df1aab | 2463 | init_waitqueue_head(&trans_pcie->ucode_write_waitq); |
a42a1844 | 2464 | |
d819c6cf JB |
2465 | err = pci_enable_device(pdev); |
2466 | if (err) | |
2467 | goto out_no_pci; | |
2468 | ||
f2532b04 EG |
2469 | if (!cfg->base_params->pcie_l1_allowed) { |
2470 | /* | |
2471 | * W/A - seems to solve weird behavior. We need to remove this | |
2472 | * if we don't want to stay in L1 all the time. This wastes a | |
2473 | * lot of power. | |
2474 | */ | |
2475 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | | |
2476 | PCIE_LINK_STATE_L1 | | |
2477 | PCIE_LINK_STATE_CLKPM); | |
2478 | } | |
a42a1844 | 2479 | |
a42a1844 EG |
2480 | pci_set_master(pdev); |
2481 | ||
2482 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2483 | if (!err) | |
2484 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2485 | if (err) { | |
2486 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2487 | if (!err) | |
2488 | err = pci_set_consistent_dma_mask(pdev, | |
20d3b647 | 2489 | DMA_BIT_MASK(32)); |
a42a1844 EG |
2490 | /* both attempts failed: */ |
2491 | if (err) { | |
6a4b09f8 | 2492 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
a42a1844 EG |
2493 | goto out_pci_disable_device; |
2494 | } | |
2495 | } | |
2496 | ||
2497 | err = pci_request_regions(pdev, DRV_NAME); | |
2498 | if (err) { | |
6a4b09f8 | 2499 | dev_err(&pdev->dev, "pci_request_regions failed\n"); |
a42a1844 EG |
2500 | goto out_pci_disable_device; |
2501 | } | |
2502 | ||
05f5b97e | 2503 | trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); |
a42a1844 | 2504 | if (!trans_pcie->hw_base) { |
6a4b09f8 | 2505 | dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); |
a42a1844 EG |
2506 | err = -ENODEV; |
2507 | goto out_pci_release_regions; | |
2508 | } | |
2509 | ||
a42a1844 EG |
2510 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2511 | * PCI Tx retries from interfering with C3 CPU state */ | |
2512 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2513 | ||
83f7a85f EG |
2514 | trans->dev = &pdev->dev; |
2515 | trans_pcie->pci_dev = pdev; | |
2516 | iwl_disable_interrupts(trans); | |
2517 | ||
a42a1844 | 2518 | err = pci_enable_msi(pdev); |
9f904b38 | 2519 | if (err) { |
6a4b09f8 | 2520 | dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err); |
9f904b38 EG |
2521 | /* enable rfkill interrupt: hw bug w/a */ |
2522 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
2523 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
2524 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
2525 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
2526 | } | |
2527 | } | |
a42a1844 | 2528 | |
08079a49 | 2529 | trans->hw_rev = iwl_read32(trans, CSR_HW_REV); |
b513ee7f LK |
2530 | /* |
2531 | * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have | |
2532 | * changed, and now the revision step also includes bit 0-1 (no more | |
2533 | * "dash" value). To keep hw_rev backwards compatible - we'll store it | |
2534 | * in the old format. | |
2535 | */ | |
7a42baa6 EH |
2536 | if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { |
2537 | unsigned long flags; | |
2538 | int ret; | |
2539 | ||
b513ee7f | 2540 | trans->hw_rev = (trans->hw_rev & 0xfff0) | |
1fc0e221 | 2541 | (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); |
b513ee7f | 2542 | |
7a42baa6 EH |
2543 | /* |
2544 | * in-order to recognize C step driver should read chip version | |
2545 | * id located at the AUX bus MISC address space. | |
2546 | */ | |
2547 | iwl_set_bit(trans, CSR_GP_CNTRL, | |
2548 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
2549 | udelay(2); | |
2550 | ||
2551 | ret = iwl_poll_bit(trans, CSR_GP_CNTRL, | |
2552 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
2553 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
2554 | 25000); | |
2555 | if (ret < 0) { | |
2556 | IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); | |
2557 | goto out_pci_disable_msi; | |
2558 | } | |
2559 | ||
2560 | if (iwl_trans_grab_nic_access(trans, false, &flags)) { | |
2561 | u32 hw_step; | |
2562 | ||
2563 | hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG); | |
2564 | hw_step |= ENABLE_WFPM; | |
2565 | __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step); | |
2566 | hw_step = __iwl_read_prph(trans, AUX_MISC_REG); | |
2567 | hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; | |
2568 | if (hw_step == 0x3) | |
2569 | trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | | |
2570 | (SILICON_C_STEP << 2); | |
2571 | iwl_trans_release_nic_access(trans, &flags); | |
2572 | } | |
2573 | } | |
2574 | ||
99673ee5 | 2575 | trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; |
9ca85961 EG |
2576 | snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), |
2577 | "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); | |
a42a1844 | 2578 | |
69a10b29 | 2579 | /* Initialize the wait queue for commands */ |
f946b529 | 2580 | init_waitqueue_head(&trans_pcie->wait_command_queue); |
69a10b29 | 2581 | |
3ec45882 JB |
2582 | snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name), |
2583 | "iwl_cmd_pool:%s", dev_name(trans->dev)); | |
59c647b6 EG |
2584 | |
2585 | trans->dev_cmd_headroom = 0; | |
2586 | trans->dev_cmd_pool = | |
3ec45882 | 2587 | kmem_cache_create(trans->dev_cmd_pool_name, |
59c647b6 EG |
2588 | sizeof(struct iwl_device_cmd) |
2589 | + trans->dev_cmd_headroom, | |
2590 | sizeof(void *), | |
2591 | SLAB_HWCACHE_ALIGN, | |
2592 | NULL); | |
2593 | ||
6965a354 LC |
2594 | if (!trans->dev_cmd_pool) { |
2595 | err = -ENOMEM; | |
59c647b6 | 2596 | goto out_pci_disable_msi; |
6965a354 | 2597 | } |
59c647b6 | 2598 | |
a8b691e6 JB |
2599 | if (iwl_pcie_alloc_ict(trans)) |
2600 | goto out_free_cmd_pool; | |
2601 | ||
85bf9da1 | 2602 | err = request_threaded_irq(pdev->irq, iwl_pcie_isr, |
6965a354 LC |
2603 | iwl_pcie_irq_handler, |
2604 | IRQF_SHARED, DRV_NAME, trans); | |
2605 | if (err) { | |
a8b691e6 JB |
2606 | IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); |
2607 | goto out_free_ict; | |
2608 | } | |
2609 | ||
83f7a85f | 2610 | trans_pcie->inta_mask = CSR_INI_SET_MASK; |
6735943f | 2611 | trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND; |
83f7a85f | 2612 | |
a42a1844 EG |
2613 | return trans; |
2614 | ||
a8b691e6 JB |
2615 | out_free_ict: |
2616 | iwl_pcie_free_ict(trans); | |
2617 | out_free_cmd_pool: | |
2618 | kmem_cache_destroy(trans->dev_cmd_pool); | |
59c647b6 EG |
2619 | out_pci_disable_msi: |
2620 | pci_disable_msi(pdev); | |
a42a1844 EG |
2621 | out_pci_release_regions: |
2622 | pci_release_regions(pdev); | |
2623 | out_pci_disable_device: | |
2624 | pci_disable_device(pdev); | |
2625 | out_no_pci: | |
2626 | kfree(trans); | |
6965a354 LC |
2627 | out: |
2628 | return ERR_PTR(err); | |
a42a1844 | 2629 | } |