projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
a05b8c58 16 along with this program; if not, see <http://www.gnu.org/licenses/>.
95ea3627
ID		 17 */
18
19/*
20 Module: rt2500pci
21 Abstract: rt2500pci device specific routines.
22 Supported chipsets: RT2560.
23 */
24
95ea3627
ID		 25#include <linux/delay.h>
26#include <linux/etherdevice.h>
95ea3627
ID		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/eeprom_93cx6.h>
5a0e3ad6 31#include <linux/slab.h>
95ea3627
ID		 32
33#include "rt2x00.h"
69a2bac8 34#include "rt2x00mmio.h"
95ea3627
ID		 35#include "rt2x00pci.h"
36#include "rt2500pci.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
c517123a 41 * rt2x00mmio_register_read and rt2x00mmio_register_write.
95ea3627
ID		 42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 */
c9c3b1a5 51#define WAIT_FOR_BBP(__dev, __reg) \
c517123a 52 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
c9c3b1a5 53#define WAIT_FOR_RF(__dev, __reg) \
c517123a 54 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 55
0e14f6d3 56static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 57 const unsigned int word, const u8 value)
58{
59 u32 reg;
60
8ff48a8b
ID		 61 mutex_lock(&rt2x00dev->csr_mutex);
62
95ea3627 63 /*
c9c3b1a5
ID		 64 * Wait until the BBP becomes available, afterwards we
65 * can safely write the new data into the register.
95ea3627 66 */
c9c3b1a5
ID		 67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
68 reg = 0;
69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
73
c517123a 74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
c9c3b1a5 75 }
8ff48a8b 76
8ff48a8b 77 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 78}
79
0e14f6d3 80static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 81 const unsigned int word, u8 *value)
82{
83 u32 reg;
84
8ff48a8b
ID		 85 mutex_lock(&rt2x00dev->csr_mutex);
86
95ea3627 87 /*
c9c3b1a5
ID		 88 * Wait until the BBP becomes available, afterwards we
89 * can safely write the read request into the register.
90 * After the data has been written, we wait until hardware
91 * returns the correct value, if at any time the register
92 * doesn't become available in time, reg will be 0xffffffff
93 * which means we return 0xff to the caller.
95ea3627 94 */
c9c3b1a5
ID		 95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
96 reg = 0;
97 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
98 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
99 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 100
c517123a 101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 102
c9c3b1a5
ID		 103 WAIT_FOR_BBP(rt2x00dev, &reg);
104 }
95ea3627
ID		 105
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 107
108 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 109}
110
0e14f6d3 111static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 112 const unsigned int word, const u32 value)
113{
114 u32 reg;
95ea3627 115
8ff48a8b
ID		 116 mutex_lock(&rt2x00dev->csr_mutex);
117
c9c3b1a5
ID		 118 /*
119 * Wait until the RF becomes available, afterwards we
120 * can safely write the new data into the register.
121 */
122 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
123 reg = 0;
124 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
125 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
126 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
127 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
128
c517123a 129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
c9c3b1a5 130 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 131 }
132
8ff48a8b 133 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 134}
135
136static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
137{
138 struct rt2x00_dev *rt2x00dev = eeprom->data;
139 u32 reg;
140
c517123a 141 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
95ea3627
ID		 142
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
145 eeprom->reg_data_clock =
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
147 eeprom->reg_chip_select =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
149}
150
151static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
152{
153 struct rt2x00_dev *rt2x00dev = eeprom->data;
154 u32 reg = 0;
155
156 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
159 !!eeprom->reg_data_clock);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
161 !!eeprom->reg_chip_select);
162
c517123a 163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
95ea3627
ID		 164}
165
166#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 167static const struct rt2x00debug rt2500pci_rt2x00debug = {
168 .owner = THIS_MODULE,
169 .csr = {
c517123a
GJ		 170 .read = rt2x00mmio_register_read,
171 .write = rt2x00mmio_register_write,
743b97ca
ID		 172 .flags = RT2X00DEBUGFS_OFFSET,
173 .word_base = CSR_REG_BASE,
95ea3627
ID		 174 .word_size = sizeof(u32),
175 .word_count = CSR_REG_SIZE / sizeof(u32),
176 },
177 .eeprom = {
178 .read = rt2x00_eeprom_read,
179 .write = rt2x00_eeprom_write,
743b97ca 180 .word_base = EEPROM_BASE,
95ea3627
ID		 181 .word_size = sizeof(u16),
182 .word_count = EEPROM_SIZE / sizeof(u16),
183 },
184 .bbp = {
185 .read = rt2500pci_bbp_read,
186 .write = rt2500pci_bbp_write,
743b97ca 187 .word_base = BBP_BASE,
95ea3627
ID		 188 .word_size = sizeof(u8),
189 .word_count = BBP_SIZE / sizeof(u8),
190 },
191 .rf = {
192 .read = rt2x00_rf_read,
193 .write = rt2500pci_rf_write,
743b97ca 194 .word_base = RF_BASE,
95ea3627
ID		 195 .word_size = sizeof(u32),
196 .word_count = RF_SIZE / sizeof(u32),
197 },
198};
199#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
200
95ea3627
ID		 201static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
202{
203 u32 reg;
204
c517123a 205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
99bdf51a 206 return rt2x00_get_field32(reg, GPIOCSR_VAL0);
95ea3627 207}
95ea3627 208
771fd565 209#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 210static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 211 enum led_brightness brightness)
212{
213 struct rt2x00_led *led =
214 container_of(led_cdev, struct rt2x00_led, led_dev);
215 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 216 u32 reg;
217
c517123a 218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
a9450b70 219
a2e1d52a 220 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 221 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 222 else if (led->type == LED_TYPE_ACTIVITY)
223 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70 224
c517123a 225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a9450b70 226}
a2e1d52a
ID		 227
228static int rt2500pci_blink_set(struct led_classdev *led_cdev,
229 unsigned long *delay_on,
230 unsigned long *delay_off)
231{
232 struct rt2x00_led *led =
233 container_of(led_cdev, struct rt2x00_led, led_dev);
234 u32 reg;
235
c517123a 236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
a2e1d52a
ID		 237 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
238 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
c517123a 239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
a2e1d52a
ID		 240
241 return 0;
242}
475433be
ID		 243
244static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
245 struct rt2x00_led *led,
246 enum led_type type)
247{
248 led->rt2x00dev = rt2x00dev;
249 led->type = type;
250 led->led_dev.brightness_set = rt2500pci_brightness_set;
251 led->led_dev.blink_set = rt2500pci_blink_set;
252 led->flags = LED_INITIALIZED;
253}
771fd565 254#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 255
95ea3627
ID		 256/*
257 * Configuration handlers.
258 */
3a643d24
ID		 259static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
260 const unsigned int filter_flags)
261{
262 u32 reg;
263
264 /*
265 * Start configuration steps.
266 * Note that the version error will always be dropped
267 * and broadcast frames will always be accepted since
268 * there is no filter for it at this time.
269 */
c517123a 270 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
3a643d24
ID		 271 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
272 !(filter_flags & FIF_FCSFAIL));
273 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
274 !(filter_flags & FIF_PLCPFAIL));
275 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
276 !(filter_flags & FIF_CONTROL));
df140465 277 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, 1);
3a643d24 278 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa 279 !rt2x00dev->intf_ap_count);
3a643d24
ID		 280 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
281 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
282 !(filter_flags & FIF_ALLMULTI));
283 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
c517123a 284 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
3a643d24
ID		 285}
286
6bb40dd1
ID		 287static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
95ea3627 291{
a2440830 292 struct data_queue *queue = rt2x00dev->bcn;
6bb40dd1 293 unsigned int bcn_preload;
95ea3627
ID		 294 u32 reg;
295
6bb40dd1 296 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 297 /*
298 * Enable beacon config
299 */
bad13639 300 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
c517123a 301 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
6bb40dd1
ID		 302 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
303 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
c517123a 304 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 305
6bb40dd1
ID		 306 /*
307 * Enable synchronisation.
308 */
c517123a 309 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1 310 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
c517123a 311 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
6bb40dd1
ID		 312 }
313
314 if (flags & CONFIG_UPDATE_MAC)
c517123a 315 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
6bb40dd1
ID		 316 conf->mac, sizeof(conf->mac));
317
318 if (flags & CONFIG_UPDATE_BSSID)
c517123a 319 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
6bb40dd1 320 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 321}
322
3a643d24 323static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 324 struct rt2x00lib_erp *erp,
325 u32 changed)
95ea3627 326{
5c58ee51 327 int preamble_mask;
95ea3627 328 u32 reg;
95ea3627 329
5c58ee51
ID		 330 /*
331 * When short preamble is enabled, we should set bit 0x08
332 */
02044643
HS		 333 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
334 preamble_mask = erp->short_preamble << 3;
335
c517123a 336 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
02044643
HS		 337 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
338 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
339 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
340 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
c517123a 341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
02044643 342
c517123a 343 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
02044643
HS		 344 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
345 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
347 GET_DURATION(ACK_SIZE, 10));
c517123a 348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
02044643 349
c517123a 350 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
02044643
HS		 351 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
352 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
353 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
354 GET_DURATION(ACK_SIZE, 20));
c517123a 355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
02044643 356
c517123a 357 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
02044643
HS		 358 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
359 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
360 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
361 GET_DURATION(ACK_SIZE, 55));
c517123a 362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
02044643 363
c517123a 364 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
02044643
HS		 365 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
366 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
367 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
368 GET_DURATION(ACK_SIZE, 110));
c517123a 369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
02044643
HS		 370 }
371
372 if (changed & BSS_CHANGED_BASIC_RATES)
c517123a 373 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
02044643
HS		 374
375 if (changed & BSS_CHANGED_ERP_SLOT) {
c517123a 376 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
02044643 377 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
c517123a 378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
02044643 379
c517123a 380 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
02044643
HS		 381 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
382 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
c517123a 383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
02044643 384
c517123a 385 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
02044643
HS		 386 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
387 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
c517123a 388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
02044643
HS		 389 }
390
391 if (changed & BSS_CHANGED_BEACON_INT) {
c517123a 392 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
02044643
HS		 393 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
394 erp->beacon_int * 16);
395 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
396 erp->beacon_int * 16);
c517123a 397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
02044643
HS		 398 }
399
95ea3627
ID		 400}
401
e4ea1c40
ID		 402static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
403 struct antenna_setup *ant)
95ea3627 404{
e4ea1c40
ID		 405 u32 reg;
406 u8 r14;
407 u8 r2;
408
409 /*
410 * We should never come here because rt2x00lib is supposed
411 * to catch this and send us the correct antenna explicitely.
412 */
413 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
414 ant->tx == ANTENNA_SW_DIVERSITY);
415
c517123a 416 rt2x00mmio_register_read(rt2x00dev, BBPCSR1, &reg);
e4ea1c40
ID		 417 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
418 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
419
420 /*
421 * Configure the TX antenna.
422 */
423 switch (ant->tx) {
424 case ANTENNA_A:
425 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
426 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
427 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
428 break;
429 case ANTENNA_B:
430 default:
431 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
432 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
433 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
434 break;
435 }
436
437 /*
438 * Configure the RX antenna.
439 */
440 switch (ant->rx) {
441 case ANTENNA_A:
442 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
443 break;
444 case ANTENNA_B:
445 default:
446 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
447 break;
448 }
449
450 /*
451 * RT2525E and RT5222 need to flip TX I/Q
452 */
5122d898 453 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
e4ea1c40
ID		 454 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
455 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
456 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
457
458 /*
459 * RT2525E does not need RX I/Q Flip.
460 */
5122d898 461 if (rt2x00_rf(rt2x00dev, RF2525E))
e4ea1c40
ID		 462 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
463 } else {
464 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
465 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
466 }
467
c517123a 468 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
e4ea1c40
ID		 469 rt2500pci_bbp_write(rt2x00dev, 14, r14);
470 rt2500pci_bbp_write(rt2x00dev, 2, r2);
95ea3627
ID		 471}
472
473static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 474 struct rf_channel *rf, const int txpower)
95ea3627 475{
95ea3627
ID		 476 u8 r70;
477
95ea3627
ID		 478 /*
479 * Set TXpower.
480 */
5c58ee51 481 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
95ea3627
ID		 482
483 /*
484 * Switch on tuning bits.
485 * For RT2523 devices we do not need to update the R1 register.
486 */
5122d898 487 if (!rt2x00_rf(rt2x00dev, RF2523))
5c58ee51
ID		 488 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
489 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627
ID		 490
491 /*
492 * For RT2525 we should first set the channel to half band higher.
493 */
5122d898 494 if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 495 static const u32 vals[] = {
496 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
497 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
498 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
499 0x00080d2e, 0x00080d3a
500 };
501
5c58ee51
ID		 502 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
503 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
504 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
505 if (rf->rf4)
506 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 507 }
508
5c58ee51
ID		 509 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
510 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
511 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
512 if (rf->rf4)
513 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
95ea3627
ID		 514
515 /*
516 * Channel 14 requires the Japan filter bit to be set.
517 */
518 r70 = 0x46;
5c58ee51 519 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
95ea3627
ID		 520 rt2500pci_bbp_write(rt2x00dev, 70, r70);
521
522 msleep(1);
523
524 /*
525 * Switch off tuning bits.
526 * For RT2523 devices we do not need to update the R1 register.
527 */
5122d898 528 if (!rt2x00_rf(rt2x00dev, RF2523)) {
5c58ee51
ID		 529 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
530 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627
ID		 531 }
532
5c58ee51
ID		 533 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
534 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 535
536 /*
537 * Clear false CRC during channel switch.
538 */
c517123a 539 rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 540}
541
542static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
543 const int txpower)
544{
545 u32 rf3;
546
547 rt2x00_rf_read(rt2x00dev, 3, &rf3);
548 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
549 rt2500pci_rf_write(rt2x00dev, 3, rf3);
550}
551
e4ea1c40
ID		 552static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
553 struct rt2x00lib_conf *libconf)
95ea3627
ID		 554{
555 u32 reg;
95ea3627 556
c517123a 557 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
e4ea1c40
ID		 558 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
559 libconf->conf->long_frame_max_tx_count);
560 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
561 libconf->conf->short_frame_max_tx_count);
c517123a 562 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 563}
564
7d7f19cc
ID		 565static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
566 struct rt2x00lib_conf *libconf)
567{
568 enum dev_state state =
569 (libconf->conf->flags & IEEE80211_CONF_PS) ?
570 STATE_SLEEP : STATE_AWAKE;
571 u32 reg;
572
573 if (state == STATE_SLEEP) {
c517123a 574 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
7d7f19cc 575 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 576 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 577 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
578 libconf->conf->listen_interval - 1);
579
580 /* We must first disable autowake before it can be enabled */
581 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
c517123a 582 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 583
584 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
c517123a 585 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
5731858d 586 } else {
c517123a 587 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
5731858d 588 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
c517123a 589 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 590 }
591
592 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
593}
594
95ea3627 595static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 596 struct rt2x00lib_conf *libconf,
597 const unsigned int flags)
95ea3627 598{
e4ea1c40 599 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 600 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
601 libconf->conf->power_level);
e4ea1c40
ID		 602 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
603 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51
ID		 604 rt2500pci_config_txpower(rt2x00dev,
605 libconf->conf->power_level);
e4ea1c40
ID		 606 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
607 rt2500pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 608 if (flags & IEEE80211_CONF_CHANGE_PS)
609 rt2500pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 610}
611
95ea3627
ID		 612/*
613 * Link tuning
614 */
ebcf26da
ID		 615static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
616 struct link_qual *qual)
95ea3627
ID		 617{
618 u32 reg;
619
620 /*
621 * Update FCS error count from register.
622 */
c517123a 623 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 624 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 625
626 /*
627 * Update False CCA count from register.
628 */
c517123a 629 rt2x00mmio_register_read(rt2x00dev, CNT3, &reg);
ebcf26da 630 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
95ea3627
ID		 631}
632
5352ff65
ID		 633static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
634 struct link_qual *qual, u8 vgc_level)
eb20b4e8 635{
5352ff65 636 if (qual->vgc_level_reg != vgc_level) {
eb20b4e8 637 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
223dcc26 638 qual->vgc_level = vgc_level;
5352ff65 639 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 640 }
641}
642
5352ff65
ID		 643static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
644 struct link_qual *qual)
95ea3627 645{
5352ff65 646 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
95ea3627
ID		 647}
648
5352ff65
ID		 649static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
650 struct link_qual *qual, const u32 count)
95ea3627 651{
95ea3627
ID		 652 /*
653 * To prevent collisions with MAC ASIC on chipsets
654 * up to version C the link tuning should halt after 20
6bb40dd1 655 * seconds while being associated.
95ea3627 656 */
5122d898 657 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
5352ff65 658 rt2x00dev->intf_associated && count > 20)
95ea3627
ID		 659 return;
660
95ea3627
ID		 661 /*
662 * Chipset versions C and lower should directly continue
6bb40dd1
ID		 663 * to the dynamic CCA tuning. Chipset version D and higher
664 * should go straight to dynamic CCA tuning when they
665 * are not associated.
95ea3627 666 */
5122d898 667 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
6bb40dd1 668 !rt2x00dev->intf_associated)
95ea3627
ID		 669 goto dynamic_cca_tune;
670
671 /*
672 * A too low RSSI will cause too much false CCA which will
673 * then corrupt the R17 tuning. To remidy this the tuning should
674 * be stopped (While making sure the R17 value will not exceed limits)
675 */
5352ff65
ID		 676 if (qual->rssi < -80 && count > 20) {
677 if (qual->vgc_level_reg >= 0x41)
678 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 679 return;
680 }
681
682 /*
683 * Special big-R17 for short distance
684 */
5352ff65
ID		 685 if (qual->rssi >= -58) {
686 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
95ea3627
ID		 687 return;
688 }
689
690 /*
691 * Special mid-R17 for middle distance
692 */
5352ff65
ID		 693 if (qual->rssi >= -74) {
694 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
95ea3627
ID		 695 return;
696 }
697
698 /*
699 * Leave short or middle distance condition, restore r17
700 * to the dynamic tuning range.
701 */
5352ff65
ID		 702 if (qual->vgc_level_reg >= 0x41) {
703 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
95ea3627
ID		 704 return;
705 }
706
707dynamic_cca_tune:
708
709 /*
710 * R17 is inside the dynamic tuning range,
711 * start tuning the link based on the false cca counter.
712 */
223dcc26 713 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
5352ff65 714 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
223dcc26 715 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
5352ff65 716 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
95ea3627
ID		 717}
718
5450b7e2
ID		 719/*
720 * Queue handlers.
721 */
722static void rt2500pci_start_queue(struct data_queue *queue)
723{
724 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
725 u32 reg;
726
727 switch (queue->qid) {
728 case QID_RX:
c517123a 729 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
5450b7e2 730 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
c517123a 731 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 732 break;
733 case QID_BEACON:
c517123a 734 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
5450b7e2
ID		 735 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
736 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
737 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
c517123a 738 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
5450b7e2
ID		 739 break;
740 default:
741 break;
742 }
743}
744
745static void rt2500pci_kick_queue(struct data_queue *queue)
746{
747 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
748 u32 reg;
749
750 switch (queue->qid) {
f615e9a3 751 case QID_AC_VO:
c517123a 752 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 753 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
c517123a 754 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2 755 break;
f615e9a3 756 case QID_AC_VI:
c517123a 757 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 758 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
c517123a 759 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 760 break;
761 case QID_ATIM:
c517123a 762 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 763 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
c517123a 764 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 765 break;
766 default:
767 break;
768 }
769}
770
771static void rt2500pci_stop_queue(struct data_queue *queue)
772{
773 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
774 u32 reg;
775
776 switch (queue->qid) {
f615e9a3
ID		 777 case QID_AC_VO:
778 case QID_AC_VI:
5450b7e2 779 case QID_ATIM:
c517123a 780 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
5450b7e2 781 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
c517123a 782 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
5450b7e2
ID		 783 break;
784 case QID_RX:
c517123a 785 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
5450b7e2 786 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
c517123a 787 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
5450b7e2
ID		 788 break;
789 case QID_BEACON:
c517123a 790 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
5450b7e2
ID		 791 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
792 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
793 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
c517123a 794 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
16222a0d
HS		 795
796 /*
797 * Wait for possibly running tbtt tasklets.
798 */
abc11994 799 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 800 break;
801 default:
802 break;
803 }
804}
805
95ea3627
ID		 806/*
807 * Initialization functions.
808 */
798b7adb 809static bool rt2500pci_get_entry_state(struct queue_entry *entry)
95ea3627 810{
c517123a 811 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 812 u32 word;
813
798b7adb
ID		 814 if (entry->queue->qid == QID_RX) {
815 rt2x00_desc_read(entry_priv->desc, 0, &word);
816
817 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
818 } else {
819 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 820
798b7adb
ID		 821 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
822 rt2x00_get_field32(word, TXD_W0_VALID));
823 }
95ea3627
ID		 824}
825
798b7adb 826static void rt2500pci_clear_entry(struct queue_entry *entry)
95ea3627 827{
c517123a 828 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
798b7adb 829 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 830 u32 word;
831
798b7adb
ID		 832 if (entry->queue->qid == QID_RX) {
833 rt2x00_desc_read(entry_priv->desc, 1, &word);
834 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
835 rt2x00_desc_write(entry_priv->desc, 1, word);
836
837 rt2x00_desc_read(entry_priv->desc, 0, &word);
838 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
839 rt2x00_desc_write(entry_priv->desc, 0, word);
840 } else {
841 rt2x00_desc_read(entry_priv->desc, 0, &word);
842 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
843 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
844 rt2x00_desc_write(entry_priv->desc, 0, word);
845 }
95ea3627
ID		 846}
847
181d6902 848static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 849{
c517123a 850 struct queue_entry_priv_mmio *entry_priv;
95ea3627
ID		 851 u32 reg;
852
95ea3627
ID		 853 /*
854 * Initialize registers.
855 */
c517123a 856 rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 857 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
858 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 859 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 860 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
c517123a 861 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
95ea3627 862
b8be63ff 863 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
c517123a 864 rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 865 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 866 entry_priv->desc_dma);
c517123a 867 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
95ea3627 868
b8be63ff 869 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
c517123a 870 rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 871 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 872 entry_priv->desc_dma);
c517123a 873 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
95ea3627 874
e74df4a7 875 entry_priv = rt2x00dev->atim->entries[0].priv_data;
c517123a 876 rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 877 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 878 entry_priv->desc_dma);
c517123a 879 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
95ea3627 880
e74df4a7 881 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
c517123a 882 rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 883 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 884 entry_priv->desc_dma);
c517123a 885 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
95ea3627 886
c517123a 887 rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
95ea3627 888 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 889 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
c517123a 890 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
95ea3627 891
b8be63ff 892 entry_priv = rt2x00dev->rx->entries[0].priv_data;
c517123a 893 rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 894 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
895 entry_priv->desc_dma);
c517123a 896 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
95ea3627
ID		 897
898 return 0;
899}
900
901static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
902{
903 u32 reg;
904
c517123a
GJ		 905 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
906 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
907 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
908 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
95ea3627 909
c517123a 910 rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
95ea3627
ID		 911 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
912 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
913 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
c517123a 914 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
95ea3627 915
c517123a 916 rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
95ea3627
ID		 917 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
918 rt2x00dev->rx->data_size / 128);
c517123a 919 rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
95ea3627
ID		 920
921 /*
922 * Always use CWmin and CWmax set in descriptor.
923 */
c517123a 924 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
95ea3627 925 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
c517123a 926 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
95ea3627 927
c517123a 928 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1f909162
ID		 929 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
930 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
931 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
932 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
933 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
934 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
935 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
936 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
c517123a 937 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1f909162 938
c517123a 939 rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
95ea3627 940
c517123a 941 rt2x00mmio_register_read(rt2x00dev, TXCSR8, &reg);
95ea3627
ID		 942 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
943 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
944 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
945 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
946 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
947 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
948 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
949 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
c517123a 950 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
95ea3627 951
c517123a 952 rt2x00mmio_register_read(rt2x00dev, ARTCSR0, &reg);
95ea3627
ID		 953 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
954 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
955 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
956 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
c517123a 957 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
95ea3627 958
c517123a 959 rt2x00mmio_register_read(rt2x00dev, ARTCSR1, &reg);
95ea3627
ID		 960 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
961 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
962 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
963 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
c517123a 964 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
95ea3627 965
c517123a 966 rt2x00mmio_register_read(rt2x00dev, ARTCSR2, &reg);
95ea3627
ID		 967 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
968 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
969 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
970 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
c517123a 971 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
95ea3627 972
c517123a 973 rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
95ea3627
ID		 974 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
975 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
976 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
977 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
978 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
979 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
980 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
981 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
c517123a 982 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
95ea3627 983
c517123a 984 rt2x00mmio_register_read(rt2x00dev, PCICSR, &reg);
95ea3627
ID		 985 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
986 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
987 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
988 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
989 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
990 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
991 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
c517123a 992 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
95ea3627 993
c517123a 994 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
95ea3627 995
c517123a
GJ		 996 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
997 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
95ea3627
ID		 998
999 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1000 return -EBUSY;
1001
c517123a
GJ		 1002 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
1003 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
95ea3627 1004
c517123a 1005 rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
95ea3627 1006 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
c517123a 1007 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
95ea3627 1008
c517123a 1009 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
95ea3627
ID		 1010 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1011 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1012 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1013 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1014 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1015 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
c517123a 1016 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
95ea3627 1017
c517123a 1018 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
95ea3627 1019
c517123a 1020 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
95ea3627 1021
c517123a 1022 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
95ea3627
ID		 1023 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1024 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1025 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
c517123a 1026 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627 1027
c517123a 1028 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
95ea3627
ID		 1029 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1030 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
c517123a 1031 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
95ea3627
ID		 1032
1033 /*
1034 * We must clear the FCS and FIFO error count.
1035 * These registers are cleared on read,
1036 * so we may pass a useless variable to store the value.
1037 */
c517123a
GJ		 1038 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
1039 rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
95ea3627
ID		 1040
1041 return 0;
1042}
1043
2b08da3f 1044static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1045{
1046 unsigned int i;
95ea3627
ID		 1047 u8 value;
1048
1049 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1050 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1051 if ((value != 0xff) && (value != 0x00))
2b08da3f 1052 return 0;
95ea3627
ID		 1053 udelay(REGISTER_BUSY_DELAY);
1054 }
1055
ec9c4989 1056 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
95ea3627 1057 return -EACCES;
2b08da3f
ID		 1058}
1059
1060static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1061{
1062 unsigned int i;
1063 u16 eeprom;
1064 u8 reg_id;
1065 u8 value;
1066
1067 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1068 return -EACCES;
95ea3627 1069
95ea3627
ID		 1070 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1071 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1072 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1073 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1074 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1075 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1076 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1077 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1078 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1079 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1080 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1081 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1082 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1083 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1084 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1085 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1086 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1087 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1088 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1089 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1090 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1091 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1092 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1093 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1094 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1095 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1096 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1097 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1098 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1099 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1100
95ea3627
ID		 1101 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1102 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1103
1104 if (eeprom != 0xffff && eeprom != 0x0000) {
1105 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1106 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1107 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1108 }
1109 }
95ea3627
ID		 1110
1111 return 0;
1112}
1113
1114/*
1115 * Device state switch handlers.
1116 */
95ea3627
ID		 1117static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1118 enum dev_state state)
1119{
b550911a 1120 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 1121 u32 reg;
16222a0d 1122 unsigned long flags;
95ea3627
ID		 1123
1124 /*
1125 * When interrupts are being enabled, the interrupt registers
1126 * should clear the register to assure a clean state.
1127 */
1128 if (state == STATE_RADIO_IRQ_ON) {
c517123a
GJ		 1129 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1130 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
95ea3627
ID		 1131 }
1132
1133 /*
1134 * Only toggle the interrupts bits we are going to use.
1135 * Non-checked interrupt bits are disabled by default.
1136 */
16222a0d
HS		 1137 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1138
c517123a 1139 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
95ea3627
ID		 1140 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1141 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1142 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1143 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1144 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
c517123a 1145 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
16222a0d
HS		 1146
1147 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1148
1149 if (state == STATE_RADIO_IRQ_OFF) {
1150 /*
1151 * Ensure that all tasklets are finished.
1152 */
abc11994
HS		 1153 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1154 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1155 tasklet_kill(&rt2x00dev->tbtt_tasklet);
16222a0d 1156 }
95ea3627
ID		 1157}
1158
1159static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1160{
1161 /*
1162 * Initialize all registers.
1163 */
2b08da3f
ID		 1164 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1165 rt2500pci_init_registers(rt2x00dev) ||
1166 rt2500pci_init_bbp(rt2x00dev)))
95ea3627 1167 return -EIO;
95ea3627 1168
95ea3627
ID		 1169 return 0;
1170}
1171
1172static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1173{
95ea3627 1174 /*
a2c9b652 1175 * Disable power
95ea3627 1176 */
c517123a 1177 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1178}
1179
1180static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1181 enum dev_state state)
1182{
9655a6ec 1183 u32 reg, reg2;
95ea3627
ID		 1184 unsigned int i;
1185 char put_to_sleep;
1186 char bbp_state;
1187 char rf_state;
1188
1189 put_to_sleep = (state != STATE_AWAKE);
1190
c517123a 1191 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
95ea3627
ID		 1192 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1193 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1194 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1195 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
c517123a 1196 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1197
1198 /*
1199 * Device is not guaranteed to be in the requested state yet.
1200 * We must wait until the register indicates that the
1201 * device has entered the correct state.
1202 */
1203 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
c517123a 1204 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
9655a6ec
GW		 1205 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1206 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1207 if (bbp_state == state && rf_state == state)
1208 return 0;
c517123a 1209 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1210 msleep(10);
1211 }
1212
95ea3627
ID		 1213 return -EBUSY;
1214}
1215
1216static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1217 enum dev_state state)
1218{
1219 int retval = 0;
1220
1221 switch (state) {
1222 case STATE_RADIO_ON:
1223 retval = rt2500pci_enable_radio(rt2x00dev);
1224 break;
1225 case STATE_RADIO_OFF:
1226 rt2500pci_disable_radio(rt2x00dev);
1227 break;
2b08da3f
ID		 1228 case STATE_RADIO_IRQ_ON:
1229 case STATE_RADIO_IRQ_OFF:
1230 rt2500pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1231 break;
1232 case STATE_DEEP_SLEEP:
1233 case STATE_SLEEP:
1234 case STATE_STANDBY:
1235 case STATE_AWAKE:
1236 retval = rt2500pci_set_state(rt2x00dev, state);
1237 break;
1238 default:
1239 retval = -ENOTSUPP;
1240 break;
1241 }
1242
2b08da3f 1243 if (unlikely(retval))
ec9c4989
JP		 1244 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1245 state, retval);
2b08da3f 1246
95ea3627
ID		 1247 return retval;
1248}
1249
1250/*
1251 * TX descriptor initialization
1252 */
93331458 1253static void rt2500pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1254 struct txentry_desc *txdesc)
95ea3627 1255{
93331458 1256 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
c517123a 1257 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
85b7a8b3 1258 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1259 u32 word;
1260
1261 /*
1262 * Start writing the descriptor words.
1263 */
85b7a8b3 1264 rt2x00_desc_read(txd, 1, &word);
c4da0048 1265 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1266 rt2x00_desc_write(txd, 1, word);
4de36fe5 1267
95ea3627
ID		 1268 rt2x00_desc_read(txd, 2, &word);
1269 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
2b23cdaa
HS		 1270 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1271 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1272 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
95ea3627
ID		 1273 rt2x00_desc_write(txd, 2, word);
1274
1275 rt2x00_desc_read(txd, 3, &word);
26a1d07f
HS		 1276 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1277 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1278 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1279 txdesc->u.plcp.length_low);
1280 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1281 txdesc->u.plcp.length_high);
95ea3627
ID		 1282 rt2x00_desc_write(txd, 3, word);
1283
1284 rt2x00_desc_read(txd, 10, &word);
1285 rt2x00_set_field32(&word, TXD_W10_RTS,
181d6902 1286 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
95ea3627
ID		 1287 rt2x00_desc_write(txd, 10, word);
1288
e01f1ec3
GW		 1289 /*
1290 * Writing TXD word 0 must the last to prevent a race condition with
1291 * the device, whereby the device may take hold of the TXD before we
1292 * finished updating it.
1293 */
95ea3627
ID		 1294 rt2x00_desc_read(txd, 0, &word);
1295 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1296 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1297 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1298 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1299 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1300 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1301 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1302 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1303 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1304 (txdesc->rate_mode == RATE_MODE_OFDM));
95ea3627 1305 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
2517794b 1306 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1307 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1308 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
df624ca5 1309 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1310 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1311 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1312
1313 /*
1314 * Register descriptor details in skb frame descriptor.
1315 */
1316 skbdesc->desc = txd;
1317 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1318}
1319
1320/*
1321 * TX data initialization
1322 */
f224f4ef
GW		 1323static void rt2500pci_write_beacon(struct queue_entry *entry,
1324 struct txentry_desc *txdesc)
bd88a781
ID		 1325{
1326 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1327 u32 reg;
1328
1329 /*
1330 * Disable beaconing while we are reloading the beacon data,
1331 * otherwise we might be sending out invalid data.
1332 */
c517123a 1333 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
bd88a781 1334 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
c517123a 1335 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781 1336
4ea545d4 1337 if (rt2x00queue_map_txskb(entry)) {
ec9c4989 1338 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
4ea545d4
SG		 1339 goto out;
1340 }
bd88a781 1341
5c3b685c
GW		 1342 /*
1343 * Write the TX descriptor for the beacon.
1344 */
93331458 1345 rt2500pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1346
1347 /*
1348 * Dump beacon to userspace through debugfs.
1349 */
1350 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
4ea545d4 1351out:
d61cb266
GW		 1352 /*
1353 * Enable beaconing again.
1354 */
d61cb266 1355 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
c517123a 1356 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1357}
1358
95ea3627
ID		 1359/*
1360 * RX control handlers
1361 */
181d6902
ID		 1362static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1363 struct rxdone_entry_desc *rxdesc)
95ea3627 1364{
c517123a 1365 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 1366 u32 word0;
1367 u32 word2;
1368
b8be63ff
ID		 1369 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1370 rt2x00_desc_read(entry_priv->desc, 2, &word2);
95ea3627 1371
4150c572 1372 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1373 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1374 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902
ID		 1375 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1376
89993890
ID		 1377 /*
1378 * Obtain the status about this packet.
1379 * When frame was received with an OFDM bitrate,
1380 * the signal is the PLCP value. If it was received with
1381 * a CCK bitrate the signal is the rate in 100kbit/s.
1382 */
181d6902
ID		 1383 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1384 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1385 entry->queue->rt2x00dev->rssi_offset;
181d6902 1386 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1387
19d30e02
ID		 1388 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1389 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1390 else
1391 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1392 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1393 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1394}
1395
1396/*
1397 * Interrupt functions.
1398 */
181d6902 1399static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1400 const enum data_queue_qid queue_idx)
95ea3627 1401{
61c6e489 1402 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
c517123a 1403 struct queue_entry_priv_mmio *entry_priv;
181d6902
ID		 1404 struct queue_entry *entry;
1405 struct txdone_entry_desc txdesc;
95ea3627 1406 u32 word;
95ea3627 1407
181d6902
ID		 1408 while (!rt2x00queue_empty(queue)) {
1409 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1410 entry_priv = entry->priv_data;
1411 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1412
1413 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1414 !rt2x00_get_field32(word, TXD_W0_VALID))
1415 break;
1416
1417 /*
1418 * Obtain the status about this packet.
1419 */
fb55f4d1
ID		 1420 txdesc.flags = 0;
1421 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1422 case 0: /* Success */
1423 case 1: /* Success with retry */
1424 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1425 break;
1426 case 2: /* Failure, excessive retries */
1427 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1428 /* Don't break, this is a failed frame! */
1429 default: /* Failure */
1430 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1431 }
181d6902 1432 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1433
e513a0b6 1434 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1435 }
95ea3627
ID		 1436}
1437
7a5a681a
HS		 1438static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1439 struct rt2x00_field32 irq_field)
95ea3627 1440{
16222a0d 1441 u32 reg;
95ea3627
ID		 1442
1443 /*
16222a0d
HS		 1444 * Enable a single interrupt. The interrupt mask register
1445 * access needs locking.
95ea3627 1446 */
0aa13b2e 1447 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1448
c517123a 1449 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
16222a0d 1450 rt2x00_set_field32(&reg, irq_field, 0);
c517123a 1451 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
95ea3627 1452
0aa13b2e 1453 spin_unlock_irq(&rt2x00dev->irqmask_lock);
16222a0d 1454}
95ea3627 1455
16222a0d
HS		 1456static void rt2500pci_txstatus_tasklet(unsigned long data)
1457{
1458 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1459 u32 reg;
95ea3627
ID		 1460
1461 /*
16222a0d 1462 * Handle all tx queues.
95ea3627 1463 */
16222a0d
HS		 1464 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1465 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1466 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1467
1468 /*
16222a0d 1469 * Enable all TXDONE interrupts again.
95ea3627 1470 */
abc11994
HS		 1471 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1472 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1473
c517123a 1474 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
abc11994
HS		 1475 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1476 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1477 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
c517123a 1478 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
78e256c9 1479
abc11994
HS		 1480 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1481 }
16222a0d
HS		 1482}
1483
1484static void rt2500pci_tbtt_tasklet(unsigned long data)
1485{
1486 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1487 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1488 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1489 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
16222a0d
HS		 1490}
1491
1492static void rt2500pci_rxdone_tasklet(unsigned long data)
1493{
1494 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
c517123a 1495 if (rt2x00mmio_rxdone(rt2x00dev))
16638937 1496 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1497 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1498 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1499}
1500
78e256c9
HS		 1501static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1502{
1503 struct rt2x00_dev *rt2x00dev = dev_instance;
16222a0d 1504 u32 reg, mask;
78e256c9
HS		 1505
1506 /*
1507 * Get the interrupt sources & saved to local variable.
1508 * Write register value back to clear pending interrupts.
1509 */
c517123a
GJ		 1510 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1511 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
78e256c9
HS		 1512
1513 if (!reg)
1514 return IRQ_NONE;
1515
1516 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1517 return IRQ_HANDLED;
1518
16222a0d
HS		 1519 mask = reg;
1520
1521 /*
1522 * Schedule tasklets for interrupt handling.
1523 */
1524 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1525 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1526
1527 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1528 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1529
1530 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1531 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1532 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1533 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1534 /*
1535 * Mask out all txdone interrupts.
1536 */
1537 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1538 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1539 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1540 }
1541
1542 /*
1543 * Disable all interrupts for which a tasklet was scheduled right now,
1544 * the tasklet will reenable the appropriate interrupts.
1545 */
0aa13b2e 1546 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1547
c517123a 1548 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
16222a0d 1549 reg |= mask;
c517123a 1550 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
16222a0d 1551
0aa13b2e 1552 spin_unlock(&rt2x00dev->irqmask_lock);
78e256c9 1553
16222a0d 1554 return IRQ_HANDLED;
78e256c9
HS		 1555}
1556
95ea3627
ID		 1557/*
1558 * Device probe functions.
1559 */
1560static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1561{
1562 struct eeprom_93cx6 eeprom;
1563 u32 reg;
1564 u16 word;
1565 u8 *mac;
1566
c517123a 1567 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
95ea3627
ID		 1568
1569 eeprom.data = rt2x00dev;
1570 eeprom.register_read = rt2500pci_eepromregister_read;
1571 eeprom.register_write = rt2500pci_eepromregister_write;
1572 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1573 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1574 eeprom.reg_data_in = 0;
1575 eeprom.reg_data_out = 0;
1576 eeprom.reg_data_clock = 0;
1577 eeprom.reg_chip_select = 0;
1578
1579 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1580 EEPROM_SIZE / sizeof(u16));
1581
1582 /*
1583 * Start validation of the data that has been read.
1584 */
1585 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1586 if (!is_valid_ether_addr(mac)) {
f4f7f414 1587 eth_random_addr(mac);
ec9c4989 1588 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1589 }
1590
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1592 if (word == 0xffff) {
1593 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1594 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1595 ANTENNA_SW_DIVERSITY);
1596 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1597 ANTENNA_SW_DIVERSITY);
1598 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1599 LED_MODE_DEFAULT);
95ea3627
ID		 1600 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1601 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1602 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1603 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
ec9c4989 1604 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
95ea3627
ID		 1605 }
1606
1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1608 if (word == 0xffff) {
1609 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1610 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1611 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1612 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
ec9c4989 1613 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
95ea3627
ID		 1614 }
1615
1616 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1617 if (word == 0xffff) {
1618 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1619 DEFAULT_RSSI_OFFSET);
1620 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
ec9c4989
JP		 1621 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1622 word);
95ea3627
ID		 1623 }
1624
1625 return 0;
1626}
1627
1628static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1629{
1630 u32 reg;
1631 u16 value;
1632 u16 eeprom;
1633
1634 /*
1635 * Read EEPROM word for configuration.
1636 */
1637 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1638
1639 /*
1640 * Identify RF chipset.
1641 */
1642 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
c517123a 1643 rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1644 rt2x00_set_chip(rt2x00dev, RT2560, value,
1645 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1646
5122d898
GW		 1647 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1648 !rt2x00_rf(rt2x00dev, RF2523) &&
1649 !rt2x00_rf(rt2x00dev, RF2524) &&
1650 !rt2x00_rf(rt2x00dev, RF2525) &&
1651 !rt2x00_rf(rt2x00dev, RF2525E) &&
1652 !rt2x00_rf(rt2x00dev, RF5222)) {
ec9c4989 1653 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
95ea3627
ID		 1654 return -ENODEV;
1655 }
1656
1657 /*
1658 * Identify default antenna configuration.
1659 */
addc81bd 1660 rt2x00dev->default_ant.tx =
95ea3627 1661 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1662 rt2x00dev->default_ant.rx =
95ea3627
ID		 1663 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1664
1665 /*
1666 * Store led mode, for correct led behaviour.
1667 */
771fd565 1668#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1669 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1670
475433be 1671 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1672 if (value == LED_MODE_TXRX_ACTIVITY ||
1673 value == LED_MODE_DEFAULT ||
1674 value == LED_MODE_ASUS)
475433be
ID		 1675 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1676 LED_TYPE_ACTIVITY);
771fd565 1677#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1678
1679 /*
1680 * Detect if this device has an hardware controlled radio.
1681 */
616a8394 1682 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) {
7dab73b3 1683 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
616a8394
SG		 1684 /*
1685 * On this device RFKILL initialized during probe does not work.
1686 */
1687 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags);
1688 }
95ea3627
ID		 1689
1690 /*
1691 * Check if the BBP tuning should be enabled.
1692 */
1693 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
27df2a9c 1694 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
7dab73b3 1695 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1696
1697 /*
1698 * Read the RSSI <-> dBm offset information.
1699 */
1700 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1701 rt2x00dev->rssi_offset =
1702 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1703
1704 return 0;
1705}
1706
1707/*
1708 * RF value list for RF2522
1709 * Supports: 2.4 GHz
1710 */
1711static const struct rf_channel rf_vals_bg_2522[] = {
1712 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1713 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1714 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1715 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1716 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1717 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1718 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1719 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1720 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1721 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1722 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1723 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1724 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1725 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1726};
1727
1728/*
1729 * RF value list for RF2523
1730 * Supports: 2.4 GHz
1731 */
1732static const struct rf_channel rf_vals_bg_2523[] = {
1733 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1734 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1735 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1736 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1737 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1738 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1739 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1740 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1741 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1742 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1743 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1744 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1745 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1746 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1747};
1748
1749/*
1750 * RF value list for RF2524
1751 * Supports: 2.4 GHz
1752 */
1753static const struct rf_channel rf_vals_bg_2524[] = {
1754 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1755 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1756 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1757 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1758 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1759 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1760 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1761 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1762 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1763 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1764 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1765 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1766 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1767 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1768};
1769
1770/*
1771 * RF value list for RF2525
1772 * Supports: 2.4 GHz
1773 */
1774static const struct rf_channel rf_vals_bg_2525[] = {
1775 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1776 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1777 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1778 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1779 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1780 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1781 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1782 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1783 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1784 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1785 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1786 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1787 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1788 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1789};
1790
1791/*
1792 * RF value list for RF2525e
1793 * Supports: 2.4 GHz
1794 */
1795static const struct rf_channel rf_vals_bg_2525e[] = {
1796 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1797 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1798 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1799 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1800 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1801 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1802 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1803 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1804 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1805 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1806 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1807 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1808 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1809 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1810};
1811
1812/*
1813 * RF value list for RF5222
1814 * Supports: 2.4 GHz & 5.2 GHz
1815 */
1816static const struct rf_channel rf_vals_5222[] = {
1817 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1818 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1819 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1820 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1821 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1822 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1823 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1824 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1825 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1826 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1827 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1828 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1829 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1830 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1831
1832 /* 802.11 UNI / HyperLan 2 */
1833 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1834 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1835 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1836 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1837 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1838 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1839 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1840 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1841
1842 /* 802.11 HyperLan 2 */
1843 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1844 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1845 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1846 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1847 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1848 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1849 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1850 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1851 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1852 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1853
1854 /* 802.11 UNII */
1855 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1856 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1857 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1858 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1859 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1860};
1861
8c5e7a5f 1862static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1863{
1864 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1865 struct channel_info *info;
1866 char *tx_power;
95ea3627
ID		 1867 unsigned int i;
1868
1869 /*
1870 * Initialize all hw fields.
1871 */
30686bf7
JB		 1872 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
1873 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
1874 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
1875 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
566bfe5a 1876
14a3bf89 1877 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1878 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1879 rt2x00_eeprom_addr(rt2x00dev,
1880 EEPROM_MAC_ADDR_0));
1881
8b0df00f
SG		 1882 /*
1883 * Disable powersaving as default.
1884 */
1885 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1886
95ea3627
ID		 1887 /*
1888 * Initialize hw_mode information.
1889 */
31562e80
ID		 1890 spec->supported_bands = SUPPORT_BAND_2GHZ;
1891 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 1892
5122d898 1893 if (rt2x00_rf(rt2x00dev, RF2522)) {
95ea3627
ID		 1894 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1895 spec->channels = rf_vals_bg_2522;
5122d898 1896 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
95ea3627
ID		 1897 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1898 spec->channels = rf_vals_bg_2523;
5122d898 1899 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
95ea3627
ID		 1900 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1901 spec->channels = rf_vals_bg_2524;
5122d898 1902 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
95ea3627
ID		 1903 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1904 spec->channels = rf_vals_bg_2525;
5122d898 1905 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
95ea3627
ID		 1906 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1907 spec->channels = rf_vals_bg_2525e;
5122d898 1908 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
31562e80 1909 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1910 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1911 spec->channels = rf_vals_5222;
95ea3627 1912 }
8c5e7a5f
ID		 1913
1914 /*
1915 * Create channel information array
1916 */
baeb2ffa 1917 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1918 if (!info)
1919 return -ENOMEM;
1920
1921 spec->channels_info = info;
1922
1923 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1924 for (i = 0; i < 14; i++) {
1925 info[i].max_power = MAX_TXPOWER;
1926 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1927 }
8c5e7a5f
ID		 1928
1929 if (spec->num_channels > 14) {
8d1331b3
ID		 1930 for (i = 14; i < spec->num_channels; i++) {
1931 info[i].max_power = MAX_TXPOWER;
1932 info[i].default_power1 = DEFAULT_TXPOWER;
1933 }
8c5e7a5f
ID		 1934 }
1935
1936 return 0;
95ea3627
ID		 1937}
1938
1939static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1940{
1941 int retval;
a396e100 1942 u32 reg;
95ea3627
ID		 1943
1944 /*
1945 * Allocate eeprom data.
1946 */
1947 retval = rt2500pci_validate_eeprom(rt2x00dev);
1948 if (retval)
1949 return retval;
1950
1951 retval = rt2500pci_init_eeprom(rt2x00dev);
1952 if (retval)
1953 return retval;
1954
a396e100
GW		 1955 /*
1956 * Enable rfkill polling by setting GPIO direction of the
1957 * rfkill switch GPIO pin correctly.
1958 */
c517123a 1959 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
a396e100 1960 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
c517123a 1961 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
a396e100 1962
95ea3627
ID		 1963 /*
1964 * Initialize hw specifications.
1965 */
8c5e7a5f
ID		 1966 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1967 if (retval)
1968 return retval;
95ea3627
ID		 1969
1970 /*
c4da0048 1971 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1972 */
7dab73b3
ID		 1973 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1974 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1975 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1976
1977 /*
1978 * Set the rssi offset.
1979 */
1980 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1981
1982 return 0;
1983}
1984
1985/*
1986 * IEEE80211 stack callback functions.
1987 */
37a41b4a
EP		 1988static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1989 struct ieee80211_vif *vif)
95ea3627
ID		 1990{
1991 struct rt2x00_dev *rt2x00dev = hw->priv;
1992 u64 tsf;
1993 u32 reg;
1994
c517123a 1995 rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
95ea3627 1996 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
c517123a 1997 rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
95ea3627
ID		 1998 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1999
2000 return tsf;
2001}
2002
95ea3627
ID		 2003static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
2004{
2005 struct rt2x00_dev *rt2x00dev = hw->priv;
2006 u32 reg;
2007
c517123a 2008 rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
95ea3627
ID		 2009 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2010}
2011
2012static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2013 .tx = rt2x00mac_tx,
4150c572
JB		 2014 .start = rt2x00mac_start,
2015 .stop = rt2x00mac_stop,
95ea3627
ID		 2016 .add_interface = rt2x00mac_add_interface,
2017 .remove_interface = rt2x00mac_remove_interface,
2018 .config = rt2x00mac_config,
3a643d24 2019 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 2020 .sw_scan_start = rt2x00mac_sw_scan_start,
2021 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2022 .get_stats = rt2x00mac_get_stats,
471b3efd 2023 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 2024 .conf_tx = rt2x00mac_conf_tx,
95ea3627 2025 .get_tsf = rt2500pci_get_tsf,
95ea3627 2026 .tx_last_beacon = rt2500pci_tx_last_beacon,
e47a5cdd 2027 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2028 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 2029 .set_antenna = rt2x00mac_set_antenna,
2030 .get_antenna = rt2x00mac_get_antenna,
e7dee444 2031 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 2032 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 2033};
2034
2035static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2036 .irq_handler = rt2500pci_interrupt,
16222a0d
HS		 2037 .txstatus_tasklet = rt2500pci_txstatus_tasklet,
2038 .tbtt_tasklet = rt2500pci_tbtt_tasklet,
2039 .rxdone_tasklet = rt2500pci_rxdone_tasklet,
95ea3627 2040 .probe_hw = rt2500pci_probe_hw,
c517123a
GJ		 2041 .initialize = rt2x00mmio_initialize,
2042 .uninitialize = rt2x00mmio_uninitialize,
798b7adb
ID		 2043 .get_entry_state = rt2500pci_get_entry_state,
2044 .clear_entry = rt2500pci_clear_entry,
95ea3627 2045 .set_device_state = rt2500pci_set_device_state,
95ea3627 2046 .rfkill_poll = rt2500pci_rfkill_poll,
95ea3627
ID		 2047 .link_stats = rt2500pci_link_stats,
2048 .reset_tuner = rt2500pci_reset_tuner,
2049 .link_tuner = rt2500pci_link_tuner,
dbba306f
ID		 2050 .start_queue = rt2500pci_start_queue,
2051 .kick_queue = rt2500pci_kick_queue,
2052 .stop_queue = rt2500pci_stop_queue,
c517123a 2053 .flush_queue = rt2x00mmio_flush_queue,
95ea3627 2054 .write_tx_desc = rt2500pci_write_tx_desc,
bd88a781 2055 .write_beacon = rt2500pci_write_beacon,
95ea3627 2056 .fill_rxdone = rt2500pci_fill_rxdone,
3a643d24 2057 .config_filter = rt2500pci_config_filter,
6bb40dd1 2058 .config_intf = rt2500pci_config_intf,
72810379 2059 .config_erp = rt2500pci_config_erp,
e4ea1c40 2060 .config_ant = rt2500pci_config_ant,
95ea3627
ID		 2061 .config = rt2500pci_config,
2062};
2063
7c030821
GJ		 2064static void rt2500pci_queue_init(struct data_queue *queue)
2065{
2066 switch (queue->qid) {
2067 case QID_RX:
2068 queue->limit = 32;
2069 queue->data_size = DATA_FRAME_SIZE;
2070 queue->desc_size = RXD_DESC_SIZE;
2071 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2072 break;
181d6902 2073
7c030821
GJ		 2074 case QID_AC_VO:
2075 case QID_AC_VI:
2076 case QID_AC_BE:
2077 case QID_AC_BK:
2078 queue->limit = 32;
2079 queue->data_size = DATA_FRAME_SIZE;
2080 queue->desc_size = TXD_DESC_SIZE;
2081 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2082 break;
181d6902 2083
7c030821
GJ		 2084 case QID_BEACON:
2085 queue->limit = 1;
2086 queue->data_size = MGMT_FRAME_SIZE;
2087 queue->desc_size = TXD_DESC_SIZE;
2088 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2089 break;
181d6902 2090
7c030821
GJ		 2091 case QID_ATIM:
2092 queue->limit = 8;
2093 queue->data_size = DATA_FRAME_SIZE;
2094 queue->desc_size = TXD_DESC_SIZE;
2095 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2096 break;
2097
2098 default:
2099 BUG();
2100 break;
2101 }
2102}
181d6902 2103
95ea3627 2104static const struct rt2x00_ops rt2500pci_ops = {
04d0362e 2105 .name = KBUILD_MODNAME,
04d0362e
GW		 2106 .max_ap_intf = 1,
2107 .eeprom_size = EEPROM_SIZE,
2108 .rf_size = RF_SIZE,
2109 .tx_queues = NUM_TX_QUEUES,
7c030821 2110 .queue_init = rt2500pci_queue_init,
04d0362e
GW		 2111 .lib = &rt2500pci_rt2x00_ops,
2112 .hw = &rt2500pci_mac80211_ops,
95ea3627 2113#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2114 .debugfs = &rt2500pci_rt2x00debug,
95ea3627
ID		 2115#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2116};
2117
2118/*
2119 * RT2500pci module information.
2120 */
9baa3c34 2121static const struct pci_device_id rt2500pci_device_table[] = {
e01ae27f 2122 { PCI_DEVICE(0x1814, 0x0201) },
95ea3627
ID		 2123 { 0, }
2124};
2125
2126MODULE_AUTHOR(DRV_PROJECT);
2127MODULE_VERSION(DRV_VERSION);
2128MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2129MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2130MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2131MODULE_LICENSE("GPL");
2132
e01ae27f
GW		 2133static int rt2500pci_probe(struct pci_dev *pci_dev,
2134 const struct pci_device_id *id)
2135{
2136 return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2137}
2138
95ea3627 2139static struct pci_driver rt2500pci_driver = {
2360157c 2140 .name = KBUILD_MODNAME,
95ea3627 2141 .id_table = rt2500pci_device_table,
e01ae27f 2142 .probe = rt2500pci_probe,
69202359 2143 .remove = rt2x00pci_remove,
95ea3627
ID		 2144 .suspend = rt2x00pci_suspend,
2145 .resume = rt2x00pci_resume,
2146};
2147
5b0a3b7e 2148module_pci_driver(rt2500pci_driver);
Linux kernel - Deliverables
This page took 1.474119 seconds and 5 git commands to generate.