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rtlwifi: rtl8192ce: Rework rtl8192ce/phy.c
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/usb.h>
35
36#include "rt2x00.h"
37#include "rt2x00usb.h"
38#include "rt73usb.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
821cde63 43static int modparam_nohwcrypt;
008c4482
ID		 44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * All access to the CSR registers will go through the methods
0f829b1d 50 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 51 * BBP and RF register require indirect register access,
52 * and use the CSR registers BBPCSR and RFCSR to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attampt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
8ff48a8b 59 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 60 */
c9c3b1a5 61#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 62 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 63#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 64 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 65
0e14f6d3 66static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
8ff48a8b 71 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 72
95ea3627 73 /*
c9c3b1a5
ID		 74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
95ea3627 76 */
c9c3b1a5
ID		 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
0f829b1d 84 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 85 }
99ade259 86
8ff48a8b 87 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 88}
89
0e14f6d3 90static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int word, u8 *value)
92{
93 u32 reg;
94
8ff48a8b 95 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 96
95ea3627 97 /*
c9c3b1a5
ID		 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
95ea3627 104 */
c9c3b1a5
ID		 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 110
0f829b1d 111 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 112
c9c3b1a5
ID		 113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
95ea3627
ID		 115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 117
8ff48a8b 118 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 119}
120
0e14f6d3 121static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 122 const unsigned int word, const u32 value)
123{
124 u32 reg;
95ea3627 125
8ff48a8b 126 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 127
4f5af6eb 128 /*
c9c3b1a5
ID		 129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
4f5af6eb 131 */
c9c3b1a5
ID		 132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 /*
136 * RF5225 and RF2527 contain 21 bits per RF register value,
137 * all others contain 20 bits.
138 */
139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
5122d898
GW		 140 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141 rt2x00_rf(rt2x00dev, RF2527)));
c9c3b1a5
ID		 142 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
0f829b1d 145 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 146 rt2x00_rf_write(rt2x00dev, word, value);
147 }
8ff48a8b
ID		 148
149 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 150}
151
152#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 153static const struct rt2x00debug rt73usb_rt2x00debug = {
154 .owner = THIS_MODULE,
155 .csr = {
0f829b1d
ID		 156 .read = rt2x00usb_register_read,
157 .write = rt2x00usb_register_write,
743b97ca
ID		 158 .flags = RT2X00DEBUGFS_OFFSET,
159 .word_base = CSR_REG_BASE,
95ea3627
ID		 160 .word_size = sizeof(u32),
161 .word_count = CSR_REG_SIZE / sizeof(u32),
162 },
163 .eeprom = {
164 .read = rt2x00_eeprom_read,
165 .write = rt2x00_eeprom_write,
743b97ca 166 .word_base = EEPROM_BASE,
95ea3627
ID		 167 .word_size = sizeof(u16),
168 .word_count = EEPROM_SIZE / sizeof(u16),
169 },
170 .bbp = {
171 .read = rt73usb_bbp_read,
172 .write = rt73usb_bbp_write,
743b97ca 173 .word_base = BBP_BASE,
95ea3627
ID		 174 .word_size = sizeof(u8),
175 .word_count = BBP_SIZE / sizeof(u8),
176 },
177 .rf = {
178 .read = rt2x00_rf_read,
179 .write = rt73usb_rf_write,
743b97ca 180 .word_base = RF_BASE,
95ea3627
ID		 181 .word_size = sizeof(u32),
182 .word_count = RF_SIZE / sizeof(u32),
183 },
184};
185#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
7396faf4
ID		 187static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188{
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193}
7396faf4 194
771fd565 195#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 196static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 197 enum led_brightness brightness)
198{
199 struct rt2x00_led *led =
200 container_of(led_cdev, struct rt2x00_led, led_dev);
201 unsigned int enabled = brightness != LED_OFF;
202 unsigned int a_mode =
203 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204 unsigned int bg_mode =
205 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207 if (led->type == LED_TYPE_RADIO) {
208 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209 MCU_LEDCS_RADIO_STATUS, enabled);
210
47b10cd1
ID		 211 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212 0, led->rt2x00dev->led_mcu_reg,
213 REGISTER_TIMEOUT);
a9450b70
ID		 214 } else if (led->type == LED_TYPE_ASSOC) {
215 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218 MCU_LEDCS_LINK_A_STATUS, a_mode);
219
47b10cd1
ID		 220 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221 0, led->rt2x00dev->led_mcu_reg,
222 REGISTER_TIMEOUT);
a9450b70
ID		 223 } else if (led->type == LED_TYPE_QUALITY) {
224 /*
225 * The brightness is divided into 6 levels (0 - 5),
226 * this means we need to convert the brightness
227 * argument into the matching level within that range.
228 */
47b10cd1
ID		 229 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230 brightness / (LED_FULL / 6),
231 led->rt2x00dev->led_mcu_reg,
232 REGISTER_TIMEOUT);
a9450b70
ID		 233 }
234}
a2e1d52a
ID		 235
236static int rt73usb_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239{
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
0f829b1d 244 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 245 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 247 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 248
249 return 0;
250}
475433be
ID		 251
252static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255{
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt73usb_brightness_set;
259 led->led_dev.blink_set = rt73usb_blink_set;
260 led->flags = LED_INITIALIZED;
261}
771fd565 262#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 263
95ea3627
ID		 264/*
265 * Configuration handlers.
266 */
906c110f
ID		 267static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268 struct rt2x00lib_crypto *crypto,
269 struct ieee80211_key_conf *key)
270{
271 struct hw_key_entry key_entry;
272 struct rt2x00_field32 field;
906c110f
ID		 273 u32 mask;
274 u32 reg;
275
276 if (crypto->cmd == SET_KEY) {
277 /*
278 * rt2x00lib can't determine the correct free
279 * key_idx for shared keys. We have 1 register
280 * with key valid bits. The goal is simple, read
281 * the register, if that is full we have no slots
282 * left.
283 * Note that each BSS is allowed to have up to 4
284 * shared keys, so put a mask over the allowed
285 * entries.
286 */
287 mask = (0xf << crypto->bssidx);
288
0f829b1d 289 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 290 reg &= mask;
291
292 if (reg && reg == mask)
293 return -ENOSPC;
294
acaf908d 295 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 296
297 /*
298 * Upload key to hardware
299 */
300 memcpy(key_entry.key, crypto->key,
301 sizeof(key_entry.key));
302 memcpy(key_entry.tx_mic, crypto->tx_mic,
303 sizeof(key_entry.tx_mic));
304 memcpy(key_entry.rx_mic, crypto->rx_mic,
305 sizeof(key_entry.rx_mic));
306
307 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 308 rt2x00usb_register_multiwrite(rt2x00dev, reg,
309 &key_entry, sizeof(key_entry));
906c110f
ID		 310
311 /*
312 * The cipher types are stored over 2 registers.
313 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314 * bssidx 1 and 2 keys are stored in SEC_CSR5.
315 * Using the correct defines correctly will cause overhead,
316 * so just calculate the correct offset.
317 */
318 if (key->hw_key_idx < 8) {
319 field.bit_offset = (3 * key->hw_key_idx);
320 field.bit_mask = 0x7 << field.bit_offset;
321
0f829b1d 322 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 323 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 324 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 325 } else {
326 field.bit_offset = (3 * (key->hw_key_idx - 8));
327 field.bit_mask = 0x7 << field.bit_offset;
328
0f829b1d 329 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 330 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 331 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 332 }
333
334 /*
335 * The driver does not support the IV/EIV generation
336 * in hardware. However it doesn't support the IV/EIV
337 * inside the ieee80211 frame either, but requires it
3ad2f3fb 338 * to be provided separately for the descriptor.
906c110f
ID		 339 * rt2x00lib will cut the IV/EIV data out of all frames
340 * given to us by mac80211, but we must tell mac80211
341 * to generate the IV/EIV data.
342 */
343 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344 }
345
346 /*
347 * SEC_CSR0 contains only single-bit fields to indicate
348 * a particular key is valid. Because using the FIELD32()
349 * defines directly will cause a lot of overhead we use
350 * a calculation to determine the correct bit directly.
351 */
352 mask = 1 << key->hw_key_idx;
353
0f829b1d 354 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 355 if (crypto->cmd == SET_KEY)
356 reg |= mask;
357 else if (crypto->cmd == DISABLE_KEY)
358 reg &= ~mask;
0f829b1d 359 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 360
361 return 0;
362}
363
364static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365 struct rt2x00lib_crypto *crypto,
366 struct ieee80211_key_conf *key)
367{
368 struct hw_pairwise_ta_entry addr_entry;
369 struct hw_key_entry key_entry;
906c110f
ID		 370 u32 mask;
371 u32 reg;
372
373 if (crypto->cmd == SET_KEY) {
374 /*
375 * rt2x00lib can't determine the correct free
376 * key_idx for pairwise keys. We have 2 registers
377 * with key valid bits. The goal is simple, read
378 * the first register, if that is full move to
379 * the next register.
380 * When both registers are full, we drop the key,
381 * otherwise we use the first invalid entry.
382 */
0f829b1d 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 384 if (reg && reg == ~0) {
385 key->hw_key_idx = 32;
0f829b1d 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 387 if (reg && reg == ~0)
388 return -ENOSPC;
389 }
390
acaf908d 391 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 392
393 /*
394 * Upload key to hardware
395 */
396 memcpy(key_entry.key, crypto->key,
397 sizeof(key_entry.key));
398 memcpy(key_entry.tx_mic, crypto->tx_mic,
399 sizeof(key_entry.tx_mic));
400 memcpy(key_entry.rx_mic, crypto->rx_mic,
401 sizeof(key_entry.rx_mic));
402
403 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 404 rt2x00usb_register_multiwrite(rt2x00dev, reg,
405 &key_entry, sizeof(key_entry));
906c110f
ID		 406
407 /*
408 * Send the address and cipher type to the hardware register.
906c110f
ID		 409 */
410 memset(&addr_entry, 0, sizeof(addr_entry));
411 memcpy(&addr_entry, crypto->address, ETH_ALEN);
412 addr_entry.cipher = crypto->cipher;
413
414 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 415 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 416 &addr_entry, sizeof(addr_entry));
417
418 /*
419 * Enable pairwise lookup table for given BSS idx,
420 * without this received frames will not be decrypted
421 * by the hardware.
422 */
0f829b1d 423 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 424 reg |= (1 << crypto->bssidx);
0f829b1d 425 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 426
427 /*
428 * The driver does not support the IV/EIV generation
429 * in hardware. However it doesn't support the IV/EIV
430 * inside the ieee80211 frame either, but requires it
3ad2f3fb 431 * to be provided separately for the descriptor.
906c110f
ID		 432 * rt2x00lib will cut the IV/EIV data out of all frames
433 * given to us by mac80211, but we must tell mac80211
434 * to generate the IV/EIV data.
435 */
436 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437 }
438
439 /*
440 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441 * a particular key is valid. Because using the FIELD32()
442 * defines directly will cause a lot of overhead we use
443 * a calculation to determine the correct bit directly.
444 */
445 if (key->hw_key_idx < 32) {
446 mask = 1 << key->hw_key_idx;
447
0f829b1d 448 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 449 if (crypto->cmd == SET_KEY)
450 reg |= mask;
451 else if (crypto->cmd == DISABLE_KEY)
452 reg &= ~mask;
0f829b1d 453 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 454 } else {
455 mask = 1 << (key->hw_key_idx - 32);
456
0f829b1d 457 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 458 if (crypto->cmd == SET_KEY)
459 reg |= mask;
460 else if (crypto->cmd == DISABLE_KEY)
461 reg &= ~mask;
0f829b1d 462 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 463 }
464
465 return 0;
466}
467
3a643d24
ID		 468static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469 const unsigned int filter_flags)
470{
471 u32 reg;
472
473 /*
474 * Start configuration steps.
475 * Note that the version error will always be dropped
476 * and broadcast frames will always be accepted since
477 * there is no filter for it at this time.
478 */
0f829b1d 479 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 480 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481 !(filter_flags & FIF_FCSFAIL));
482 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483 !(filter_flags & FIF_PLCPFAIL));
484 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 485 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487 !(filter_flags & FIF_PROMISC_IN_BSS));
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 489 !(filter_flags & FIF_PROMISC_IN_BSS) &&
490 !rt2x00dev->intf_ap_count);
3a643d24
ID		 491 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493 !(filter_flags & FIF_ALLMULTI));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496 !(filter_flags & FIF_CONTROL));
0f829b1d 497 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 498}
499
6bb40dd1
ID		 500static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501 struct rt2x00_intf *intf,
502 struct rt2x00intf_conf *conf,
503 const unsigned int flags)
95ea3627 504{
6bb40dd1 505 u32 reg;
95ea3627 506
6bb40dd1 507 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 508 /*
509 * Enable synchronisation.
510 */
0f829b1d 511 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1 512 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
0f829b1d 513 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 514 }
95ea3627 515
6bb40dd1
ID		 516 if (flags & CONFIG_UPDATE_MAC) {
517 reg = le32_to_cpu(conf->mac[1]);
518 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
519 conf->mac[1] = cpu_to_le32(reg);
95ea3627 520
0f829b1d 521 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 522 conf->mac, sizeof(conf->mac));
523 }
95ea3627 524
6bb40dd1
ID		 525 if (flags & CONFIG_UPDATE_BSSID) {
526 reg = le32_to_cpu(conf->bssid[1]);
527 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
528 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 529
0f829b1d 530 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 531 conf->bssid, sizeof(conf->bssid));
532 }
95ea3627
ID		 533}
534
3a643d24 535static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 536 struct rt2x00lib_erp *erp,
537 u32 changed)
95ea3627 538{
95ea3627 539 u32 reg;
95ea3627 540
0f829b1d 541 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 542 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 543 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 544 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 545
02044643
HS		 546 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
547 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
548 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
549 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
550 !!erp->short_preamble);
551 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
552 }
95ea3627 553
02044643
HS		 554 if (changed & BSS_CHANGED_BASIC_RATES)
555 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
556 erp->basic_rates);
95ea3627 557
02044643
HS		 558 if (changed & BSS_CHANGED_BEACON_INT) {
559 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
560 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
561 erp->beacon_int * 16);
562 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
563 }
8a566afe 564
02044643
HS		 565 if (changed & BSS_CHANGED_ERP_SLOT) {
566 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
567 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
568 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 569
02044643
HS		 570 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
571 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
572 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
573 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
574 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
575 }
95ea3627
ID		 576}
577
578static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 579 struct antenna_setup *ant)
95ea3627
ID		 580{
581 u8 r3;
582 u8 r4;
583 u8 r77;
2676c94d 584 u8 temp;
95ea3627
ID		 585
586 rt73usb_bbp_read(rt2x00dev, 3, &r3);
587 rt73usb_bbp_read(rt2x00dev, 4, &r4);
588 rt73usb_bbp_read(rt2x00dev, 77, &r77);
589
590 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
591
e4cd2ff8
ID		 592 /*
593 * Configure the RX antenna.
594 */
addc81bd 595 switch (ant->rx) {
95ea3627 596 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 597 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
598 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 599 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 600 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 601 break;
602 case ANTENNA_A:
2676c94d 603 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 604 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 605 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 606 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
607 else
608 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 609 break;
610 case ANTENNA_B:
a4fe07d9 611 default:
2676c94d 612 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 613 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 614 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 615 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
616 else
617 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 618 break;
619 }
620
621 rt73usb_bbp_write(rt2x00dev, 77, r77);
622 rt73usb_bbp_write(rt2x00dev, 3, r3);
623 rt73usb_bbp_write(rt2x00dev, 4, r4);
624}
625
626static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 627 struct antenna_setup *ant)
95ea3627
ID		 628{
629 u8 r3;
630 u8 r4;
631 u8 r77;
632
633 rt73usb_bbp_read(rt2x00dev, 3, &r3);
634 rt73usb_bbp_read(rt2x00dev, 4, &r4);
635 rt73usb_bbp_read(rt2x00dev, 77, &r77);
636
637 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
638 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
639 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
640
e4cd2ff8
ID		 641 /*
642 * Configure the RX antenna.
643 */
addc81bd 644 switch (ant->rx) {
95ea3627 645 case ANTENNA_HW_DIVERSITY:
2676c94d 646 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 647 break;
648 case ANTENNA_A:
2676c94d
MN		 649 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
650 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 651 break;
652 case ANTENNA_B:
a4fe07d9 653 default:
2676c94d
MN		 654 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
655 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 656 break;
657 }
658
659 rt73usb_bbp_write(rt2x00dev, 77, r77);
660 rt73usb_bbp_write(rt2x00dev, 3, r3);
661 rt73usb_bbp_write(rt2x00dev, 4, r4);
662}
663
664struct antenna_sel {
665 u8 word;
666 /*
667 * value[0] -> non-LNA
668 * value[1] -> LNA
669 */
670 u8 value[2];
671};
672
673static const struct antenna_sel antenna_sel_a[] = {
674 { 96, { 0x58, 0x78 } },
675 { 104, { 0x38, 0x48 } },
676 { 75, { 0xfe, 0x80 } },
677 { 86, { 0xfe, 0x80 } },
678 { 88, { 0xfe, 0x80 } },
679 { 35, { 0x60, 0x60 } },
680 { 97, { 0x58, 0x58 } },
681 { 98, { 0x58, 0x58 } },
682};
683
684static const struct antenna_sel antenna_sel_bg[] = {
685 { 96, { 0x48, 0x68 } },
686 { 104, { 0x2c, 0x3c } },
687 { 75, { 0xfe, 0x80 } },
688 { 86, { 0xfe, 0x80 } },
689 { 88, { 0xfe, 0x80 } },
690 { 35, { 0x50, 0x50 } },
691 { 97, { 0x48, 0x48 } },
692 { 98, { 0x48, 0x48 } },
693};
694
e4ea1c40
ID		 695static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
696 struct antenna_setup *ant)
95ea3627
ID		 697{
698 const struct antenna_sel *sel;
699 unsigned int lna;
700 unsigned int i;
701 u32 reg;
702
a4fe07d9
ID		 703 /*
704 * We should never come here because rt2x00lib is supposed
705 * to catch this and send us the correct antenna explicitely.
706 */
707 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
708 ant->tx == ANTENNA_SW_DIVERSITY);
709
8318d78a 710 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 711 sel = antenna_sel_a;
712 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 713 } else {
714 sel = antenna_sel_bg;
715 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 716 }
717
2676c94d
MN		 718 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
719 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
720
0f829b1d 721 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 722
ddc827f9 723 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 724 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 726 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 727
0f829b1d 728 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 729
5122d898 730 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
addc81bd 731 rt73usb_config_antenna_5x(rt2x00dev, ant);
5122d898 732 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
addc81bd 733 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 734}
735
e4ea1c40 736static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 737 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 738{
739 u16 eeprom;
740 short lna_gain = 0;
741
742 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
743 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
744 lna_gain += 14;
745
746 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
747 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
748 } else {
749 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
750 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
751 }
752
753 rt2x00dev->lna_gain = lna_gain;
754}
755
756static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
757 struct rf_channel *rf, const int txpower)
758{
759 u8 r3;
760 u8 r94;
761 u8 smart;
762
763 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
764 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
765
5122d898 766 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 767
768 rt73usb_bbp_read(rt2x00dev, 3, &r3);
769 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
770 rt73usb_bbp_write(rt2x00dev, 3, r3);
771
772 r94 = 6;
773 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
774 r94 += txpower - MAX_TXPOWER;
775 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
776 r94 += txpower;
777 rt73usb_bbp_write(rt2x00dev, 94, r94);
778
779 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
780 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
781 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
782 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
783
784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
792 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794 udelay(10);
795}
796
797static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
798 const int txpower)
799{
800 struct rf_channel rf;
801
802 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
803 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
804 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
805 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
806
807 rt73usb_config_channel(rt2x00dev, &rf, txpower);
808}
809
810static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
811 struct rt2x00lib_conf *libconf)
95ea3627
ID		 812{
813 u32 reg;
814
0f829b1d 815 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 816 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
817 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
818 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 819 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
820 libconf->conf->long_frame_max_tx_count);
821 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
822 libconf->conf->short_frame_max_tx_count);
0f829b1d 823 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 824}
95ea3627 825
7d7f19cc
ID		 826static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
827 struct rt2x00lib_conf *libconf)
828{
829 enum dev_state state =
830 (libconf->conf->flags & IEEE80211_CONF_PS) ?
831 STATE_SLEEP : STATE_AWAKE;
832 u32 reg;
833
834 if (state == STATE_SLEEP) {
835 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
836 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 837 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 838 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
839 libconf->conf->listen_interval - 1);
840 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
841
842 /* We must first disable autowake before it can be enabled */
843 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
844 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
845
846 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
847 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
848
849 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
850 USB_MODE_SLEEP, REGISTER_TIMEOUT);
851 } else {
7d7f19cc
ID		 852 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
853 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
854 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
855 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
856 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
857 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
5731858d
GW		 858
859 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
860 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
7d7f19cc
ID		 861 }
862}
863
95ea3627 864static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 865 struct rt2x00lib_conf *libconf,
866 const unsigned int flags)
95ea3627 867{
ba2ab471
ID		 868 /* Always recalculate LNA gain before changing configuration */
869 rt73usb_config_lna_gain(rt2x00dev, libconf);
870
e4ea1c40 871 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 872 rt73usb_config_channel(rt2x00dev, &libconf->rf,
873 libconf->conf->power_level);
e4ea1c40
ID		 874 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
875 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 876 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 877 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
878 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 879 if (flags & IEEE80211_CONF_CHANGE_PS)
880 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 881}
882
95ea3627
ID		 883/*
884 * Link tuning
885 */
ebcf26da
ID		 886static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
887 struct link_qual *qual)
95ea3627
ID		 888{
889 u32 reg;
890
891 /*
892 * Update FCS error count from register.
893 */
0f829b1d 894 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 895 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 896
897 /*
898 * Update False CCA count from register.
899 */
0f829b1d 900 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 901 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 902}
903
5352ff65
ID		 904static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
905 struct link_qual *qual, u8 vgc_level)
eb20b4e8 906{
5352ff65 907 if (qual->vgc_level != vgc_level) {
eb20b4e8 908 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 909 qual->vgc_level = vgc_level;
910 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 911 }
912}
913
5352ff65
ID		 914static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
915 struct link_qual *qual)
95ea3627 916{
5352ff65 917 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 918}
919
5352ff65
ID		 920static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
921 struct link_qual *qual, const u32 count)
95ea3627 922{
95ea3627
ID		 923 u8 up_bound;
924 u8 low_bound;
925
95ea3627
ID		 926 /*
927 * Determine r17 bounds.
928 */
e5ef5bad 929 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 930 low_bound = 0x28;
931 up_bound = 0x48;
932
933 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
934 low_bound += 0x10;
935 up_bound += 0x10;
936 }
937 } else {
5352ff65 938 if (qual->rssi > -82) {
95ea3627
ID		 939 low_bound = 0x1c;
940 up_bound = 0x40;
5352ff65 941 } else if (qual->rssi > -84) {
95ea3627
ID		 942 low_bound = 0x1c;
943 up_bound = 0x20;
944 } else {
945 low_bound = 0x1c;
946 up_bound = 0x1c;
947 }
948
949 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
950 low_bound += 0x14;
951 up_bound += 0x10;
952 }
953 }
954
6bb40dd1
ID		 955 /*
956 * If we are not associated, we should go straight to the
957 * dynamic CCA tuning.
958 */
959 if (!rt2x00dev->intf_associated)
960 goto dynamic_cca_tune;
961
95ea3627
ID		 962 /*
963 * Special big-R17 for very short distance
964 */
5352ff65
ID		 965 if (qual->rssi > -35) {
966 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 967 return;
968 }
969
970 /*
971 * Special big-R17 for short distance
972 */
5352ff65
ID		 973 if (qual->rssi >= -58) {
974 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 975 return;
976 }
977
978 /*
979 * Special big-R17 for middle-short distance
980 */
5352ff65
ID		 981 if (qual->rssi >= -66) {
982 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 983 return;
984 }
985
986 /*
987 * Special mid-R17 for middle distance
988 */
5352ff65
ID		 989 if (qual->rssi >= -74) {
990 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 991 return;
992 }
993
994 /*
995 * Special case: Change up_bound based on the rssi.
996 * Lower up_bound when rssi is weaker then -74 dBm.
997 */
5352ff65 998 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 999 if (low_bound > up_bound)
1000 up_bound = low_bound;
1001
5352ff65
ID		 1002 if (qual->vgc_level > up_bound) {
1003 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1004 return;
1005 }
1006
6bb40dd1
ID		 1007dynamic_cca_tune:
1008
95ea3627
ID		 1009 /*
1010 * r17 does not yet exceed upper limit, continue and base
1011 * the r17 tuning on the false CCA count.
1012 */
5352ff65
ID		 1013 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1014 rt73usb_set_vgc(rt2x00dev, qual,
1015 min_t(u8, qual->vgc_level + 4, up_bound));
1016 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1017 rt73usb_set_vgc(rt2x00dev, qual,
1018 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1019}
1020
5450b7e2
ID		 1021/*
1022 * Queue handlers.
1023 */
1024static void rt73usb_start_queue(struct data_queue *queue)
1025{
1026 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1027 u32 reg;
1028
1029 switch (queue->qid) {
1030 case QID_RX:
1031 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1032 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1033 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1034 break;
1035 case QID_BEACON:
1036 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1037 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1038 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1039 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1040 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1041 break;
1042 default:
1043 break;
1044 }
1045}
1046
1047static void rt73usb_stop_queue(struct data_queue *queue)
1048{
1049 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1050 u32 reg;
1051
1052 switch (queue->qid) {
1053 case QID_RX:
1054 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1055 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1056 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1057 break;
1058 case QID_BEACON:
1059 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1060 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1061 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1062 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1063 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1064 break;
1065 default:
1066 break;
1067 }
5450b7e2
ID		 1068}
1069
95ea3627 1070/*
a7f3a06c 1071 * Firmware functions
95ea3627
ID		 1072 */
1073static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1074{
1075 return FIRMWARE_RT2571;
1076}
1077
0cbe0064
ID		 1078static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1079 const u8 *data, const size_t len)
a7f3a06c 1080{
0cbe0064 1081 u16 fw_crc;
a7f3a06c
ID		 1082 u16 crc;
1083
1084 /*
0cbe0064
ID		 1085 * Only support 2kb firmware files.
1086 */
1087 if (len != 2048)
1088 return FW_BAD_LENGTH;
1089
1090 /*
a7f3a06c
ID		 1091 * The last 2 bytes in the firmware array are the crc checksum itself,
1092 * this means that we should never pass those 2 bytes to the crc
1093 * algorithm.
1094 */
0cbe0064
ID		 1095 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1096
1097 /*
1098 * Use the crc itu-t algorithm.
1099 */
a7f3a06c
ID		 1100 crc = crc_itu_t(0, data, len - 2);
1101 crc = crc_itu_t_byte(crc, 0);
1102 crc = crc_itu_t_byte(crc, 0);
1103
0cbe0064 1104 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1105}
1106
0cbe0064
ID		 1107static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1108 const u8 *data, const size_t len)
95ea3627
ID		 1109{
1110 unsigned int i;
1111 int status;
1112 u32 reg;
95ea3627
ID		 1113
1114 /*
1115 * Wait for stable hardware.
1116 */
1117 for (i = 0; i < 100; i++) {
0f829b1d 1118 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1119 if (reg)
1120 break;
1121 msleep(1);
1122 }
1123
1124 if (!reg) {
1125 ERROR(rt2x00dev, "Unstable hardware.\n");
1126 return -EBUSY;
1127 }
1128
1129 /*
1130 * Write firmware to device.
95ea3627 1131 */
96b61baf 1132 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
95ea3627
ID		 1133
1134 /*
1135 * Send firmware request to device to load firmware,
1136 * we need to specify a long timeout time.
1137 */
1138 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1139 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1140 REGISTER_TIMEOUT_FIRMWARE);
1141 if (status < 0) {
1142 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1143 return status;
1144 }
1145
95ea3627
ID		 1146 return 0;
1147}
1148
a7f3a06c
ID		 1149/*
1150 * Initialization functions.
1151 */
95ea3627
ID		 1152static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1153{
1154 u32 reg;
1155
0f829b1d 1156 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1157 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1158 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1159 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1160 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1161
0f829b1d 1162 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1163 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1164 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1165 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1166 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1167 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1168 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1169 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1170 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1171 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1172
1173 /*
1174 * CCK TXD BBP registers
1175 */
0f829b1d 1176 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1177 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1178 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1179 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1180 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1181 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1182 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1183 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1184 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1185 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1186
1187 /*
1188 * OFDM TXD BBP registers
1189 */
0f829b1d 1190 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1191 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1192 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1193 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1194 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1195 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1196 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1197 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1198
0f829b1d 1199 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1200 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1201 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1202 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1203 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1204 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1205
0f829b1d 1206 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1207 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1208 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1209 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1210 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1211 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1212
0f829b1d 1213 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1214 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1215 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1216 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1217 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1218 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1219 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1220 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1221
0f829b1d 1222 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1223
0f829b1d 1224 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1225 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1226 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1227
0f829b1d 1228 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1229
1230 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1231 return -EBUSY;
1232
0f829b1d 1233 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1234
1235 /*
1236 * Invalidate all Shared Keys (SEC_CSR0),
1237 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1238 */
0f829b1d
ID		 1239 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1240 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1241 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1242
1243 reg = 0x000023b0;
5122d898 1244 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
95ea3627 1245 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1246 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1247
0f829b1d
ID		 1248 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1249 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1250 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1251
0f829b1d 1252 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1253 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1254 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1255
6bb40dd1
ID		 1256 /*
1257 * Clear all beacons
1258 * For the Beacon base registers we only need to clear
1259 * the first byte since that byte contains the VALID and OWNER
1260 * bits which (when set to 0) will invalidate the entire beacon.
1261 */
0f829b1d
ID		 1262 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1263 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1264 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1265 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1266
95ea3627
ID		 1267 /*
1268 * We must clear the error counters.
1269 * These registers are cleared on read,
1270 * so we may pass a useless variable to store the value.
1271 */
0f829b1d
ID		 1272 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1273 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1274 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1275
1276 /*
1277 * Reset MAC and BBP registers.
1278 */
0f829b1d 1279 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1280 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1281 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1282 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1283
0f829b1d 1284 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1285 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1286 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1287 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1288
0f829b1d 1289 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1290 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1291 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1292
1293 return 0;
1294}
1295
2b08da3f 1296static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1297{
1298 unsigned int i;
95ea3627
ID		 1299 u8 value;
1300
1301 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1302 rt73usb_bbp_read(rt2x00dev, 0, &value);
1303 if ((value != 0xff) && (value != 0x00))
2b08da3f 1304 return 0;
95ea3627
ID		 1305 udelay(REGISTER_BUSY_DELAY);
1306 }
1307
1308 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1309 return -EACCES;
2b08da3f
ID		 1310}
1311
1312static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1313{
1314 unsigned int i;
1315 u16 eeprom;
1316 u8 reg_id;
1317 u8 value;
1318
1319 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1320 return -EACCES;
95ea3627 1321
95ea3627
ID		 1322 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1323 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1324 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1325 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1326 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1327 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1328 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1329 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1330 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1331 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1332 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1333 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1334 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1335 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1336 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1337 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1338 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1339 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1340 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1341 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1342 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1343 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1344 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1345 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1346 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1347
95ea3627
ID		 1348 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1349 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1350
1351 if (eeprom != 0xffff && eeprom != 0x0000) {
1352 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1353 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1354 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1355 }
1356 }
95ea3627
ID		 1357
1358 return 0;
1359}
1360
1361/*
1362 * Device state switch handlers.
1363 */
95ea3627
ID		 1364static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1365{
1366 /*
1367 * Initialize all registers.
1368 */
2b08da3f
ID		 1369 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1370 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1371 return -EIO;
95ea3627 1372
95ea3627
ID		 1373 return 0;
1374}
1375
1376static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1377{
0f829b1d 1378 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1379
1380 /*
1381 * Disable synchronisation.
1382 */
0f829b1d 1383 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1384
1385 rt2x00usb_disable_radio(rt2x00dev);
1386}
1387
1388static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1389{
9655a6ec 1390 u32 reg, reg2;
95ea3627
ID		 1391 unsigned int i;
1392 char put_to_sleep;
95ea3627
ID		 1393
1394 put_to_sleep = (state != STATE_AWAKE);
1395
0f829b1d 1396 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1397 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1398 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1399 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1400
1401 /*
1402 * Device is not guaranteed to be in the requested state yet.
1403 * We must wait until the register indicates that the
1404 * device has entered the correct state.
1405 */
1406 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1407 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1408 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1409 if (state == !put_to_sleep)
95ea3627 1410 return 0;
9655a6ec 1411 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1412 msleep(10);
1413 }
1414
95ea3627
ID		 1415 return -EBUSY;
1416}
1417
1418static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1419 enum dev_state state)
1420{
1421 int retval = 0;
1422
1423 switch (state) {
1424 case STATE_RADIO_ON:
1425 retval = rt73usb_enable_radio(rt2x00dev);
1426 break;
1427 case STATE_RADIO_OFF:
1428 rt73usb_disable_radio(rt2x00dev);
1429 break;
2b08da3f
ID		 1430 case STATE_RADIO_IRQ_ON:
1431 case STATE_RADIO_IRQ_OFF:
1432 /* No support, but no error either */
95ea3627
ID		 1433 break;
1434 case STATE_DEEP_SLEEP:
1435 case STATE_SLEEP:
1436 case STATE_STANDBY:
1437 case STATE_AWAKE:
1438 retval = rt73usb_set_state(rt2x00dev, state);
1439 break;
1440 default:
1441 retval = -ENOTSUPP;
1442 break;
1443 }
1444
2b08da3f
ID		 1445 if (unlikely(retval))
1446 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1447 state, retval);
1448
95ea3627
ID		 1449 return retval;
1450}
1451
1452/*
1453 * TX descriptor initialization
1454 */
93331458 1455static void rt73usb_write_tx_desc(struct queue_entry *entry,
906c110f 1456 struct txentry_desc *txdesc)
95ea3627 1457{
93331458
ID		 1458 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1459 __le32 *txd = (__le32 *) entry->skb->data;
95ea3627
ID		 1460 u32 word;
1461
1462 /*
1463 * Start writing the descriptor words.
1464 */
e01f1ec3
GW		 1465 rt2x00_desc_read(txd, 0, &word);
1466 rt2x00_set_field32(&word, TXD_W0_BURST,
1467 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1468 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1469 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1470 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1471 rt2x00_set_field32(&word, TXD_W0_ACK,
1472 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1473 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1474 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1475 rt2x00_set_field32(&word, TXD_W0_OFDM,
1476 (txdesc->rate_mode == RATE_MODE_OFDM));
1477 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1478 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1479 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1480 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1481 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1482 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1483 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1484 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1485 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1486 rt2x00_set_field32(&word, TXD_W0_BURST2,
1487 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1488 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1489 rt2x00_desc_write(txd, 0, word);
1490
95ea3627 1491 rt2x00_desc_read(txd, 1, &word);
2b23cdaa
HS		 1492 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1493 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1494 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1495 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
906c110f 1496 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1497 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1498 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1499 rt2x00_desc_write(txd, 1, word);
1500
1501 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1502 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1503 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1504 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1505 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1506 rt2x00_desc_write(txd, 2, word);
1507
906c110f 1508 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1509 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1510 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1511 }
1512
95ea3627
ID		 1513 rt2x00_desc_read(txd, 5, &word);
1514 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
93331458 1515 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
95ea3627
ID		 1516 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1517 rt2x00_desc_write(txd, 5, word);
1518
85b7a8b3
GW		 1519 /*
1520 * Register descriptor details in skb frame descriptor.
1521 */
0b8004aa 1522 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
85b7a8b3
GW		 1523 skbdesc->desc = txd;
1524 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1525}
1526
bd88a781
ID		 1527/*
1528 * TX data initialization
1529 */
f224f4ef
GW		 1530static void rt73usb_write_beacon(struct queue_entry *entry,
1531 struct txentry_desc *txdesc)
bd88a781
ID		 1532{
1533 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781 1534 unsigned int beacon_base;
739fd940 1535 unsigned int padding_len;
bd88a781
ID		 1536 u32 reg;
1537
bd88a781
ID		 1538 /*
1539 * Disable beaconing while we are reloading the beacon data,
1540 * otherwise we might be sending out invalid data.
1541 */
0f829b1d 1542 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781 1543 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1544 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781 1545
0b8004aa
GW		 1546 /*
1547 * Add space for the descriptor in front of the skb.
1548 */
1549 skb_push(entry->skb, TXD_DESC_SIZE);
1550 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1551
5c3b685c
GW		 1552 /*
1553 * Write the TX descriptor for the beacon.
1554 */
93331458 1555 rt73usb_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1556
1557 /*
1558 * Dump beacon to userspace through debugfs.
1559 */
1560 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1561
bd88a781 1562 /*
739fd940 1563 * Write entire beacon with descriptor and padding to register.
bd88a781 1564 */
739fd940
WK		 1565 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1566 skb_pad(entry->skb, padding_len);
bd88a781 1567 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
739fd940
WK		 1568 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1569 entry->skb->len + padding_len);
bd88a781 1570
d61cb266
GW		 1571 /*
1572 * Enable beaconing again.
1573 *
1574 * For Wi-Fi faily generated beacons between participating stations.
1575 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1576 */
1577 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1578
d61cb266
GW		 1579 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1580 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1581
bd88a781
ID		 1582 /*
1583 * Clean up the beacon skb.
1584 */
1585 dev_kfree_skb(entry->skb);
1586 entry->skb = NULL;
1587}
1588
69cf36a4
HS		 1589static void rt73usb_clear_beacon(struct queue_entry *entry)
1590{
1591 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1592 unsigned int beacon_base;
1593 u32 reg;
1594
1595 /*
1596 * Disable beaconing while we are reloading the beacon data,
1597 * otherwise we might be sending out invalid data.
1598 */
1599 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1600 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1601 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1602
1603 /*
1604 * Clear beacon.
1605 */
1606 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1607 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1608
1609 /*
1610 * Enable beaconing again.
1611 */
1612 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1613 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1614}
1615
f1ca2167 1616static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1617{
1618 int length;
1619
1620 /*
1621 * The length _must_ be a multiple of 4,
1622 * but it must _not_ be a multiple of the USB packet size.
1623 */
f1ca2167
ID		 1624 length = roundup(entry->skb->len, 4);
1625 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1626
1627 return length;
1628}
1629
95ea3627
ID		 1630/*
1631 * RX control handlers
1632 */
1633static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1634{
ba2ab471 1635 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1636 u8 lna;
1637
1638 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1639 switch (lna) {
1640 case 3:
ba2ab471 1641 offset += 90;
95ea3627
ID		 1642 break;
1643 case 2:
ba2ab471 1644 offset += 74;
95ea3627
ID		 1645 break;
1646 case 1:
ba2ab471 1647 offset += 64;
95ea3627
ID		 1648 break;
1649 default:
1650 return 0;
1651 }
1652
e5ef5bad 1653 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1654 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1655 if (lna == 3 || lna == 2)
1656 offset += 10;
1657 } else {
1658 if (lna == 3)
1659 offset += 6;
1660 else if (lna == 2)
1661 offset += 8;
1662 }
95ea3627
ID		 1663 }
1664
1665 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1666}
1667
181d6902 1668static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1669 struct rxdone_entry_desc *rxdesc)
95ea3627 1670{
906c110f 1671 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1672 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1673 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1674 u32 word0;
1675 u32 word1;
1676
f855c10b 1677 /*
a26cbc65
GW		 1678 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1679 * frame data in rt2x00usb.
f855c10b 1680 */
a26cbc65 1681 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1682 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1683
1684 /*
70a96109 1685 * It is now safe to read the descriptor on all architectures.
f855c10b 1686 */
95ea3627
ID		 1687 rt2x00_desc_read(rxd, 0, &word0);
1688 rt2x00_desc_read(rxd, 1, &word1);
1689
4150c572 1690 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1691 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1692
78b8f3b0
GW		 1693 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1694 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
906c110f
ID		 1695
1696 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1697 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1698 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1699 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1700
906c110f 1701 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1702 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1703
1704 /*
1705 * Hardware has stripped IV/EIV data from 802.11 frame during
3ad2f3fb 1706 * decryption. It has provided the data separately but rt2x00lib
906c110f
ID		 1707 * should decide if it should be reinserted.
1708 */
1709 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1710
1711 /*
a0aff623
GW		 1712 * The hardware has already checked the Michael Mic and has
1713 * stripped it from the frame. Signal this to mac80211.
906c110f
ID		 1714 */
1715 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1716
1717 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1718 rxdesc->flags |= RX_FLAG_DECRYPTED;
1719 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1720 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1721 }
1722
95ea3627
ID		 1723 /*
1724 * Obtain the status about this packet.
89993890
ID		 1725 * When frame was received with an OFDM bitrate,
1726 * the signal is the PLCP value. If it was received with
1727 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1728 */
181d6902 1729 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1730 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1731 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1732
19d30e02
ID		 1733 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1734 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1735 else
1736 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1737 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1738 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1739
2ae23854 1740 /*
70a96109 1741 * Set skb pointers, and update frame information.
2ae23854 1742 */
70a96109 1743 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1744 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1745}
1746
1747/*
1748 * Device probe functions.
1749 */
1750static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1751{
1752 u16 word;
1753 u8 *mac;
1754 s8 value;
1755
1756 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1757
1758 /*
1759 * Start validation of the data that has been read.
1760 */
1761 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1762 if (!is_valid_ether_addr(mac)) {
1763 random_ether_addr(mac);
e174961c 1764 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1765 }
1766
1767 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1768 if (word == 0xffff) {
1769 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1770 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1771 ANTENNA_B);
1772 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1773 ANTENNA_B);
95ea3627
ID		 1774 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1775 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1776 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1777 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1778 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1779 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1780 }
1781
1782 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1783 if (word == 0xffff) {
1784 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1785 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1786 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1787 }
1788
1789 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1790 if (word == 0xffff) {
1791 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1792 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1793 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1794 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1795 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1796 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1797 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1798 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1799 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1800 LED_MODE_DEFAULT);
1801 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1802 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1803 }
1804
1805 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1806 if (word == 0xffff) {
1807 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1808 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1809 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1810 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1811 }
1812
1813 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1814 if (word == 0xffff) {
1815 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1816 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1817 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1818 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1819 } else {
1820 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1821 if (value < -10 || value > 10)
1822 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1823 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1824 if (value < -10 || value > 10)
1825 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1826 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1827 }
1828
1829 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1830 if (word == 0xffff) {
1831 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1832 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1833 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1834 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1835 } else {
1836 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1837 if (value < -10 || value > 10)
1838 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1839 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1840 if (value < -10 || value > 10)
1841 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1842 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1843 }
1844
1845 return 0;
1846}
1847
1848static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1849{
1850 u32 reg;
1851 u16 value;
1852 u16 eeprom;
1853
1854 /*
1855 * Read EEPROM word for configuration.
1856 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1858
1859 /*
1860 * Identify RF chipset.
1861 */
1862 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1863 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 1864 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1865 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 1866
49e721ec 1867 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
95ea3627
ID		 1868 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1869 return -ENODEV;
1870 }
1871
5122d898
GW		 1872 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1873 !rt2x00_rf(rt2x00dev, RF2528) &&
1874 !rt2x00_rf(rt2x00dev, RF5225) &&
1875 !rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 1876 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1877 return -ENODEV;
1878 }
1879
1880 /*
1881 * Identify default antenna configuration.
1882 */
addc81bd 1883 rt2x00dev->default_ant.tx =
95ea3627 1884 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1885 rt2x00dev->default_ant.rx =
95ea3627
ID		 1886 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1887
1888 /*
1889 * Read the Frame type.
1890 */
1891 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1892 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1893
7396faf4
ID		 1894 /*
1895 * Detect if this device has an hardware controlled radio.
1896 */
7396faf4
ID		 1897 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1898 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1899
95ea3627
ID		 1900 /*
1901 * Read frequency offset.
1902 */
1903 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1904 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1905
1906 /*
1907 * Read external LNA informations.
1908 */
1909 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1910
1911 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1912 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1913 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1914 }
1915
1916 /*
1917 * Store led settings, for correct led behaviour.
1918 */
771fd565 1919#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1920 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1921
475433be
ID		 1922 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1923 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1924 if (value == LED_MODE_SIGNAL_STRENGTH)
1925 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1926 LED_TYPE_QUALITY);
a9450b70
ID		 1927
1928 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1929 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1930 rt2x00_get_field16(eeprom,
1931 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1932 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1933 rt2x00_get_field16(eeprom,
1934 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1935 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1936 rt2x00_get_field16(eeprom,
1937 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1938 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1939 rt2x00_get_field16(eeprom,
1940 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1941 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1942 rt2x00_get_field16(eeprom,
1943 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1944 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1945 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1946 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1947 rt2x00_get_field16(eeprom,
1948 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1949 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1950 rt2x00_get_field16(eeprom,
1951 EEPROM_LED_POLARITY_RDY_A));
771fd565 1952#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1953
1954 return 0;
1955}
1956
1957/*
1958 * RF value list for RF2528
1959 * Supports: 2.4 GHz
1960 */
1961static const struct rf_channel rf_vals_bg_2528[] = {
1962 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1963 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1964 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1965 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1966 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1967 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1968 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1969 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1970 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1971 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1972 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1973 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1974 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1975 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1976};
1977
1978/*
1979 * RF value list for RF5226
1980 * Supports: 2.4 GHz & 5.2 GHz
1981 */
1982static const struct rf_channel rf_vals_5226[] = {
1983 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1984 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1985 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1986 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1987 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1988 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1989 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1990 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1991 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1992 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1993 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1994 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1995 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1996 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1997
1998 /* 802.11 UNI / HyperLan 2 */
1999 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2000 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2001 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2002 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2003 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2004 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2005 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2006 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2007
2008 /* 802.11 HyperLan 2 */
2009 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2010 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2011 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2012 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2013 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2014 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2015 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2016 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2017 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2018 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2019
2020 /* 802.11 UNII */
2021 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2022 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2023 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2024 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2025 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2026 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2027
2028 /* MMAC(Japan)J52 ch 34,38,42,46 */
2029 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2030 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2031 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2032 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2033};
2034
2035/*
2036 * RF value list for RF5225 & RF2527
2037 * Supports: 2.4 GHz & 5.2 GHz
2038 */
2039static const struct rf_channel rf_vals_5225_2527[] = {
2040 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2041 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2042 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2043 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2044 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2045 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2046 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2047 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2048 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2049 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2050 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2051 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2052 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2053 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2054
2055 /* 802.11 UNI / HyperLan 2 */
2056 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2057 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2058 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2059 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2060 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2061 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2062 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2063 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2064
2065 /* 802.11 HyperLan 2 */
2066 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2067 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2068 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2069 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2070 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2071 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2072 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2073 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2074 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2075 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2076
2077 /* 802.11 UNII */
2078 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2079 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2080 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2081 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2082 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2083 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2084
2085 /* MMAC(Japan)J52 ch 34,38,42,46 */
2086 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2087 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2088 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2089 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2090};
2091
2092
8c5e7a5f 2093static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2094{
2095 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2096 struct channel_info *info;
2097 char *tx_power;
95ea3627
ID		 2098 unsigned int i;
2099
2100 /*
2101 * Initialize all hw fields.
5a5b6ed6
HS		 2102 *
2103 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2104 * capable of sending the buffered frames out after the DTIM
2105 * transmission using rt2x00lib_beacondone. This will send out
2106 * multicast and broadcast traffic immediately instead of buffering it
2107 * infinitly and thus dropping it after some time.
95ea3627
ID		 2108 */
2109 rt2x00dev->hw->flags =
4be8c387
JB		 2110 IEEE80211_HW_SIGNAL_DBM |
2111 IEEE80211_HW_SUPPORTS_PS |
2112 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2113
14a3bf89 2114 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2115 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2116 rt2x00_eeprom_addr(rt2x00dev,
2117 EEPROM_MAC_ADDR_0));
2118
95ea3627
ID		 2119 /*
2120 * Initialize hw_mode information.
2121 */
31562e80
ID		 2122 spec->supported_bands = SUPPORT_BAND_2GHZ;
2123 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2124
5122d898 2125 if (rt2x00_rf(rt2x00dev, RF2528)) {
95ea3627
ID		 2126 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2127 spec->channels = rf_vals_bg_2528;
5122d898 2128 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
31562e80 2129 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2130 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2131 spec->channels = rf_vals_5226;
5122d898 2132 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 2133 spec->num_channels = 14;
2134 spec->channels = rf_vals_5225_2527;
5122d898 2135 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
31562e80 2136 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2137 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2138 spec->channels = rf_vals_5225_2527;
2139 }
2140
8c5e7a5f
ID		 2141 /*
2142 * Create channel information array
2143 */
baeb2ffa 2144 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2145 if (!info)
2146 return -ENOMEM;
95ea3627 2147
8c5e7a5f
ID		 2148 spec->channels_info = info;
2149
2150 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
8d1331b3
ID		 2151 for (i = 0; i < 14; i++) {
2152 info[i].max_power = MAX_TXPOWER;
2153 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2154 }
8c5e7a5f
ID		 2155
2156 if (spec->num_channels > 14) {
2157 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
8d1331b3
ID		 2158 for (i = 14; i < spec->num_channels; i++) {
2159 info[i].max_power = MAX_TXPOWER;
2160 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2161 }
95ea3627 2162 }
8c5e7a5f
ID		 2163
2164 return 0;
95ea3627
ID		 2165}
2166
2167static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2168{
2169 int retval;
2170
2171 /*
2172 * Allocate eeprom data.
2173 */
2174 retval = rt73usb_validate_eeprom(rt2x00dev);
2175 if (retval)
2176 return retval;
2177
2178 retval = rt73usb_init_eeprom(rt2x00dev);
2179 if (retval)
2180 return retval;
2181
2182 /*
2183 * Initialize hw specifications.
2184 */
8c5e7a5f
ID		 2185 retval = rt73usb_probe_hw_mode(rt2x00dev);
2186 if (retval)
2187 return retval;
95ea3627 2188
1afcfd54
IP		 2189 /*
2190 * This device has multiple filters for control frames,
2191 * but has no a separate filter for PS Poll frames.
2192 */
2193 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2194
95ea3627 2195 /*
9404ef34 2196 * This device requires firmware.
95ea3627 2197 */
066cb637 2198 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
008c4482
ID		 2199 if (!modparam_nohwcrypt)
2200 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 2201 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
c965c74b 2202 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
95ea3627
ID		 2203
2204 /*
2205 * Set the rssi offset.
2206 */
2207 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2208
2209 return 0;
2210}
2211
2212/*
2213 * IEEE80211 stack callback functions.
2214 */
2af0a570
ID		 2215static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2216 const struct ieee80211_tx_queue_params *params)
2217{
2218 struct rt2x00_dev *rt2x00dev = hw->priv;
2219 struct data_queue *queue;
2220 struct rt2x00_field32 field;
2221 int retval;
2222 u32 reg;
5e790023 2223 u32 offset;
2af0a570
ID		 2224
2225 /*
2226 * First pass the configuration through rt2x00lib, that will
2227 * update the queue settings and validate the input. After that
2228 * we are free to update the registers based on the value
2229 * in the queue parameter.
2230 */
2231 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2232 if (retval)
2233 return retval;
2234
5e790023
ID		 2235 /*
2236 * We only need to perform additional register initialization
2237 * for WMM queues/
2238 */
2239 if (queue_idx >= 4)
2240 return 0;
2241
2af0a570
ID		 2242 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2243
2244 /* Update WMM TXOP register */
5e790023
ID		 2245 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2246 field.bit_offset = (queue_idx & 1) * 16;
2247 field.bit_mask = 0xffff << field.bit_offset;
2248
2249 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2250 rt2x00_set_field32(&reg, field, queue->txop);
2251 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2252
2253 /* Update WMM registers */
2254 field.bit_offset = queue_idx * 4;
2255 field.bit_mask = 0xf << field.bit_offset;
2256
0f829b1d 2257 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2258 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2259 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2260
0f829b1d 2261 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2262 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2263 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2264
0f829b1d 2265 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2266 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2267 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2268
2269 return 0;
2270}
2271
95ea3627
ID		 2272static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2273{
2274 struct rt2x00_dev *rt2x00dev = hw->priv;
2275 u64 tsf;
2276 u32 reg;
2277
0f829b1d 2278 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2279 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2280 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2281 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2282
2283 return tsf;
2284}
95ea3627 2285
95ea3627
ID		 2286static const struct ieee80211_ops rt73usb_mac80211_ops = {
2287 .tx = rt2x00mac_tx,
4150c572
JB		 2288 .start = rt2x00mac_start,
2289 .stop = rt2x00mac_stop,
95ea3627
ID		 2290 .add_interface = rt2x00mac_add_interface,
2291 .remove_interface = rt2x00mac_remove_interface,
2292 .config = rt2x00mac_config,
3a643d24 2293 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2294 .set_tim = rt2x00mac_set_tim,
906c110f 2295 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2296 .sw_scan_start = rt2x00mac_sw_scan_start,
2297 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2298 .get_stats = rt2x00mac_get_stats,
471b3efd 2299 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2300 .conf_tx = rt73usb_conf_tx,
95ea3627 2301 .get_tsf = rt73usb_get_tsf,
e47a5cdd 2302 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2303 .flush = rt2x00mac_flush,
95ea3627
ID		 2304};
2305
2306static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2307 .probe_hw = rt73usb_probe_hw,
2308 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2309 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2310 .load_firmware = rt73usb_load_firmware,
2311 .initialize = rt2x00usb_initialize,
2312 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2313 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2314 .set_device_state = rt73usb_set_device_state,
7396faf4 2315 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2316 .link_stats = rt73usb_link_stats,
2317 .reset_tuner = rt73usb_reset_tuner,
2318 .link_tuner = rt73usb_link_tuner,
c965c74b 2319 .watchdog = rt2x00usb_watchdog,
dbba306f
ID		 2320 .start_queue = rt73usb_start_queue,
2321 .kick_queue = rt2x00usb_kick_queue,
2322 .stop_queue = rt73usb_stop_queue,
5be65609 2323 .flush_queue = rt2x00usb_flush_queue,
95ea3627 2324 .write_tx_desc = rt73usb_write_tx_desc,
bd88a781 2325 .write_beacon = rt73usb_write_beacon,
69cf36a4 2326 .clear_beacon = rt73usb_clear_beacon,
dd9fa2d2 2327 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2328 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2329 .config_shared_key = rt73usb_config_shared_key,
2330 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2331 .config_filter = rt73usb_config_filter,
6bb40dd1 2332 .config_intf = rt73usb_config_intf,
72810379 2333 .config_erp = rt73usb_config_erp,
e4ea1c40 2334 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2335 .config = rt73usb_config,
2336};
2337
181d6902 2338static const struct data_queue_desc rt73usb_queue_rx = {
efd2f271 2339 .entry_num = 32,
181d6902
ID		 2340 .data_size = DATA_FRAME_SIZE,
2341 .desc_size = RXD_DESC_SIZE,
b8be63ff 2342 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2343};
2344
2345static const struct data_queue_desc rt73usb_queue_tx = {
efd2f271 2346 .entry_num = 32,
181d6902
ID		 2347 .data_size = DATA_FRAME_SIZE,
2348 .desc_size = TXD_DESC_SIZE,
b8be63ff 2349 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2350};
2351
2352static const struct data_queue_desc rt73usb_queue_bcn = {
efd2f271 2353 .entry_num = 4,
181d6902
ID		 2354 .data_size = MGMT_FRAME_SIZE,
2355 .desc_size = TXINFO_SIZE,
b8be63ff 2356 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2357};
2358
95ea3627 2359static const struct rt2x00_ops rt73usb_ops = {
04d0362e
GW		 2360 .name = KBUILD_MODNAME,
2361 .max_sta_intf = 1,
2362 .max_ap_intf = 4,
2363 .eeprom_size = EEPROM_SIZE,
2364 .rf_size = RF_SIZE,
2365 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2366 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 2367 .rx = &rt73usb_queue_rx,
2368 .tx = &rt73usb_queue_tx,
2369 .bcn = &rt73usb_queue_bcn,
2370 .lib = &rt73usb_rt2x00_ops,
2371 .hw = &rt73usb_mac80211_ops,
95ea3627 2372#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2373 .debugfs = &rt73usb_rt2x00debug,
95ea3627
ID		 2374#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2375};
2376
2377/*
2378 * rt73usb module information.
2379 */
2380static struct usb_device_id rt73usb_device_table[] = {
2381 /* AboCom */
ef4bb70d
XVP		 2382 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2383 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2384 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2385 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2386 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2387 /* AL */
2388 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2389 /* Amigo */
2390 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2391 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2392 /* AMIT */
2393 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2394 /* Askey */
2395 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2396 /* ASUS */
2397 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2398 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2399 /* Belkin */
2400 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2402 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2403 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2404 /* Billionton */
2405 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2406 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2407 /* Buffalo */
964d6ad9 2408 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
050e8a47 2409 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2410 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
6aabd4c4
ID		 2411 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2412 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
b1ef7252 2413 { USB_DEVICE(0x0411, 0x0137), USB_DEVICE_DATA(&rt73usb_ops) },
51b2853f
BP		 2414 /* CEIVA */
2415 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2416 /* CNet */
2417 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2418 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2419 /* Conceptronic */
2420 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2421 /* Corega */
2422 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2423 /* D-Link */
2424 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2425 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2426 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2427 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2428 /* Edimax */
2429 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2430 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2431 /* EnGenius */
2432 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2433 /* Gemtek */
2434 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2435 /* Gigabyte */
2436 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2437 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2438 /* Huawei-3Com */
2439 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2440 /* Hercules */
78bd6bbf 2441 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2442 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2443 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2444 /* Linksys */
2445 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2446 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2447 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2448 /* MSI */
22720645 2449 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2450 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2451 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2452 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2453 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2454 /* Ovislink */
2455 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2456 /* Ralink */
144d9ad9 2457 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2458 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2459 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
9c4cf6d9 2460 { USB_DEVICE(0x0812, 0x3101), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2461 /* Qcom */
2462 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2463 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2464 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2465 /* Samsung */
2466 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2467 /* Senao */
2468 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2469 /* Sitecom */
ef4bb70d
XVP		 2470 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2471 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2472 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2473 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2474 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2475 /* Surecom */
2476 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
14344b81
ID		 2477 /* Tilgin */
2478 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2479 /* Philips */
2480 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2481 /* Planex */
2482 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2483 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2484 /* WideTell */
2485 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2486 /* Zcom */
2487 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2488 /* ZyXEL */
2489 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2490 { 0, }
2491};
2492
2493MODULE_AUTHOR(DRV_PROJECT);
2494MODULE_VERSION(DRV_VERSION);
2495MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2496MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2497MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2498MODULE_FIRMWARE(FIRMWARE_RT2571);
2499MODULE_LICENSE("GPL");
2500
2501static struct usb_driver rt73usb_driver = {
2360157c 2502 .name = KBUILD_MODNAME,
95ea3627
ID		 2503 .id_table = rt73usb_device_table,
2504 .probe = rt2x00usb_probe,
2505 .disconnect = rt2x00usb_disconnect,
2506 .suspend = rt2x00usb_suspend,
2507 .resume = rt2x00usb_resume,
2508};
2509
2510static int __init rt73usb_init(void)
2511{
2512 return usb_register(&rt73usb_driver);
2513}
2514
2515static void __exit rt73usb_exit(void)
2516{
2517 usb_deregister(&rt73usb_driver);
2518}
2519
2520module_init(rt73usb_init);
2521module_exit(rt73usb_exit);
Linux kernel - Deliverables
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