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---|---|---|
95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
a05b8c58 | 16 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
95ea3627 ID |
17 | */ |
18 | ||
19 | /* | |
20 | Module: rt73usb | |
21 | Abstract: rt73usb device specific routines. | |
22 | Supported chipsets: rt2571W & rt2671. | |
23 | */ | |
24 | ||
a7f3a06c | 25 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
26 | #include <linux/delay.h> |
27 | #include <linux/etherdevice.h> | |
95ea3627 ID |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
95ea3627 ID |
31 | #include <linux/usb.h> |
32 | ||
33 | #include "rt2x00.h" | |
34 | #include "rt2x00usb.h" | |
35 | #include "rt73usb.h" | |
36 | ||
008c4482 ID |
37 | /* |
38 | * Allow hardware encryption to be disabled. | |
39 | */ | |
eb939922 | 40 | static bool modparam_nohwcrypt; |
008c4482 ID |
41 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
42 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
43 | ||
95ea3627 ID |
44 | /* |
45 | * Register access. | |
46 | * All access to the CSR registers will go through the methods | |
0f829b1d | 47 | * rt2x00usb_register_read and rt2x00usb_register_write. |
95ea3627 ID |
48 | * BBP and RF register require indirect register access, |
49 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
50 | * These indirect registers work with busy bits, | |
51 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
52 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
53 | * between each attampt. When the busy bit is still set at that time, | |
54 | * the access attempt is considered to have failed, | |
55 | * and we will print an error. | |
8ff48a8b | 56 | * The _lock versions must be used if you already hold the csr_mutex |
95ea3627 | 57 | */ |
c9c3b1a5 | 58 | #define WAIT_FOR_BBP(__dev, __reg) \ |
0f829b1d | 59 | rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
c9c3b1a5 | 60 | #define WAIT_FOR_RF(__dev, __reg) \ |
0f829b1d | 61 | rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
c9c3b1a5 | 62 | |
0e14f6d3 | 63 | static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
64 | const unsigned int word, const u8 value) |
65 | { | |
66 | u32 reg; | |
67 | ||
8ff48a8b | 68 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 69 | |
95ea3627 | 70 | /* |
c9c3b1a5 ID |
71 | * Wait until the BBP becomes available, afterwards we |
72 | * can safely write the new data into the register. | |
95ea3627 | 73 | */ |
c9c3b1a5 ID |
74 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
75 | reg = 0; | |
76 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
77 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
78 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
79 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
80 | ||
0f829b1d | 81 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
c9c3b1a5 | 82 | } |
99ade259 | 83 | |
8ff48a8b | 84 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
85 | } |
86 | ||
0e14f6d3 | 87 | static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
88 | const unsigned int word, u8 *value) |
89 | { | |
90 | u32 reg; | |
91 | ||
8ff48a8b | 92 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 93 | |
95ea3627 | 94 | /* |
c9c3b1a5 ID |
95 | * Wait until the BBP becomes available, afterwards we |
96 | * can safely write the read request into the register. | |
97 | * After the data has been written, we wait until hardware | |
98 | * returns the correct value, if at any time the register | |
99 | * doesn't become available in time, reg will be 0xffffffff | |
100 | * which means we return 0xff to the caller. | |
95ea3627 | 101 | */ |
c9c3b1a5 ID |
102 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
103 | reg = 0; | |
104 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
105 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
106 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
95ea3627 | 107 | |
0f829b1d | 108 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
95ea3627 | 109 | |
c9c3b1a5 ID |
110 | WAIT_FOR_BBP(rt2x00dev, ®); |
111 | } | |
95ea3627 ID |
112 | |
113 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
99ade259 | 114 | |
8ff48a8b | 115 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
116 | } |
117 | ||
0e14f6d3 | 118 | static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
119 | const unsigned int word, const u32 value) |
120 | { | |
121 | u32 reg; | |
95ea3627 | 122 | |
8ff48a8b | 123 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 124 | |
4f5af6eb | 125 | /* |
c9c3b1a5 ID |
126 | * Wait until the RF becomes available, afterwards we |
127 | * can safely write the new data into the register. | |
4f5af6eb | 128 | */ |
c9c3b1a5 ID |
129 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
130 | reg = 0; | |
131 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
132 | /* | |
133 | * RF5225 and RF2527 contain 21 bits per RF register value, | |
134 | * all others contain 20 bits. | |
135 | */ | |
136 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, | |
5122d898 GW |
137 | 20 + (rt2x00_rf(rt2x00dev, RF5225) || |
138 | rt2x00_rf(rt2x00dev, RF2527))); | |
c9c3b1a5 ID |
139 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); |
140 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
141 | ||
0f829b1d | 142 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); |
c9c3b1a5 ID |
143 | rt2x00_rf_write(rt2x00dev, word, value); |
144 | } | |
8ff48a8b ID |
145 | |
146 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
147 | } |
148 | ||
149 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
150 | static const struct rt2x00debug rt73usb_rt2x00debug = { |
151 | .owner = THIS_MODULE, | |
152 | .csr = { | |
0f829b1d ID |
153 | .read = rt2x00usb_register_read, |
154 | .write = rt2x00usb_register_write, | |
743b97ca ID |
155 | .flags = RT2X00DEBUGFS_OFFSET, |
156 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
157 | .word_size = sizeof(u32), |
158 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
159 | }, | |
160 | .eeprom = { | |
161 | .read = rt2x00_eeprom_read, | |
162 | .write = rt2x00_eeprom_write, | |
743b97ca | 163 | .word_base = EEPROM_BASE, |
95ea3627 ID |
164 | .word_size = sizeof(u16), |
165 | .word_count = EEPROM_SIZE / sizeof(u16), | |
166 | }, | |
167 | .bbp = { | |
168 | .read = rt73usb_bbp_read, | |
169 | .write = rt73usb_bbp_write, | |
743b97ca | 170 | .word_base = BBP_BASE, |
95ea3627 ID |
171 | .word_size = sizeof(u8), |
172 | .word_count = BBP_SIZE / sizeof(u8), | |
173 | }, | |
174 | .rf = { | |
175 | .read = rt2x00_rf_read, | |
176 | .write = rt73usb_rf_write, | |
743b97ca | 177 | .word_base = RF_BASE, |
95ea3627 ID |
178 | .word_size = sizeof(u32), |
179 | .word_count = RF_SIZE / sizeof(u32), | |
180 | }, | |
181 | }; | |
182 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
183 | ||
7396faf4 ID |
184 | static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
185 | { | |
186 | u32 reg; | |
187 | ||
188 | rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); | |
99bdf51a | 189 | return rt2x00_get_field32(reg, MAC_CSR13_VAL7); |
7396faf4 | 190 | } |
7396faf4 | 191 | |
771fd565 | 192 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 193 | static void rt73usb_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
194 | enum led_brightness brightness) |
195 | { | |
196 | struct rt2x00_led *led = | |
197 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
198 | unsigned int enabled = brightness != LED_OFF; | |
199 | unsigned int a_mode = | |
200 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
201 | unsigned int bg_mode = | |
202 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
203 | ||
204 | if (led->type == LED_TYPE_RADIO) { | |
205 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
206 | MCU_LEDCS_RADIO_STATUS, enabled); | |
207 | ||
47b10cd1 ID |
208 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
209 | 0, led->rt2x00dev->led_mcu_reg, | |
210 | REGISTER_TIMEOUT); | |
a9450b70 ID |
211 | } else if (led->type == LED_TYPE_ASSOC) { |
212 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
213 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
214 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
215 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
216 | ||
47b10cd1 ID |
217 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
218 | 0, led->rt2x00dev->led_mcu_reg, | |
219 | REGISTER_TIMEOUT); | |
a9450b70 ID |
220 | } else if (led->type == LED_TYPE_QUALITY) { |
221 | /* | |
222 | * The brightness is divided into 6 levels (0 - 5), | |
223 | * this means we need to convert the brightness | |
224 | * argument into the matching level within that range. | |
225 | */ | |
47b10cd1 ID |
226 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
227 | brightness / (LED_FULL / 6), | |
228 | led->rt2x00dev->led_mcu_reg, | |
229 | REGISTER_TIMEOUT); | |
a9450b70 ID |
230 | } |
231 | } | |
a2e1d52a ID |
232 | |
233 | static int rt73usb_blink_set(struct led_classdev *led_cdev, | |
234 | unsigned long *delay_on, | |
235 | unsigned long *delay_off) | |
236 | { | |
237 | struct rt2x00_led *led = | |
238 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
239 | u32 reg; | |
240 | ||
0f829b1d | 241 | rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, ®); |
a2e1d52a ID |
242 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
243 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
0f829b1d | 244 | rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); |
a2e1d52a ID |
245 | |
246 | return 0; | |
247 | } | |
475433be ID |
248 | |
249 | static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev, | |
250 | struct rt2x00_led *led, | |
251 | enum led_type type) | |
252 | { | |
253 | led->rt2x00dev = rt2x00dev; | |
254 | led->type = type; | |
255 | led->led_dev.brightness_set = rt73usb_brightness_set; | |
256 | led->led_dev.blink_set = rt73usb_blink_set; | |
257 | led->flags = LED_INITIALIZED; | |
258 | } | |
771fd565 | 259 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 260 | |
95ea3627 ID |
261 | /* |
262 | * Configuration handlers. | |
263 | */ | |
906c110f ID |
264 | static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, |
265 | struct rt2x00lib_crypto *crypto, | |
266 | struct ieee80211_key_conf *key) | |
267 | { | |
268 | struct hw_key_entry key_entry; | |
269 | struct rt2x00_field32 field; | |
906c110f ID |
270 | u32 mask; |
271 | u32 reg; | |
272 | ||
273 | if (crypto->cmd == SET_KEY) { | |
274 | /* | |
275 | * rt2x00lib can't determine the correct free | |
276 | * key_idx for shared keys. We have 1 register | |
277 | * with key valid bits. The goal is simple, read | |
278 | * the register, if that is full we have no slots | |
279 | * left. | |
280 | * Note that each BSS is allowed to have up to 4 | |
281 | * shared keys, so put a mask over the allowed | |
282 | * entries. | |
283 | */ | |
284 | mask = (0xf << crypto->bssidx); | |
285 | ||
0f829b1d | 286 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
287 | reg &= mask; |
288 | ||
289 | if (reg && reg == mask) | |
290 | return -ENOSPC; | |
291 | ||
acaf908d | 292 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
293 | |
294 | /* | |
295 | * Upload key to hardware | |
296 | */ | |
297 | memcpy(key_entry.key, crypto->key, | |
298 | sizeof(key_entry.key)); | |
299 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
300 | sizeof(key_entry.tx_mic)); | |
301 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
302 | sizeof(key_entry.rx_mic)); | |
303 | ||
304 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
305 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
306 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
307 | |
308 | /* | |
309 | * The cipher types are stored over 2 registers. | |
310 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
311 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
312 | * Using the correct defines correctly will cause overhead, | |
313 | * so just calculate the correct offset. | |
314 | */ | |
315 | if (key->hw_key_idx < 8) { | |
316 | field.bit_offset = (3 * key->hw_key_idx); | |
317 | field.bit_mask = 0x7 << field.bit_offset; | |
318 | ||
0f829b1d | 319 | rt2x00usb_register_read(rt2x00dev, SEC_CSR1, ®); |
906c110f | 320 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 321 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); |
906c110f ID |
322 | } else { |
323 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
324 | field.bit_mask = 0x7 << field.bit_offset; | |
325 | ||
0f829b1d | 326 | rt2x00usb_register_read(rt2x00dev, SEC_CSR5, ®); |
906c110f | 327 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 328 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); |
906c110f ID |
329 | } |
330 | ||
331 | /* | |
332 | * The driver does not support the IV/EIV generation | |
333 | * in hardware. However it doesn't support the IV/EIV | |
334 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 335 | * to be provided separately for the descriptor. |
906c110f ID |
336 | * rt2x00lib will cut the IV/EIV data out of all frames |
337 | * given to us by mac80211, but we must tell mac80211 | |
338 | * to generate the IV/EIV data. | |
339 | */ | |
340 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
341 | } | |
342 | ||
343 | /* | |
344 | * SEC_CSR0 contains only single-bit fields to indicate | |
345 | * a particular key is valid. Because using the FIELD32() | |
346 | * defines directly will cause a lot of overhead we use | |
347 | * a calculation to determine the correct bit directly. | |
348 | */ | |
349 | mask = 1 << key->hw_key_idx; | |
350 | ||
0f829b1d | 351 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
352 | if (crypto->cmd == SET_KEY) |
353 | reg |= mask; | |
354 | else if (crypto->cmd == DISABLE_KEY) | |
355 | reg &= ~mask; | |
0f829b1d | 356 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); |
906c110f ID |
357 | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
362 | struct rt2x00lib_crypto *crypto, | |
363 | struct ieee80211_key_conf *key) | |
364 | { | |
365 | struct hw_pairwise_ta_entry addr_entry; | |
366 | struct hw_key_entry key_entry; | |
906c110f ID |
367 | u32 mask; |
368 | u32 reg; | |
369 | ||
370 | if (crypto->cmd == SET_KEY) { | |
371 | /* | |
372 | * rt2x00lib can't determine the correct free | |
373 | * key_idx for pairwise keys. We have 2 registers | |
374 | * with key valid bits. The goal is simple, read | |
375 | * the first register, if that is full move to | |
376 | * the next register. | |
377 | * When both registers are full, we drop the key, | |
378 | * otherwise we use the first invalid entry. | |
379 | */ | |
0f829b1d | 380 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
381 | if (reg && reg == ~0) { |
382 | key->hw_key_idx = 32; | |
0f829b1d | 383 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
384 | if (reg && reg == ~0) |
385 | return -ENOSPC; | |
386 | } | |
387 | ||
acaf908d | 388 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
389 | |
390 | /* | |
391 | * Upload key to hardware | |
392 | */ | |
393 | memcpy(key_entry.key, crypto->key, | |
394 | sizeof(key_entry.key)); | |
395 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
396 | sizeof(key_entry.tx_mic)); | |
397 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
398 | sizeof(key_entry.rx_mic)); | |
399 | ||
400 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
401 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
402 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
403 | |
404 | /* | |
405 | * Send the address and cipher type to the hardware register. | |
906c110f ID |
406 | */ |
407 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
408 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
409 | addr_entry.cipher = crypto->cipher; | |
410 | ||
411 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
0f829b1d | 412 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
906c110f ID |
413 | &addr_entry, sizeof(addr_entry)); |
414 | ||
415 | /* | |
416 | * Enable pairwise lookup table for given BSS idx, | |
417 | * without this received frames will not be decrypted | |
418 | * by the hardware. | |
419 | */ | |
0f829b1d | 420 | rt2x00usb_register_read(rt2x00dev, SEC_CSR4, ®); |
906c110f | 421 | reg |= (1 << crypto->bssidx); |
0f829b1d | 422 | rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); |
906c110f ID |
423 | |
424 | /* | |
425 | * The driver does not support the IV/EIV generation | |
426 | * in hardware. However it doesn't support the IV/EIV | |
427 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 428 | * to be provided separately for the descriptor. |
906c110f ID |
429 | * rt2x00lib will cut the IV/EIV data out of all frames |
430 | * given to us by mac80211, but we must tell mac80211 | |
431 | * to generate the IV/EIV data. | |
432 | */ | |
433 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
434 | } | |
435 | ||
436 | /* | |
437 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
438 | * a particular key is valid. Because using the FIELD32() | |
439 | * defines directly will cause a lot of overhead we use | |
440 | * a calculation to determine the correct bit directly. | |
441 | */ | |
442 | if (key->hw_key_idx < 32) { | |
443 | mask = 1 << key->hw_key_idx; | |
444 | ||
0f829b1d | 445 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
446 | if (crypto->cmd == SET_KEY) |
447 | reg |= mask; | |
448 | else if (crypto->cmd == DISABLE_KEY) | |
449 | reg &= ~mask; | |
0f829b1d | 450 | rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); |
906c110f ID |
451 | } else { |
452 | mask = 1 << (key->hw_key_idx - 32); | |
453 | ||
0f829b1d | 454 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
455 | if (crypto->cmd == SET_KEY) |
456 | reg |= mask; | |
457 | else if (crypto->cmd == DISABLE_KEY) | |
458 | reg &= ~mask; | |
0f829b1d | 459 | rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); |
906c110f ID |
460 | } |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
3a643d24 ID |
465 | static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev, |
466 | const unsigned int filter_flags) | |
467 | { | |
468 | u32 reg; | |
469 | ||
470 | /* | |
471 | * Start configuration steps. | |
472 | * Note that the version error will always be dropped | |
473 | * and broadcast frames will always be accepted since | |
474 | * there is no filter for it at this time. | |
475 | */ | |
0f829b1d | 476 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
3a643d24 ID |
477 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
478 | !(filter_flags & FIF_FCSFAIL)); | |
479 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
480 | !(filter_flags & FIF_PLCPFAIL)); | |
481 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
1afcfd54 | 482 | !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); |
3a643d24 ID |
483 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
484 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
485 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
e0b005fa ID |
486 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
487 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
488 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
489 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
490 | !(filter_flags & FIF_ALLMULTI)); | |
491 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
492 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
493 | !(filter_flags & FIF_CONTROL)); | |
0f829b1d | 494 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
3a643d24 ID |
495 | } |
496 | ||
6bb40dd1 ID |
497 | static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, |
498 | struct rt2x00_intf *intf, | |
499 | struct rt2x00intf_conf *conf, | |
500 | const unsigned int flags) | |
95ea3627 | 501 | { |
6bb40dd1 | 502 | u32 reg; |
95ea3627 | 503 | |
6bb40dd1 | 504 | if (flags & CONFIG_UPDATE_TYPE) { |
6bb40dd1 ID |
505 | /* |
506 | * Enable synchronisation. | |
507 | */ | |
0f829b1d | 508 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
6bb40dd1 | 509 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
0f829b1d | 510 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
6bb40dd1 | 511 | } |
95ea3627 | 512 | |
6bb40dd1 ID |
513 | if (flags & CONFIG_UPDATE_MAC) { |
514 | reg = le32_to_cpu(conf->mac[1]); | |
515 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
516 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 517 | |
0f829b1d | 518 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2, |
6bb40dd1 ID |
519 | conf->mac, sizeof(conf->mac)); |
520 | } | |
95ea3627 | 521 | |
6bb40dd1 ID |
522 | if (flags & CONFIG_UPDATE_BSSID) { |
523 | reg = le32_to_cpu(conf->bssid[1]); | |
524 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
525 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 526 | |
0f829b1d | 527 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4, |
6bb40dd1 ID |
528 | conf->bssid, sizeof(conf->bssid)); |
529 | } | |
95ea3627 ID |
530 | } |
531 | ||
3a643d24 | 532 | static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
533 | struct rt2x00lib_erp *erp, |
534 | u32 changed) | |
95ea3627 | 535 | { |
95ea3627 | 536 | u32 reg; |
95ea3627 | 537 | |
0f829b1d | 538 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
4789666e | 539 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); |
8a566afe | 540 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
0f829b1d | 541 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 542 | |
02044643 HS |
543 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
544 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
545 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); | |
546 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, | |
547 | !!erp->short_preamble); | |
548 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
549 | } | |
95ea3627 | 550 | |
02044643 HS |
551 | if (changed & BSS_CHANGED_BASIC_RATES) |
552 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, | |
553 | erp->basic_rates); | |
95ea3627 | 554 | |
02044643 HS |
555 | if (changed & BSS_CHANGED_BEACON_INT) { |
556 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
557 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, | |
558 | erp->beacon_int * 16); | |
559 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
560 | } | |
8a566afe | 561 | |
02044643 HS |
562 | if (changed & BSS_CHANGED_ERP_SLOT) { |
563 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); | |
564 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); | |
565 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); | |
95ea3627 | 566 | |
02044643 HS |
567 | rt2x00usb_register_read(rt2x00dev, MAC_CSR8, ®); |
568 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); | |
569 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
570 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); | |
571 | rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); | |
572 | } | |
95ea3627 ID |
573 | } |
574 | ||
575 | static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 576 | struct antenna_setup *ant) |
95ea3627 ID |
577 | { |
578 | u8 r3; | |
579 | u8 r4; | |
580 | u8 r77; | |
2676c94d | 581 | u8 temp; |
95ea3627 ID |
582 | |
583 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
584 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
585 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
586 | ||
587 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
588 | ||
e4cd2ff8 ID |
589 | /* |
590 | * Configure the RX antenna. | |
591 | */ | |
addc81bd | 592 | switch (ant->rx) { |
95ea3627 | 593 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 594 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
7e43f3b0 GJ |
595 | temp = !rt2x00_has_cap_frame_type(rt2x00dev) && |
596 | (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); | |
2676c94d | 597 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); |
95ea3627 ID |
598 | break; |
599 | case ANTENNA_A: | |
2676c94d | 600 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 601 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 602 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
603 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
604 | else | |
605 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
606 | break; |
607 | case ANTENNA_B: | |
a4fe07d9 | 608 | default: |
2676c94d | 609 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 610 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 611 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
612 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
613 | else | |
614 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
615 | break; |
616 | } | |
617 | ||
618 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
619 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
620 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
621 | } | |
622 | ||
623 | static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 624 | struct antenna_setup *ant) |
95ea3627 ID |
625 | { |
626 | u8 r3; | |
627 | u8 r4; | |
628 | u8 r77; | |
629 | ||
630 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
631 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
632 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
633 | ||
634 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
635 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
7e43f3b0 | 636 | !rt2x00_has_cap_frame_type(rt2x00dev)); |
95ea3627 | 637 | |
e4cd2ff8 ID |
638 | /* |
639 | * Configure the RX antenna. | |
640 | */ | |
addc81bd | 641 | switch (ant->rx) { |
95ea3627 | 642 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 643 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
644 | break; |
645 | case ANTENNA_A: | |
2676c94d MN |
646 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
647 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
648 | break; |
649 | case ANTENNA_B: | |
a4fe07d9 | 650 | default: |
2676c94d MN |
651 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
652 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
653 | break; |
654 | } | |
655 | ||
656 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
657 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
658 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
659 | } | |
660 | ||
661 | struct antenna_sel { | |
662 | u8 word; | |
663 | /* | |
664 | * value[0] -> non-LNA | |
665 | * value[1] -> LNA | |
666 | */ | |
667 | u8 value[2]; | |
668 | }; | |
669 | ||
670 | static const struct antenna_sel antenna_sel_a[] = { | |
671 | { 96, { 0x58, 0x78 } }, | |
672 | { 104, { 0x38, 0x48 } }, | |
673 | { 75, { 0xfe, 0x80 } }, | |
674 | { 86, { 0xfe, 0x80 } }, | |
675 | { 88, { 0xfe, 0x80 } }, | |
676 | { 35, { 0x60, 0x60 } }, | |
677 | { 97, { 0x58, 0x58 } }, | |
678 | { 98, { 0x58, 0x58 } }, | |
679 | }; | |
680 | ||
681 | static const struct antenna_sel antenna_sel_bg[] = { | |
682 | { 96, { 0x48, 0x68 } }, | |
683 | { 104, { 0x2c, 0x3c } }, | |
684 | { 75, { 0xfe, 0x80 } }, | |
685 | { 86, { 0xfe, 0x80 } }, | |
686 | { 88, { 0xfe, 0x80 } }, | |
687 | { 35, { 0x50, 0x50 } }, | |
688 | { 97, { 0x48, 0x48 } }, | |
689 | { 98, { 0x48, 0x48 } }, | |
690 | }; | |
691 | ||
e4ea1c40 ID |
692 | static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev, |
693 | struct antenna_setup *ant) | |
95ea3627 ID |
694 | { |
695 | const struct antenna_sel *sel; | |
696 | unsigned int lna; | |
697 | unsigned int i; | |
698 | u32 reg; | |
699 | ||
a4fe07d9 ID |
700 | /* |
701 | * We should never come here because rt2x00lib is supposed | |
702 | * to catch this and send us the correct antenna explicitely. | |
703 | */ | |
704 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
705 | ant->tx == ANTENNA_SW_DIVERSITY); | |
706 | ||
8318d78a | 707 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 | 708 | sel = antenna_sel_a; |
7e43f3b0 | 709 | lna = rt2x00_has_cap_external_lna_a(rt2x00dev); |
95ea3627 ID |
710 | } else { |
711 | sel = antenna_sel_bg; | |
7e43f3b0 | 712 | lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); |
95ea3627 ID |
713 | } |
714 | ||
2676c94d MN |
715 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
716 | rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
717 | ||
0f829b1d | 718 | rt2x00usb_register_read(rt2x00dev, PHY_CSR0, ®); |
2676c94d | 719 | |
ddc827f9 | 720 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
8318d78a | 721 | (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); |
ddc827f9 | 722 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
8318d78a | 723 | (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); |
ddc827f9 | 724 | |
0f829b1d | 725 | rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); |
95ea3627 | 726 | |
5122d898 | 727 | if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225)) |
addc81bd | 728 | rt73usb_config_antenna_5x(rt2x00dev, ant); |
5122d898 | 729 | else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527)) |
addc81bd | 730 | rt73usb_config_antenna_2x(rt2x00dev, ant); |
95ea3627 ID |
731 | } |
732 | ||
e4ea1c40 | 733 | static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
5c58ee51 | 734 | struct rt2x00lib_conf *libconf) |
e4ea1c40 ID |
735 | { |
736 | u16 eeprom; | |
737 | short lna_gain = 0; | |
738 | ||
675a0b04 | 739 | if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) { |
7e43f3b0 | 740 | if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) |
e4ea1c40 ID |
741 | lna_gain += 14; |
742 | ||
743 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
744 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
745 | } else { | |
746 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
747 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
748 | } | |
749 | ||
750 | rt2x00dev->lna_gain = lna_gain; | |
751 | } | |
752 | ||
753 | static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, | |
754 | struct rf_channel *rf, const int txpower) | |
755 | { | |
756 | u8 r3; | |
757 | u8 r94; | |
758 | u8 smart; | |
759 | ||
760 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
761 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
762 | ||
5122d898 | 763 | smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); |
e4ea1c40 ID |
764 | |
765 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
766 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
767 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
768 | ||
769 | r94 = 6; | |
770 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
771 | r94 += txpower - MAX_TXPOWER; | |
772 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
773 | r94 += txpower; | |
774 | rt73usb_bbp_write(rt2x00dev, 94, r94); | |
775 | ||
776 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
777 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
778 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
779 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
780 | ||
781 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
782 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
783 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
784 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
785 | ||
786 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
787 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
788 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
789 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
790 | ||
791 | udelay(10); | |
792 | } | |
793 | ||
794 | static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, | |
795 | const int txpower) | |
796 | { | |
797 | struct rf_channel rf; | |
798 | ||
799 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
800 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
801 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
802 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
803 | ||
804 | rt73usb_config_channel(rt2x00dev, &rf, txpower); | |
805 | } | |
806 | ||
807 | static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
808 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
809 | { |
810 | u32 reg; | |
811 | ||
0f829b1d | 812 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
e1b4d7b7 ID |
813 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); |
814 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); | |
815 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); | |
e4ea1c40 ID |
816 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
817 | libconf->conf->long_frame_max_tx_count); | |
818 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, | |
819 | libconf->conf->short_frame_max_tx_count); | |
0f829b1d | 820 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
e4ea1c40 | 821 | } |
95ea3627 | 822 | |
7d7f19cc ID |
823 | static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev, |
824 | struct rt2x00lib_conf *libconf) | |
825 | { | |
826 | enum dev_state state = | |
827 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
828 | STATE_SLEEP : STATE_AWAKE; | |
829 | u32 reg; | |
830 | ||
831 | if (state == STATE_SLEEP) { | |
832 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); | |
833 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, | |
6b347bff | 834 | rt2x00dev->beacon_int - 10); |
7d7f19cc ID |
835 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, |
836 | libconf->conf->listen_interval - 1); | |
837 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); | |
838 | ||
839 | /* We must first disable autowake before it can be enabled */ | |
840 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
841 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
842 | ||
843 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); | |
844 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
845 | ||
846 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
847 | USB_MODE_SLEEP, REGISTER_TIMEOUT); | |
848 | } else { | |
7d7f19cc ID |
849 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); |
850 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); | |
851 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); | |
852 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
853 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); | |
854 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
5731858d GW |
855 | |
856 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
857 | USB_MODE_WAKEUP, REGISTER_TIMEOUT); | |
7d7f19cc ID |
858 | } |
859 | } | |
860 | ||
95ea3627 | 861 | static void rt73usb_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
862 | struct rt2x00lib_conf *libconf, |
863 | const unsigned int flags) | |
95ea3627 | 864 | { |
ba2ab471 ID |
865 | /* Always recalculate LNA gain before changing configuration */ |
866 | rt73usb_config_lna_gain(rt2x00dev, libconf); | |
867 | ||
e4ea1c40 | 868 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
869 | rt73usb_config_channel(rt2x00dev, &libconf->rf, |
870 | libconf->conf->power_level); | |
e4ea1c40 ID |
871 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
872 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 | 873 | rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); |
e4ea1c40 ID |
874 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
875 | rt73usb_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
876 | if (flags & IEEE80211_CONF_CHANGE_PS) |
877 | rt73usb_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
878 | } |
879 | ||
95ea3627 ID |
880 | /* |
881 | * Link tuning | |
882 | */ | |
ebcf26da ID |
883 | static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, |
884 | struct link_qual *qual) | |
95ea3627 ID |
885 | { |
886 | u32 reg; | |
887 | ||
888 | /* | |
889 | * Update FCS error count from register. | |
890 | */ | |
0f829b1d | 891 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
ebcf26da | 892 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
893 | |
894 | /* | |
895 | * Update False CCA count from register. | |
896 | */ | |
0f829b1d | 897 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); |
ebcf26da | 898 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
899 | } |
900 | ||
5352ff65 ID |
901 | static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev, |
902 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 903 | { |
5352ff65 | 904 | if (qual->vgc_level != vgc_level) { |
eb20b4e8 | 905 | rt73usb_bbp_write(rt2x00dev, 17, vgc_level); |
5352ff65 ID |
906 | qual->vgc_level = vgc_level; |
907 | qual->vgc_level_reg = vgc_level; | |
eb20b4e8 ID |
908 | } |
909 | } | |
910 | ||
5352ff65 ID |
911 | static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev, |
912 | struct link_qual *qual) | |
95ea3627 | 913 | { |
5352ff65 | 914 | rt73usb_set_vgc(rt2x00dev, qual, 0x20); |
95ea3627 ID |
915 | } |
916 | ||
5352ff65 ID |
917 | static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev, |
918 | struct link_qual *qual, const u32 count) | |
95ea3627 | 919 | { |
95ea3627 ID |
920 | u8 up_bound; |
921 | u8 low_bound; | |
922 | ||
95ea3627 ID |
923 | /* |
924 | * Determine r17 bounds. | |
925 | */ | |
e5ef5bad | 926 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
927 | low_bound = 0x28; |
928 | up_bound = 0x48; | |
929 | ||
7e43f3b0 | 930 | if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { |
95ea3627 ID |
931 | low_bound += 0x10; |
932 | up_bound += 0x10; | |
933 | } | |
934 | } else { | |
5352ff65 | 935 | if (qual->rssi > -82) { |
95ea3627 ID |
936 | low_bound = 0x1c; |
937 | up_bound = 0x40; | |
5352ff65 | 938 | } else if (qual->rssi > -84) { |
95ea3627 ID |
939 | low_bound = 0x1c; |
940 | up_bound = 0x20; | |
941 | } else { | |
942 | low_bound = 0x1c; | |
943 | up_bound = 0x1c; | |
944 | } | |
945 | ||
7e43f3b0 | 946 | if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { |
95ea3627 ID |
947 | low_bound += 0x14; |
948 | up_bound += 0x10; | |
949 | } | |
950 | } | |
951 | ||
6bb40dd1 ID |
952 | /* |
953 | * If we are not associated, we should go straight to the | |
954 | * dynamic CCA tuning. | |
955 | */ | |
956 | if (!rt2x00dev->intf_associated) | |
957 | goto dynamic_cca_tune; | |
958 | ||
95ea3627 ID |
959 | /* |
960 | * Special big-R17 for very short distance | |
961 | */ | |
5352ff65 ID |
962 | if (qual->rssi > -35) { |
963 | rt73usb_set_vgc(rt2x00dev, qual, 0x60); | |
95ea3627 ID |
964 | return; |
965 | } | |
966 | ||
967 | /* | |
968 | * Special big-R17 for short distance | |
969 | */ | |
5352ff65 ID |
970 | if (qual->rssi >= -58) { |
971 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
972 | return; |
973 | } | |
974 | ||
975 | /* | |
976 | * Special big-R17 for middle-short distance | |
977 | */ | |
5352ff65 ID |
978 | if (qual->rssi >= -66) { |
979 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10); | |
95ea3627 ID |
980 | return; |
981 | } | |
982 | ||
983 | /* | |
984 | * Special mid-R17 for middle distance | |
985 | */ | |
5352ff65 ID |
986 | if (qual->rssi >= -74) { |
987 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08); | |
95ea3627 ID |
988 | return; |
989 | } | |
990 | ||
991 | /* | |
992 | * Special case: Change up_bound based on the rssi. | |
993 | * Lower up_bound when rssi is weaker then -74 dBm. | |
994 | */ | |
5352ff65 | 995 | up_bound -= 2 * (-74 - qual->rssi); |
95ea3627 ID |
996 | if (low_bound > up_bound) |
997 | up_bound = low_bound; | |
998 | ||
5352ff65 ID |
999 | if (qual->vgc_level > up_bound) { |
1000 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
1001 | return; |
1002 | } | |
1003 | ||
6bb40dd1 ID |
1004 | dynamic_cca_tune: |
1005 | ||
95ea3627 ID |
1006 | /* |
1007 | * r17 does not yet exceed upper limit, continue and base | |
1008 | * the r17 tuning on the false CCA count. | |
1009 | */ | |
5352ff65 ID |
1010 | if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) |
1011 | rt73usb_set_vgc(rt2x00dev, qual, | |
1012 | min_t(u8, qual->vgc_level + 4, up_bound)); | |
1013 | else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) | |
1014 | rt73usb_set_vgc(rt2x00dev, qual, | |
1015 | max_t(u8, qual->vgc_level - 4, low_bound)); | |
95ea3627 ID |
1016 | } |
1017 | ||
5450b7e2 ID |
1018 | /* |
1019 | * Queue handlers. | |
1020 | */ | |
1021 | static void rt73usb_start_queue(struct data_queue *queue) | |
1022 | { | |
1023 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1024 | u32 reg; | |
1025 | ||
1026 | switch (queue->qid) { | |
1027 | case QID_RX: | |
1028 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1029 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1030 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1031 | break; | |
1032 | case QID_BEACON: | |
1033 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1034 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); | |
1035 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
1036 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1037 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1038 | break; | |
1039 | default: | |
1040 | break; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | static void rt73usb_stop_queue(struct data_queue *queue) | |
1045 | { | |
1046 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1047 | u32 reg; | |
1048 | ||
1049 | switch (queue->qid) { | |
1050 | case QID_RX: | |
1051 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1052 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); | |
1053 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1054 | break; | |
1055 | case QID_BEACON: | |
1056 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1057 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1058 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1059 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1060 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1061 | break; | |
1062 | default: | |
1063 | break; | |
1064 | } | |
5450b7e2 ID |
1065 | } |
1066 | ||
95ea3627 | 1067 | /* |
a7f3a06c | 1068 | * Firmware functions |
95ea3627 ID |
1069 | */ |
1070 | static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1071 | { | |
1072 | return FIRMWARE_RT2571; | |
1073 | } | |
1074 | ||
0cbe0064 ID |
1075 | static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev, |
1076 | const u8 *data, const size_t len) | |
a7f3a06c | 1077 | { |
0cbe0064 | 1078 | u16 fw_crc; |
a7f3a06c ID |
1079 | u16 crc; |
1080 | ||
1081 | /* | |
0cbe0064 ID |
1082 | * Only support 2kb firmware files. |
1083 | */ | |
1084 | if (len != 2048) | |
1085 | return FW_BAD_LENGTH; | |
1086 | ||
1087 | /* | |
a7f3a06c ID |
1088 | * The last 2 bytes in the firmware array are the crc checksum itself, |
1089 | * this means that we should never pass those 2 bytes to the crc | |
1090 | * algorithm. | |
1091 | */ | |
0cbe0064 ID |
1092 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
1093 | ||
1094 | /* | |
1095 | * Use the crc itu-t algorithm. | |
1096 | */ | |
a7f3a06c ID |
1097 | crc = crc_itu_t(0, data, len - 2); |
1098 | crc = crc_itu_t_byte(crc, 0); | |
1099 | crc = crc_itu_t_byte(crc, 0); | |
1100 | ||
0cbe0064 | 1101 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
a7f3a06c ID |
1102 | } |
1103 | ||
0cbe0064 ID |
1104 | static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, |
1105 | const u8 *data, const size_t len) | |
95ea3627 ID |
1106 | { |
1107 | unsigned int i; | |
1108 | int status; | |
1109 | u32 reg; | |
95ea3627 ID |
1110 | |
1111 | /* | |
1112 | * Wait for stable hardware. | |
1113 | */ | |
1114 | for (i = 0; i < 100; i++) { | |
0f829b1d | 1115 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1116 | if (reg) |
1117 | break; | |
1118 | msleep(1); | |
1119 | } | |
1120 | ||
1121 | if (!reg) { | |
ec9c4989 | 1122 | rt2x00_err(rt2x00dev, "Unstable hardware\n"); |
95ea3627 ID |
1123 | return -EBUSY; |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * Write firmware to device. | |
95ea3627 | 1128 | */ |
96b61baf | 1129 | rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len); |
95ea3627 ID |
1130 | |
1131 | /* | |
1132 | * Send firmware request to device to load firmware, | |
1133 | * we need to specify a long timeout time. | |
1134 | */ | |
1135 | status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, | |
3b640f21 | 1136 | 0, USB_MODE_FIRMWARE, |
95ea3627 ID |
1137 | REGISTER_TIMEOUT_FIRMWARE); |
1138 | if (status < 0) { | |
ec9c4989 | 1139 | rt2x00_err(rt2x00dev, "Failed to write Firmware to device\n"); |
95ea3627 ID |
1140 | return status; |
1141 | } | |
1142 | ||
95ea3627 ID |
1143 | return 0; |
1144 | } | |
1145 | ||
a7f3a06c ID |
1146 | /* |
1147 | * Initialization functions. | |
1148 | */ | |
95ea3627 ID |
1149 | static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) |
1150 | { | |
1151 | u32 reg; | |
1152 | ||
0f829b1d | 1153 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 ID |
1154 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
1155 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1156 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
0f829b1d | 1157 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 1158 | |
0f829b1d | 1159 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, ®); |
95ea3627 ID |
1160 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
1161 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1162 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1163 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1164 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1165 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1166 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1167 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
0f829b1d | 1168 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); |
95ea3627 ID |
1169 | |
1170 | /* | |
1171 | * CCK TXD BBP registers | |
1172 | */ | |
0f829b1d | 1173 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, ®); |
95ea3627 ID |
1174 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
1175 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1176 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1177 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1178 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1179 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1180 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1181 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
0f829b1d | 1182 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); |
95ea3627 ID |
1183 | |
1184 | /* | |
1185 | * OFDM TXD BBP registers | |
1186 | */ | |
0f829b1d | 1187 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, ®); |
95ea3627 ID |
1188 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
1189 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1190 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1191 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1192 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1193 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
0f829b1d | 1194 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); |
95ea3627 | 1195 | |
0f829b1d | 1196 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, ®); |
95ea3627 ID |
1197 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
1198 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1199 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1200 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
0f829b1d | 1201 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); |
95ea3627 | 1202 | |
0f829b1d | 1203 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, ®); |
95ea3627 ID |
1204 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
1205 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1206 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1207 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
0f829b1d | 1208 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); |
95ea3627 | 1209 | |
0f829b1d | 1210 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
1f909162 ID |
1211 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
1212 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1213 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1214 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1215 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1216 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
0f829b1d | 1217 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
1f909162 | 1218 | |
0f829b1d | 1219 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
95ea3627 | 1220 | |
0f829b1d | 1221 | rt2x00usb_register_read(rt2x00dev, MAC_CSR6, ®); |
95ea3627 | 1222 | rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); |
0f829b1d | 1223 | rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); |
95ea3627 | 1224 | |
0f829b1d | 1225 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); |
95ea3627 ID |
1226 | |
1227 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1228 | return -EBUSY; | |
1229 | ||
0f829b1d | 1230 | rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); |
95ea3627 ID |
1231 | |
1232 | /* | |
1233 | * Invalidate all Shared Keys (SEC_CSR0), | |
1234 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1235 | */ | |
0f829b1d ID |
1236 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
1237 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1238 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
95ea3627 ID |
1239 | |
1240 | reg = 0x000023b0; | |
5122d898 | 1241 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)) |
95ea3627 | 1242 | rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); |
0f829b1d | 1243 | rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); |
95ea3627 | 1244 | |
0f829b1d ID |
1245 | rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); |
1246 | rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1247 | rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); | |
95ea3627 | 1248 | |
0f829b1d | 1249 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); |
95ea3627 | 1250 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
0f829b1d | 1251 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 1252 | |
6bb40dd1 ID |
1253 | /* |
1254 | * Clear all beacons | |
1255 | * For the Beacon base registers we only need to clear | |
1256 | * the first byte since that byte contains the VALID and OWNER | |
1257 | * bits which (when set to 0) will invalidate the entire beacon. | |
1258 | */ | |
0f829b1d ID |
1259 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
1260 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1261 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1262 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
6bb40dd1 | 1263 | |
95ea3627 ID |
1264 | /* |
1265 | * We must clear the error counters. | |
1266 | * These registers are cleared on read, | |
1267 | * so we may pass a useless variable to store the value. | |
1268 | */ | |
0f829b1d ID |
1269 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
1270 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); | |
1271 | rt2x00usb_register_read(rt2x00dev, STA_CSR2, ®); | |
95ea3627 ID |
1272 | |
1273 | /* | |
1274 | * Reset MAC and BBP registers. | |
1275 | */ | |
0f829b1d | 1276 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1277 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
1278 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
0f829b1d | 1279 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1280 | |
0f829b1d | 1281 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1282 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1283 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
0f829b1d | 1284 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1285 | |
0f829b1d | 1286 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1287 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
0f829b1d | 1288 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
2b08da3f | 1293 | static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1294 | { |
1295 | unsigned int i; | |
95ea3627 ID |
1296 | u8 value; |
1297 | ||
7a5a7352 | 1298 | for (i = 0; i < REGISTER_USB_BUSY_COUNT; i++) { |
95ea3627 ID |
1299 | rt73usb_bbp_read(rt2x00dev, 0, &value); |
1300 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1301 | return 0; |
95ea3627 ID |
1302 | udelay(REGISTER_BUSY_DELAY); |
1303 | } | |
1304 | ||
ec9c4989 | 1305 | rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); |
95ea3627 | 1306 | return -EACCES; |
2b08da3f ID |
1307 | } |
1308 | ||
1309 | static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1310 | { | |
1311 | unsigned int i; | |
1312 | u16 eeprom; | |
1313 | u8 reg_id; | |
1314 | u8 value; | |
1315 | ||
1316 | if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev))) | |
1317 | return -EACCES; | |
95ea3627 | 1318 | |
95ea3627 ID |
1319 | rt73usb_bbp_write(rt2x00dev, 3, 0x80); |
1320 | rt73usb_bbp_write(rt2x00dev, 15, 0x30); | |
1321 | rt73usb_bbp_write(rt2x00dev, 21, 0xc8); | |
1322 | rt73usb_bbp_write(rt2x00dev, 22, 0x38); | |
1323 | rt73usb_bbp_write(rt2x00dev, 23, 0x06); | |
1324 | rt73usb_bbp_write(rt2x00dev, 24, 0xfe); | |
1325 | rt73usb_bbp_write(rt2x00dev, 25, 0x0a); | |
1326 | rt73usb_bbp_write(rt2x00dev, 26, 0x0d); | |
1327 | rt73usb_bbp_write(rt2x00dev, 32, 0x0b); | |
1328 | rt73usb_bbp_write(rt2x00dev, 34, 0x12); | |
1329 | rt73usb_bbp_write(rt2x00dev, 37, 0x07); | |
1330 | rt73usb_bbp_write(rt2x00dev, 39, 0xf8); | |
1331 | rt73usb_bbp_write(rt2x00dev, 41, 0x60); | |
1332 | rt73usb_bbp_write(rt2x00dev, 53, 0x10); | |
1333 | rt73usb_bbp_write(rt2x00dev, 54, 0x18); | |
1334 | rt73usb_bbp_write(rt2x00dev, 60, 0x10); | |
1335 | rt73usb_bbp_write(rt2x00dev, 61, 0x04); | |
1336 | rt73usb_bbp_write(rt2x00dev, 62, 0x04); | |
1337 | rt73usb_bbp_write(rt2x00dev, 75, 0xfe); | |
1338 | rt73usb_bbp_write(rt2x00dev, 86, 0xfe); | |
1339 | rt73usb_bbp_write(rt2x00dev, 88, 0xfe); | |
1340 | rt73usb_bbp_write(rt2x00dev, 90, 0x0f); | |
1341 | rt73usb_bbp_write(rt2x00dev, 99, 0x00); | |
1342 | rt73usb_bbp_write(rt2x00dev, 102, 0x16); | |
1343 | rt73usb_bbp_write(rt2x00dev, 107, 0x04); | |
1344 | ||
95ea3627 ID |
1345 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1346 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1347 | ||
1348 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1349 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1350 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1351 | rt73usb_bbp_write(rt2x00dev, reg_id, value); |
1352 | } | |
1353 | } | |
95ea3627 ID |
1354 | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | /* | |
1359 | * Device state switch handlers. | |
1360 | */ | |
95ea3627 ID |
1361 | static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) |
1362 | { | |
1363 | /* | |
1364 | * Initialize all registers. | |
1365 | */ | |
2b08da3f ID |
1366 | if (unlikely(rt73usb_init_registers(rt2x00dev) || |
1367 | rt73usb_init_bbp(rt2x00dev))) | |
95ea3627 | 1368 | return -EIO; |
95ea3627 | 1369 | |
95ea3627 ID |
1370 | return 0; |
1371 | } | |
1372 | ||
1373 | static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1374 | { | |
0f829b1d | 1375 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
95ea3627 ID |
1376 | |
1377 | /* | |
1378 | * Disable synchronisation. | |
1379 | */ | |
0f829b1d | 1380 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0); |
95ea3627 ID |
1381 | |
1382 | rt2x00usb_disable_radio(rt2x00dev); | |
1383 | } | |
1384 | ||
1385 | static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1386 | { | |
9655a6ec | 1387 | u32 reg, reg2; |
95ea3627 ID |
1388 | unsigned int i; |
1389 | char put_to_sleep; | |
95ea3627 ID |
1390 | |
1391 | put_to_sleep = (state != STATE_AWAKE); | |
1392 | ||
0f829b1d | 1393 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); |
95ea3627 ID |
1394 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
1395 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
0f829b1d | 1396 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1397 | |
1398 | /* | |
1399 | * Device is not guaranteed to be in the requested state yet. | |
1400 | * We must wait until the register indicates that the | |
1401 | * device has entered the correct state. | |
1402 | */ | |
1403 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
9655a6ec GW |
1404 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®2); |
1405 | state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); | |
2b08da3f | 1406 | if (state == !put_to_sleep) |
95ea3627 | 1407 | return 0; |
9655a6ec | 1408 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1409 | msleep(10); |
1410 | } | |
1411 | ||
95ea3627 ID |
1412 | return -EBUSY; |
1413 | } | |
1414 | ||
1415 | static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1416 | enum dev_state state) | |
1417 | { | |
1418 | int retval = 0; | |
1419 | ||
1420 | switch (state) { | |
1421 | case STATE_RADIO_ON: | |
1422 | retval = rt73usb_enable_radio(rt2x00dev); | |
1423 | break; | |
1424 | case STATE_RADIO_OFF: | |
1425 | rt73usb_disable_radio(rt2x00dev); | |
1426 | break; | |
2b08da3f ID |
1427 | case STATE_RADIO_IRQ_ON: |
1428 | case STATE_RADIO_IRQ_OFF: | |
1429 | /* No support, but no error either */ | |
95ea3627 ID |
1430 | break; |
1431 | case STATE_DEEP_SLEEP: | |
1432 | case STATE_SLEEP: | |
1433 | case STATE_STANDBY: | |
1434 | case STATE_AWAKE: | |
1435 | retval = rt73usb_set_state(rt2x00dev, state); | |
1436 | break; | |
1437 | default: | |
1438 | retval = -ENOTSUPP; | |
1439 | break; | |
1440 | } | |
1441 | ||
2b08da3f | 1442 | if (unlikely(retval)) |
ec9c4989 JP |
1443 | rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", |
1444 | state, retval); | |
2b08da3f | 1445 | |
95ea3627 ID |
1446 | return retval; |
1447 | } | |
1448 | ||
1449 | /* | |
1450 | * TX descriptor initialization | |
1451 | */ | |
93331458 | 1452 | static void rt73usb_write_tx_desc(struct queue_entry *entry, |
906c110f | 1453 | struct txentry_desc *txdesc) |
95ea3627 | 1454 | { |
93331458 ID |
1455 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1456 | __le32 *txd = (__le32 *) entry->skb->data; | |
95ea3627 ID |
1457 | u32 word; |
1458 | ||
1459 | /* | |
1460 | * Start writing the descriptor words. | |
1461 | */ | |
e01f1ec3 GW |
1462 | rt2x00_desc_read(txd, 0, &word); |
1463 | rt2x00_set_field32(&word, TXD_W0_BURST, | |
1464 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1465 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1466 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
1467 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
1468 | rt2x00_set_field32(&word, TXD_W0_ACK, | |
1469 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
1470 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, | |
1471 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
1472 | rt2x00_set_field32(&word, TXD_W0_OFDM, | |
1473 | (txdesc->rate_mode == RATE_MODE_OFDM)); | |
2517794b | 1474 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
e01f1ec3 GW |
1475 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1476 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | |
1477 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, | |
1478 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1479 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1480 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1481 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
1482 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); | |
1483 | rt2x00_set_field32(&word, TXD_W0_BURST2, | |
1484 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1485 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); | |
1486 | rt2x00_desc_write(txd, 0, word); | |
1487 | ||
95ea3627 | 1488 | rt2x00_desc_read(txd, 1, &word); |
2b23cdaa HS |
1489 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); |
1490 | rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); | |
1491 | rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); | |
1492 | rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); | |
906c110f | 1493 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1494 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1495 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
95ea3627 ID |
1496 | rt2x00_desc_write(txd, 1, word); |
1497 | ||
1498 | rt2x00_desc_read(txd, 2, &word); | |
26a1d07f HS |
1499 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1500 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); | |
1501 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, | |
1502 | txdesc->u.plcp.length_low); | |
1503 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, | |
1504 | txdesc->u.plcp.length_high); | |
95ea3627 ID |
1505 | rt2x00_desc_write(txd, 2, word); |
1506 | ||
906c110f | 1507 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1ce9cdac ID |
1508 | _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); |
1509 | _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); | |
906c110f ID |
1510 | } |
1511 | ||
95ea3627 ID |
1512 | rt2x00_desc_read(txd, 5, &word); |
1513 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | |
93331458 | 1514 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
95ea3627 ID |
1515 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1516 | rt2x00_desc_write(txd, 5, word); | |
1517 | ||
85b7a8b3 GW |
1518 | /* |
1519 | * Register descriptor details in skb frame descriptor. | |
1520 | */ | |
0b8004aa | 1521 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; |
85b7a8b3 GW |
1522 | skbdesc->desc = txd; |
1523 | skbdesc->desc_len = TXD_DESC_SIZE; | |
95ea3627 ID |
1524 | } |
1525 | ||
bd88a781 ID |
1526 | /* |
1527 | * TX data initialization | |
1528 | */ | |
f224f4ef GW |
1529 | static void rt73usb_write_beacon(struct queue_entry *entry, |
1530 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1531 | { |
1532 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bd88a781 | 1533 | unsigned int beacon_base; |
739fd940 | 1534 | unsigned int padding_len; |
d76dfc61 | 1535 | u32 orig_reg, reg; |
bd88a781 | 1536 | |
bd88a781 ID |
1537 | /* |
1538 | * Disable beaconing while we are reloading the beacon data, | |
1539 | * otherwise we might be sending out invalid data. | |
1540 | */ | |
0f829b1d | 1541 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
d76dfc61 | 1542 | orig_reg = reg; |
bd88a781 | 1543 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
0f829b1d | 1544 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
bd88a781 | 1545 | |
0b8004aa GW |
1546 | /* |
1547 | * Add space for the descriptor in front of the skb. | |
1548 | */ | |
1549 | skb_push(entry->skb, TXD_DESC_SIZE); | |
1550 | memset(entry->skb->data, 0, TXD_DESC_SIZE); | |
1551 | ||
5c3b685c GW |
1552 | /* |
1553 | * Write the TX descriptor for the beacon. | |
1554 | */ | |
93331458 | 1555 | rt73usb_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1556 | |
1557 | /* | |
1558 | * Dump beacon to userspace through debugfs. | |
1559 | */ | |
1560 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
1561 | ||
bd88a781 | 1562 | /* |
739fd940 | 1563 | * Write entire beacon with descriptor and padding to register. |
bd88a781 | 1564 | */ |
739fd940 | 1565 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
d76dfc61 | 1566 | if (padding_len && skb_pad(entry->skb, padding_len)) { |
ec9c4989 | 1567 | rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); |
d76dfc61 SF |
1568 | /* skb freed by skb_pad() on failure */ |
1569 | entry->skb = NULL; | |
1570 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg); | |
1571 | return; | |
1572 | } | |
1573 | ||
bd88a781 | 1574 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
1575 | rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
1576 | entry->skb->len + padding_len); | |
bd88a781 | 1577 | |
d61cb266 GW |
1578 | /* |
1579 | * Enable beaconing again. | |
1580 | * | |
1581 | * For Wi-Fi faily generated beacons between participating stations. | |
1582 | * Set TBTT phase adaptive adjustment step to 8us (default 16us) | |
1583 | */ | |
1584 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); | |
1585 | ||
d61cb266 GW |
1586 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
1587 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1588 | ||
bd88a781 ID |
1589 | /* |
1590 | * Clean up the beacon skb. | |
1591 | */ | |
1592 | dev_kfree_skb(entry->skb); | |
1593 | entry->skb = NULL; | |
1594 | } | |
1595 | ||
69cf36a4 HS |
1596 | static void rt73usb_clear_beacon(struct queue_entry *entry) |
1597 | { | |
1598 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1599 | unsigned int beacon_base; | |
bc0df75a | 1600 | u32 orig_reg, reg; |
69cf36a4 HS |
1601 | |
1602 | /* | |
1603 | * Disable beaconing while we are reloading the beacon data, | |
1604 | * otherwise we might be sending out invalid data. | |
1605 | */ | |
bc0df75a SG |
1606 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); |
1607 | reg = orig_reg; | |
69cf36a4 HS |
1608 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
1609 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1610 | ||
1611 | /* | |
1612 | * Clear beacon. | |
1613 | */ | |
1614 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); | |
1615 | rt2x00usb_register_write(rt2x00dev, beacon_base, 0); | |
1616 | ||
1617 | /* | |
bc0df75a | 1618 | * Restore beaconing state. |
69cf36a4 | 1619 | */ |
bc0df75a | 1620 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg); |
69cf36a4 HS |
1621 | } |
1622 | ||
f1ca2167 | 1623 | static int rt73usb_get_tx_data_len(struct queue_entry *entry) |
dd9fa2d2 ID |
1624 | { |
1625 | int length; | |
1626 | ||
1627 | /* | |
1628 | * The length _must_ be a multiple of 4, | |
1629 | * but it must _not_ be a multiple of the USB packet size. | |
1630 | */ | |
f1ca2167 ID |
1631 | length = roundup(entry->skb->len, 4); |
1632 | length += (4 * !(length % entry->queue->usb_maxpacket)); | |
dd9fa2d2 ID |
1633 | |
1634 | return length; | |
1635 | } | |
1636 | ||
95ea3627 ID |
1637 | /* |
1638 | * RX control handlers | |
1639 | */ | |
1640 | static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1641 | { | |
ba2ab471 | 1642 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
1643 | u8 lna; |
1644 | ||
1645 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1646 | switch (lna) { | |
1647 | case 3: | |
ba2ab471 | 1648 | offset += 90; |
95ea3627 ID |
1649 | break; |
1650 | case 2: | |
ba2ab471 | 1651 | offset += 74; |
95ea3627 ID |
1652 | break; |
1653 | case 1: | |
ba2ab471 | 1654 | offset += 64; |
95ea3627 ID |
1655 | break; |
1656 | default: | |
1657 | return 0; | |
1658 | } | |
1659 | ||
e5ef5bad | 1660 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
7e43f3b0 | 1661 | if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { |
95ea3627 ID |
1662 | if (lna == 3 || lna == 2) |
1663 | offset += 10; | |
1664 | } else { | |
1665 | if (lna == 3) | |
1666 | offset += 6; | |
1667 | else if (lna == 2) | |
1668 | offset += 8; | |
1669 | } | |
95ea3627 ID |
1670 | } |
1671 | ||
1672 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1673 | } | |
1674 | ||
181d6902 | 1675 | static void rt73usb_fill_rxdone(struct queue_entry *entry, |
55887511 | 1676 | struct rxdone_entry_desc *rxdesc) |
95ea3627 | 1677 | { |
906c110f | 1678 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
181d6902 | 1679 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
4bd7c452 | 1680 | __le32 *rxd = (__le32 *)entry->skb->data; |
95ea3627 ID |
1681 | u32 word0; |
1682 | u32 word1; | |
1683 | ||
f855c10b | 1684 | /* |
a26cbc65 GW |
1685 | * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of |
1686 | * frame data in rt2x00usb. | |
f855c10b | 1687 | */ |
a26cbc65 | 1688 | memcpy(skbdesc->desc, rxd, skbdesc->desc_len); |
70a96109 | 1689 | rxd = (__le32 *)skbdesc->desc; |
f855c10b ID |
1690 | |
1691 | /* | |
70a96109 | 1692 | * It is now safe to read the descriptor on all architectures. |
f855c10b | 1693 | */ |
95ea3627 ID |
1694 | rt2x00_desc_read(rxd, 0, &word0); |
1695 | rt2x00_desc_read(rxd, 1, &word1); | |
1696 | ||
4150c572 | 1697 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1698 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 1699 | |
78b8f3b0 GW |
1700 | rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); |
1701 | rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
906c110f ID |
1702 | |
1703 | if (rxdesc->cipher != CIPHER_NONE) { | |
1ce9cdac ID |
1704 | _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); |
1705 | _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); | |
74415edb ID |
1706 | rxdesc->dev_flags |= RXDONE_CRYPTO_IV; |
1707 | ||
906c110f | 1708 | _rt2x00_desc_read(rxd, 4, &rxdesc->icv); |
74415edb | 1709 | rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; |
906c110f ID |
1710 | |
1711 | /* | |
1712 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
3ad2f3fb | 1713 | * decryption. It has provided the data separately but rt2x00lib |
906c110f ID |
1714 | * should decide if it should be reinserted. |
1715 | */ | |
1716 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
1717 | ||
1718 | /* | |
a0aff623 GW |
1719 | * The hardware has already checked the Michael Mic and has |
1720 | * stripped it from the frame. Signal this to mac80211. | |
906c110f ID |
1721 | */ |
1722 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
1723 | ||
1724 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
1725 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
1726 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
1727 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
1728 | } | |
1729 | ||
95ea3627 ID |
1730 | /* |
1731 | * Obtain the status about this packet. | |
89993890 ID |
1732 | * When frame was received with an OFDM bitrate, |
1733 | * the signal is the PLCP value. If it was received with | |
1734 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 1735 | */ |
181d6902 | 1736 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
906c110f | 1737 | rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 1738 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1739 | |
19d30e02 ID |
1740 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1741 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1742 | else |
1743 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1744 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1745 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
181d6902 | 1746 | |
2ae23854 | 1747 | /* |
70a96109 | 1748 | * Set skb pointers, and update frame information. |
2ae23854 | 1749 | */ |
70a96109 | 1750 | skb_pull(entry->skb, entry->queue->desc_size); |
2ae23854 | 1751 | skb_trim(entry->skb, rxdesc->size); |
95ea3627 ID |
1752 | } |
1753 | ||
1754 | /* | |
1755 | * Device probe functions. | |
1756 | */ | |
1757 | static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1758 | { | |
1759 | u16 word; | |
1760 | u8 *mac; | |
1761 | s8 value; | |
1762 | ||
1763 | rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); | |
1764 | ||
1765 | /* | |
1766 | * Start validation of the data that has been read. | |
1767 | */ | |
1768 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1769 | if (!is_valid_ether_addr(mac)) { | |
f4f7f414 | 1770 | eth_random_addr(mac); |
ec9c4989 | 1771 | rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1772 | } |
1773 | ||
1774 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1775 | if (word == 0xffff) { | |
1776 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1777 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1778 | ANTENNA_B); | |
1779 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1780 | ANTENNA_B); | |
95ea3627 ID |
1781 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
1782 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
1783 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1784 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); | |
1785 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
ec9c4989 | 1786 | rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); |
95ea3627 ID |
1787 | } |
1788 | ||
1789 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1790 | if (word == 0xffff) { | |
1791 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); | |
1792 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
ec9c4989 | 1793 | rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); |
95ea3627 ID |
1794 | } |
1795 | ||
1796 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
1797 | if (word == 0xffff) { | |
1798 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); | |
1799 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); | |
1800 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); | |
1801 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); | |
1802 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); | |
1803 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); | |
1804 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); | |
1805 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); | |
1806 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
1807 | LED_MODE_DEFAULT); | |
1808 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
ec9c4989 | 1809 | rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); |
95ea3627 ID |
1810 | } |
1811 | ||
1812 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1813 | if (word == 0xffff) { | |
1814 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1815 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
1816 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
ec9c4989 | 1817 | rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); |
95ea3627 ID |
1818 | } |
1819 | ||
1820 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
1821 | if (word == 0xffff) { | |
1822 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1823 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1824 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
ec9c4989 | 1825 | rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); |
95ea3627 ID |
1826 | } else { |
1827 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
1828 | if (value < -10 || value > 10) | |
1829 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1830 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
1831 | if (value < -10 || value > 10) | |
1832 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1833 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1834 | } | |
1835 | ||
1836 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
1837 | if (word == 0xffff) { | |
1838 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1839 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1840 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
ec9c4989 | 1841 | rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
1842 | } else { |
1843 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
1844 | if (value < -10 || value > 10) | |
1845 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1846 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
1847 | if (value < -10 || value > 10) | |
1848 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1849 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1850 | } | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1856 | { | |
1857 | u32 reg; | |
1858 | u16 value; | |
1859 | u16 eeprom; | |
1860 | ||
1861 | /* | |
1862 | * Read EEPROM word for configuration. | |
1863 | */ | |
1864 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1865 | ||
1866 | /* | |
1867 | * Identify RF chipset. | |
1868 | */ | |
1869 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
0f829b1d | 1870 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
49e721ec GW |
1871 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
1872 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
95ea3627 | 1873 | |
49e721ec | 1874 | if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) { |
ec9c4989 | 1875 | rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n"); |
95ea3627 ID |
1876 | return -ENODEV; |
1877 | } | |
1878 | ||
5122d898 GW |
1879 | if (!rt2x00_rf(rt2x00dev, RF5226) && |
1880 | !rt2x00_rf(rt2x00dev, RF2528) && | |
1881 | !rt2x00_rf(rt2x00dev, RF5225) && | |
1882 | !rt2x00_rf(rt2x00dev, RF2527)) { | |
ec9c4989 | 1883 | rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); |
95ea3627 ID |
1884 | return -ENODEV; |
1885 | } | |
1886 | ||
1887 | /* | |
1888 | * Identify default antenna configuration. | |
1889 | */ | |
addc81bd | 1890 | rt2x00dev->default_ant.tx = |
95ea3627 | 1891 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1892 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1893 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1894 | ||
1895 | /* | |
1896 | * Read the Frame type. | |
1897 | */ | |
1898 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
7dab73b3 | 1899 | __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); |
95ea3627 | 1900 | |
7396faf4 ID |
1901 | /* |
1902 | * Detect if this device has an hardware controlled radio. | |
1903 | */ | |
7396faf4 | 1904 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
7dab73b3 | 1905 | __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); |
7396faf4 | 1906 | |
95ea3627 ID |
1907 | /* |
1908 | * Read frequency offset. | |
1909 | */ | |
1910 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1911 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1912 | ||
1913 | /* | |
1914 | * Read external LNA informations. | |
1915 | */ | |
1916 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1917 | ||
1918 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { | |
7dab73b3 ID |
1919 | __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); |
1920 | __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); | |
95ea3627 ID |
1921 | } |
1922 | ||
1923 | /* | |
1924 | * Store led settings, for correct led behaviour. | |
1925 | */ | |
771fd565 | 1926 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 ID |
1927 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
1928 | ||
475433be ID |
1929 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
1930 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
1931 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
1932 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
1933 | LED_TYPE_QUALITY); | |
a9450b70 ID |
1934 | |
1935 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); | |
1936 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
1937 | rt2x00_get_field16(eeprom, |
1938 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 1939 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
1940 | rt2x00_get_field16(eeprom, |
1941 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 1942 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
1943 | rt2x00_get_field16(eeprom, |
1944 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 1945 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
1946 | rt2x00_get_field16(eeprom, |
1947 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 1948 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
1949 | rt2x00_get_field16(eeprom, |
1950 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 1951 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 1952 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 1953 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
1954 | rt2x00_get_field16(eeprom, |
1955 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 1956 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
1957 | rt2x00_get_field16(eeprom, |
1958 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 1959 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1960 | |
1961 | return 0; | |
1962 | } | |
1963 | ||
1964 | /* | |
1965 | * RF value list for RF2528 | |
1966 | * Supports: 2.4 GHz | |
1967 | */ | |
1968 | static const struct rf_channel rf_vals_bg_2528[] = { | |
1969 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1970 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1971 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1972 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1973 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1974 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1975 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1976 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1977 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1978 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1979 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1980 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1981 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1982 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1983 | }; | |
1984 | ||
1985 | /* | |
1986 | * RF value list for RF5226 | |
1987 | * Supports: 2.4 GHz & 5.2 GHz | |
1988 | */ | |
1989 | static const struct rf_channel rf_vals_5226[] = { | |
1990 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1991 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1992 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1993 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1994 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1995 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1996 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1997 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1998 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1999 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
2000 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
2001 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
2002 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
2003 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
2004 | ||
2005 | /* 802.11 UNI / HyperLan 2 */ | |
2006 | { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, | |
2007 | { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, | |
2008 | { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, | |
2009 | { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, | |
2010 | { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, | |
2011 | { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, | |
2012 | { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, | |
2013 | { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, | |
2014 | ||
2015 | /* 802.11 HyperLan 2 */ | |
2016 | { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, | |
2017 | { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, | |
2018 | { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, | |
2019 | { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, | |
2020 | { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, | |
2021 | { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, | |
2022 | { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, | |
2023 | { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, | |
2024 | { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, | |
2025 | { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, | |
2026 | ||
2027 | /* 802.11 UNII */ | |
2028 | { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, | |
2029 | { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, | |
2030 | { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, | |
2031 | { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, | |
2032 | { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, | |
2033 | { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, | |
2034 | ||
2035 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2036 | { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, | |
2037 | { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, | |
2038 | { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, | |
2039 | { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, | |
2040 | }; | |
2041 | ||
2042 | /* | |
2043 | * RF value list for RF5225 & RF2527 | |
2044 | * Supports: 2.4 GHz & 5.2 GHz | |
2045 | */ | |
2046 | static const struct rf_channel rf_vals_5225_2527[] = { | |
2047 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2048 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2049 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2050 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2051 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2052 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2053 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2054 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2055 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2056 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2057 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2058 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2059 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2060 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2061 | ||
2062 | /* 802.11 UNI / HyperLan 2 */ | |
2063 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
2064 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
2065 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
2066 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
2067 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
2068 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
2069 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
2070 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
2071 | ||
2072 | /* 802.11 HyperLan 2 */ | |
2073 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
2074 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
2075 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
2076 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
2077 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
2078 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
2079 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
2080 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
2081 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
2082 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
2083 | ||
2084 | /* 802.11 UNII */ | |
2085 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
2086 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
2087 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
2088 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
2089 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
2090 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2091 | ||
2092 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2093 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2094 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2095 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2096 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2097 | }; | |
2098 | ||
2099 | ||
8c5e7a5f | 2100 | static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2101 | { |
2102 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2103 | struct channel_info *info; |
2104 | char *tx_power; | |
95ea3627 ID |
2105 | unsigned int i; |
2106 | ||
2107 | /* | |
2108 | * Initialize all hw fields. | |
5a5b6ed6 HS |
2109 | * |
2110 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are | |
2111 | * capable of sending the buffered frames out after the DTIM | |
2112 | * transmission using rt2x00lib_beacondone. This will send out | |
2113 | * multicast and broadcast traffic immediately instead of buffering it | |
2114 | * infinitly and thus dropping it after some time. | |
95ea3627 ID |
2115 | */ |
2116 | rt2x00dev->hw->flags = | |
4be8c387 JB |
2117 | IEEE80211_HW_SIGNAL_DBM | |
2118 | IEEE80211_HW_SUPPORTS_PS | | |
2119 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
95ea3627 | 2120 | |
14a3bf89 | 2121 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2122 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2123 | rt2x00_eeprom_addr(rt2x00dev, | |
2124 | EEPROM_MAC_ADDR_0)); | |
2125 | ||
95ea3627 ID |
2126 | /* |
2127 | * Initialize hw_mode information. | |
2128 | */ | |
31562e80 ID |
2129 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2130 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 | 2131 | |
5122d898 | 2132 | if (rt2x00_rf(rt2x00dev, RF2528)) { |
95ea3627 ID |
2133 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); |
2134 | spec->channels = rf_vals_bg_2528; | |
5122d898 | 2135 | } else if (rt2x00_rf(rt2x00dev, RF5226)) { |
31562e80 | 2136 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2137 | spec->num_channels = ARRAY_SIZE(rf_vals_5226); |
2138 | spec->channels = rf_vals_5226; | |
5122d898 | 2139 | } else if (rt2x00_rf(rt2x00dev, RF2527)) { |
95ea3627 ID |
2140 | spec->num_channels = 14; |
2141 | spec->channels = rf_vals_5225_2527; | |
5122d898 | 2142 | } else if (rt2x00_rf(rt2x00dev, RF5225)) { |
31562e80 | 2143 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2144 | spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); |
2145 | spec->channels = rf_vals_5225_2527; | |
2146 | } | |
2147 | ||
8c5e7a5f ID |
2148 | /* |
2149 | * Create channel information array | |
2150 | */ | |
baeb2ffa | 2151 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
2152 | if (!info) |
2153 | return -ENOMEM; | |
95ea3627 | 2154 | |
8c5e7a5f ID |
2155 | spec->channels_info = info; |
2156 | ||
2157 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | |
8d1331b3 ID |
2158 | for (i = 0; i < 14; i++) { |
2159 | info[i].max_power = MAX_TXPOWER; | |
2160 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2161 | } | |
8c5e7a5f ID |
2162 | |
2163 | if (spec->num_channels > 14) { | |
2164 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
8d1331b3 ID |
2165 | for (i = 14; i < spec->num_channels; i++) { |
2166 | info[i].max_power = MAX_TXPOWER; | |
0a6f3a8e GJ |
2167 | info[i].default_power1 = |
2168 | TXPOWER_FROM_DEV(tx_power[i - 14]); | |
8d1331b3 | 2169 | } |
95ea3627 | 2170 | } |
8c5e7a5f ID |
2171 | |
2172 | return 0; | |
95ea3627 ID |
2173 | } |
2174 | ||
2175 | static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2176 | { | |
2177 | int retval; | |
a396e100 | 2178 | u32 reg; |
95ea3627 ID |
2179 | |
2180 | /* | |
2181 | * Allocate eeprom data. | |
2182 | */ | |
2183 | retval = rt73usb_validate_eeprom(rt2x00dev); | |
2184 | if (retval) | |
2185 | return retval; | |
2186 | ||
2187 | retval = rt73usb_init_eeprom(rt2x00dev); | |
2188 | if (retval) | |
2189 | return retval; | |
2190 | ||
a396e100 GW |
2191 | /* |
2192 | * Enable rfkill polling by setting GPIO direction of the | |
2193 | * rfkill switch GPIO pin correctly. | |
2194 | */ | |
2195 | rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); | |
99bdf51a | 2196 | rt2x00_set_field32(®, MAC_CSR13_DIR7, 0); |
a396e100 GW |
2197 | rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg); |
2198 | ||
95ea3627 ID |
2199 | /* |
2200 | * Initialize hw specifications. | |
2201 | */ | |
8c5e7a5f ID |
2202 | retval = rt73usb_probe_hw_mode(rt2x00dev); |
2203 | if (retval) | |
2204 | return retval; | |
95ea3627 | 2205 | |
1afcfd54 IP |
2206 | /* |
2207 | * This device has multiple filters for control frames, | |
2208 | * but has no a separate filter for PS Poll frames. | |
2209 | */ | |
7dab73b3 | 2210 | __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); |
1afcfd54 | 2211 | |
95ea3627 | 2212 | /* |
9404ef34 | 2213 | * This device requires firmware. |
95ea3627 | 2214 | */ |
7dab73b3 | 2215 | __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); |
008c4482 | 2216 | if (!modparam_nohwcrypt) |
7dab73b3 ID |
2217 | __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); |
2218 | __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); | |
1c0bcf89 | 2219 | __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); |
95ea3627 ID |
2220 | |
2221 | /* | |
2222 | * Set the rssi offset. | |
2223 | */ | |
2224 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
2229 | /* | |
2230 | * IEEE80211 stack callback functions. | |
2231 | */ | |
8a3a3c85 EP |
2232 | static int rt73usb_conf_tx(struct ieee80211_hw *hw, |
2233 | struct ieee80211_vif *vif, u16 queue_idx, | |
2af0a570 ID |
2234 | const struct ieee80211_tx_queue_params *params) |
2235 | { | |
2236 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2237 | struct data_queue *queue; | |
2238 | struct rt2x00_field32 field; | |
2239 | int retval; | |
2240 | u32 reg; | |
5e790023 | 2241 | u32 offset; |
2af0a570 ID |
2242 | |
2243 | /* | |
2244 | * First pass the configuration through rt2x00lib, that will | |
2245 | * update the queue settings and validate the input. After that | |
2246 | * we are free to update the registers based on the value | |
2247 | * in the queue parameter. | |
2248 | */ | |
8a3a3c85 | 2249 | retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); |
2af0a570 ID |
2250 | if (retval) |
2251 | return retval; | |
2252 | ||
5e790023 ID |
2253 | /* |
2254 | * We only need to perform additional register initialization | |
2255 | * for WMM queues/ | |
2256 | */ | |
2257 | if (queue_idx >= 4) | |
2258 | return 0; | |
2259 | ||
11f818e0 | 2260 | queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
2af0a570 ID |
2261 | |
2262 | /* Update WMM TXOP register */ | |
5e790023 ID |
2263 | offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); |
2264 | field.bit_offset = (queue_idx & 1) * 16; | |
2265 | field.bit_mask = 0xffff << field.bit_offset; | |
2266 | ||
2267 | rt2x00usb_register_read(rt2x00dev, offset, ®); | |
2268 | rt2x00_set_field32(®, field, queue->txop); | |
2269 | rt2x00usb_register_write(rt2x00dev, offset, reg); | |
2af0a570 ID |
2270 | |
2271 | /* Update WMM registers */ | |
2272 | field.bit_offset = queue_idx * 4; | |
2273 | field.bit_mask = 0xf << field.bit_offset; | |
2274 | ||
0f829b1d | 2275 | rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, ®); |
2af0a570 | 2276 | rt2x00_set_field32(®, field, queue->aifs); |
0f829b1d | 2277 | rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); |
2af0a570 | 2278 | |
0f829b1d | 2279 | rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, ®); |
2af0a570 | 2280 | rt2x00_set_field32(®, field, queue->cw_min); |
0f829b1d | 2281 | rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); |
2af0a570 | 2282 | |
0f829b1d | 2283 | rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, ®); |
2af0a570 | 2284 | rt2x00_set_field32(®, field, queue->cw_max); |
0f829b1d | 2285 | rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); |
2af0a570 ID |
2286 | |
2287 | return 0; | |
2288 | } | |
2289 | ||
37a41b4a | 2290 | static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
95ea3627 ID |
2291 | { |
2292 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2293 | u64 tsf; | |
2294 | u32 reg; | |
2295 | ||
0f829b1d | 2296 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, ®); |
95ea3627 | 2297 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
0f829b1d | 2298 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, ®); |
95ea3627 ID |
2299 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
2300 | ||
2301 | return tsf; | |
2302 | } | |
95ea3627 | 2303 | |
95ea3627 ID |
2304 | static const struct ieee80211_ops rt73usb_mac80211_ops = { |
2305 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2306 | .start = rt2x00mac_start, |
2307 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2308 | .add_interface = rt2x00mac_add_interface, |
2309 | .remove_interface = rt2x00mac_remove_interface, | |
2310 | .config = rt2x00mac_config, | |
3a643d24 | 2311 | .configure_filter = rt2x00mac_configure_filter, |
930c06f2 | 2312 | .set_tim = rt2x00mac_set_tim, |
906c110f | 2313 | .set_key = rt2x00mac_set_key, |
d8147f9d ID |
2314 | .sw_scan_start = rt2x00mac_sw_scan_start, |
2315 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 2316 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2317 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2318 | .conf_tx = rt73usb_conf_tx, |
95ea3627 | 2319 | .get_tsf = rt73usb_get_tsf, |
e47a5cdd | 2320 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 2321 | .flush = rt2x00mac_flush, |
0ed7b3c0 ID |
2322 | .set_antenna = rt2x00mac_set_antenna, |
2323 | .get_antenna = rt2x00mac_get_antenna, | |
e7dee444 | 2324 | .get_ringparam = rt2x00mac_get_ringparam, |
5f0dd296 | 2325 | .tx_frames_pending = rt2x00mac_tx_frames_pending, |
95ea3627 ID |
2326 | }; |
2327 | ||
2328 | static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { | |
2329 | .probe_hw = rt73usb_probe_hw, | |
2330 | .get_firmware_name = rt73usb_get_firmware_name, | |
0cbe0064 | 2331 | .check_firmware = rt73usb_check_firmware, |
95ea3627 ID |
2332 | .load_firmware = rt73usb_load_firmware, |
2333 | .initialize = rt2x00usb_initialize, | |
2334 | .uninitialize = rt2x00usb_uninitialize, | |
798b7adb | 2335 | .clear_entry = rt2x00usb_clear_entry, |
95ea3627 | 2336 | .set_device_state = rt73usb_set_device_state, |
7396faf4 | 2337 | .rfkill_poll = rt73usb_rfkill_poll, |
95ea3627 ID |
2338 | .link_stats = rt73usb_link_stats, |
2339 | .reset_tuner = rt73usb_reset_tuner, | |
2340 | .link_tuner = rt73usb_link_tuner, | |
c965c74b | 2341 | .watchdog = rt2x00usb_watchdog, |
dbba306f ID |
2342 | .start_queue = rt73usb_start_queue, |
2343 | .kick_queue = rt2x00usb_kick_queue, | |
2344 | .stop_queue = rt73usb_stop_queue, | |
5be65609 | 2345 | .flush_queue = rt2x00usb_flush_queue, |
95ea3627 | 2346 | .write_tx_desc = rt73usb_write_tx_desc, |
bd88a781 | 2347 | .write_beacon = rt73usb_write_beacon, |
69cf36a4 | 2348 | .clear_beacon = rt73usb_clear_beacon, |
dd9fa2d2 | 2349 | .get_tx_data_len = rt73usb_get_tx_data_len, |
95ea3627 | 2350 | .fill_rxdone = rt73usb_fill_rxdone, |
906c110f ID |
2351 | .config_shared_key = rt73usb_config_shared_key, |
2352 | .config_pairwise_key = rt73usb_config_pairwise_key, | |
3a643d24 | 2353 | .config_filter = rt73usb_config_filter, |
6bb40dd1 | 2354 | .config_intf = rt73usb_config_intf, |
72810379 | 2355 | .config_erp = rt73usb_config_erp, |
e4ea1c40 | 2356 | .config_ant = rt73usb_config_ant, |
95ea3627 ID |
2357 | .config = rt73usb_config, |
2358 | }; | |
2359 | ||
0d7aada3 GJ |
2360 | static void rt73usb_queue_init(struct data_queue *queue) |
2361 | { | |
2362 | switch (queue->qid) { | |
2363 | case QID_RX: | |
2364 | queue->limit = 32; | |
2365 | queue->data_size = DATA_FRAME_SIZE; | |
2366 | queue->desc_size = RXD_DESC_SIZE; | |
2367 | queue->priv_size = sizeof(struct queue_entry_priv_usb); | |
2368 | break; | |
181d6902 | 2369 | |
0d7aada3 GJ |
2370 | case QID_AC_VO: |
2371 | case QID_AC_VI: | |
2372 | case QID_AC_BE: | |
2373 | case QID_AC_BK: | |
2374 | queue->limit = 32; | |
2375 | queue->data_size = DATA_FRAME_SIZE; | |
2376 | queue->desc_size = TXD_DESC_SIZE; | |
2377 | queue->priv_size = sizeof(struct queue_entry_priv_usb); | |
2378 | break; | |
181d6902 | 2379 | |
0d7aada3 GJ |
2380 | case QID_BEACON: |
2381 | queue->limit = 4; | |
2382 | queue->data_size = MGMT_FRAME_SIZE; | |
2383 | queue->desc_size = TXINFO_SIZE; | |
2384 | queue->priv_size = sizeof(struct queue_entry_priv_usb); | |
2385 | break; | |
2386 | ||
2387 | case QID_ATIM: | |
2388 | /* fallthrough */ | |
2389 | default: | |
2390 | BUG(); | |
2391 | break; | |
2392 | } | |
2393 | } | |
181d6902 | 2394 | |
95ea3627 | 2395 | static const struct rt2x00_ops rt73usb_ops = { |
04d0362e | 2396 | .name = KBUILD_MODNAME, |
04d0362e GW |
2397 | .max_ap_intf = 4, |
2398 | .eeprom_size = EEPROM_SIZE, | |
2399 | .rf_size = RF_SIZE, | |
2400 | .tx_queues = NUM_TX_QUEUES, | |
0d7aada3 | 2401 | .queue_init = rt73usb_queue_init, |
04d0362e GW |
2402 | .lib = &rt73usb_rt2x00_ops, |
2403 | .hw = &rt73usb_mac80211_ops, | |
95ea3627 | 2404 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 2405 | .debugfs = &rt73usb_rt2x00debug, |
95ea3627 ID |
2406 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
2407 | }; | |
2408 | ||
2409 | /* | |
2410 | * rt73usb module information. | |
2411 | */ | |
2412 | static struct usb_device_id rt73usb_device_table[] = { | |
2413 | /* AboCom */ | |
e01ae27f GW |
2414 | { USB_DEVICE(0x07b8, 0xb21b) }, |
2415 | { USB_DEVICE(0x07b8, 0xb21c) }, | |
2416 | { USB_DEVICE(0x07b8, 0xb21d) }, | |
2417 | { USB_DEVICE(0x07b8, 0xb21e) }, | |
2418 | { USB_DEVICE(0x07b8, 0xb21f) }, | |
ef4bb70d | 2419 | /* AL */ |
e01ae27f | 2420 | { USB_DEVICE(0x14b2, 0x3c10) }, |
144d9ad9 | 2421 | /* Amigo */ |
e01ae27f GW |
2422 | { USB_DEVICE(0x148f, 0x9021) }, |
2423 | { USB_DEVICE(0x0eb0, 0x9021) }, | |
ef4bb70d | 2424 | /* AMIT */ |
e01ae27f | 2425 | { USB_DEVICE(0x18c5, 0x0002) }, |
95ea3627 | 2426 | /* Askey */ |
e01ae27f | 2427 | { USB_DEVICE(0x1690, 0x0722) }, |
95ea3627 | 2428 | /* ASUS */ |
e01ae27f GW |
2429 | { USB_DEVICE(0x0b05, 0x1723) }, |
2430 | { USB_DEVICE(0x0b05, 0x1724) }, | |
95ea3627 | 2431 | /* Belkin */ |
8f35f787 | 2432 | { USB_DEVICE(0x050d, 0x7050) }, /* FCC ID: K7SF5D7050B ver. 3.x */ |
e01ae27f GW |
2433 | { USB_DEVICE(0x050d, 0x705a) }, |
2434 | { USB_DEVICE(0x050d, 0x905b) }, | |
2435 | { USB_DEVICE(0x050d, 0x905c) }, | |
95ea3627 | 2436 | /* Billionton */ |
e01ae27f GW |
2437 | { USB_DEVICE(0x1631, 0xc019) }, |
2438 | { USB_DEVICE(0x08dd, 0x0120) }, | |
95ea3627 | 2439 | /* Buffalo */ |
e01ae27f GW |
2440 | { USB_DEVICE(0x0411, 0x00d8) }, |
2441 | { USB_DEVICE(0x0411, 0x00d9) }, | |
b8b1ec61 | 2442 | { USB_DEVICE(0x0411, 0x00e6) }, |
e01ae27f GW |
2443 | { USB_DEVICE(0x0411, 0x00f4) }, |
2444 | { USB_DEVICE(0x0411, 0x0116) }, | |
2445 | { USB_DEVICE(0x0411, 0x0119) }, | |
2446 | { USB_DEVICE(0x0411, 0x0137) }, | |
51b2853f | 2447 | /* CEIVA */ |
e01ae27f | 2448 | { USB_DEVICE(0x178d, 0x02be) }, |
95ea3627 | 2449 | /* CNet */ |
e01ae27f GW |
2450 | { USB_DEVICE(0x1371, 0x9022) }, |
2451 | { USB_DEVICE(0x1371, 0x9032) }, | |
95ea3627 | 2452 | /* Conceptronic */ |
e01ae27f | 2453 | { USB_DEVICE(0x14b2, 0x3c22) }, |
0a74892b | 2454 | /* Corega */ |
e01ae27f | 2455 | { USB_DEVICE(0x07aa, 0x002e) }, |
95ea3627 | 2456 | /* D-Link */ |
e01ae27f GW |
2457 | { USB_DEVICE(0x07d1, 0x3c03) }, |
2458 | { USB_DEVICE(0x07d1, 0x3c04) }, | |
2459 | { USB_DEVICE(0x07d1, 0x3c06) }, | |
2460 | { USB_DEVICE(0x07d1, 0x3c07) }, | |
ef4bb70d | 2461 | /* Edimax */ |
e01ae27f GW |
2462 | { USB_DEVICE(0x7392, 0x7318) }, |
2463 | { USB_DEVICE(0x7392, 0x7618) }, | |
ef4bb70d | 2464 | /* EnGenius */ |
e01ae27f | 2465 | { USB_DEVICE(0x1740, 0x3701) }, |
95ea3627 | 2466 | /* Gemtek */ |
e01ae27f | 2467 | { USB_DEVICE(0x15a9, 0x0004) }, |
95ea3627 | 2468 | /* Gigabyte */ |
e01ae27f GW |
2469 | { USB_DEVICE(0x1044, 0x8008) }, |
2470 | { USB_DEVICE(0x1044, 0x800a) }, | |
95ea3627 | 2471 | /* Huawei-3Com */ |
e01ae27f | 2472 | { USB_DEVICE(0x1472, 0x0009) }, |
95ea3627 | 2473 | /* Hercules */ |
e01ae27f GW |
2474 | { USB_DEVICE(0x06f8, 0xe002) }, |
2475 | { USB_DEVICE(0x06f8, 0xe010) }, | |
2476 | { USB_DEVICE(0x06f8, 0xe020) }, | |
95ea3627 | 2477 | /* Linksys */ |
e01ae27f GW |
2478 | { USB_DEVICE(0x13b1, 0x0020) }, |
2479 | { USB_DEVICE(0x13b1, 0x0023) }, | |
2480 | { USB_DEVICE(0x13b1, 0x0028) }, | |
95ea3627 | 2481 | /* MSI */ |
e01ae27f GW |
2482 | { USB_DEVICE(0x0db0, 0x4600) }, |
2483 | { USB_DEVICE(0x0db0, 0x6877) }, | |
2484 | { USB_DEVICE(0x0db0, 0x6874) }, | |
2485 | { USB_DEVICE(0x0db0, 0xa861) }, | |
2486 | { USB_DEVICE(0x0db0, 0xa874) }, | |
22720645 | 2487 | /* Ovislink */ |
e01ae27f | 2488 | { USB_DEVICE(0x1b75, 0x7318) }, |
95ea3627 | 2489 | /* Ralink */ |
e01ae27f GW |
2490 | { USB_DEVICE(0x04bb, 0x093d) }, |
2491 | { USB_DEVICE(0x148f, 0x2573) }, | |
2492 | { USB_DEVICE(0x148f, 0x2671) }, | |
2493 | { USB_DEVICE(0x0812, 0x3101) }, | |
95ea3627 | 2494 | /* Qcom */ |
e01ae27f GW |
2495 | { USB_DEVICE(0x18e8, 0x6196) }, |
2496 | { USB_DEVICE(0x18e8, 0x6229) }, | |
2497 | { USB_DEVICE(0x18e8, 0x6238) }, | |
ef4bb70d | 2498 | /* Samsung */ |
e01ae27f | 2499 | { USB_DEVICE(0x04e8, 0x4471) }, |
95ea3627 | 2500 | /* Senao */ |
e01ae27f | 2501 | { USB_DEVICE(0x1740, 0x7100) }, |
95ea3627 | 2502 | /* Sitecom */ |
e01ae27f GW |
2503 | { USB_DEVICE(0x0df6, 0x0024) }, |
2504 | { USB_DEVICE(0x0df6, 0x0027) }, | |
2505 | { USB_DEVICE(0x0df6, 0x002f) }, | |
2506 | { USB_DEVICE(0x0df6, 0x90ac) }, | |
2507 | { USB_DEVICE(0x0df6, 0x9712) }, | |
95ea3627 | 2508 | /* Surecom */ |
e01ae27f | 2509 | { USB_DEVICE(0x0769, 0x31f3) }, |
14344b81 | 2510 | /* Tilgin */ |
e01ae27f | 2511 | { USB_DEVICE(0x6933, 0x5001) }, |
ef4bb70d | 2512 | /* Philips */ |
e01ae27f | 2513 | { USB_DEVICE(0x0471, 0x200a) }, |
95ea3627 | 2514 | /* Planex */ |
e01ae27f GW |
2515 | { USB_DEVICE(0x2019, 0xab01) }, |
2516 | { USB_DEVICE(0x2019, 0xab50) }, | |
22720645 | 2517 | /* WideTell */ |
e01ae27f | 2518 | { USB_DEVICE(0x7167, 0x3840) }, |
ef4bb70d | 2519 | /* Zcom */ |
e01ae27f | 2520 | { USB_DEVICE(0x0cde, 0x001c) }, |
144d9ad9 | 2521 | /* ZyXEL */ |
e01ae27f | 2522 | { USB_DEVICE(0x0586, 0x3415) }, |
95ea3627 ID |
2523 | { 0, } |
2524 | }; | |
2525 | ||
2526 | MODULE_AUTHOR(DRV_PROJECT); | |
2527 | MODULE_VERSION(DRV_VERSION); | |
2528 | MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); | |
2529 | MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); | |
2530 | MODULE_DEVICE_TABLE(usb, rt73usb_device_table); | |
2531 | MODULE_FIRMWARE(FIRMWARE_RT2571); | |
2532 | MODULE_LICENSE("GPL"); | |
2533 | ||
e01ae27f GW |
2534 | static int rt73usb_probe(struct usb_interface *usb_intf, |
2535 | const struct usb_device_id *id) | |
2536 | { | |
2537 | return rt2x00usb_probe(usb_intf, &rt73usb_ops); | |
2538 | } | |
2539 | ||
95ea3627 | 2540 | static struct usb_driver rt73usb_driver = { |
2360157c | 2541 | .name = KBUILD_MODNAME, |
95ea3627 | 2542 | .id_table = rt73usb_device_table, |
e01ae27f | 2543 | .probe = rt73usb_probe, |
95ea3627 ID |
2544 | .disconnect = rt2x00usb_disconnect, |
2545 | .suspend = rt2x00usb_suspend, | |
2546 | .resume = rt2x00usb_resume, | |
761ce8c4 | 2547 | .reset_resume = rt2x00usb_resume, |
e1f12eb6 | 2548 | .disable_hub_initiated_lpm = 1, |
95ea3627 ID |
2549 | }; |
2550 | ||
d632eb1b | 2551 | module_usb_driver(rt73usb_driver); |