Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
17 | #define PCI_CFG_SPACE_SIZE 256 | |
18 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
19 | ||
20 | /* Ugh. Need to stop exporting this to modules. */ | |
21 | LIST_HEAD(pci_root_buses); | |
22 | EXPORT_SYMBOL(pci_root_buses); | |
23 | ||
70308923 GKH |
24 | |
25 | static int find_anything(struct device *dev, void *data) | |
26 | { | |
27 | return 1; | |
28 | } | |
1da177e4 | 29 | |
ed4aaadb ZY |
30 | /* |
31 | * Some device drivers need know if pci is initiated. | |
32 | * Basically, we think pci is not initiated when there | |
70308923 | 33 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
34 | */ |
35 | int no_pci_devices(void) | |
36 | { | |
70308923 GKH |
37 | struct device *dev; |
38 | int no_devices; | |
ed4aaadb | 39 | |
70308923 GKH |
40 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
41 | no_devices = (dev == NULL); | |
42 | put_device(dev); | |
43 | return no_devices; | |
44 | } | |
ed4aaadb ZY |
45 | EXPORT_SYMBOL(no_pci_devices); |
46 | ||
1da177e4 LT |
47 | #ifdef HAVE_PCI_LEGACY |
48 | /** | |
49 | * pci_create_legacy_files - create legacy I/O port and memory files | |
50 | * @b: bus to create files under | |
51 | * | |
52 | * Some platforms allow access to legacy I/O port and ISA memory space on | |
53 | * a per-bus basis. This routine creates the files and ties them into | |
54 | * their associated read, write and mmap files from pci-sysfs.c | |
55 | */ | |
56 | static void pci_create_legacy_files(struct pci_bus *b) | |
57 | { | |
f5afe806 | 58 | b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, |
1da177e4 LT |
59 | GFP_ATOMIC); |
60 | if (b->legacy_io) { | |
1da177e4 LT |
61 | b->legacy_io->attr.name = "legacy_io"; |
62 | b->legacy_io->size = 0xffff; | |
63 | b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 LT |
64 | b->legacy_io->read = pci_read_legacy_io; |
65 | b->legacy_io->write = pci_write_legacy_io; | |
fd7d1ced | 66 | device_create_bin_file(&b->dev, b->legacy_io); |
1da177e4 LT |
67 | |
68 | /* Allocated above after the legacy_io struct */ | |
69 | b->legacy_mem = b->legacy_io + 1; | |
70 | b->legacy_mem->attr.name = "legacy_mem"; | |
71 | b->legacy_mem->size = 1024*1024; | |
72 | b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 | 73 | b->legacy_mem->mmap = pci_mmap_legacy_mem; |
fd7d1ced | 74 | device_create_bin_file(&b->dev, b->legacy_mem); |
1da177e4 LT |
75 | } |
76 | } | |
77 | ||
78 | void pci_remove_legacy_files(struct pci_bus *b) | |
79 | { | |
80 | if (b->legacy_io) { | |
fd7d1ced GKH |
81 | device_remove_bin_file(&b->dev, b->legacy_io); |
82 | device_remove_bin_file(&b->dev, b->legacy_mem); | |
1da177e4 LT |
83 | kfree(b->legacy_io); /* both are allocated here */ |
84 | } | |
85 | } | |
86 | #else /* !HAVE_PCI_LEGACY */ | |
87 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
88 | void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
89 | #endif /* HAVE_PCI_LEGACY */ | |
90 | ||
91 | /* | |
92 | * PCI Bus Class Devices | |
93 | */ | |
fd7d1ced | 94 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 95 | int type, |
fd7d1ced | 96 | struct device_attribute *attr, |
4327edf6 | 97 | char *buf) |
1da177e4 | 98 | { |
1da177e4 | 99 | int ret; |
4327edf6 | 100 | cpumask_t cpumask; |
1da177e4 | 101 | |
fd7d1ced | 102 | cpumask = pcibus_to_cpumask(to_pci_bus(dev)); |
39106dcf MT |
103 | ret = type? |
104 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask): | |
105 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
106 | buf[ret++] = '\n'; | |
107 | buf[ret] = '\0'; | |
1da177e4 LT |
108 | return ret; |
109 | } | |
39106dcf MT |
110 | |
111 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
112 | struct device_attribute *attr, | |
113 | char *buf) | |
114 | { | |
115 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
116 | } | |
117 | ||
118 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
119 | struct device_attribute *attr, | |
120 | char *buf) | |
121 | { | |
122 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
123 | } | |
124 | ||
125 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
126 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
127 | |
128 | /* | |
129 | * PCI Bus Class | |
130 | */ | |
fd7d1ced | 131 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 132 | { |
fd7d1ced | 133 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
134 | |
135 | if (pci_bus->bridge) | |
136 | put_device(pci_bus->bridge); | |
137 | kfree(pci_bus); | |
138 | } | |
139 | ||
140 | static struct class pcibus_class = { | |
141 | .name = "pci_bus", | |
fd7d1ced | 142 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
143 | }; |
144 | ||
145 | static int __init pcibus_class_init(void) | |
146 | { | |
147 | return class_register(&pcibus_class); | |
148 | } | |
149 | postcore_initcall(pcibus_class_init); | |
150 | ||
151 | /* | |
152 | * Translate the low bits of the PCI base | |
153 | * to the resource type | |
154 | */ | |
155 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
156 | { | |
157 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
158 | return IORESOURCE_IO; | |
159 | ||
160 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
161 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
162 | ||
163 | return IORESOURCE_MEM; | |
164 | } | |
165 | ||
166 | /* | |
167 | * Find the extent of a PCI decode.. | |
168 | */ | |
f797f9cc | 169 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) |
1da177e4 LT |
170 | { |
171 | u32 size = mask & maxbase; /* Find the significant bits */ | |
172 | if (!size) | |
173 | return 0; | |
174 | ||
175 | /* Get the lowest of them to find the decode size, and | |
176 | from that the extent. */ | |
177 | size = (size & ~(size-1)) - 1; | |
178 | ||
179 | /* base == maxbase can be valid only if the BAR has | |
180 | already been programmed with all 1s. */ | |
181 | if (base == maxbase && ((base | size) & mask) != mask) | |
182 | return 0; | |
183 | ||
184 | return size; | |
185 | } | |
186 | ||
07eddf3d YL |
187 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) |
188 | { | |
189 | u64 size = mask & maxbase; /* Find the significant bits */ | |
190 | if (!size) | |
191 | return 0; | |
192 | ||
193 | /* Get the lowest of them to find the decode size, and | |
194 | from that the extent. */ | |
195 | size = (size & ~(size-1)) - 1; | |
196 | ||
197 | /* base == maxbase can be valid only if the BAR has | |
198 | already been programmed with all 1s. */ | |
199 | if (base == maxbase && ((base | size) & mask) != mask) | |
200 | return 0; | |
201 | ||
202 | return size; | |
203 | } | |
204 | ||
205 | static inline int is_64bit_memory(u32 mask) | |
206 | { | |
207 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == | |
208 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) | |
209 | return 1; | |
210 | return 0; | |
211 | } | |
212 | ||
1da177e4 LT |
213 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
214 | { | |
215 | unsigned int pos, reg, next; | |
216 | u32 l, sz; | |
217 | struct resource *res; | |
218 | ||
219 | for(pos=0; pos<howmany; pos = next) { | |
07eddf3d YL |
220 | u64 l64; |
221 | u64 sz64; | |
222 | u32 raw_sz; | |
223 | ||
1da177e4 LT |
224 | next = pos+1; |
225 | res = &dev->resource[pos]; | |
226 | res->name = pci_name(dev); | |
227 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); | |
228 | pci_read_config_dword(dev, reg, &l); | |
229 | pci_write_config_dword(dev, reg, ~0); | |
230 | pci_read_config_dword(dev, reg, &sz); | |
231 | pci_write_config_dword(dev, reg, l); | |
232 | if (!sz || sz == 0xffffffff) | |
233 | continue; | |
234 | if (l == 0xffffffff) | |
235 | l = 0; | |
07eddf3d YL |
236 | raw_sz = sz; |
237 | if ((l & PCI_BASE_ADDRESS_SPACE) == | |
238 | PCI_BASE_ADDRESS_SPACE_MEMORY) { | |
3c6de929 | 239 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); |
07eddf3d YL |
240 | /* |
241 | * For 64bit prefetchable memory sz could be 0, if the | |
242 | * real size is bigger than 4G, so we need to check | |
243 | * szhi for that. | |
244 | */ | |
245 | if (!is_64bit_memory(l) && !sz) | |
1da177e4 LT |
246 | continue; |
247 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; | |
248 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; | |
249 | } else { | |
250 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); | |
251 | if (!sz) | |
252 | continue; | |
253 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; | |
254 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; | |
255 | } | |
256 | res->end = res->start + (unsigned long) sz; | |
88452565 | 257 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
07eddf3d | 258 | if (is_64bit_memory(l)) { |
17d6dc8f | 259 | u32 szhi, lhi; |
07eddf3d | 260 | |
17d6dc8f PA |
261 | pci_read_config_dword(dev, reg+4, &lhi); |
262 | pci_write_config_dword(dev, reg+4, ~0); | |
263 | pci_read_config_dword(dev, reg+4, &szhi); | |
264 | pci_write_config_dword(dev, reg+4, lhi); | |
07eddf3d YL |
265 | sz64 = ((u64)szhi << 32) | raw_sz; |
266 | l64 = ((u64)lhi << 32) | l; | |
267 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); | |
1da177e4 LT |
268 | next++; |
269 | #if BITS_PER_LONG == 64 | |
07eddf3d YL |
270 | if (!sz64) { |
271 | res->start = 0; | |
272 | res->end = 0; | |
273 | res->flags = 0; | |
274 | continue; | |
1da177e4 | 275 | } |
07eddf3d YL |
276 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
277 | res->end = res->start + sz64; | |
1da177e4 | 278 | #else |
07eddf3d | 279 | if (sz64 > 0x100000000ULL) { |
80ccba11 BH |
280 | dev_err(&dev->dev, "BAR %d: can't handle 64-bit" |
281 | " BAR\n", pos); | |
1da177e4 LT |
282 | res->start = 0; |
283 | res->flags = 0; | |
ea28502d | 284 | } else if (lhi) { |
17d6dc8f | 285 | /* 64-bit wide address, treat as disabled */ |
07eddf3d YL |
286 | pci_write_config_dword(dev, reg, |
287 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); | |
17d6dc8f PA |
288 | pci_write_config_dword(dev, reg+4, 0); |
289 | res->start = 0; | |
290 | res->end = sz; | |
1da177e4 LT |
291 | } |
292 | #endif | |
293 | } | |
294 | } | |
295 | if (rom) { | |
296 | dev->rom_base_reg = rom; | |
297 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
298 | res->name = pci_name(dev); | |
299 | pci_read_config_dword(dev, rom, &l); | |
300 | pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); | |
301 | pci_read_config_dword(dev, rom, &sz); | |
302 | pci_write_config_dword(dev, rom, l); | |
303 | if (l == 0xffffffff) | |
304 | l = 0; | |
305 | if (sz && sz != 0xffffffff) { | |
3c6de929 | 306 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); |
1da177e4 LT |
307 | if (sz) { |
308 | res->flags = (l & IORESOURCE_ROM_ENABLE) | | |
bb446093 | 309 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
88452565 IK |
310 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | |
311 | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
312 | res->start = l & PCI_ROM_ADDRESS_MASK; |
313 | res->end = res->start + (unsigned long) sz; | |
314 | } | |
315 | } | |
316 | } | |
317 | } | |
318 | ||
0ab2b57f | 319 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
320 | { |
321 | struct pci_dev *dev = child->self; | |
322 | u8 io_base_lo, io_limit_lo; | |
323 | u16 mem_base_lo, mem_limit_lo; | |
324 | unsigned long base, limit; | |
325 | struct resource *res; | |
326 | int i; | |
327 | ||
328 | if (!dev) /* It's a host bus, nothing to read */ | |
329 | return; | |
330 | ||
331 | if (dev->transparent) { | |
80ccba11 | 332 | dev_info(&dev->dev, "transparent bridge\n"); |
90b54929 IK |
333 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
334 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
335 | } |
336 | ||
337 | for(i=0; i<3; i++) | |
338 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
339 | ||
340 | res = child->resource[0]; | |
341 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
342 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
343 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
344 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
345 | ||
346 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
347 | u16 io_base_hi, io_limit_hi; | |
348 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
349 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
350 | base |= (io_base_hi << 16); | |
351 | limit |= (io_limit_hi << 16); | |
352 | } | |
353 | ||
354 | if (base <= limit) { | |
355 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
356 | if (!res->start) |
357 | res->start = base; | |
358 | if (!res->end) | |
359 | res->end = limit + 0xfff; | |
1da177e4 LT |
360 | } |
361 | ||
362 | res = child->resource[1]; | |
363 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
364 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
365 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
366 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
367 | if (base <= limit) { | |
368 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
369 | res->start = base; | |
370 | res->end = limit + 0xfffff; | |
371 | } | |
372 | ||
373 | res = child->resource[2]; | |
374 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
375 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
376 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
377 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
378 | ||
379 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
380 | u32 mem_base_hi, mem_limit_hi; | |
381 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
382 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
383 | ||
384 | /* | |
385 | * Some bridges set the base > limit by default, and some | |
386 | * (broken) BIOSes do not initialize them. If we find | |
387 | * this, just assume they are not being used. | |
388 | */ | |
389 | if (mem_base_hi <= mem_limit_hi) { | |
390 | #if BITS_PER_LONG == 64 | |
391 | base |= ((long) mem_base_hi) << 32; | |
392 | limit |= ((long) mem_limit_hi) << 32; | |
393 | #else | |
394 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
395 | dev_err(&dev->dev, "can't handle 64-bit " |
396 | "address space for bridge\n"); | |
1da177e4 LT |
397 | return; |
398 | } | |
399 | #endif | |
400 | } | |
401 | } | |
402 | if (base <= limit) { | |
403 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
404 | res->start = base; | |
405 | res->end = limit + 0xfffff; | |
406 | } | |
407 | } | |
408 | ||
96bde06a | 409 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
410 | { |
411 | struct pci_bus *b; | |
412 | ||
f5afe806 | 413 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 414 | if (b) { |
1da177e4 LT |
415 | INIT_LIST_HEAD(&b->node); |
416 | INIT_LIST_HEAD(&b->children); | |
417 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 418 | INIT_LIST_HEAD(&b->slots); |
1da177e4 LT |
419 | } |
420 | return b; | |
421 | } | |
422 | ||
cbd4e055 AB |
423 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
424 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
425 | { |
426 | struct pci_bus *child; | |
427 | int i; | |
428 | ||
429 | /* | |
430 | * Allocate a new bus, and inherit stuff from the parent.. | |
431 | */ | |
432 | child = pci_alloc_bus(); | |
433 | if (!child) | |
434 | return NULL; | |
435 | ||
436 | child->self = bridge; | |
437 | child->parent = parent; | |
438 | child->ops = parent->ops; | |
439 | child->sysdata = parent->sysdata; | |
6e325a62 | 440 | child->bus_flags = parent->bus_flags; |
1da177e4 LT |
441 | child->bridge = get_device(&bridge->dev); |
442 | ||
fd7d1ced GKH |
443 | /* initialize some portions of the bus device, but don't register it |
444 | * now as the parent is not properly set up yet. This device will get | |
445 | * registered later in pci_bus_add_devices() | |
446 | */ | |
447 | child->dev.class = &pcibus_class; | |
448 | sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); | |
1da177e4 LT |
449 | |
450 | /* | |
451 | * Set up the primary, secondary and subordinate | |
452 | * bus numbers. | |
453 | */ | |
454 | child->number = child->secondary = busnr; | |
455 | child->primary = parent->secondary; | |
456 | child->subordinate = 0xff; | |
457 | ||
458 | /* Set up default resource pointers and names.. */ | |
459 | for (i = 0; i < 4; i++) { | |
460 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; | |
461 | child->resource[i]->name = child->name; | |
462 | } | |
463 | bridge->subordinate = child; | |
464 | ||
465 | return child; | |
466 | } | |
467 | ||
451124a7 | 468 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
469 | { |
470 | struct pci_bus *child; | |
471 | ||
472 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 473 | if (child) { |
d71374da | 474 | down_write(&pci_bus_sem); |
1da177e4 | 475 | list_add_tail(&child->node, &parent->children); |
d71374da | 476 | up_write(&pci_bus_sem); |
e4ea9bb7 | 477 | } |
1da177e4 LT |
478 | return child; |
479 | } | |
480 | ||
96bde06a | 481 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
482 | { |
483 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
484 | |
485 | /* Attempts to fix that up are really dangerous unless | |
486 | we're going to re-assign all bus numbers. */ | |
487 | if (!pcibios_assign_all_busses()) | |
488 | return; | |
489 | ||
26f674ae GKH |
490 | while (parent->parent && parent->subordinate < max) { |
491 | parent->subordinate = max; | |
492 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
493 | parent = parent->parent; | |
494 | } | |
495 | } | |
496 | ||
1da177e4 LT |
497 | /* |
498 | * If it's a bridge, configure it and scan the bus behind it. | |
499 | * For CardBus bridges, we don't scan behind as the devices will | |
500 | * be handled by the bridge driver itself. | |
501 | * | |
502 | * We need to process bridges in two passes -- first we scan those | |
503 | * already configured by the BIOS and after we are done with all of | |
504 | * them, we proceed to assigning numbers to the remaining buses in | |
505 | * order to avoid overlaps between old and new bus numbers. | |
506 | */ | |
0ab2b57f | 507 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
508 | { |
509 | struct pci_bus *child; | |
510 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 511 | u32 buses, i, j = 0; |
1da177e4 LT |
512 | u16 bctl; |
513 | ||
514 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
515 | ||
80ccba11 BH |
516 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
517 | buses & 0xffffff, pass); | |
1da177e4 LT |
518 | |
519 | /* Disable MasterAbortMode during probing to avoid reporting | |
520 | of bus errors (in some architectures) */ | |
521 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
522 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
523 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
524 | ||
1da177e4 LT |
525 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
526 | unsigned int cmax, busnr; | |
527 | /* | |
528 | * Bus already configured by firmware, process it in the first | |
529 | * pass and just note the configuration. | |
530 | */ | |
531 | if (pass) | |
bbe8f9a3 | 532 | goto out; |
1da177e4 LT |
533 | busnr = (buses >> 8) & 0xFF; |
534 | ||
535 | /* | |
536 | * If we already got to this bus through a different bridge, | |
537 | * ignore it. This can happen with the i450NX chipset. | |
538 | */ | |
539 | if (pci_find_bus(pci_domain_nr(bus), busnr)) { | |
80ccba11 BH |
540 | dev_info(&dev->dev, "bus %04x:%02x already known\n", |
541 | pci_domain_nr(bus), busnr); | |
bbe8f9a3 | 542 | goto out; |
1da177e4 LT |
543 | } |
544 | ||
6ef6f0e3 | 545 | child = pci_add_new_bus(bus, dev, busnr); |
1da177e4 | 546 | if (!child) |
bbe8f9a3 | 547 | goto out; |
1da177e4 LT |
548 | child->primary = buses & 0xFF; |
549 | child->subordinate = (buses >> 16) & 0xFF; | |
11949255 | 550 | child->bridge_ctl = bctl; |
1da177e4 LT |
551 | |
552 | cmax = pci_scan_child_bus(child); | |
553 | if (cmax > max) | |
554 | max = cmax; | |
555 | if (child->subordinate > max) | |
556 | max = child->subordinate; | |
557 | } else { | |
558 | /* | |
559 | * We need to assign a number to this bus which we always | |
560 | * do in the second pass. | |
561 | */ | |
12f44f46 IK |
562 | if (!pass) { |
563 | if (pcibios_assign_all_busses()) | |
564 | /* Temporarily disable forwarding of the | |
565 | configuration cycles on all bridges in | |
566 | this bus segment to avoid possible | |
567 | conflicts in the second pass between two | |
568 | bridges programmed with overlapping | |
569 | bus ranges. */ | |
570 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
571 | buses & ~0xffffff); | |
bbe8f9a3 | 572 | goto out; |
12f44f46 | 573 | } |
1da177e4 LT |
574 | |
575 | /* Clear errors */ | |
576 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
577 | ||
cc57450f RS |
578 | /* Prevent assigning a bus number that already exists. |
579 | * This can happen when a bridge is hot-plugged */ | |
580 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 581 | goto out; |
6ef6f0e3 | 582 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
583 | buses = (buses & 0xff000000) |
584 | | ((unsigned int)(child->primary) << 0) | |
585 | | ((unsigned int)(child->secondary) << 8) | |
586 | | ((unsigned int)(child->subordinate) << 16); | |
587 | ||
588 | /* | |
589 | * yenta.c forces a secondary latency timer of 176. | |
590 | * Copy that behaviour here. | |
591 | */ | |
592 | if (is_cardbus) { | |
593 | buses &= ~0xff000000; | |
594 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
595 | } | |
596 | ||
597 | /* | |
598 | * We need to blast all three values with a single write. | |
599 | */ | |
600 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
601 | ||
602 | if (!is_cardbus) { | |
11949255 | 603 | child->bridge_ctl = bctl; |
26f674ae GKH |
604 | /* |
605 | * Adjust subordinate busnr in parent buses. | |
606 | * We do this before scanning for children because | |
607 | * some devices may not be detected if the bios | |
608 | * was lazy. | |
609 | */ | |
610 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
611 | /* Now we can scan all subordinate buses... */ |
612 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
613 | /* |
614 | * now fix it up again since we have found | |
615 | * the real value of max. | |
616 | */ | |
617 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
618 | } else { |
619 | /* | |
620 | * For CardBus bridges, we leave 4 bus numbers | |
621 | * as cards with a PCI-to-PCI bridge can be | |
622 | * inserted later. | |
623 | */ | |
49887941 DB |
624 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
625 | struct pci_bus *parent = bus; | |
cc57450f RS |
626 | if (pci_find_bus(pci_domain_nr(bus), |
627 | max+i+1)) | |
628 | break; | |
49887941 DB |
629 | while (parent->parent) { |
630 | if ((!pcibios_assign_all_busses()) && | |
631 | (parent->subordinate > max) && | |
632 | (parent->subordinate <= max+i)) { | |
633 | j = 1; | |
634 | } | |
635 | parent = parent->parent; | |
636 | } | |
637 | if (j) { | |
638 | /* | |
639 | * Often, there are two cardbus bridges | |
640 | * -- try to leave one valid bus number | |
641 | * for each one. | |
642 | */ | |
643 | i /= 2; | |
644 | break; | |
645 | } | |
646 | } | |
cc57450f | 647 | max += i; |
26f674ae | 648 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
649 | } |
650 | /* | |
651 | * Set the subordinate bus number to its real value. | |
652 | */ | |
653 | child->subordinate = max; | |
654 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
655 | } | |
656 | ||
cb3576fa GH |
657 | sprintf(child->name, |
658 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
659 | pci_domain_nr(bus), child->number); | |
1da177e4 | 660 | |
d55bef51 | 661 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
662 | while (bus->parent) { |
663 | if ((child->subordinate > bus->subordinate) || | |
664 | (child->number > bus->subordinate) || | |
665 | (child->number < bus->number) || | |
666 | (child->subordinate < bus->number)) { | |
a6f29a98 | 667 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
668 | "hidden behind%s bridge #%02x (-#%02x)\n", |
669 | child->number, child->subordinate, | |
670 | (bus->number > child->subordinate && | |
671 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
672 | "wholly" : "partially", |
673 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 674 | bus->number, bus->subordinate); |
49887941 DB |
675 | } |
676 | bus = bus->parent; | |
677 | } | |
678 | ||
bbe8f9a3 RB |
679 | out: |
680 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
681 | ||
1da177e4 LT |
682 | return max; |
683 | } | |
684 | ||
685 | /* | |
686 | * Read interrupt line and base address registers. | |
687 | * The architecture-dependent code can tweak these, of course. | |
688 | */ | |
689 | static void pci_read_irq(struct pci_dev *dev) | |
690 | { | |
691 | unsigned char irq; | |
692 | ||
693 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 694 | dev->pin = irq; |
1da177e4 LT |
695 | if (irq) |
696 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
697 | dev->irq = irq; | |
698 | } | |
699 | ||
01abc2aa | 700 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 701 | |
1da177e4 LT |
702 | /** |
703 | * pci_setup_device - fill in class and map information of a device | |
704 | * @dev: the device structure to fill | |
705 | * | |
706 | * Initialize the device structure with information about the device's | |
707 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
708 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
709 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge | |
710 | * or CardBus). | |
711 | */ | |
712 | static int pci_setup_device(struct pci_dev * dev) | |
713 | { | |
714 | u32 class; | |
715 | ||
8b285ce8 DH |
716 | snprintf(dev->dev.bus_id, BUS_ID_SIZE, |
717 | "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), | |
718 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
719 | |
720 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 721 | dev->revision = class & 0xff; |
1da177e4 LT |
722 | class >>= 8; /* upper 3 bytes */ |
723 | dev->class = class; | |
724 | class >>= 8; | |
725 | ||
80ccba11 | 726 | dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n", |
1da177e4 LT |
727 | dev->vendor, dev->device, class, dev->hdr_type); |
728 | ||
729 | /* "Unknown power state" */ | |
3fe9d19f | 730 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
731 | |
732 | /* Early fixups, before probing the BARs */ | |
733 | pci_fixup_device(pci_fixup_early, dev); | |
734 | class = dev->class >> 8; | |
735 | ||
736 | switch (dev->hdr_type) { /* header type */ | |
737 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
738 | if (class == PCI_CLASS_BRIDGE_PCI) | |
739 | goto bad; | |
740 | pci_read_irq(dev); | |
741 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
742 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
743 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
744 | |
745 | /* | |
746 | * Do the ugly legacy mode stuff here rather than broken chip | |
747 | * quirk code. Legacy mode ATA controllers have fixed | |
748 | * addresses. These are not always echoed in BAR0-3, and | |
749 | * BAR0-3 in a few cases contain junk! | |
750 | */ | |
751 | if (class == PCI_CLASS_STORAGE_IDE) { | |
752 | u8 progif; | |
753 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
754 | if ((progif & 1) == 0) { | |
af1bff4f LT |
755 | dev->resource[0].start = 0x1F0; |
756 | dev->resource[0].end = 0x1F7; | |
757 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
758 | dev->resource[1].start = 0x3F6; | |
759 | dev->resource[1].end = 0x3F6; | |
760 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
761 | } |
762 | if ((progif & 4) == 0) { | |
af1bff4f LT |
763 | dev->resource[2].start = 0x170; |
764 | dev->resource[2].end = 0x177; | |
765 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
766 | dev->resource[3].start = 0x376; | |
767 | dev->resource[3].end = 0x376; | |
768 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
769 | } |
770 | } | |
1da177e4 LT |
771 | break; |
772 | ||
773 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
774 | if (class != PCI_CLASS_BRIDGE_PCI) | |
775 | goto bad; | |
776 | /* The PCI-to-PCI bridge spec requires that subtractive | |
777 | decoding (i.e. transparent) bridge must have programming | |
778 | interface code of 0x01. */ | |
3efd273b | 779 | pci_read_irq(dev); |
1da177e4 LT |
780 | dev->transparent = ((dev->class & 0xff) == 1); |
781 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
782 | break; | |
783 | ||
784 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
785 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
786 | goto bad; | |
787 | pci_read_irq(dev); | |
788 | pci_read_bases(dev, 1, 0); | |
789 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
790 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
791 | break; | |
792 | ||
793 | default: /* unknown header */ | |
80ccba11 BH |
794 | dev_err(&dev->dev, "unknown header type %02x, " |
795 | "ignoring device\n", dev->hdr_type); | |
1da177e4 LT |
796 | return -1; |
797 | ||
798 | bad: | |
80ccba11 BH |
799 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
800 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
801 | dev->class = PCI_CLASS_NOT_DEFINED; |
802 | } | |
803 | ||
804 | /* We found a fine healthy device, go go go... */ | |
805 | return 0; | |
806 | } | |
807 | ||
808 | /** | |
809 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
810 | * @dev: device that's been disconnected | |
811 | * | |
812 | * Will be called only by the device core when all users of this pci device are | |
813 | * done. | |
814 | */ | |
815 | static void pci_release_dev(struct device *dev) | |
816 | { | |
817 | struct pci_dev *pci_dev; | |
818 | ||
819 | pci_dev = to_pci_dev(dev); | |
94e61088 | 820 | pci_vpd_release(pci_dev); |
1da177e4 LT |
821 | kfree(pci_dev); |
822 | } | |
823 | ||
994a65e2 KA |
824 | static void set_pcie_port_type(struct pci_dev *pdev) |
825 | { | |
826 | int pos; | |
827 | u16 reg16; | |
828 | ||
829 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
830 | if (!pos) | |
831 | return; | |
832 | pdev->is_pcie = 1; | |
833 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
834 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
835 | } | |
836 | ||
1da177e4 LT |
837 | /** |
838 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 839 | * @dev: PCI device |
1da177e4 LT |
840 | * |
841 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
842 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
843 | * access it. Maybe we don't have a way to generate extended config space | |
844 | * accesses, or the device is behind a reverse Express bridge. So we try | |
845 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
846 | * capability header. | |
847 | */ | |
70b9f7dc | 848 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 849 | { |
1da177e4 LT |
850 | u32 status; |
851 | ||
70b9f7dc YL |
852 | if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) |
853 | goto fail; | |
854 | if (status == 0xffffffff) | |
855 | goto fail; | |
856 | ||
857 | return PCI_CFG_SPACE_EXP_SIZE; | |
858 | ||
859 | fail: | |
860 | return PCI_CFG_SPACE_SIZE; | |
861 | } | |
862 | ||
49db1399 ZY |
863 | /** |
864 | * pci_disable_pme - Disable the PME function of PCI device | |
865 | * @dev: PCI device affected | |
866 | * -EINVAL is returned if PCI device doesn't support PME. | |
867 | * Zero is returned if the PME is supported and can be disabled. | |
868 | */ | |
869 | static int pci_disable_pme(struct pci_dev *dev) | |
870 | { | |
871 | int pm; | |
872 | u16 value; | |
873 | ||
874 | /* find PCI PM capability in list */ | |
875 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
876 | ||
877 | /* If device doesn't support PM Capabilities, it means that PME is | |
878 | * not supported. | |
879 | */ | |
880 | if (!pm) | |
881 | return -EINVAL; | |
882 | /* Check device's ability to generate PME# */ | |
883 | pci_read_config_word(dev, pm + PCI_PM_PMC, &value); | |
884 | ||
885 | value &= PCI_PM_CAP_PME_MASK; | |
886 | /* Check if it can generate PME# */ | |
887 | if (!value) { | |
888 | /* | |
889 | * If it is zero, it means that PME is still unsupported | |
890 | * although there exists the PM capability. | |
891 | */ | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
895 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
896 | ||
897 | /* Clear PME_Status by writing 1 to it */ | |
898 | value |= PCI_PM_CTRL_PME_STATUS ; | |
899 | /* Disable PME enable bit */ | |
900 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
901 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
70b9f7dc YL |
906 | int pci_cfg_space_size(struct pci_dev *dev) |
907 | { | |
908 | int pos; | |
909 | u32 status; | |
57741a77 | 910 | |
1da177e4 LT |
911 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
912 | if (!pos) { | |
913 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
914 | if (!pos) | |
915 | goto fail; | |
916 | ||
917 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
918 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
919 | goto fail; | |
920 | } | |
921 | ||
70b9f7dc | 922 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
923 | |
924 | fail: | |
925 | return PCI_CFG_SPACE_SIZE; | |
926 | } | |
927 | ||
928 | static void pci_release_bus_bridge_dev(struct device *dev) | |
929 | { | |
930 | kfree(dev); | |
931 | } | |
932 | ||
65891215 ME |
933 | struct pci_dev *alloc_pci_dev(void) |
934 | { | |
935 | struct pci_dev *dev; | |
936 | ||
937 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
938 | if (!dev) | |
939 | return NULL; | |
940 | ||
65891215 ME |
941 | INIT_LIST_HEAD(&dev->bus_list); |
942 | ||
4aa9bc95 ME |
943 | pci_msi_init_pci_dev(dev); |
944 | ||
65891215 ME |
945 | return dev; |
946 | } | |
947 | EXPORT_SYMBOL(alloc_pci_dev); | |
948 | ||
1da177e4 LT |
949 | /* |
950 | * Read the config data for a PCI device, sanity-check it | |
951 | * and fill in the dev structure... | |
952 | */ | |
7f7b5de2 | 953 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
954 | { |
955 | struct pci_dev *dev; | |
956 | u32 l; | |
957 | u8 hdr_type; | |
958 | int delay = 1; | |
959 | ||
960 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
961 | return NULL; | |
962 | ||
963 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
964 | if (l == 0xffffffff || l == 0x00000000 || | |
965 | l == 0x0000ffff || l == 0xffff0000) | |
966 | return NULL; | |
967 | ||
968 | /* Configuration request Retry Status */ | |
969 | while (l == 0xffff0001) { | |
970 | msleep(delay); | |
971 | delay *= 2; | |
972 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
973 | return NULL; | |
974 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
975 | if (delay > 60 * 1000) { | |
80ccba11 | 976 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
977 | "responding\n", pci_domain_nr(bus), |
978 | bus->number, PCI_SLOT(devfn), | |
979 | PCI_FUNC(devfn)); | |
980 | return NULL; | |
981 | } | |
982 | } | |
983 | ||
984 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) | |
985 | return NULL; | |
986 | ||
bab41e9b | 987 | dev = alloc_pci_dev(); |
1da177e4 LT |
988 | if (!dev) |
989 | return NULL; | |
990 | ||
1da177e4 LT |
991 | dev->bus = bus; |
992 | dev->sysdata = bus->sysdata; | |
993 | dev->dev.parent = bus->bridge; | |
994 | dev->dev.bus = &pci_bus_type; | |
995 | dev->devfn = devfn; | |
996 | dev->hdr_type = hdr_type & 0x7f; | |
997 | dev->multifunction = !!(hdr_type & 0x80); | |
998 | dev->vendor = l & 0xffff; | |
999 | dev->device = (l >> 16) & 0xffff; | |
1000 | dev->cfg_size = pci_cfg_space_size(dev); | |
82081797 | 1001 | dev->error_state = pci_channel_io_normal; |
994a65e2 | 1002 | set_pcie_port_type(dev); |
1da177e4 LT |
1003 | |
1004 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1005 | set this higher, assuming the system even supports it. */ | |
1006 | dev->dma_mask = 0xffffffff; | |
1007 | if (pci_setup_device(dev) < 0) { | |
1008 | kfree(dev); | |
1009 | return NULL; | |
1010 | } | |
1da177e4 | 1011 | |
94e61088 | 1012 | pci_vpd_pci22_init(dev); |
49db1399 | 1013 | pci_disable_pme(dev); |
94e61088 | 1014 | |
1da177e4 LT |
1015 | return dev; |
1016 | } | |
1017 | ||
96bde06a | 1018 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1019 | { |
cdb9b9f7 PM |
1020 | device_initialize(&dev->dev); |
1021 | dev->dev.release = pci_release_dev; | |
1022 | pci_dev_get(dev); | |
1da177e4 | 1023 | |
cdb9b9f7 | 1024 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1025 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1026 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1027 | |
4d57cdfa | 1028 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1029 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1030 | |
1da177e4 LT |
1031 | /* Fix up broken headers */ |
1032 | pci_fixup_device(pci_fixup_header, dev); | |
1033 | ||
1034 | /* | |
1035 | * Add the device to our list of discovered devices | |
1036 | * and the bus list for fixup functions, etc. | |
1037 | */ | |
d71374da | 1038 | down_write(&pci_bus_sem); |
1da177e4 | 1039 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1040 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1041 | } |
1042 | ||
451124a7 | 1043 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1044 | { |
1045 | struct pci_dev *dev; | |
1046 | ||
1047 | dev = pci_scan_device(bus, devfn); | |
1048 | if (!dev) | |
1049 | return NULL; | |
1050 | ||
1051 | pci_device_add(dev, bus); | |
1da177e4 LT |
1052 | |
1053 | return dev; | |
1054 | } | |
b73e9687 | 1055 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
1056 | |
1057 | /** | |
1058 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1059 | * @bus: PCI bus to scan | |
1060 | * @devfn: slot number to scan (must have zero function.) | |
1061 | * | |
1062 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1063 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1064 | * will not have is_added set. |
1da177e4 | 1065 | */ |
96bde06a | 1066 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 LT |
1067 | { |
1068 | int func, nr = 0; | |
1069 | int scan_all_fns; | |
1070 | ||
1071 | scan_all_fns = pcibios_scan_all_fns(bus, devfn); | |
1072 | ||
1073 | for (func = 0; func < 8; func++, devfn++) { | |
1074 | struct pci_dev *dev; | |
1075 | ||
1076 | dev = pci_scan_single_device(bus, devfn); | |
1077 | if (dev) { | |
1078 | nr++; | |
1079 | ||
1080 | /* | |
1081 | * If this is a single function device, | |
1082 | * don't scan past the first function. | |
1083 | */ | |
1084 | if (!dev->multifunction) { | |
1085 | if (func > 0) { | |
1086 | dev->multifunction = 1; | |
1087 | } else { | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | } else { | |
1092 | if (func == 0 && !scan_all_fns) | |
1093 | break; | |
1094 | } | |
1095 | } | |
7d715a6c SL |
1096 | |
1097 | if (bus->self) | |
1098 | pcie_aspm_init_link_state(bus->self); | |
1099 | ||
1da177e4 LT |
1100 | return nr; |
1101 | } | |
1102 | ||
0ab2b57f | 1103 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1104 | { |
1105 | unsigned int devfn, pass, max = bus->secondary; | |
1106 | struct pci_dev *dev; | |
1107 | ||
1108 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1109 | ||
1110 | /* Go find them, Rover! */ | |
1111 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1112 | pci_scan_slot(bus, devfn); | |
1113 | ||
1114 | /* | |
1115 | * After performing arch-dependent fixup of the bus, look behind | |
1116 | * all PCI-to-PCI bridges on this bus. | |
1117 | */ | |
1118 | pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1119 | pcibios_fixup_bus(bus); | |
1120 | for (pass=0; pass < 2; pass++) | |
1121 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1122 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1123 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1124 | max = pci_scan_bridge(bus, dev, max, pass); | |
1125 | } | |
1126 | ||
1127 | /* | |
1128 | * We've scanned the bus and so we know all about what's on | |
1129 | * the other side of any bridges that may be on this bus plus | |
1130 | * any devices. | |
1131 | * | |
1132 | * Return how far we've got finding sub-buses. | |
1133 | */ | |
1134 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1135 | pci_domain_nr(bus), bus->number, max); | |
1136 | return max; | |
1137 | } | |
1138 | ||
30a18d6c YL |
1139 | void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b) |
1140 | { | |
1141 | } | |
1142 | ||
96bde06a | 1143 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1144 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1145 | { |
1146 | int error; | |
1147 | struct pci_bus *b; | |
1148 | struct device *dev; | |
1149 | ||
1150 | b = pci_alloc_bus(); | |
1151 | if (!b) | |
1152 | return NULL; | |
1153 | ||
1154 | dev = kmalloc(sizeof(*dev), GFP_KERNEL); | |
1155 | if (!dev){ | |
1156 | kfree(b); | |
1157 | return NULL; | |
1158 | } | |
1159 | ||
1160 | b->sysdata = sysdata; | |
1161 | b->ops = ops; | |
1162 | ||
1163 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1164 | /* If we already got to this bus through a different bridge, ignore it */ | |
1165 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1166 | goto err_out; | |
1167 | } | |
d71374da ZY |
1168 | |
1169 | down_write(&pci_bus_sem); | |
1da177e4 | 1170 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1171 | up_write(&pci_bus_sem); |
1da177e4 LT |
1172 | |
1173 | memset(dev, 0, sizeof(*dev)); | |
1174 | dev->parent = parent; | |
1175 | dev->release = pci_release_bus_bridge_dev; | |
1176 | sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); | |
1177 | error = device_register(dev); | |
1178 | if (error) | |
1179 | goto dev_reg_err; | |
1180 | b->bridge = get_device(dev); | |
1181 | ||
0d358f22 YL |
1182 | if (!parent) |
1183 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1184 | ||
fd7d1ced GKH |
1185 | b->dev.class = &pcibus_class; |
1186 | b->dev.parent = b->bridge; | |
1187 | sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); | |
1188 | error = device_register(&b->dev); | |
1da177e4 LT |
1189 | if (error) |
1190 | goto class_dev_reg_err; | |
fd7d1ced | 1191 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1192 | if (error) |
fd7d1ced | 1193 | goto dev_create_file_err; |
1da177e4 LT |
1194 | |
1195 | /* Create legacy_io and legacy_mem files for this bus */ | |
1196 | pci_create_legacy_files(b); | |
1197 | ||
1da177e4 LT |
1198 | b->number = b->secondary = bus; |
1199 | b->resource[0] = &ioport_resource; | |
1200 | b->resource[1] = &iomem_resource; | |
1201 | ||
30a18d6c YL |
1202 | set_pci_bus_resources_arch_default(b); |
1203 | ||
1da177e4 LT |
1204 | return b; |
1205 | ||
fd7d1ced GKH |
1206 | dev_create_file_err: |
1207 | device_unregister(&b->dev); | |
1da177e4 LT |
1208 | class_dev_reg_err: |
1209 | device_unregister(dev); | |
1210 | dev_reg_err: | |
d71374da | 1211 | down_write(&pci_bus_sem); |
1da177e4 | 1212 | list_del(&b->node); |
d71374da | 1213 | up_write(&pci_bus_sem); |
1da177e4 LT |
1214 | err_out: |
1215 | kfree(dev); | |
1216 | kfree(b); | |
1217 | return NULL; | |
1218 | } | |
cdb9b9f7 | 1219 | |
0ab2b57f | 1220 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1221 | int bus, struct pci_ops *ops, void *sysdata) |
1222 | { | |
1223 | struct pci_bus *b; | |
1224 | ||
1225 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1226 | if (b) | |
1227 | b->subordinate = pci_scan_child_bus(b); | |
1228 | return b; | |
1229 | } | |
1da177e4 LT |
1230 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1231 | ||
1232 | #ifdef CONFIG_HOTPLUG | |
1233 | EXPORT_SYMBOL(pci_add_new_bus); | |
1da177e4 LT |
1234 | EXPORT_SYMBOL(pci_scan_slot); |
1235 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1236 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1237 | #endif | |
6b4b78fe MD |
1238 | |
1239 | static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b) | |
1240 | { | |
1241 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; | |
1242 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1243 | ||
1244 | if (a->bus->number < b->bus->number) return -1; | |
1245 | else if (a->bus->number > b->bus->number) return 1; | |
1246 | ||
1247 | if (a->devfn < b->devfn) return -1; | |
1248 | else if (a->devfn > b->devfn) return 1; | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | /* | |
1254 | * Yes, this forcably breaks the klist abstraction temporarily. It | |
1255 | * just wants to sort the klist, not change reference counts and | |
1256 | * take/drop locks rapidly in the process. It does all this while | |
1257 | * holding the lock for the list, so objects can't otherwise be | |
1258 | * added/removed while we're swizzling. | |
1259 | */ | |
1260 | static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list) | |
1261 | { | |
1262 | struct list_head *pos; | |
1263 | struct klist_node *n; | |
1264 | struct device *dev; | |
1265 | struct pci_dev *b; | |
1266 | ||
1267 | list_for_each(pos, list) { | |
1268 | n = container_of(pos, struct klist_node, n_node); | |
1269 | dev = container_of(n, struct device, knode_bus); | |
1270 | b = to_pci_dev(dev); | |
1271 | if (pci_sort_bf_cmp(a, b) <= 0) { | |
1272 | list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node); | |
1273 | return; | |
1274 | } | |
1275 | } | |
1276 | list_move_tail(&a->dev.knode_bus.n_node, list); | |
1277 | } | |
1278 | ||
5ff580c1 | 1279 | void __init pci_sort_breadthfirst(void) |
6b4b78fe MD |
1280 | { |
1281 | LIST_HEAD(sorted_devices); | |
1282 | struct list_head *pos, *tmp; | |
1283 | struct klist_node *n; | |
1284 | struct device *dev; | |
1285 | struct pci_dev *pdev; | |
b249072e | 1286 | struct klist *device_klist; |
6b4b78fe | 1287 | |
b249072e GKH |
1288 | device_klist = bus_get_device_klist(&pci_bus_type); |
1289 | ||
1290 | spin_lock(&device_klist->k_lock); | |
1291 | list_for_each_safe(pos, tmp, &device_klist->k_list) { | |
6b4b78fe MD |
1292 | n = container_of(pos, struct klist_node, n_node); |
1293 | dev = container_of(n, struct device, knode_bus); | |
1294 | pdev = to_pci_dev(dev); | |
1295 | pci_insertion_sort_klist(pdev, &sorted_devices); | |
1296 | } | |
b249072e GKH |
1297 | list_splice(&sorted_devices, &device_klist->k_list); |
1298 | spin_unlock(&device_klist->k_lock); | |
6b4b78fe | 1299 | } |