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8b8b091b TL |
1 | /* |
2 | * Generic device tree based pinctrl driver for one register per pin | |
3 | * type pinmux controllers | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/list.h> | |
18 | ||
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/of_address.h> | |
22 | ||
23 | #include <linux/pinctrl/pinctrl.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | ||
26 | #include "core.h" | |
27 | ||
28 | #define DRIVER_NAME "pinctrl-single" | |
9e605cb6 PU |
29 | #define PCS_MUX_PINS_NAME "pinctrl-single,pins" |
30 | #define PCS_MUX_BITS_NAME "pinctrl-single,bits" | |
8b8b091b TL |
31 | #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) |
32 | #define PCS_OFF_DISABLED ~0U | |
2e8b2eab | 33 | #define PCS_MAX_GPIO_VALUES 2 |
8b8b091b TL |
34 | |
35 | /** | |
36 | * struct pcs_pingroup - pingroups for a function | |
37 | * @np: pingroup device node pointer | |
38 | * @name: pingroup name | |
39 | * @gpins: array of the pins in the group | |
40 | * @ngpins: number of pins in the group | |
41 | * @node: list node | |
42 | */ | |
43 | struct pcs_pingroup { | |
44 | struct device_node *np; | |
45 | const char *name; | |
46 | int *gpins; | |
47 | int ngpins; | |
48 | struct list_head node; | |
49 | }; | |
50 | ||
51 | /** | |
52 | * struct pcs_func_vals - mux function register offset and value pair | |
53 | * @reg: register virtual address | |
54 | * @val: register value | |
55 | */ | |
56 | struct pcs_func_vals { | |
57 | void __iomem *reg; | |
58 | unsigned val; | |
9e605cb6 | 59 | unsigned mask; |
8b8b091b TL |
60 | }; |
61 | ||
62 | /** | |
63 | * struct pcs_function - pinctrl function | |
64 | * @name: pinctrl function name | |
65 | * @vals: register and vals array | |
66 | * @nvals: number of entries in vals array | |
67 | * @pgnames: array of pingroup names the function uses | |
68 | * @npgnames: number of pingroup names the function uses | |
69 | * @node: list node | |
70 | */ | |
71 | struct pcs_function { | |
72 | const char *name; | |
73 | struct pcs_func_vals *vals; | |
74 | unsigned nvals; | |
75 | const char **pgnames; | |
76 | int npgnames; | |
77 | struct list_head node; | |
78 | }; | |
79 | ||
2e8b2eab HZ |
80 | /** |
81 | * struct pcs_gpio_range - pinctrl gpio range | |
82 | * @range: subrange of the GPIO number space | |
83 | * @gpio_func: gpio function value in the pinmux register | |
84 | */ | |
85 | struct pcs_gpio_range { | |
86 | struct pinctrl_gpio_range range; | |
87 | int gpio_func; | |
88 | }; | |
89 | ||
8b8b091b TL |
90 | /** |
91 | * struct pcs_data - wrapper for data needed by pinctrl framework | |
92 | * @pa: pindesc array | |
93 | * @cur: index to current element | |
94 | * | |
95 | * REVISIT: We should be able to drop this eventually by adding | |
96 | * support for registering pins individually in the pinctrl | |
97 | * framework for those drivers that don't need a static array. | |
98 | */ | |
99 | struct pcs_data { | |
100 | struct pinctrl_pin_desc *pa; | |
101 | int cur; | |
102 | }; | |
103 | ||
104 | /** | |
105 | * struct pcs_name - register name for a pin | |
106 | * @name: name of the pinctrl register | |
107 | * | |
108 | * REVISIT: We may want to make names optional in the pinctrl | |
109 | * framework as some drivers may not care about pin names to | |
110 | * avoid kernel bloat. The pin names can be deciphered by user | |
111 | * space tools using debugfs based on the register address and | |
112 | * SoC packaging information. | |
113 | */ | |
114 | struct pcs_name { | |
115 | char name[PCS_REG_NAME_LEN]; | |
116 | }; | |
117 | ||
118 | /** | |
119 | * struct pcs_device - pinctrl device instance | |
120 | * @res: resources | |
121 | * @base: virtual address of the controller | |
122 | * @size: size of the ioremapped area | |
123 | * @dev: device entry | |
124 | * @pctl: pin controller device | |
125 | * @mutex: mutex protecting the lists | |
126 | * @width: bits per mux register | |
127 | * @fmask: function register mask | |
128 | * @fshift: function register shift | |
129 | * @foff: value to turn mux off | |
130 | * @fmax: max number of functions in fmask | |
131 | * @names: array of register names for pins | |
132 | * @pins: physical pins on the SoC | |
133 | * @pgtree: pingroup index radix tree | |
134 | * @ftree: function index radix tree | |
135 | * @pingroups: list of pingroups | |
136 | * @functions: list of functions | |
137 | * @ngroups: number of pingroups | |
138 | * @nfuncs: number of functions | |
139 | * @desc: pin controller descriptor | |
140 | * @read: register read function to use | |
141 | * @write: register write function to use | |
142 | */ | |
143 | struct pcs_device { | |
144 | struct resource *res; | |
145 | void __iomem *base; | |
146 | unsigned size; | |
147 | struct device *dev; | |
148 | struct pinctrl_dev *pctl; | |
149 | struct mutex mutex; | |
150 | unsigned width; | |
151 | unsigned fmask; | |
152 | unsigned fshift; | |
153 | unsigned foff; | |
154 | unsigned fmax; | |
9e605cb6 | 155 | bool bits_per_mux; |
8b8b091b TL |
156 | struct pcs_name *names; |
157 | struct pcs_data pins; | |
158 | struct radix_tree_root pgtree; | |
159 | struct radix_tree_root ftree; | |
160 | struct list_head pingroups; | |
161 | struct list_head functions; | |
162 | unsigned ngroups; | |
163 | unsigned nfuncs; | |
164 | struct pinctrl_desc desc; | |
165 | unsigned (*read)(void __iomem *reg); | |
166 | void (*write)(unsigned val, void __iomem *reg); | |
167 | }; | |
168 | ||
169 | /* | |
170 | * REVISIT: Reads and writes could eventually use regmap or something | |
171 | * generic. But at least on omaps, some mux registers are performance | |
172 | * critical as they may need to be remuxed every time before and after | |
173 | * idle. Adding tests for register access width for every read and | |
174 | * write like regmap is doing is not desired, and caching the registers | |
175 | * does not help in this case. | |
176 | */ | |
177 | ||
178 | static unsigned __maybe_unused pcs_readb(void __iomem *reg) | |
179 | { | |
180 | return readb(reg); | |
181 | } | |
182 | ||
183 | static unsigned __maybe_unused pcs_readw(void __iomem *reg) | |
184 | { | |
185 | return readw(reg); | |
186 | } | |
187 | ||
188 | static unsigned __maybe_unused pcs_readl(void __iomem *reg) | |
189 | { | |
190 | return readl(reg); | |
191 | } | |
192 | ||
193 | static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) | |
194 | { | |
195 | writeb(val, reg); | |
196 | } | |
197 | ||
198 | static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) | |
199 | { | |
200 | writew(val, reg); | |
201 | } | |
202 | ||
203 | static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) | |
204 | { | |
205 | writel(val, reg); | |
206 | } | |
207 | ||
208 | static int pcs_get_groups_count(struct pinctrl_dev *pctldev) | |
209 | { | |
210 | struct pcs_device *pcs; | |
211 | ||
212 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
213 | ||
214 | return pcs->ngroups; | |
215 | } | |
216 | ||
217 | static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, | |
218 | unsigned gselector) | |
219 | { | |
220 | struct pcs_device *pcs; | |
221 | struct pcs_pingroup *group; | |
222 | ||
223 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
224 | group = radix_tree_lookup(&pcs->pgtree, gselector); | |
225 | if (!group) { | |
226 | dev_err(pcs->dev, "%s could not find pingroup%i\n", | |
227 | __func__, gselector); | |
228 | return NULL; | |
229 | } | |
230 | ||
231 | return group->name; | |
232 | } | |
233 | ||
234 | static int pcs_get_group_pins(struct pinctrl_dev *pctldev, | |
235 | unsigned gselector, | |
236 | const unsigned **pins, | |
237 | unsigned *npins) | |
238 | { | |
239 | struct pcs_device *pcs; | |
240 | struct pcs_pingroup *group; | |
241 | ||
242 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
243 | group = radix_tree_lookup(&pcs->pgtree, gselector); | |
244 | if (!group) { | |
245 | dev_err(pcs->dev, "%s could not find pingroup%i\n", | |
246 | __func__, gselector); | |
247 | return -EINVAL; | |
248 | } | |
249 | ||
250 | *pins = group->gpins; | |
251 | *npins = group->ngpins; | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, | |
257 | struct seq_file *s, | |
e7ed6718 | 258 | unsigned pin) |
8b8b091b | 259 | { |
7d66ce7f | 260 | struct pcs_device *pcs; |
e7ed6718 | 261 | unsigned val, mux_bytes; |
7d66ce7f MP |
262 | |
263 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
264 | ||
e7ed6718 HZ |
265 | mux_bytes = pcs->width / BITS_PER_BYTE; |
266 | val = pcs->read(pcs->base + pin * mux_bytes); | |
7d66ce7f MP |
267 | |
268 | seq_printf(s, "%08x %s " , val, DRIVER_NAME); | |
8b8b091b TL |
269 | } |
270 | ||
271 | static void pcs_dt_free_map(struct pinctrl_dev *pctldev, | |
272 | struct pinctrl_map *map, unsigned num_maps) | |
273 | { | |
274 | struct pcs_device *pcs; | |
275 | ||
276 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
277 | devm_kfree(pcs->dev, map); | |
278 | } | |
279 | ||
280 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
281 | struct device_node *np_config, | |
282 | struct pinctrl_map **map, unsigned *num_maps); | |
283 | ||
284 | static struct pinctrl_ops pcs_pinctrl_ops = { | |
285 | .get_groups_count = pcs_get_groups_count, | |
286 | .get_group_name = pcs_get_group_name, | |
287 | .get_group_pins = pcs_get_group_pins, | |
288 | .pin_dbg_show = pcs_pin_dbg_show, | |
289 | .dt_node_to_map = pcs_dt_node_to_map, | |
290 | .dt_free_map = pcs_dt_free_map, | |
291 | }; | |
292 | ||
293 | static int pcs_get_functions_count(struct pinctrl_dev *pctldev) | |
294 | { | |
295 | struct pcs_device *pcs; | |
296 | ||
297 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
298 | ||
299 | return pcs->nfuncs; | |
300 | } | |
301 | ||
302 | static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, | |
303 | unsigned fselector) | |
304 | { | |
305 | struct pcs_device *pcs; | |
306 | struct pcs_function *func; | |
307 | ||
308 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
309 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
310 | if (!func) { | |
311 | dev_err(pcs->dev, "%s could not find function%i\n", | |
312 | __func__, fselector); | |
313 | return NULL; | |
314 | } | |
315 | ||
316 | return func->name; | |
317 | } | |
318 | ||
319 | static int pcs_get_function_groups(struct pinctrl_dev *pctldev, | |
320 | unsigned fselector, | |
321 | const char * const **groups, | |
322 | unsigned * const ngroups) | |
323 | { | |
324 | struct pcs_device *pcs; | |
325 | struct pcs_function *func; | |
326 | ||
327 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
328 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
329 | if (!func) { | |
330 | dev_err(pcs->dev, "%s could not find function%i\n", | |
331 | __func__, fselector); | |
332 | return -EINVAL; | |
333 | } | |
334 | *groups = func->pgnames; | |
335 | *ngroups = func->npgnames; | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, | |
341 | unsigned group) | |
342 | { | |
343 | struct pcs_device *pcs; | |
344 | struct pcs_function *func; | |
345 | int i; | |
346 | ||
347 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
348 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
349 | if (!func) | |
350 | return -EINVAL; | |
351 | ||
352 | dev_dbg(pcs->dev, "enabling %s function%i\n", | |
353 | func->name, fselector); | |
354 | ||
355 | for (i = 0; i < func->nvals; i++) { | |
356 | struct pcs_func_vals *vals; | |
9e605cb6 | 357 | unsigned val, mask; |
8b8b091b TL |
358 | |
359 | vals = &func->vals[i]; | |
360 | val = pcs->read(vals->reg); | |
9e605cb6 PU |
361 | if (!vals->mask) |
362 | mask = pcs->fmask; | |
363 | else | |
364 | mask = pcs->fmask & vals->mask; | |
365 | ||
366 | val &= ~mask; | |
367 | val |= (vals->val & mask); | |
8b8b091b TL |
368 | pcs->write(val, vals->reg); |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, | |
375 | unsigned group) | |
376 | { | |
377 | struct pcs_device *pcs; | |
378 | struct pcs_function *func; | |
379 | int i; | |
380 | ||
381 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
382 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
383 | if (!func) { | |
384 | dev_err(pcs->dev, "%s could not find function%i\n", | |
385 | __func__, fselector); | |
386 | return; | |
387 | } | |
388 | ||
389 | /* | |
390 | * Ignore disable if function-off is not specified. Some hardware | |
391 | * does not have clearly defined disable function. For pin specific | |
392 | * off modes, you can use alternate named states as described in | |
393 | * pinctrl-bindings.txt. | |
394 | */ | |
395 | if (pcs->foff == PCS_OFF_DISABLED) { | |
396 | dev_dbg(pcs->dev, "ignoring disable for %s function%i\n", | |
397 | func->name, fselector); | |
398 | return; | |
399 | } | |
400 | ||
401 | dev_dbg(pcs->dev, "disabling function%i %s\n", | |
402 | fselector, func->name); | |
403 | ||
404 | for (i = 0; i < func->nvals; i++) { | |
405 | struct pcs_func_vals *vals; | |
406 | unsigned val; | |
407 | ||
408 | vals = &func->vals[i]; | |
409 | val = pcs->read(vals->reg); | |
410 | val &= ~pcs->fmask; | |
411 | val |= pcs->foff << pcs->fshift; | |
412 | pcs->write(val, vals->reg); | |
413 | } | |
414 | } | |
415 | ||
416 | static int pcs_request_gpio(struct pinctrl_dev *pctldev, | |
2e8b2eab | 417 | struct pinctrl_gpio_range *range, unsigned pin) |
8b8b091b | 418 | { |
2e8b2eab HZ |
419 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
420 | struct pcs_gpio_range *gpio = NULL; | |
421 | int end, mux_bytes; | |
422 | unsigned data; | |
423 | ||
424 | gpio = container_of(range, struct pcs_gpio_range, range); | |
425 | end = range->pin_base + range->npins - 1; | |
426 | if (pin < range->pin_base || pin > end) { | |
427 | dev_err(pctldev->dev, | |
428 | "pin %d isn't in the range of %d to %d\n", | |
429 | pin, range->pin_base, end); | |
430 | return -EINVAL; | |
431 | } | |
432 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
433 | data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; | |
434 | data |= gpio->gpio_func; | |
435 | pcs->write(data, pcs->base + pin * mux_bytes); | |
436 | return 0; | |
8b8b091b TL |
437 | } |
438 | ||
439 | static struct pinmux_ops pcs_pinmux_ops = { | |
440 | .get_functions_count = pcs_get_functions_count, | |
441 | .get_function_name = pcs_get_function_name, | |
442 | .get_function_groups = pcs_get_function_groups, | |
443 | .enable = pcs_enable, | |
444 | .disable = pcs_disable, | |
445 | .gpio_request_enable = pcs_request_gpio, | |
446 | }; | |
447 | ||
448 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, | |
449 | unsigned pin, unsigned long *config) | |
450 | { | |
451 | return -ENOTSUPP; | |
452 | } | |
453 | ||
454 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, | |
455 | unsigned pin, unsigned long config) | |
456 | { | |
457 | return -ENOTSUPP; | |
458 | } | |
459 | ||
460 | static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, | |
461 | unsigned group, unsigned long *config) | |
462 | { | |
463 | return -ENOTSUPP; | |
464 | } | |
465 | ||
466 | static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, | |
467 | unsigned group, unsigned long config) | |
468 | { | |
469 | return -ENOTSUPP; | |
470 | } | |
471 | ||
472 | static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
473 | struct seq_file *s, unsigned offset) | |
474 | { | |
475 | } | |
476 | ||
477 | static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
478 | struct seq_file *s, unsigned selector) | |
479 | { | |
480 | } | |
481 | ||
482 | static struct pinconf_ops pcs_pinconf_ops = { | |
483 | .pin_config_get = pcs_pinconf_get, | |
484 | .pin_config_set = pcs_pinconf_set, | |
485 | .pin_config_group_get = pcs_pinconf_group_get, | |
486 | .pin_config_group_set = pcs_pinconf_group_set, | |
487 | .pin_config_dbg_show = pcs_pinconf_dbg_show, | |
488 | .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, | |
489 | }; | |
490 | ||
491 | /** | |
492 | * pcs_add_pin() - add a pin to the static per controller pin array | |
493 | * @pcs: pcs driver instance | |
494 | * @offset: register offset from base | |
495 | */ | |
496 | static int __devinit pcs_add_pin(struct pcs_device *pcs, unsigned offset) | |
497 | { | |
498 | struct pinctrl_pin_desc *pin; | |
499 | struct pcs_name *pn; | |
500 | int i; | |
501 | ||
502 | i = pcs->pins.cur; | |
503 | if (i >= pcs->desc.npins) { | |
504 | dev_err(pcs->dev, "too many pins, max %i\n", | |
505 | pcs->desc.npins); | |
506 | return -ENOMEM; | |
507 | } | |
508 | ||
509 | pin = &pcs->pins.pa[i]; | |
510 | pn = &pcs->names[i]; | |
511 | sprintf(pn->name, "%lx", | |
512 | (unsigned long)pcs->res->start + offset); | |
513 | pin->name = pn->name; | |
514 | pin->number = i; | |
515 | pcs->pins.cur++; | |
516 | ||
517 | return i; | |
518 | } | |
519 | ||
520 | /** | |
521 | * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver | |
522 | * @pcs: pcs driver instance | |
523 | * | |
524 | * In case of errors, resources are freed in pcs_free_resources. | |
525 | * | |
526 | * If your hardware needs holes in the address space, then just set | |
527 | * up multiple driver instances. | |
528 | */ | |
529 | static int __devinit pcs_allocate_pin_table(struct pcs_device *pcs) | |
530 | { | |
531 | int mux_bytes, nr_pins, i; | |
532 | ||
533 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
534 | nr_pins = pcs->size / mux_bytes; | |
535 | ||
536 | dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); | |
537 | pcs->pins.pa = devm_kzalloc(pcs->dev, | |
538 | sizeof(*pcs->pins.pa) * nr_pins, | |
539 | GFP_KERNEL); | |
540 | if (!pcs->pins.pa) | |
541 | return -ENOMEM; | |
542 | ||
543 | pcs->names = devm_kzalloc(pcs->dev, | |
544 | sizeof(struct pcs_name) * nr_pins, | |
545 | GFP_KERNEL); | |
546 | if (!pcs->names) | |
547 | return -ENOMEM; | |
548 | ||
549 | pcs->desc.pins = pcs->pins.pa; | |
550 | pcs->desc.npins = nr_pins; | |
551 | ||
552 | for (i = 0; i < pcs->desc.npins; i++) { | |
553 | unsigned offset; | |
554 | int res; | |
555 | ||
556 | offset = i * mux_bytes; | |
557 | res = pcs_add_pin(pcs, offset); | |
558 | if (res < 0) { | |
559 | dev_err(pcs->dev, "error adding pins: %i\n", res); | |
560 | return res; | |
561 | } | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | /** | |
568 | * pcs_add_function() - adds a new function to the function list | |
569 | * @pcs: pcs driver instance | |
570 | * @np: device node of the mux entry | |
571 | * @name: name of the function | |
572 | * @vals: array of mux register value pairs used by the function | |
573 | * @nvals: number of mux register value pairs | |
574 | * @pgnames: array of pingroup names for the function | |
575 | * @npgnames: number of pingroup names | |
576 | */ | |
577 | static struct pcs_function *pcs_add_function(struct pcs_device *pcs, | |
578 | struct device_node *np, | |
579 | const char *name, | |
580 | struct pcs_func_vals *vals, | |
581 | unsigned nvals, | |
582 | const char **pgnames, | |
583 | unsigned npgnames) | |
584 | { | |
585 | struct pcs_function *function; | |
586 | ||
587 | function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); | |
588 | if (!function) | |
589 | return NULL; | |
590 | ||
591 | function->name = name; | |
592 | function->vals = vals; | |
593 | function->nvals = nvals; | |
594 | function->pgnames = pgnames; | |
595 | function->npgnames = npgnames; | |
596 | ||
597 | mutex_lock(&pcs->mutex); | |
598 | list_add_tail(&function->node, &pcs->functions); | |
599 | radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); | |
600 | pcs->nfuncs++; | |
601 | mutex_unlock(&pcs->mutex); | |
602 | ||
603 | return function; | |
604 | } | |
605 | ||
606 | static void pcs_remove_function(struct pcs_device *pcs, | |
607 | struct pcs_function *function) | |
608 | { | |
609 | int i; | |
610 | ||
611 | mutex_lock(&pcs->mutex); | |
612 | for (i = 0; i < pcs->nfuncs; i++) { | |
613 | struct pcs_function *found; | |
614 | ||
615 | found = radix_tree_lookup(&pcs->ftree, i); | |
616 | if (found == function) | |
617 | radix_tree_delete(&pcs->ftree, i); | |
618 | } | |
619 | list_del(&function->node); | |
620 | mutex_unlock(&pcs->mutex); | |
621 | } | |
622 | ||
623 | /** | |
624 | * pcs_add_pingroup() - add a pingroup to the pingroup list | |
625 | * @pcs: pcs driver instance | |
626 | * @np: device node of the mux entry | |
627 | * @name: name of the pingroup | |
628 | * @gpins: array of the pins that belong to the group | |
629 | * @ngpins: number of pins in the group | |
630 | */ | |
631 | static int pcs_add_pingroup(struct pcs_device *pcs, | |
632 | struct device_node *np, | |
633 | const char *name, | |
634 | int *gpins, | |
635 | int ngpins) | |
636 | { | |
637 | struct pcs_pingroup *pingroup; | |
638 | ||
639 | pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); | |
640 | if (!pingroup) | |
641 | return -ENOMEM; | |
642 | ||
643 | pingroup->name = name; | |
644 | pingroup->np = np; | |
645 | pingroup->gpins = gpins; | |
646 | pingroup->ngpins = ngpins; | |
647 | ||
648 | mutex_lock(&pcs->mutex); | |
649 | list_add_tail(&pingroup->node, &pcs->pingroups); | |
650 | radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); | |
651 | pcs->ngroups++; | |
652 | mutex_unlock(&pcs->mutex); | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | /** | |
658 | * pcs_get_pin_by_offset() - get a pin index based on the register offset | |
659 | * @pcs: pcs driver instance | |
660 | * @offset: register offset from the base | |
661 | * | |
662 | * Note that this is OK as long as the pins are in a static array. | |
663 | */ | |
664 | static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) | |
665 | { | |
666 | unsigned index; | |
667 | ||
668 | if (offset >= pcs->size) { | |
669 | dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
670 | offset, pcs->size); | |
671 | return -EINVAL; | |
672 | } | |
673 | ||
674 | index = offset / (pcs->width / BITS_PER_BYTE); | |
675 | ||
676 | return index; | |
677 | } | |
678 | ||
679 | /** | |
680 | * smux_parse_one_pinctrl_entry() - parses a device tree mux entry | |
681 | * @pcs: pinctrl driver instance | |
682 | * @np: device node of the mux entry | |
683 | * @map: map entry | |
684 | * @pgnames: pingroup names | |
685 | * | |
686 | * Note that this binding currently supports only sets of one register + value. | |
687 | * | |
688 | * Also note that this driver tries to avoid understanding pin and function | |
689 | * names because of the extra bloat they would cause especially in the case of | |
690 | * a large number of pins. This driver just sets what is specified for the board | |
691 | * in the .dts file. Further user space debugging tools can be developed to | |
692 | * decipher the pin and function names using debugfs. | |
693 | * | |
694 | * If you are concerned about the boot time, set up the static pins in | |
695 | * the bootloader, and only set up selected pins as device tree entries. | |
696 | */ | |
697 | static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, | |
698 | struct device_node *np, | |
699 | struct pinctrl_map **map, | |
700 | const char **pgnames) | |
701 | { | |
702 | struct pcs_func_vals *vals; | |
703 | const __be32 *mux; | |
9e605cb6 | 704 | int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; |
8b8b091b TL |
705 | struct pcs_function *function; |
706 | ||
9e605cb6 PU |
707 | if (pcs->bits_per_mux) { |
708 | params = 3; | |
709 | mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); | |
710 | } else { | |
711 | params = 2; | |
712 | mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); | |
713 | } | |
714 | ||
715 | if (!mux) { | |
716 | dev_err(pcs->dev, "no valid property for %s\n", np->name); | |
717 | return -EINVAL; | |
718 | } | |
719 | ||
720 | if (size < (sizeof(*mux) * params)) { | |
721 | dev_err(pcs->dev, "bad data for %s\n", np->name); | |
8b8b091b TL |
722 | return -EINVAL; |
723 | } | |
724 | ||
725 | size /= sizeof(*mux); /* Number of elements in array */ | |
9e605cb6 | 726 | rows = size / params; |
8b8b091b TL |
727 | |
728 | vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); | |
729 | if (!vals) | |
730 | return -ENOMEM; | |
731 | ||
732 | pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); | |
733 | if (!pins) | |
734 | goto free_vals; | |
735 | ||
736 | while (index < size) { | |
737 | unsigned offset, val; | |
738 | int pin; | |
739 | ||
740 | offset = be32_to_cpup(mux + index++); | |
741 | val = be32_to_cpup(mux + index++); | |
742 | vals[found].reg = pcs->base + offset; | |
743 | vals[found].val = val; | |
9e605cb6 PU |
744 | if (params == 3) { |
745 | val = be32_to_cpup(mux + index++); | |
746 | vals[found].mask = val; | |
747 | } | |
8b8b091b TL |
748 | |
749 | pin = pcs_get_pin_by_offset(pcs, offset); | |
750 | if (pin < 0) { | |
751 | dev_err(pcs->dev, | |
752 | "could not add functions for %s %ux\n", | |
753 | np->name, offset); | |
754 | break; | |
755 | } | |
756 | pins[found++] = pin; | |
757 | } | |
758 | ||
759 | pgnames[0] = np->name; | |
760 | function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); | |
761 | if (!function) | |
762 | goto free_pins; | |
763 | ||
764 | res = pcs_add_pingroup(pcs, np, np->name, pins, found); | |
765 | if (res < 0) | |
766 | goto free_function; | |
767 | ||
768 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
769 | (*map)->data.mux.group = np->name; | |
770 | (*map)->data.mux.function = np->name; | |
771 | ||
772 | return 0; | |
773 | ||
774 | free_function: | |
775 | pcs_remove_function(pcs, function); | |
776 | ||
777 | free_pins: | |
778 | devm_kfree(pcs->dev, pins); | |
779 | ||
780 | free_vals: | |
781 | devm_kfree(pcs->dev, vals); | |
782 | ||
783 | return res; | |
784 | } | |
785 | /** | |
786 | * pcs_dt_node_to_map() - allocates and parses pinctrl maps | |
787 | * @pctldev: pinctrl instance | |
788 | * @np_config: device tree pinmux entry | |
789 | * @map: array of map entries | |
790 | * @num_maps: number of maps | |
791 | */ | |
792 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
793 | struct device_node *np_config, | |
794 | struct pinctrl_map **map, unsigned *num_maps) | |
795 | { | |
796 | struct pcs_device *pcs; | |
797 | const char **pgnames; | |
798 | int ret; | |
799 | ||
800 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
801 | ||
802 | *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); | |
803 | if (!map) | |
804 | return -ENOMEM; | |
805 | ||
806 | *num_maps = 0; | |
807 | ||
808 | pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); | |
809 | if (!pgnames) { | |
810 | ret = -ENOMEM; | |
811 | goto free_map; | |
812 | } | |
813 | ||
814 | ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); | |
815 | if (ret < 0) { | |
816 | dev_err(pcs->dev, "no pins entries for %s\n", | |
817 | np_config->name); | |
818 | goto free_pgnames; | |
819 | } | |
820 | *num_maps = 1; | |
821 | ||
822 | return 0; | |
823 | ||
824 | free_pgnames: | |
825 | devm_kfree(pcs->dev, pgnames); | |
826 | free_map: | |
827 | devm_kfree(pcs->dev, *map); | |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
832 | /** | |
833 | * pcs_free_funcs() - free memory used by functions | |
834 | * @pcs: pcs driver instance | |
835 | */ | |
836 | static void pcs_free_funcs(struct pcs_device *pcs) | |
837 | { | |
838 | struct list_head *pos, *tmp; | |
839 | int i; | |
840 | ||
841 | mutex_lock(&pcs->mutex); | |
842 | for (i = 0; i < pcs->nfuncs; i++) { | |
843 | struct pcs_function *func; | |
844 | ||
845 | func = radix_tree_lookup(&pcs->ftree, i); | |
846 | if (!func) | |
847 | continue; | |
848 | radix_tree_delete(&pcs->ftree, i); | |
849 | } | |
850 | list_for_each_safe(pos, tmp, &pcs->functions) { | |
851 | struct pcs_function *function; | |
852 | ||
853 | function = list_entry(pos, struct pcs_function, node); | |
854 | list_del(&function->node); | |
855 | } | |
856 | mutex_unlock(&pcs->mutex); | |
857 | } | |
858 | ||
859 | /** | |
860 | * pcs_free_pingroups() - free memory used by pingroups | |
861 | * @pcs: pcs driver instance | |
862 | */ | |
863 | static void pcs_free_pingroups(struct pcs_device *pcs) | |
864 | { | |
865 | struct list_head *pos, *tmp; | |
866 | int i; | |
867 | ||
868 | mutex_lock(&pcs->mutex); | |
869 | for (i = 0; i < pcs->ngroups; i++) { | |
870 | struct pcs_pingroup *pingroup; | |
871 | ||
872 | pingroup = radix_tree_lookup(&pcs->pgtree, i); | |
873 | if (!pingroup) | |
874 | continue; | |
875 | radix_tree_delete(&pcs->pgtree, i); | |
876 | } | |
877 | list_for_each_safe(pos, tmp, &pcs->pingroups) { | |
878 | struct pcs_pingroup *pingroup; | |
879 | ||
880 | pingroup = list_entry(pos, struct pcs_pingroup, node); | |
881 | list_del(&pingroup->node); | |
882 | } | |
883 | mutex_unlock(&pcs->mutex); | |
884 | } | |
885 | ||
886 | /** | |
887 | * pcs_free_resources() - free memory used by this driver | |
888 | * @pcs: pcs driver instance | |
889 | */ | |
890 | static void pcs_free_resources(struct pcs_device *pcs) | |
891 | { | |
892 | if (pcs->pctl) | |
893 | pinctrl_unregister(pcs->pctl); | |
894 | ||
895 | pcs_free_funcs(pcs); | |
896 | pcs_free_pingroups(pcs); | |
897 | } | |
898 | ||
899 | #define PCS_GET_PROP_U32(name, reg, err) \ | |
900 | do { \ | |
901 | ret = of_property_read_u32(np, name, reg); \ | |
902 | if (ret) { \ | |
903 | dev_err(pcs->dev, err); \ | |
904 | return ret; \ | |
905 | } \ | |
906 | } while (0); | |
907 | ||
908 | static struct of_device_id pcs_of_match[]; | |
909 | ||
2e8b2eab HZ |
910 | static int __devinit pcs_add_gpio_range(struct device_node *node, |
911 | struct pcs_device *pcs) | |
912 | { | |
913 | struct pcs_gpio_range *gpio; | |
914 | struct device_node *child; | |
915 | struct resource r; | |
916 | const char name[] = "pinctrl-single"; | |
917 | u32 gpiores[PCS_MAX_GPIO_VALUES]; | |
918 | int ret, i = 0, mux_bytes = 0; | |
919 | ||
920 | for_each_child_of_node(node, child) { | |
921 | ret = of_address_to_resource(child, 0, &r); | |
922 | if (ret < 0) | |
923 | continue; | |
924 | memset(gpiores, 0, sizeof(u32) * PCS_MAX_GPIO_VALUES); | |
925 | ret = of_property_read_u32_array(child, "pinctrl-single,gpio", | |
926 | gpiores, PCS_MAX_GPIO_VALUES); | |
927 | if (ret < 0) | |
928 | continue; | |
929 | gpio = devm_kzalloc(pcs->dev, sizeof(*gpio), GFP_KERNEL); | |
930 | if (!gpio) { | |
931 | dev_err(pcs->dev, "failed to allocate pcs gpio\n"); | |
932 | return -ENOMEM; | |
933 | } | |
934 | gpio->range.name = devm_kzalloc(pcs->dev, sizeof(name), | |
935 | GFP_KERNEL); | |
936 | if (!gpio->range.name) { | |
937 | dev_err(pcs->dev, "failed to allocate range name\n"); | |
938 | return -ENOMEM; | |
939 | } | |
940 | memcpy((char *)gpio->range.name, name, sizeof(name)); | |
941 | ||
942 | gpio->range.id = i++; | |
943 | gpio->range.base = gpiores[0]; | |
944 | gpio->gpio_func = gpiores[1]; | |
945 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
946 | gpio->range.pin_base = (r.start - pcs->res->start) / mux_bytes; | |
947 | gpio->range.npins = (r.end - r.start) / mux_bytes + 1; | |
948 | ||
949 | pinctrl_add_gpio_range(pcs->pctl, &gpio->range); | |
950 | } | |
951 | return 0; | |
952 | } | |
953 | ||
8b8b091b TL |
954 | static int __devinit pcs_probe(struct platform_device *pdev) |
955 | { | |
956 | struct device_node *np = pdev->dev.of_node; | |
957 | const struct of_device_id *match; | |
958 | struct resource *res; | |
959 | struct pcs_device *pcs; | |
960 | int ret; | |
961 | ||
962 | match = of_match_device(pcs_of_match, &pdev->dev); | |
963 | if (!match) | |
964 | return -EINVAL; | |
965 | ||
966 | pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); | |
967 | if (!pcs) { | |
968 | dev_err(&pdev->dev, "could not allocate\n"); | |
969 | return -ENOMEM; | |
970 | } | |
971 | pcs->dev = &pdev->dev; | |
972 | mutex_init(&pcs->mutex); | |
973 | INIT_LIST_HEAD(&pcs->pingroups); | |
974 | INIT_LIST_HEAD(&pcs->functions); | |
975 | ||
976 | PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, | |
977 | "register width not specified\n"); | |
978 | ||
979 | PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, | |
980 | "function register mask not specified\n"); | |
981 | pcs->fshift = ffs(pcs->fmask) - 1; | |
982 | pcs->fmax = pcs->fmask >> pcs->fshift; | |
983 | ||
984 | ret = of_property_read_u32(np, "pinctrl-single,function-off", | |
985 | &pcs->foff); | |
986 | if (ret) | |
987 | pcs->foff = PCS_OFF_DISABLED; | |
988 | ||
9e605cb6 PU |
989 | pcs->bits_per_mux = of_property_read_bool(np, |
990 | "pinctrl-single,bit-per-mux"); | |
991 | ||
8b8b091b TL |
992 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
993 | if (!res) { | |
994 | dev_err(pcs->dev, "could not get resource\n"); | |
995 | return -ENODEV; | |
996 | } | |
997 | ||
998 | pcs->res = devm_request_mem_region(pcs->dev, res->start, | |
999 | resource_size(res), DRIVER_NAME); | |
1000 | if (!pcs->res) { | |
1001 | dev_err(pcs->dev, "could not get mem_region\n"); | |
1002 | return -EBUSY; | |
1003 | } | |
1004 | ||
1005 | pcs->size = resource_size(pcs->res); | |
1006 | pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); | |
1007 | if (!pcs->base) { | |
1008 | dev_err(pcs->dev, "could not ioremap\n"); | |
1009 | return -ENODEV; | |
1010 | } | |
1011 | ||
1012 | INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); | |
1013 | INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); | |
1014 | platform_set_drvdata(pdev, pcs); | |
1015 | ||
1016 | switch (pcs->width) { | |
1017 | case 8: | |
1018 | pcs->read = pcs_readb; | |
1019 | pcs->write = pcs_writeb; | |
1020 | break; | |
1021 | case 16: | |
1022 | pcs->read = pcs_readw; | |
1023 | pcs->write = pcs_writew; | |
1024 | break; | |
1025 | case 32: | |
1026 | pcs->read = pcs_readl; | |
1027 | pcs->write = pcs_writel; | |
1028 | break; | |
1029 | default: | |
1030 | break; | |
1031 | } | |
1032 | ||
1033 | pcs->desc.name = DRIVER_NAME; | |
1034 | pcs->desc.pctlops = &pcs_pinctrl_ops; | |
1035 | pcs->desc.pmxops = &pcs_pinmux_ops; | |
1036 | pcs->desc.confops = &pcs_pinconf_ops; | |
1037 | pcs->desc.owner = THIS_MODULE; | |
1038 | ||
1039 | ret = pcs_allocate_pin_table(pcs); | |
1040 | if (ret < 0) | |
1041 | goto free; | |
1042 | ||
1043 | pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); | |
1044 | if (!pcs->pctl) { | |
1045 | dev_err(pcs->dev, "could not register single pinctrl driver\n"); | |
1046 | ret = -EINVAL; | |
1047 | goto free; | |
1048 | } | |
1049 | ||
2e8b2eab HZ |
1050 | ret = pcs_add_gpio_range(np, pcs); |
1051 | if (ret < 0) | |
1052 | goto free; | |
1053 | ||
8b8b091b TL |
1054 | dev_info(pcs->dev, "%i pins at pa %p size %u\n", |
1055 | pcs->desc.npins, pcs->base, pcs->size); | |
1056 | ||
1057 | return 0; | |
1058 | ||
1059 | free: | |
1060 | pcs_free_resources(pcs); | |
1061 | ||
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | static int __devexit pcs_remove(struct platform_device *pdev) | |
1066 | { | |
1067 | struct pcs_device *pcs = platform_get_drvdata(pdev); | |
1068 | ||
1069 | if (!pcs) | |
1070 | return 0; | |
1071 | ||
1072 | pcs_free_resources(pcs); | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static struct of_device_id pcs_of_match[] __devinitdata = { | |
1078 | { .compatible = DRIVER_NAME, }, | |
1079 | { }, | |
1080 | }; | |
1081 | MODULE_DEVICE_TABLE(of, pcs_of_match); | |
1082 | ||
1083 | static struct platform_driver pcs_driver = { | |
1084 | .probe = pcs_probe, | |
1085 | .remove = __devexit_p(pcs_remove), | |
1086 | .driver = { | |
1087 | .owner = THIS_MODULE, | |
1088 | .name = DRIVER_NAME, | |
1089 | .of_match_table = pcs_of_match, | |
1090 | }, | |
1091 | }; | |
1092 | ||
1093 | module_platform_driver(pcs_driver); | |
1094 | ||
1095 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
1096 | MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); | |
1097 | MODULE_LICENSE("GPL v2"); |