[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
{
	struct resource *res;
	int k;

	if (pdev->num_resources == 0) {
		pfc->num_windows = 0;
		return 0;
	}

	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
				   sizeof(*pfc->window), GFP_NOWAIT);
	if (!pfc->window)
		return -ENOMEM;

	pfc->num_windows = pdev->num_resources;

	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
		WARN_ON(resource_type(res) != IORESOURCE_MEM);
		pfc->window[k].phys = res->start;
		pfc->window[k].size = resource_size(res);
		pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
							   resource_size(res));
		if (!pfc->window[k].virt)
			return -ENOMEM;
	}

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
					 unsigned long address)
{
	struct sh_pfc_window *window;
	int k;

	/* scan through physical windows and convert address */
	for (k = 0; k < pfc->num_windows; k++) {
		window = pfc->window + k;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	/* no windows defined, register must be 1:1 mapped virt:phys */
	return (void __iomem *)address;
}

static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
{
	return (gpio < pfc->info->nr_pins) &&
	       (pfc->info->pins[gpio].enum_id != 0);
}

bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
{
	return (gpio >= pfc->info->nr_pins) &&
	       (gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) &&
	       (pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0);
}

static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
					 unsigned long reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
				 unsigned long reg_width, unsigned long data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	pr_debug("read_bit: addr = %lx, pos = %ld, "
		 "r_width = %ld\n", dr->reg, pos, dr->reg_width);

	return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
}

void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
		      unsigned long value)
{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
		 "r_width = %ld\n",
		 dr->reg, !!value, pos, dr->reg_width);

	if (value)
		set_bit(pos, &dr->reg_shadow);
	else
		clear_bit(pos, &dr->reg_shadow);

	sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     struct pinmux_cfg_reg *crp,
				     unsigned long in_pos,
				     void __iomem **mapped_regp,
				     unsigned long *maskp,
				     unsigned long *posp)
{
	int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
				  struct pinmux_cfg_reg *crp,
				  unsigned long field)
{
	void __iomem *mapped_reg;
	unsigned long mask, pos;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	pr_debug("read_reg: addr = %lx, field = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 crp->reg, field, crp->reg_width, crp->field_width);

	return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    struct pinmux_cfg_reg *crp,
				    unsigned long field, unsigned long value)
{
	void __iomem *mapped_reg;
	unsigned long mask, pos, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
	struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
	struct pinmux_data_reg *data_reg;
	int k, n;

	if (!sh_pfc_gpio_is_pin(pfc, gpio))
		return -1;

	k = 0;
	while (1) {
		data_reg = pfc->info->data_regs + k;

		if (!data_reg->reg_width)
			break;

		data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);

		for (n = 0; n < data_reg->reg_width; n++) {
			if (data_reg->enum_ids[n] == gpiop->enum_id) {
				gpiop->flags &= ~PINMUX_FLAG_DREG;
				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
				gpiop->flags &= ~PINMUX_FLAG_DBIT;
				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
				return 0;
			}
		}
		k++;
	}

	BUG();

	return -1;
}

static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
{
	struct pinmux_data_reg *drp;
	int k;

	for (k = 0; k < pfc->info->nr_pins; k++)
		sh_pfc_setup_data_reg(pfc, k);

	k = 0;
	while (1) {
		drp = pfc->info->data_regs + k;

		if (!drp->reg_width)
			break;

		drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
						      drp->reg_width);
		k++;
	}
}

int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
			struct pinmux_data_reg **drp, int *bitp)
{
	struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
	int k, n;

	if (!sh_pfc_gpio_is_pin(pfc, gpio))
		return -1;

	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	*drp = pfc->info->data_regs + k;
	*bitp = n;
	return 0;
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
				 struct pinmux_cfg_reg **crp, int *fieldp,
				 int *valuep, unsigned long **cntp)
{
	struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;

	k = 0;
	while (1) {
		config_reg = pfc->info->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;

		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					*cntp = &config_reg->cnt[m];
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -1;
}

int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
			pinmux_enum_t *enum_idp)
{
	pinmux_enum_t *data = pfc->info->gpio_data;
	pinmux_enum_t enum_id;
	int k;

	if (sh_pfc_gpio_is_pin(pfc, gpio)) {
		enum_id = pfc->info->pins[gpio].enum_id;
	} else if (sh_pfc_gpio_is_function(pfc, gpio)) {
		unsigned int offset = gpio - pfc->info->nr_pins;
		enum_id = pfc->info->func_gpios[offset].enum_id;
	} else {
		pr_err("non data/mark enum_id for gpio %d\n", gpio);
		return -1;
	}

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->gpio_data_size; k++) {
		if (data[k] == enum_id) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	return -1;
}

int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
		       int cfg_mode)
{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
	int in_range, pos, field, value;
	unsigned long *cntp;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	case PINMUX_TYPE_INPUT_PULLUP:
		range = &pfc->info->input_pu;
		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
		range = &pfc->info->input_pd;
		break;

	default:
		goto out_err;
	}

	pos = 0;
	enum_id = 0;
	field = 0;
	value = 0;
	while (1) {
		pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
		if (pos <= 0)
			goto out_err;

		if (!enum_id)
			break;

		/* first check if this is a function enum */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			/* not a function enum */
			if (range) {
				/*
				 * other range exists, so this pin is
				 * a regular GPIO pin that now is being
				 * bound to a specific direction.
				 *
				 * for this case we only allow function enums
				 * and the enums that match the other range.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			} else {
				/*
				 * no other range exists, so this pin
				 * must then be of the function type.
				 *
				 * allow function type pins to select
				 * any combination of function/in/out
				 * in their MARK lists.
				 */
				in_range = 1;
			}
		}

		if (!in_range)
			continue;

		if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
					  &field, &value, &cntp) != 0)
			goto out_err;

		switch (cfg_mode) {
		case GPIO_CFG_DRYRUN:
			if (!*cntp ||
			    (sh_pfc_read_config_reg(pfc, cr, field) != value))
				continue;
			break;

		case GPIO_CFG_REQ:
			sh_pfc_write_config_reg(pfc, cr, field, value);
			*cntp = *cntp + 1;
			break;

		case GPIO_CFG_FREE:
			*cntp = *cntp - 1;
			break;
		}
	}

	return 0;
 out_err:
	return -1;
}

static int sh_pfc_probe(struct platform_device *pdev)
{
	struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

	/*
	 * Ensure that the type encoding fits
	 */
	BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));

	info = pdev->id_entry->driver_data
	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_ioremap(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	pinctrl_provide_dummies();
	sh_pfc_setup_data_regs(pfc);

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		return ret;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		pr_notice("failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	pr_info("%s support registered\n", info->name);

	return 0;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
f9492fda	13	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
b72421d8	14
90efde22	15	#include <linux/bitops.h>
2967dab1	16	#include <linux/err.h>
90efde22	17	#include <linux/errno.h>
2967dab1	18	#include <linux/io.h>
b0e10211	19	#include <linux/ioport.h>
90efde22 LP	20	#include <linux/kernel.h>
90efde22 LP	21	#include <linux/module.h>
ca5481c6	22	#include <linux/pinctrl/machine.h>
c6193eac	23	#include <linux/platform_device.h>
90efde22	24	#include <linux/slab.h>
b0e10211	25
f9165132 LP	26	#include "core.h"
f9165132 LP	27
973931ae	28	static int sh_pfc_ioremap(struct sh_pfc pfc, struct platform_device pdev)
b0e10211 MD	29	{
	30	struct resource *res;
	31	int k;
	32
56dc04af	33	if (pdev->num_resources == 0) {
973931ae	34	pfc->num_windows = 0;
b0e10211	35	return 0;
973931ae	36	}
b0e10211	37
56dc04af	38	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
1724acfd	39	sizeof(*pfc->window), GFP_NOWAIT);
b3c185a7	40	if (!pfc->window)
1724acfd	41	return -ENOMEM;
b0e10211	42
56dc04af	43	pfc->num_windows = pdev->num_resources;
973931ae	44
56dc04af	45	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
b0e10211	46	WARN_ON(resource_type(res) != IORESOURCE_MEM);
b3c185a7 PM	47	pfc->window[k].phys = res->start;
b3c185a7 PM	48	pfc->window[k].size = resource_size(res);
c9fa88e2 LP	49	pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
	50	resource_size(res));
	51	if (!pfc->window[k].virt)
1724acfd	52	return -ENOMEM;
b0e10211 MD	53	}
	54
	55	return 0;
b0e10211 MD	56	}
b0e10211 MD	57
4aeacd5b LP	58	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc,
4aeacd5b LP	59	unsigned long address)
b0e10211	60	{
4aeacd5b	61	struct sh_pfc_window *window;
b0e10211 MD	62	int k;
	63
	64	/* scan through physical windows and convert address */
973931ae	65	for (k = 0; k < pfc->num_windows; k++) {
b3c185a7	66	window = pfc->window + k;
b0e10211 MD	67
	68	if (address < window->phys)
	69	continue;
	70
	71	if (address >= (window->phys + window->size))
	72	continue;
	73
	74	return window->virt + (address - window->phys);
	75	}
	76
	77	/* no windows defined, register must be 1:1 mapped virt:phys */
	78	return (void __iomem *)address;
	79	}
2967dab1	80
4aeacd5b	81	static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
2967dab1 MD	82	{
	83	if (enum_id < r->begin)
	84	return 0;
	85
	86	if (enum_id > r->end)
	87	return 0;
	88
	89	return 1;
	90	}
	91
caa5bac3 LP	92	static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
	93	{
	94	return (gpio < pfc->info->nr_pins) &&
a373ed0a	95	(pfc->info->pins[gpio].enum_id != 0);
caa5bac3 LP	96	}
caa5bac3 LP	97
2119f7c9	98	bool sh_pfc_gpio_is_function(struct sh_pfc *pfc, unsigned int gpio)
caa5bac3	99	{
a373ed0a LP	100	return (gpio >= pfc->info->nr_pins) &&
	101	(gpio < pfc->info->nr_pins + pfc->info->nr_func_gpios) &&
	102	(pfc->info->func_gpios[gpio - pfc->info->nr_pins].enum_id != 0);
caa5bac3 LP	103	}
caa5bac3 LP	104
4aeacd5b LP	105	static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
4aeacd5b LP	106	unsigned long reg_width)
3292094e MD	107	{
	108	switch (reg_width) {
	109	case 8:
b0e10211	110	return ioread8(mapped_reg);
3292094e	111	case 16:
b0e10211	112	return ioread16(mapped_reg);
3292094e	113	case 32:
b0e10211	114	return ioread32(mapped_reg);
3292094e MD	115	}
	116
	117	BUG();
	118	return 0;
	119	}
	120
4aeacd5b LP	121	static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
4aeacd5b LP	122	unsigned long reg_width, unsigned long data)
3292094e MD	123	{
	124	switch (reg_width) {
	125	case 8:
b0e10211	126	iowrite8(data, mapped_reg);
3292094e MD	127	return;
3292094e MD	128	case 16:
b0e10211	129	iowrite16(data, mapped_reg);
3292094e MD	130	return;
3292094e MD	131	case 32:
b0e10211	132	iowrite32(data, mapped_reg);
3292094e MD	133	return;
	134	}
	135
	136	BUG();
	137	}
	138
b3c185a7	139	int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
92554d97 MD	140	{
	141	unsigned long pos;
	142
	143	pos = dr->reg_width - (in_pos + 1);
	144
	145	pr_debug("read_bit: addr = %lx, pos = %ld, "
	146	"r_width = %ld\n", dr->reg, pos, dr->reg_width);
	147
4aeacd5b	148	return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
92554d97 MD	149	}
92554d97 MD	150
b3c185a7 PM	151	void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
b3c185a7 PM	152	unsigned long value)
3292094e MD	153	{
	154	unsigned long pos;
	155
	156	pos = dr->reg_width - (in_pos + 1);
	157
ca6f2d7f	158	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
fd2cb0ce PM	159	"r_width = %ld\n",
fd2cb0ce PM	160	dr->reg, !!value, pos, dr->reg_width);
3292094e MD	161
	162	if (value)
	163	set_bit(pos, &dr->reg_shadow);
	164	else
	165	clear_bit(pos, &dr->reg_shadow);
	166
4aeacd5b	167	sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
3292094e MD	168	}
3292094e MD	169
4aeacd5b LP	170	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
	171	struct pinmux_cfg_reg *crp,
	172	unsigned long in_pos,
	173	void __iomem **mapped_regp,
	174	unsigned long *maskp,
	175	unsigned long *posp)
2967dab1	176	{
f78a26f5 MD	177	int k;
f78a26f5 MD	178
4aeacd5b	179	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	180
f78a26f5 MD	181	if (crp->field_width) {
	182	*maskp = (1 << crp->field_width) - 1;
	183	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	184	} else {
	185	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	186	*posp = crp->reg_width;
	187	for (k = 0; k <= in_pos; k++)
	188	*posp -= crp->var_field_width[k];
	189	}
18925e11 MD	190	}
18925e11 MD	191
4aeacd5b LP	192	static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
	193	struct pinmux_cfg_reg *crp,
	194	unsigned long field)
18925e11 MD	195	{
	196	void __iomem *mapped_reg;
	197	unsigned long mask, pos;
	198
4aeacd5b	199	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	200
18925e11	201	pr_debug("read_reg: addr = %lx, field = %ld, "
fd2cb0ce	202	"r_width = %ld, f_width = %ld\n",
18925e11	203	crp->reg, field, crp->reg_width, crp->field_width);
2967dab1	204
4aeacd5b	205	return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
0fc64cc0 MD	206	}
0fc64cc0 MD	207
4aeacd5b LP	208	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
	209	struct pinmux_cfg_reg *crp,
	210	unsigned long field, unsigned long value)
0fc64cc0	211	{
18925e11	212	void __iomem *mapped_reg;
e499ada8	213	unsigned long mask, pos, data;
0fc64cc0	214
4aeacd5b	215	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	216
18925e11	217	pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
fd2cb0ce	218	"r_width = %ld, f_width = %ld\n",
18925e11	219	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	220
	221	mask = ~(mask << pos);
	222	value = value << pos;
2967dab1	223
4aeacd5b	224	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	225	data &= mask;
	226	data \|= value;
	227
19bb7fe3	228	if (pfc->info->unlock_reg)
4aeacd5b	229	sh_pfc_write_raw_reg(
19bb7fe3	230	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	231	~data);
e499ada8	232
4aeacd5b	233	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	234	}
2967dab1 MD	235
4aeacd5b	236	static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
2967dab1	237	{
a373ed0a	238	struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
2967dab1 MD	239	struct pinmux_data_reg *data_reg;
	240	int k, n;
	241
caa5bac3	242	if (!sh_pfc_gpio_is_pin(pfc, gpio))
2967dab1 MD	243	return -1;
	244
	245	k = 0;
	246	while (1) {
19bb7fe3	247	data_reg = pfc->info->data_regs + k;
2967dab1 MD	248
	249	if (!data_reg->reg_width)
	250	break;
	251
4aeacd5b	252	data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
b0e10211	253
2967dab1	254	for (n = 0; n < data_reg->reg_width; n++) {
18801be7 MD	255	if (data_reg->enum_ids[n] == gpiop->enum_id) {
	256	gpiop->flags &= ~PINMUX_FLAG_DREG;
	257	gpiop->flags \|= (k << PINMUX_FLAG_DREG_SHIFT);
	258	gpiop->flags &= ~PINMUX_FLAG_DBIT;
	259	gpiop->flags \|= (n << PINMUX_FLAG_DBIT_SHIFT);
2967dab1	260	return 0;
2967dab1 MD	261	}
	262	}
	263	k++;
	264	}
	265
18801be7 MD	266	BUG();
18801be7 MD	267
2967dab1 MD	268	return -1;
	269	}
	270
4aeacd5b	271	static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
3292094e MD	272	{
	273	struct pinmux_data_reg *drp;
	274	int k;
	275
caa5bac3	276	for (k = 0; k < pfc->info->nr_pins; k++)
4aeacd5b	277	sh_pfc_setup_data_reg(pfc, k);
3292094e MD	278
	279	k = 0;
	280	while (1) {
19bb7fe3	281	drp = pfc->info->data_regs + k;
3292094e MD	282
	283	if (!drp->reg_width)
	284	break;
	285
4aeacd5b LP	286	drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
4aeacd5b LP	287	drp->reg_width);
3292094e MD	288	k++;
	289	}
	290	}
	291
b3c185a7	292	int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
18801be7 MD	293	struct pinmux_data_reg *drp, int bitp)
18801be7 MD	294	{
a373ed0a	295	struct pinmux_pin *gpiop = &pfc->info->pins[gpio];
18801be7 MD	296	int k, n;
18801be7 MD	297
caa5bac3	298	if (!sh_pfc_gpio_is_pin(pfc, gpio))
18801be7 MD	299	return -1;
	300
	301	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	302	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
19bb7fe3	303	*drp = pfc->info->data_regs + k;
18801be7 MD	304	*bitp = n;
	305	return 0;
	306	}
	307
4aeacd5b LP	308	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
	309	struct pinmux_cfg_reg *crp, int fieldp,
	310	int valuep, unsigned long *cntp)
2967dab1 MD	311	{
2967dab1 MD	312	struct pinmux_cfg_reg *config_reg;
f78a26f5 MD	313	unsigned long r_width, f_width, curr_width, ncomb;
f78a26f5 MD	314	int k, m, n, pos, bit_pos;
2967dab1 MD	315
	316	k = 0;
	317	while (1) {
19bb7fe3	318	config_reg = pfc->info->cfg_regs + k;
2967dab1 MD	319
	320	r_width = config_reg->reg_width;
	321	f_width = config_reg->field_width;
	322
	323	if (!r_width)
	324	break;
f78a26f5 MD	325
	326	pos = 0;
	327	m = 0;
	328	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
	329	if (f_width)
	330	curr_width = f_width;
	331	else
	332	curr_width = config_reg->var_field_width[m];
	333
	334	ncomb = 1 << curr_width;
	335	for (n = 0; n < ncomb; n++) {
	336	if (config_reg->enum_ids[pos + n] == enum_id) {
	337	*crp = config_reg;
	338	*fieldp = m;
	339	*valuep = n;
	340	*cntp = &config_reg->cnt[m];
	341	return 0;
	342	}
2967dab1	343	}
f78a26f5 MD	344	pos += ncomb;
f78a26f5 MD	345	m++;
2967dab1 MD	346	}
	347	k++;
	348	}
	349
	350	return -1;
	351	}
	352
b3c185a7 PM	353	int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
b3c185a7 PM	354	pinmux_enum_t *enum_idp)
2967dab1	355	{
19bb7fe3	356	pinmux_enum_t *data = pfc->info->gpio_data;
a373ed0a	357	pinmux_enum_t enum_id;
2967dab1 MD	358	int k;
2967dab1 MD	359
a373ed0a LP	360	if (sh_pfc_gpio_is_pin(pfc, gpio)) {
	361	enum_id = pfc->info->pins[gpio].enum_id;
	362	} else if (sh_pfc_gpio_is_function(pfc, gpio)) {
	363	unsigned int offset = gpio - pfc->info->nr_pins;
	364	enum_id = pfc->info->func_gpios[offset].enum_id;
	365	} else {
caa5bac3 LP	366	pr_err("non data/mark enum_id for gpio %d\n", gpio);
caa5bac3 LP	367	return -1;
2967dab1 MD	368	}
	369
	370	if (pos) {
	371	*enum_idp = data[pos + 1];
	372	return pos + 1;
	373	}
	374
19bb7fe3	375	for (k = 0; k < pfc->info->gpio_data_size; k++) {
2967dab1 MD	376	if (data[k] == enum_id) {
	377	*enum_idp = data[k + 1];
	378	return k + 1;
	379	}
	380	}
	381
	382	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	383	return -1;
	384	}
	385
b3c185a7 PM	386	int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
b3c185a7 PM	387	int cfg_mode)
2967dab1 MD	388	{
	389	struct pinmux_cfg_reg *cr = NULL;
	390	pinmux_enum_t enum_id;
	391	struct pinmux_range *range;
ad4a07ff	392	int in_range, pos, field, value;
2967dab1 MD	393	unsigned long *cntp;
	394
	395	switch (pinmux_type) {
	396
	397	case PINMUX_TYPE_FUNCTION:
	398	range = NULL;
	399	break;
	400
	401	case PINMUX_TYPE_OUTPUT:
19bb7fe3	402	range = &pfc->info->output;
2967dab1 MD	403	break;
	404
	405	case PINMUX_TYPE_INPUT:
19bb7fe3	406	range = &pfc->info->input;
2967dab1 MD	407	break;
	408
	409	case PINMUX_TYPE_INPUT_PULLUP:
19bb7fe3	410	range = &pfc->info->input_pu;
2967dab1 MD	411	break;
	412
	413	case PINMUX_TYPE_INPUT_PULLDOWN:
19bb7fe3	414	range = &pfc->info->input_pd;
2967dab1 MD	415	break;
	416
	417	default:
	418	goto out_err;
	419	}
	420
	421	pos = 0;
	422	enum_id = 0;
ad4a07ff MD	423	field = 0;
ad4a07ff MD	424	value = 0;
2967dab1	425	while (1) {
b3c185a7	426	pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
2967dab1 MD	427	if (pos <= 0)
	428	goto out_err;
	429
	430	if (!enum_id)
	431	break;
	432
50dd3145	433	/* first check if this is a function enum */
19bb7fe3	434	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145 MD	435	if (!in_range) {
	436	/* not a function enum */
	437	if (range) {
	438	/*
	439	* other range exists, so this pin is
	440	* a regular GPIO pin that now is being
	441	* bound to a specific direction.
	442	*
	443	* for this case we only allow function enums
	444	* and the enums that match the other range.
	445	*/
4aeacd5b	446	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	447
	448	/*
	449	* special case pass through for fixed
	450	* input-only or output-only pins without
	451	* function enum register association.
	452	*/
	453	if (in_range && enum_id == range->force)
	454	continue;
	455	} else {
	456	/*
	457	* no other range exists, so this pin
	458	* must then be of the function type.
	459	*
	460	* allow function type pins to select
	461	* any combination of function/in/out
	462	* in their MARK lists.
	463	*/
	464	in_range = 1;
	465	}
42eed42b MD	466	}
42eed42b MD	467
2967dab1 MD	468	if (!in_range)
	469	continue;
	470
4aeacd5b LP	471	if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
4aeacd5b LP	472	&field, &value, &cntp) != 0)
2967dab1 MD	473	goto out_err;
	474
	475	switch (cfg_mode) {
	476	case GPIO_CFG_DRYRUN:
18925e11	477	if (!*cntp \|\|
4aeacd5b	478	(sh_pfc_read_config_reg(pfc, cr, field) != value))
2967dab1 MD	479	continue;
	480	break;
	481
	482	case GPIO_CFG_REQ:
4aeacd5b	483	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	484	cntp = cntp + 1;
	485	break;
	486
	487	case GPIO_CFG_FREE:
	488	cntp = cntp - 1;
	489	break;
	490	}
	491	}
	492
	493	return 0;
	494	out_err:
	495	return -1;
	496	}
	497
c6193eac	498	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	499	{
19bb7fe3	500	struct sh_pfc_soc_info *info;
c6193eac	501	struct sh_pfc *pfc;
0fc64cc0	502	int ret;
2967dab1	503
06d5631f PM	504	/*
	505	* Ensure that the type encoding fits
	506	*/
	507	BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
	508
19bb7fe3 LP	509	info = pdev->id_entry->driver_data
	510	? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
	511	if (info == NULL)
c6193eac	512	return -ENODEV;
2967dab1	513
8c43fcc7	514	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	515	if (pfc == NULL)
c6193eac LP	516	return -ENOMEM;
d4e62d00	517
19bb7fe3	518	pfc->info = info;
c6193eac LP	519	pfc->dev = &pdev->dev;
c6193eac LP	520
973931ae	521	ret = sh_pfc_ioremap(pfc, pdev);
c6193eac	522	if (unlikely(ret < 0))
b0e10211 MD	523	return ret;
b0e10211 MD	524
c6193eac	525	spin_lock_init(&pfc->lock);
69edbba0	526
ca5481c6	527	pinctrl_provide_dummies();
4aeacd5b	528	sh_pfc_setup_data_regs(pfc);
b0e10211	529
ca5481c6 PM	530	/*
	531	* Initialize pinctrl bindings first
	532	*/
c6193eac	533	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	534	if (unlikely(ret != 0))
c9fa88e2	535	return ret;
ca5481c6	536
6f6a4a68	537	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	538	/*
	539	* Then the GPIO chip
	540	*/
c6193eac	541	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	542	if (unlikely(ret != 0)) {
ca5481c6 PM	543	/*
	544	* If the GPIO chip fails to come up we still leave the
	545	* PFC state as it is, given that there are already
	546	* extant users of it that have succeeded by this point.
	547	*/
6f6a4a68	548	pr_notice("failed to init GPIO chip, ignoring...\n");
b3c185a7	549	}
6f6a4a68	550	#endif
b72421d8	551
c6193eac LP	552	platform_set_drvdata(pdev, pfc);
c6193eac LP	553
19bb7fe3	554	pr_info("%s support registered\n", info->name);
ca5481c6	555
b3c185a7	556	return 0;
b72421d8	557	}
6f6a4a68	558
c6193eac LP	559	static int sh_pfc_remove(struct platform_device *pdev)
	560	{
	561	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	562
	563	#ifdef CONFIG_GPIO_SH_PFC
	564	sh_pfc_unregister_gpiochip(pfc);
	565	#endif
	566	sh_pfc_unregister_pinctrl(pfc);
	567
c6193eac LP	568	platform_set_drvdata(pdev, NULL);
	569
	570	return 0;
	571	}
	572
	573	static const struct platform_device_id sh_pfc_id_table[] = {
d5b1521a LP	574	#ifdef CONFIG_PINCTRL_PFC_R8A7740
d5b1521a LP	575	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
881023d2 LP	576	#endif
	577	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	578	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
6e5469a6	579	#endif
ccda552e LP	580	#ifdef CONFIG_PINCTRL_PFC_SH7203
	581	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	582	#endif
a8d42fc4 LP	583	#ifdef CONFIG_PINCTRL_PFC_SH7264
	584	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	585	#endif
f5e811f2 LP	586	#ifdef CONFIG_PINCTRL_PFC_SH7269
	587	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	588	#endif
6e5469a6 LP	589	#ifdef CONFIG_PINCTRL_PFC_SH7372
6e5469a6 LP	590	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
5d5166dc LP	591	#endif
	592	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	593	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
74cad605 LP	594	#endif
	595	#ifdef CONFIG_PINCTRL_PFC_SH7720
	596	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	597	#endif
	598	#ifdef CONFIG_PINCTRL_PFC_SH7722
	599	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	600	#endif
	601	#ifdef CONFIG_PINCTRL_PFC_SH7723
	602	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	603	#endif
	604	#ifdef CONFIG_PINCTRL_PFC_SH7724
	605	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	606	#endif
	607	#ifdef CONFIG_PINCTRL_PFC_SH7734
	608	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	609	#endif
	610	#ifdef CONFIG_PINCTRL_PFC_SH7757
	611	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	612	#endif
	613	#ifdef CONFIG_PINCTRL_PFC_SH7785
	614	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	615	#endif
	616	#ifdef CONFIG_PINCTRL_PFC_SH7786
	617	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	618	#endif
	619	#ifdef CONFIG_PINCTRL_PFC_SHX3
	620	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	621	#endif
c6193eac LP	622	{ "sh-pfc", 0 },
	623	{ },
	624	};
	625	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	626
	627	static struct platform_driver sh_pfc_driver = {
	628	.probe = sh_pfc_probe,
	629	.remove = sh_pfc_remove,
	630	.id_table = sh_pfc_id_table,
	631	.driver = {
	632	.name = DRV_NAME,
	633	.owner = THIS_MODULE,
	634	},
	635	};
	636
40ee6fce LP	637	static int __init sh_pfc_init(void)
	638	{
	639	return platform_driver_register(&sh_pfc_driver);
c6193eac	640	}
40ee6fce	641	postcore_initcall(sh_pfc_init);
c6193eac LP	642
	643	static void __exit sh_pfc_exit(void)
	644	{
	645	platform_driver_unregister(&sh_pfc_driver);
	646	}
	647	module_exit(sh_pfc_exit);
	648
6f6a4a68 LP	649	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	650	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	651	MODULE_LICENSE("GPL v2");