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[SCSI] dh_rdac: Associate HBA and storage in rdac_controller to support partitions...
[deliverable/linux.git] / drivers / scsi / bnx2fc / bnx2fc_hwi.c
CommitLineData
853e2bd2
BG		 1/* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
2 * This file contains the code that low level functions that interact
3 * with 57712 FCoE firmware.
4 *
5 * Copyright (c) 2008 - 2010 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
12 */
13
14#include "bnx2fc.h"
15
16DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
17
18static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
19 struct fcoe_kcqe *new_cqe_kcqe);
20static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
21 struct fcoe_kcqe *ofld_kcqe);
22static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
23 struct fcoe_kcqe *ofld_kcqe);
24static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
25static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
aea71a02 26 struct fcoe_kcqe *destroy_kcqe);
853e2bd2
BG		 27
28int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
29{
30 struct fcoe_kwqe_stat stat_req;
31 struct kwqe *kwqe_arr[2];
32 int num_kwqes = 1;
33 int rc = 0;
34
35 memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
36 stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
37 stat_req.hdr.flags =
38 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
39
40 stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
41 stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
42
43 kwqe_arr[0] = (struct kwqe *) &stat_req;
44
45 if (hba->cnic && hba->cnic->submit_kwqes)
46 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
47
48 return rc;
49}
50
51/**
52 * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
53 *
54 * @hba: adapter structure pointer
55 *
56 * Send down FCoE firmware init KWQEs which initiates the initial handshake
57 * with the f/w.
58 *
59 */
60int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
61{
62 struct fcoe_kwqe_init1 fcoe_init1;
63 struct fcoe_kwqe_init2 fcoe_init2;
64 struct fcoe_kwqe_init3 fcoe_init3;
65 struct kwqe *kwqe_arr[3];
66 int num_kwqes = 3;
67 int rc = 0;
68
69 if (!hba->cnic) {
aea71a02 70 printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
853e2bd2
BG		 71 return -ENODEV;
72 }
73
74 /* fill init1 KWQE */
75 memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
76 fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
77 fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
78 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
79
80 fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
81 fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
82 fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
83 fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
84 fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
85 fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
86 fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
87 fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
88 fcoe_init1.task_list_pbl_addr_hi =
89 (u32) ((u64) hba->task_ctx_bd_dma >> 32);
1294bfe6 90 fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
853e2bd2
BG		 91
92 fcoe_init1.flags = (PAGE_SHIFT <<
93 FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
94
95 fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
96
97 /* fill init2 KWQE */
98 memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
99 fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
100 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
101 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
102
619c5cb6
VZ		 103 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
104 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
105
aea71a02 106
853e2bd2
BG		 107 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
108 fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
109 ((u64) hba->hash_tbl_pbl_dma >> 32);
110
111 fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
112 fcoe_init2.t2_hash_tbl_addr_hi = (u32)
113 ((u64) hba->t2_hash_tbl_dma >> 32);
114
115 fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
116 fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
117 ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
118
119 fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
120
121 /* fill init3 KWQE */
122 memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
123 fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
124 fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
125 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
126 fcoe_init3.error_bit_map_lo = 0xffffffff;
127 fcoe_init3.error_bit_map_hi = 0xffffffff;
128
619c5cb6 129 fcoe_init3.perf_config = 1;
853e2bd2
BG		 130
131 kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
132 kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
133 kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
134
135 if (hba->cnic && hba->cnic->submit_kwqes)
136 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
137
138 return rc;
139}
140int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
141{
142 struct fcoe_kwqe_destroy fcoe_destroy;
143 struct kwqe *kwqe_arr[2];
144 int num_kwqes = 1;
145 int rc = -1;
146
147 /* fill destroy KWQE */
148 memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
149 fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
150 fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
151 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
152 kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
153
154 if (hba->cnic && hba->cnic->submit_kwqes)
155 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
156 return rc;
157}
158
159/**
160 * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
161 *
162 * @port: port structure pointer
163 * @tgt: bnx2fc_rport structure pointer
164 */
165int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
166 struct bnx2fc_rport *tgt)
167{
168 struct fc_lport *lport = port->lport;
aea71a02
BPG		 169 struct bnx2fc_interface *interface = port->priv;
170 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 171 struct kwqe *kwqe_arr[4];
172 struct fcoe_kwqe_conn_offload1 ofld_req1;
173 struct fcoe_kwqe_conn_offload2 ofld_req2;
174 struct fcoe_kwqe_conn_offload3 ofld_req3;
175 struct fcoe_kwqe_conn_offload4 ofld_req4;
176 struct fc_rport_priv *rdata = tgt->rdata;
177 struct fc_rport *rport = tgt->rport;
178 int num_kwqes = 4;
179 u32 port_id;
180 int rc = 0;
181 u16 conn_id;
182
183 /* Initialize offload request 1 structure */
184 memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
185
186 ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
187 ofld_req1.hdr.flags =
188 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
189
190
191 conn_id = (u16)tgt->fcoe_conn_id;
192 ofld_req1.fcoe_conn_id = conn_id;
193
194
195 ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
196 ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
197
198 ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
199 ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
200
201 ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
202 ofld_req1.rq_first_pbe_addr_hi =
203 (u32)((u64) tgt->rq_dma >> 32);
204
205 ofld_req1.rq_prod = 0x8000;
206
207 /* Initialize offload request 2 structure */
208 memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
209
210 ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
211 ofld_req2.hdr.flags =
212 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
213
214 ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
215
216 ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
217 ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
218
219 ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
220 ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
221
222 ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
223 ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
224
225 /* Initialize offload request 3 structure */
226 memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
227
228 ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
229 ofld_req3.hdr.flags =
230 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
231
aea71a02 232 ofld_req3.vlan_tag = interface->vlan_id <<
853e2bd2
BG		 233 FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
234 ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
235
236 port_id = fc_host_port_id(lport->host);
237 if (port_id == 0) {
238 BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
239 return -EINVAL;
240 }
241
242 /*
243 * Store s_id of the initiator for further reference. This will
244 * be used during disable/destroy during linkdown processing as
245 * when the lport is reset, the port_id also is reset to 0
246 */
247 tgt->sid = port_id;
248 ofld_req3.s_id[0] = (port_id & 0x000000FF);
249 ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
250 ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
251
252 port_id = rport->port_id;
253 ofld_req3.d_id[0] = (port_id & 0x000000FF);
254 ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
255 ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
256
257 ofld_req3.tx_total_conc_seqs = rdata->max_seq;
258
259 ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
260 ofld_req3.rx_max_fc_pay_len = lport->mfs;
261
262 ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
263 ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
264 ofld_req3.rx_open_seqs_exch_c3 = 1;
265
266 ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
267 ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
268
269 /* set mul_n_port_ids supported flag to 0, until it is supported */
270 ofld_req3.flags = 0;
271 /*
272 ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
273 FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
274 */
275 /* Info from PLOGI response */
276 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
277 FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
278
279 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
280 FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
281
b252f4c7
BPG		 282 /*
283 * Info from PRLI response, this info is used for sequence level error
284 * recovery support
285 */
286 if (tgt->dev_type == TYPE_TAPE) {
287 ofld_req3.flags |= 1 <<
288 FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
289 ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
290 ? 1 : 0) <<
291 FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
292 }
293
853e2bd2 294 /* vlan flag */
aea71a02 295 ofld_req3.flags |= (interface->vlan_enabled <<
853e2bd2
BG		 296 FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
297
298 /* C2_VALID and ACK flags are not set as they are not suppported */
299
300
301 /* Initialize offload request 4 structure */
302 memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
303 ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
304 ofld_req4.hdr.flags =
305 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
306
307 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
308
309
619c5cb6 310 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
853e2bd2 311 /* local mac */
619c5cb6
VZ		 312 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
313 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
314 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
315 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
316 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
aea71a02
BPG		 317 ofld_req4.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
318 /* fcf mac */
319 ofld_req4.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
320 ofld_req4.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
321 ofld_req4.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
322 ofld_req4.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
323 ofld_req4.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
853e2bd2
BG		 324
325 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
326 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
327
328 ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
329 ofld_req4.confq_pbl_base_addr_hi =
330 (u32)((u64) tgt->confq_pbl_dma >> 32);
331
332 kwqe_arr[0] = (struct kwqe *) &ofld_req1;
333 kwqe_arr[1] = (struct kwqe *) &ofld_req2;
334 kwqe_arr[2] = (struct kwqe *) &ofld_req3;
335 kwqe_arr[3] = (struct kwqe *) &ofld_req4;
336
337 if (hba->cnic && hba->cnic->submit_kwqes)
338 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
339
340 return rc;
341}
342
343/**
344 * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
345 *
346 * @port: port structure pointer
347 * @tgt: bnx2fc_rport structure pointer
348 */
349static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
350 struct bnx2fc_rport *tgt)
351{
352 struct kwqe *kwqe_arr[2];
aea71a02
BPG		 353 struct bnx2fc_interface *interface = port->priv;
354 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 355 struct fcoe_kwqe_conn_enable_disable enbl_req;
356 struct fc_lport *lport = port->lport;
357 struct fc_rport *rport = tgt->rport;
358 int num_kwqes = 1;
359 int rc = 0;
360 u32 port_id;
361
362 memset(&enbl_req, 0x00,
363 sizeof(struct fcoe_kwqe_conn_enable_disable));
364 enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
365 enbl_req.hdr.flags =
366 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
367
619c5cb6 368 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
853e2bd2 369 /* local mac */
619c5cb6
VZ		 370 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
371 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
372 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
373 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
374 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
375 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
376
aea71a02
BPG		 377 enbl_req.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
378 enbl_req.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
379 enbl_req.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
380 enbl_req.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
381 enbl_req.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
382 enbl_req.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
853e2bd2
BG		 383
384 port_id = fc_host_port_id(lport->host);
385 if (port_id != tgt->sid) {
386 printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
387 "sid = 0x%x\n", port_id, tgt->sid);
388 port_id = tgt->sid;
389 }
390 enbl_req.s_id[0] = (port_id & 0x000000FF);
391 enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
392 enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
393
394 port_id = rport->port_id;
395 enbl_req.d_id[0] = (port_id & 0x000000FF);
396 enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
397 enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
aea71a02 398 enbl_req.vlan_tag = interface->vlan_id <<
853e2bd2
BG		 399 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
400 enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
aea71a02 401 enbl_req.vlan_flag = interface->vlan_enabled;
853e2bd2
BG		 402 enbl_req.context_id = tgt->context_id;
403 enbl_req.conn_id = tgt->fcoe_conn_id;
404
405 kwqe_arr[0] = (struct kwqe *) &enbl_req;
406
407 if (hba->cnic && hba->cnic->submit_kwqes)
408 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
409 return rc;
410}
411
412/**
413 * bnx2fc_send_session_disable_req - initiates FCoE Session disable
414 *
415 * @port: port structure pointer
416 * @tgt: bnx2fc_rport structure pointer
417 */
418int bnx2fc_send_session_disable_req(struct fcoe_port *port,
419 struct bnx2fc_rport *tgt)
420{
aea71a02
BPG		 421 struct bnx2fc_interface *interface = port->priv;
422 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 423 struct fcoe_kwqe_conn_enable_disable disable_req;
424 struct kwqe *kwqe_arr[2];
425 struct fc_rport *rport = tgt->rport;
426 int num_kwqes = 1;
427 int rc = 0;
428 u32 port_id;
429
430 memset(&disable_req, 0x00,
431 sizeof(struct fcoe_kwqe_conn_enable_disable));
432 disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
433 disable_req.hdr.flags =
434 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
435
619c5cb6
VZ		 436 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
437 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
438 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
439 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
440 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
441 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
853e2bd2 442
aea71a02
BPG		 443 disable_req.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
444 disable_req.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
445 disable_req.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
446 disable_req.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
447 disable_req.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
448 disable_req.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
853e2bd2
BG		 449
450 port_id = tgt->sid;
451 disable_req.s_id[0] = (port_id & 0x000000FF);
452 disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
453 disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
454
455
456 port_id = rport->port_id;
457 disable_req.d_id[0] = (port_id & 0x000000FF);
458 disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
459 disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
460 disable_req.context_id = tgt->context_id;
461 disable_req.conn_id = tgt->fcoe_conn_id;
aea71a02 462 disable_req.vlan_tag = interface->vlan_id <<
853e2bd2
BG		 463 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
464 disable_req.vlan_tag |=
465 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
aea71a02 466 disable_req.vlan_flag = interface->vlan_enabled;
853e2bd2
BG		 467
468 kwqe_arr[0] = (struct kwqe *) &disable_req;
469
470 if (hba->cnic && hba->cnic->submit_kwqes)
471 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
472
473 return rc;
474}
475
476/**
477 * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
478 *
479 * @port: port structure pointer
480 * @tgt: bnx2fc_rport structure pointer
481 */
482int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
483 struct bnx2fc_rport *tgt)
484{
485 struct fcoe_kwqe_conn_destroy destroy_req;
486 struct kwqe *kwqe_arr[2];
487 int num_kwqes = 1;
488 int rc = 0;
489
490 memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
491 destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
492 destroy_req.hdr.flags =
493 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
494
495 destroy_req.context_id = tgt->context_id;
496 destroy_req.conn_id = tgt->fcoe_conn_id;
497
498 kwqe_arr[0] = (struct kwqe *) &destroy_req;
499
500 if (hba->cnic && hba->cnic->submit_kwqes)
501 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
502
503 return rc;
504}
505
d36b3279
BPG		 506static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
507{
508 struct bnx2fc_lport *blport;
509
510 spin_lock_bh(&hba->hba_lock);
511 list_for_each_entry(blport, &hba->vports, list) {
512 if (blport->lport == lport) {
513 spin_unlock_bh(&hba->hba_lock);
514 return true;
515 }
516 }
517 spin_unlock_bh(&hba->hba_lock);
518 return false;
519
520}
521
522
853e2bd2
BG		 523static void bnx2fc_unsol_els_work(struct work_struct *work)
524{
525 struct bnx2fc_unsol_els *unsol_els;
526 struct fc_lport *lport;
d36b3279 527 struct bnx2fc_hba *hba;
853e2bd2
BG		 528 struct fc_frame *fp;
529
530 unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
531 lport = unsol_els->lport;
532 fp = unsol_els->fp;
d36b3279
BPG		 533 hba = unsol_els->hba;
534 if (is_valid_lport(hba, lport))
535 fc_exch_recv(lport, fp);
853e2bd2
BG		 536 kfree(unsol_els);
537}
538
539void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
540 unsigned char *buf,
541 u32 frame_len, u16 l2_oxid)
542{
543 struct fcoe_port *port = tgt->port;
544 struct fc_lport *lport = port->lport;
aea71a02 545 struct bnx2fc_interface *interface = port->priv;
853e2bd2
BG		 546 struct bnx2fc_unsol_els *unsol_els;
547 struct fc_frame_header *fh;
548 struct fc_frame *fp;
549 struct sk_buff *skb;
550 u32 payload_len;
551 u32 crc;
552 u8 op;
553
554
555 unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
556 if (!unsol_els) {
557 BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
558 return;
559 }
560
561 BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
562 l2_oxid, frame_len);
563
564 payload_len = frame_len - sizeof(struct fc_frame_header);
565
566 fp = fc_frame_alloc(lport, payload_len);
567 if (!fp) {
568 printk(KERN_ERR PFX "fc_frame_alloc failure\n");
5c2dce26 569 kfree(unsol_els);
853e2bd2
BG		 570 return;
571 }
572
573 fh = (struct fc_frame_header *) fc_frame_header_get(fp);
574 /* Copy FC Frame header and payload into the frame */
575 memcpy(fh, buf, frame_len);
576
577 if (l2_oxid != FC_XID_UNKNOWN)
578 fh->fh_ox_id = htons(l2_oxid);
579
580 skb = fp_skb(fp);
581
582 if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
583 (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
584
585 if (fh->fh_type == FC_TYPE_ELS) {
586 op = fc_frame_payload_op(fp);
587 if ((op == ELS_TEST) || (op == ELS_ESTC) ||
588 (op == ELS_FAN) || (op == ELS_CSU)) {
589 /*
590 * No need to reply for these
591 * ELS requests
592 */
593 printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
594 kfree_skb(skb);
5c2dce26 595 kfree(unsol_els);
853e2bd2
BG		 596 return;
597 }
598 }
599 crc = fcoe_fc_crc(fp);
600 fc_frame_init(fp);
601 fr_dev(fp) = lport;
602 fr_sof(fp) = FC_SOF_I3;
603 fr_eof(fp) = FC_EOF_T;
604 fr_crc(fp) = cpu_to_le32(~crc);
605 unsol_els->lport = lport;
aea71a02 606 unsol_els->hba = interface->hba;
853e2bd2
BG		 607 unsol_els->fp = fp;
608 INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
609 queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
610 } else {
611 BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
612 kfree_skb(skb);
5c2dce26 613 kfree(unsol_els);
853e2bd2
BG		 614 }
615}
616
617static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
618{
619 u8 num_rq;
620 struct fcoe_err_report_entry *err_entry;
621 unsigned char *rq_data;
622 unsigned char *buf = NULL, *buf1;
623 int i;
624 u16 xid;
625 u32 frame_len, len;
626 struct bnx2fc_cmd *io_req = NULL;
627 struct fcoe_task_ctx_entry *task, *task_page;
aea71a02
BPG		 628 struct bnx2fc_interface *interface = tgt->port->priv;
629 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 630 int task_idx, index;
631 int rc = 0;
632
633
634 BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
635 switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
636 case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
637 frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
638 FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
639
640 num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
641
68695973 642 spin_lock_bh(&tgt->tgt_lock);
853e2bd2 643 rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
68695973
NS		 644 spin_unlock_bh(&tgt->tgt_lock);
645
853e2bd2
BG		 646 if (rq_data) {
647 buf = rq_data;
648 } else {
649 buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
650 GFP_ATOMIC);
651
652 if (!buf1) {
653 BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
654 break;
655 }
656
657 for (i = 0; i < num_rq; i++) {
68695973 658 spin_lock_bh(&tgt->tgt_lock);
853e2bd2
BG		 659 rq_data = (unsigned char *)
660 bnx2fc_get_next_rqe(tgt, 1);
68695973 661 spin_unlock_bh(&tgt->tgt_lock);
853e2bd2
BG		 662 len = BNX2FC_RQ_BUF_SZ;
663 memcpy(buf1, rq_data, len);
664 buf1 += len;
665 }
666 }
667 bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
668 FC_XID_UNKNOWN);
669
670 if (buf != rq_data)
671 kfree(buf);
68695973 672 spin_lock_bh(&tgt->tgt_lock);
853e2bd2 673 bnx2fc_return_rqe(tgt, num_rq);
68695973 674 spin_unlock_bh(&tgt->tgt_lock);
853e2bd2
BG		 675 break;
676
677 case FCOE_ERROR_DETECTION_CQE_TYPE:
678 /*
68695973
NS		 679 * In case of error reporting CQE a single RQ entry
680 * is consumed.
853e2bd2
BG		 681 */
682 spin_lock_bh(&tgt->tgt_lock);
683 num_rq = 1;
684 err_entry = (struct fcoe_err_report_entry *)
685 bnx2fc_get_next_rqe(tgt, 1);
686 xid = err_entry->fc_hdr.ox_id;
687 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
688 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
619c5cb6
VZ		 689 err_entry->data.err_warn_bitmap_hi,
690 err_entry->data.err_warn_bitmap_lo);
853e2bd2 691 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
619c5cb6 692 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
853e2bd2
BG		 693
694 bnx2fc_return_rqe(tgt, 1);
695
696 if (xid > BNX2FC_MAX_XID) {
697 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
698 xid);
699 spin_unlock_bh(&tgt->tgt_lock);
700 break;
701 }
702
703 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
704 index = xid % BNX2FC_TASKS_PER_PAGE;
705 task_page = (struct fcoe_task_ctx_entry *)
aea71a02 706 hba->task_ctx[task_idx];
853e2bd2
BG		 707 task = &(task_page[index]);
708
709 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
710 if (!io_req) {
711 spin_unlock_bh(&tgt->tgt_lock);
712 break;
713 }
714
715 if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
716 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
717 spin_unlock_bh(&tgt->tgt_lock);
718 break;
719 }
720
721 if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
722 &io_req->req_flags)) {
723 BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
724 "progress.. ignore unsol err\n");
725 spin_unlock_bh(&tgt->tgt_lock);
726 break;
727 }
728
729 /*
730 * If ABTS is already in progress, and FW error is
731 * received after that, do not cancel the timeout_work
732 * and let the error recovery continue by explicitly
733 * logging out the target, when the ABTS eventually
734 * times out.
735 */
736 if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
737 &io_req->req_flags)) {
738 /*
739 * Cancel the timeout_work, as we received IO
740 * completion with FW error.
741 */
742 if (cancel_delayed_work(&io_req->timeout_work))
743 kref_put(&io_req->refcount,
744 bnx2fc_cmd_release); /* timer hold */
745
746 rc = bnx2fc_initiate_abts(io_req);
747 if (rc != SUCCESS) {
748 BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
749 "failed. issue cleanup\n");
750 rc = bnx2fc_initiate_cleanup(io_req);
751 BUG_ON(rc);
752 }
753 } else
754 printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
755 "in ABTS processing\n", xid);
756 spin_unlock_bh(&tgt->tgt_lock);
757 break;
758
759 case FCOE_WARNING_DETECTION_CQE_TYPE:
760 /*
761 *In case of warning reporting CQE a single RQ entry
762 * is consumes.
763 */
68695973 764 spin_lock_bh(&tgt->tgt_lock);
853e2bd2
BG		 765 num_rq = 1;
766 err_entry = (struct fcoe_err_report_entry *)
767 bnx2fc_get_next_rqe(tgt, 1);
768 xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
769 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
770 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
619c5cb6
VZ		 771 err_entry->data.err_warn_bitmap_hi,
772 err_entry->data.err_warn_bitmap_lo);
853e2bd2 773 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
619c5cb6 774 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
853e2bd2
BG		 775
776 bnx2fc_return_rqe(tgt, 1);
68695973 777 spin_unlock_bh(&tgt->tgt_lock);
853e2bd2
BG		 778 break;
779
780 default:
781 printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
782 break;
783 }
784}
785
786void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
787{
788 struct fcoe_task_ctx_entry *task;
789 struct fcoe_task_ctx_entry *task_page;
790 struct fcoe_port *port = tgt->port;
aea71a02
BPG		 791 struct bnx2fc_interface *interface = port->priv;
792 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 793 struct bnx2fc_cmd *io_req;
794 int task_idx, index;
795 u16 xid;
796 u8 cmd_type;
797 u8 rx_state = 0;
798 u8 num_rq;
799
800 spin_lock_bh(&tgt->tgt_lock);
801 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
802 if (xid >= BNX2FC_MAX_TASKS) {
b2a554ff 803 printk(KERN_ERR PFX "ERROR:xid out of range\n");
853e2bd2
BG		 804 spin_unlock_bh(&tgt->tgt_lock);
805 return;
806 }
807 task_idx = xid / BNX2FC_TASKS_PER_PAGE;
808 index = xid % BNX2FC_TASKS_PER_PAGE;
809 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
810 task = &(task_page[index]);
811
619c5cb6
VZ		 812 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
813 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
814 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
853e2bd2
BG		 815
816 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
817
818 if (io_req == NULL) {
819 printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
820 spin_unlock_bh(&tgt->tgt_lock);
821 return;
822 }
823
824 /* Timestamp IO completion time */
825 cmd_type = io_req->cmd_type;
826
619c5cb6
VZ		 827 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
828 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
829 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
853e2bd2 830
619c5cb6
VZ		 831 /* Process other IO completion types */
832 switch (cmd_type) {
833 case BNX2FC_SCSI_CMD:
853e2bd2
BG		 834 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
835 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
836 spin_unlock_bh(&tgt->tgt_lock);
837 return;
838 }
853e2bd2 839
853e2bd2
BG		 840 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
841 bnx2fc_process_abts_compl(io_req, task, num_rq);
842 else if (rx_state ==
843 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
844 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
845 else
846 printk(KERN_ERR PFX "Invalid rx state - %d\n",
847 rx_state);
848 break;
849
850 case BNX2FC_TASK_MGMT_CMD:
851 BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
852 bnx2fc_process_tm_compl(io_req, task, num_rq);
853 break;
854
855 case BNX2FC_ABTS:
856 /*
857 * ABTS request received by firmware. ABTS response
858 * will be delivered to the task belonging to the IO
859 * that was aborted
860 */
861 BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
862 kref_put(&io_req->refcount, bnx2fc_cmd_release);
863 break;
864
865 case BNX2FC_ELS:
619c5cb6
VZ		 866 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
867 bnx2fc_process_els_compl(io_req, task, num_rq);
868 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
869 bnx2fc_process_abts_compl(io_req, task, num_rq);
870 else if (rx_state ==
871 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
872 bnx2fc_process_cleanup_compl(io_req, task, num_rq);
873 else
874 printk(KERN_ERR PFX "Invalid rx state = %d\n",
875 rx_state);
853e2bd2
BG		 876 break;
877
878 case BNX2FC_CLEANUP:
879 BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
880 kref_put(&io_req->refcount, bnx2fc_cmd_release);
881 break;
882
883 default:
884 printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
885 break;
886 }
887 spin_unlock_bh(&tgt->tgt_lock);
888}
889
619c5cb6
VZ		 890void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
891{
892 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
893 u32 msg;
894
895 wmb();
896 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
897 FCOE_CQE_TOGGLE_BIT_SHIFT);
898 msg = *((u32 *)rx_db);
899 writel(cpu_to_le32(msg), tgt->ctx_base);
900 mmiowb();
901
902}
903
853e2bd2
BG		 904struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
905{
906 struct bnx2fc_work *work;
907 work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
908 if (!work)
909 return NULL;
910
911 INIT_LIST_HEAD(&work->list);
912 work->tgt = tgt;
913 work->wqe = wqe;
914 return work;
915}
916
917int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
918{
919 struct fcoe_cqe *cq;
920 u32 cq_cons;
921 struct fcoe_cqe *cqe;
619c5cb6 922 u32 num_free_sqes = 0;
853e2bd2 923 u16 wqe;
853e2bd2
BG		 924
925 /*
926 * cq_lock is a low contention lock used to protect
927 * the CQ data structure from being freed up during
928 * the upload operation
929 */
930 spin_lock_bh(&tgt->cq_lock);
931
932 if (!tgt->cq) {
933 printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
934 spin_unlock_bh(&tgt->cq_lock);
935 return 0;
936 }
937 cq = tgt->cq;
938 cq_cons = tgt->cq_cons_idx;
939 cqe = &cq[cq_cons];
940
619c5cb6
VZ		 941 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
942 (tgt->cq_curr_toggle_bit <<
943 FCOE_CQE_TOGGLE_BIT_SHIFT)) {
853e2bd2 944
619c5cb6
VZ		 945 /* new entry on the cq */
946 if (wqe & FCOE_CQE_CQE_TYPE) {
947 /* Unsolicited event notification */
948 bnx2fc_process_unsol_compl(tgt, wqe);
949 } else {
950 /* Pending work request completion */
951 struct bnx2fc_work *work = NULL;
952 struct bnx2fc_percpu_s *fps = NULL;
953 unsigned int cpu = wqe % num_possible_cpus();
954
955 fps = &per_cpu(bnx2fc_percpu, cpu);
956 spin_lock_bh(&fps->fp_work_lock);
957 if (unlikely(!fps->iothread))
958 goto unlock;
959
960 work = bnx2fc_alloc_work(tgt, wqe);
961 if (work)
962 list_add_tail(&work->list,
963 &fps->work_list);
853e2bd2 964unlock:
619c5cb6 965 spin_unlock_bh(&fps->fp_work_lock);
853e2bd2 966
619c5cb6
VZ		 967 /* Pending work request completion */
968 if (fps->iothread && work)
969 wake_up_process(fps->iothread);
970 else
971 bnx2fc_process_cq_compl(tgt, wqe);
853e2bd2 972 }
619c5cb6
VZ		 973 cqe++;
974 tgt->cq_cons_idx++;
975 num_free_sqes++;
976
977 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
978 tgt->cq_cons_idx = 0;
979 cqe = cq;
980 tgt->cq_curr_toggle_bit =
981 1 - tgt->cq_curr_toggle_bit;
853e2bd2 982 }
619c5cb6
VZ		 983 }
984 bnx2fc_arm_cq(tgt);
985 atomic_add(num_free_sqes, &tgt->free_sqes);
853e2bd2
BG		 986 spin_unlock_bh(&tgt->cq_lock);
987 return 0;
988}
989
990/**
991 * bnx2fc_fastpath_notification - process global event queue (KCQ)
992 *
993 * @hba: adapter structure pointer
994 * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
995 *
996 * Fast path event notification handler
997 */
998static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
999 struct fcoe_kcqe *new_cqe_kcqe)
1000{
1001 u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
1002 struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
1003
1004 if (!tgt) {
b2a554ff 1005 printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
853e2bd2
BG		 1006 return;
1007 }
1008
1009 bnx2fc_process_new_cqes(tgt);
1010}
1011
1012/**
1013 * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
1014 *
1015 * @hba: adapter structure pointer
1016 * @ofld_kcqe: connection offload kcqe pointer
1017 *
1018 * handle session offload completion, enable the session if offload is
1019 * successful.
1020 */
1021static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
1022 struct fcoe_kcqe *ofld_kcqe)
1023{
1024 struct bnx2fc_rport *tgt;
1025 struct fcoe_port *port;
aea71a02 1026 struct bnx2fc_interface *interface;
853e2bd2
BG		 1027 u32 conn_id;
1028 u32 context_id;
1029 int rc;
1030
1031 conn_id = ofld_kcqe->fcoe_conn_id;
1032 context_id = ofld_kcqe->fcoe_conn_context_id;
1033 tgt = hba->tgt_ofld_list[conn_id];
1034 if (!tgt) {
aea71a02 1035 printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
853e2bd2
BG		 1036 return;
1037 }
1038 BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
1039 ofld_kcqe->fcoe_conn_context_id);
1040 port = tgt->port;
aea71a02
BPG		 1041 interface = tgt->port->priv;
1042 if (hba != interface->hba) {
1043 printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
853e2bd2
BG		 1044 goto ofld_cmpl_err;
1045 }
1046 /*
1047 * cnic has allocated a context_id for this session; use this
1048 * while enabling the session.
1049 */
1050 tgt->context_id = context_id;
1051 if (ofld_kcqe->completion_status) {
1052 if (ofld_kcqe->completion_status ==
1053 FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
1054 printk(KERN_ERR PFX "unable to allocate FCoE context "
1055 "resources\n");
1056 set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
1057 }
1058 goto ofld_cmpl_err;
1059 } else {
1060
1061 /* now enable the session */
1062 rc = bnx2fc_send_session_enable_req(port, tgt);
1063 if (rc) {
b2a554ff 1064 printk(KERN_ERR PFX "enable session failed\n");
853e2bd2
BG		 1065 goto ofld_cmpl_err;
1066 }
1067 }
1068 return;
1069ofld_cmpl_err:
1070 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1071 wake_up_interruptible(&tgt->ofld_wait);
1072}
1073
1074/**
1075 * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
1076 *
1077 * @hba: adapter structure pointer
1078 * @ofld_kcqe: connection offload kcqe pointer
1079 *
1080 * handle session enable completion, mark the rport as ready
1081 */
1082
1083static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
1084 struct fcoe_kcqe *ofld_kcqe)
1085{
1086 struct bnx2fc_rport *tgt;
aea71a02 1087 struct bnx2fc_interface *interface;
853e2bd2
BG		 1088 u32 conn_id;
1089 u32 context_id;
1090
1091 context_id = ofld_kcqe->fcoe_conn_context_id;
1092 conn_id = ofld_kcqe->fcoe_conn_id;
1093 tgt = hba->tgt_ofld_list[conn_id];
1094 if (!tgt) {
b2a554ff 1095 printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
853e2bd2
BG		 1096 return;
1097 }
1098
1099 BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
1100 ofld_kcqe->fcoe_conn_context_id);
1101
1102 /*
1103 * context_id should be the same for this target during offload
1104 * and enable
1105 */
1106 if (tgt->context_id != context_id) {
b2a554ff 1107 printk(KERN_ERR PFX "context id mis-match\n");
853e2bd2
BG		 1108 return;
1109 }
aea71a02
BPG		 1110 interface = tgt->port->priv;
1111 if (hba != interface->hba) {
1112 printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
853e2bd2
BG		 1113 goto enbl_cmpl_err;
1114 }
aea71a02 1115 if (ofld_kcqe->completion_status)
853e2bd2 1116 goto enbl_cmpl_err;
aea71a02 1117 else {
853e2bd2
BG		 1118 /* enable successful - rport ready for issuing IOs */
1119 set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1120 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1121 wake_up_interruptible(&tgt->ofld_wait);
1122 }
1123 return;
1124
1125enbl_cmpl_err:
1126 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
1127 wake_up_interruptible(&tgt->ofld_wait);
1128}
1129
1130static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
1131 struct fcoe_kcqe *disable_kcqe)
1132{
1133
1134 struct bnx2fc_rport *tgt;
1135 u32 conn_id;
1136
1137 conn_id = disable_kcqe->fcoe_conn_id;
1138 tgt = hba->tgt_ofld_list[conn_id];
1139 if (!tgt) {
b2a554ff 1140 printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
853e2bd2
BG		 1141 return;
1142 }
1143
1144 BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
1145
1146 if (disable_kcqe->completion_status) {
b2a554ff 1147 printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
853e2bd2
BG		 1148 disable_kcqe->completion_status);
1149 return;
1150 } else {
1151 /* disable successful */
1152 BNX2FC_TGT_DBG(tgt, "disable successful\n");
1153 clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
1154 set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1155 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1156 wake_up_interruptible(&tgt->upld_wait);
1157 }
1158}
1159
1160static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
1161 struct fcoe_kcqe *destroy_kcqe)
1162{
1163 struct bnx2fc_rport *tgt;
1164 u32 conn_id;
1165
1166 conn_id = destroy_kcqe->fcoe_conn_id;
1167 tgt = hba->tgt_ofld_list[conn_id];
1168 if (!tgt) {
b2a554ff 1169 printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
853e2bd2
BG		 1170 return;
1171 }
1172
1173 BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
1174
1175 if (destroy_kcqe->completion_status) {
b2a554ff 1176 printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
853e2bd2
BG		 1177 destroy_kcqe->completion_status);
1178 return;
1179 } else {
1180 /* destroy successful */
1181 BNX2FC_TGT_DBG(tgt, "upload successful\n");
1182 clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
1183 set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
1184 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
1185 wake_up_interruptible(&tgt->upld_wait);
1186 }
1187}
1188
1189static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
1190{
1191 switch (err_code) {
1192 case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
1193 printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
1194 break;
1195
1196 case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
1197 printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
1198 break;
1199
1200 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
1201 printk(KERN_ERR PFX "init_failure due to NIC error\n");
1202 break;
619c5cb6
VZ		 1203 case FCOE_KCQE_COMPLETION_STATUS_ERROR:
1204 printk(KERN_ERR PFX "init failure due to compl status err\n");
1205 break;
1206 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
1207 printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
b2a554ff 1208 break;
853e2bd2
BG		 1209 default:
1210 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
1211 }
1212}
1213
1214/**
1215 * bnx2fc_indicae_kcqe - process KCQE
1216 *
1217 * @hba: adapter structure pointer
1218 * @kcqe: kcqe pointer
1219 * @num_cqe: Number of completion queue elements
1220 *
1221 * Generic KCQ event handler
1222 */
1223void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
1224 u32 num_cqe)
1225{
1226 struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
1227 int i = 0;
1228 struct fcoe_kcqe *kcqe = NULL;
1229
1230 while (i < num_cqe) {
1231 kcqe = (struct fcoe_kcqe *) kcq[i++];
1232
1233 switch (kcqe->op_code) {
1234 case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
1235 bnx2fc_fastpath_notification(hba, kcqe);
1236 break;
1237
1238 case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
1239 bnx2fc_process_ofld_cmpl(hba, kcqe);
1240 break;
1241
1242 case FCOE_KCQE_OPCODE_ENABLE_CONN:
1243 bnx2fc_process_enable_conn_cmpl(hba, kcqe);
1244 break;
1245
1246 case FCOE_KCQE_OPCODE_INIT_FUNC:
1247 if (kcqe->completion_status !=
1248 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1249 bnx2fc_init_failure(hba,
1250 kcqe->completion_status);
1251 } else {
1252 set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
1253 bnx2fc_get_link_state(hba);
1254 printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
1255 (u8)hba->pcidev->bus->number);
1256 }
1257 break;
1258
1259 case FCOE_KCQE_OPCODE_DESTROY_FUNC:
1260 if (kcqe->completion_status !=
1261 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
1262
1263 printk(KERN_ERR PFX "DESTROY failed\n");
1264 } else {
1265 printk(KERN_ERR PFX "DESTROY success\n");
1266 }
aea71a02 1267 set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
853e2bd2
BG		 1268 wake_up_interruptible(&hba->destroy_wait);
1269 break;
1270
1271 case FCOE_KCQE_OPCODE_DISABLE_CONN:
1272 bnx2fc_process_conn_disable_cmpl(hba, kcqe);
1273 break;
1274
1275 case FCOE_KCQE_OPCODE_DESTROY_CONN:
1276 bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
1277 break;
1278
1279 case FCOE_KCQE_OPCODE_STAT_FUNC:
1280 if (kcqe->completion_status !=
1281 FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
1282 printk(KERN_ERR PFX "STAT failed\n");
1283 complete(&hba->stat_req_done);
1284 break;
1285
1286 case FCOE_KCQE_OPCODE_FCOE_ERROR:
1287 /* fall thru */
1288 default:
b2a554ff 1289 printk(KERN_ERR PFX "unknown opcode 0x%x\n",
853e2bd2
BG		 1290 kcqe->op_code);
1291 }
1292 }
1293}
1294
1295void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
1296{
1297 struct fcoe_sqe *sqe;
1298
1299 sqe = &tgt->sq[tgt->sq_prod_idx];
1300
1301 /* Fill SQ WQE */
1302 sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
1303 sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
1304
1305 /* Advance SQ Prod Idx */
1306 if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
1307 tgt->sq_prod_idx = 0;
1308 tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
1309 }
1310}
1311
1312void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
1313{
619c5cb6 1314 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
853e2bd2
BG		 1315 u32 msg;
1316
1317 wmb();
619c5cb6 1318 sq_db->prod = tgt->sq_prod_idx |
853e2bd2 1319 (tgt->sq_curr_toggle_bit << 15);
619c5cb6 1320 msg = *((u32 *)sq_db);
853e2bd2 1321 writel(cpu_to_le32(msg), tgt->ctx_base);
853e2bd2
BG		 1322 mmiowb();
1323
1324}
1325
1326int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
1327{
1328 u32 context_id = tgt->context_id;
1329 struct fcoe_port *port = tgt->port;
1330 u32 reg_off;
1331 resource_size_t reg_base;
aea71a02
BPG		 1332 struct bnx2fc_interface *interface = port->priv;
1333 struct bnx2fc_hba *hba = interface->hba;
853e2bd2
BG		 1334
1335 reg_base = pci_resource_start(hba->pcidev,
1336 BNX2X_DOORBELL_PCI_BAR);
1337 reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
1338 (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
1339 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
1340 if (!tgt->ctx_base)
1341 return -ENOMEM;
1342 return 0;
1343}
1344
1345char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1346{
1347 char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
1348
1349 if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
1350 return NULL;
1351
1352 tgt->rq_cons_idx += num_items;
1353
1354 if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
1355 tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
1356
1357 return buf;
1358}
1359
1360void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
1361{
1362 /* return the rq buffer */
1363 u32 next_prod_idx = tgt->rq_prod_idx + num_items;
1364 if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
1365 /* Wrap around RQ */
1366 next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
1367 }
1368 tgt->rq_prod_idx = next_prod_idx;
1369 tgt->conn_db->rq_prod = tgt->rq_prod_idx;
1370}
1371
1372void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
1373 struct fcoe_task_ctx_entry *task,
1374 u16 orig_xid)
1375{
1376 u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
1377 struct bnx2fc_rport *tgt = io_req->tgt;
1378 u32 context_id = tgt->context_id;
1379
1380 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1381
1382 /* Tx Write Rx Read */
619c5cb6
VZ		 1383 /* init flags */
1384 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1385 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1386 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1387 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1388 task->txwr_rxrd.const_ctx.init_flags |=
1389 FCOE_TASK_DEV_TYPE_DISK <<
1390 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1391 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
1392
1393 /* Tx flags */
1394 task->txwr_rxrd.const_ctx.tx_flags =
1395 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
1396 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
1397
1398 /* Rx Read Tx Write */
1399 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1400 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1401 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1402 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
853e2bd2
BG		 1403}
1404
1405void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
1406 struct fcoe_task_ctx_entry *task)
1407{
1408 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
1409 struct bnx2fc_rport *tgt = io_req->tgt;
1410 struct fc_frame_header *fc_hdr;
619c5cb6 1411 struct fcoe_ext_mul_sges_ctx *sgl;
853e2bd2
BG		 1412 u8 task_type = 0;
1413 u64 *hdr;
1414 u64 temp_hdr[3];
1415 u32 context_id;
1416
1417
1418 /* Obtain task_type */
1419 if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
1420 (io_req->cmd_type == BNX2FC_ELS)) {
1421 task_type = FCOE_TASK_TYPE_MIDPATH;
1422 } else if (io_req->cmd_type == BNX2FC_ABTS) {
1423 task_type = FCOE_TASK_TYPE_ABTS;
1424 }
1425
1426 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1427
1428 /* Setup the task from io_req for easy reference */
1429 io_req->task = task;
1430
1431 BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
1432 io_req->cmd_type, task_type);
1433
1434 /* Tx only */
1435 if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
1436 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
619c5cb6 1437 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
853e2bd2 1438 (u32)mp_req->mp_req_bd_dma;
619c5cb6 1439 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
853e2bd2 1440 (u32)((u64)mp_req->mp_req_bd_dma >> 32);
619c5cb6 1441 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
853e2bd2
BG		 1442 }
1443
1444 /* Tx Write Rx Read */
619c5cb6
VZ		 1445 /* init flags */
1446 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1447 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1448 task->txwr_rxrd.const_ctx.init_flags |=
1449 FCOE_TASK_DEV_TYPE_DISK <<
1450 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1451 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1452 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1453
1454 /* tx flags */
1455 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
1456 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
853e2bd2
BG		 1457
1458 /* Rx Write Tx Read */
619c5cb6
VZ		 1459 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1460
1461 /* rx flags */
1462 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1463 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1464
1465 context_id = tgt->context_id;
1466 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1467 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1468
853e2bd2
BG		 1469 fc_hdr = &(mp_req->req_fc_hdr);
1470 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
1471 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
1472 fc_hdr->fh_rx_id = htons(0xffff);
619c5cb6 1473 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
853e2bd2
BG		 1474 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
1475 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
1476 }
1477
1478 /* Fill FC Header into middle path buffer */
619c5cb6 1479 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
853e2bd2
BG		 1480 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
1481 hdr[0] = cpu_to_be64(temp_hdr[0]);
1482 hdr[1] = cpu_to_be64(temp_hdr[1]);
1483 hdr[2] = cpu_to_be64(temp_hdr[2]);
1484
1485 /* Rx Only */
1486 if (task_type == FCOE_TASK_TYPE_MIDPATH) {
619c5cb6 1487 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
853e2bd2 1488
619c5cb6
VZ		 1489 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
1490 sgl->mul_sgl.cur_sge_addr.hi =
853e2bd2 1491 (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
619c5cb6 1492 sgl->mul_sgl.sgl_size = 1;
853e2bd2
BG		 1493 }
1494}
1495
1496void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
1497 struct fcoe_task_ctx_entry *task)
1498{
1499 u8 task_type;
1500 struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
1501 struct io_bdt *bd_tbl = io_req->bd_tbl;
1502 struct bnx2fc_rport *tgt = io_req->tgt;
619c5cb6
VZ		 1503 struct fcoe_cached_sge_ctx *cached_sge;
1504 struct fcoe_ext_mul_sges_ctx *sgl;
853e2bd2
BG		 1505 u64 *fcp_cmnd;
1506 u64 tmp_fcp_cmnd[4];
1507 u32 context_id;
1508 int cnt, i;
1509 int bd_count;
1510
1511 memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
1512
1513 /* Setup the task from io_req for easy reference */
1514 io_req->task = task;
1515
1516 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
1517 task_type = FCOE_TASK_TYPE_WRITE;
1518 else
1519 task_type = FCOE_TASK_TYPE_READ;
1520
1521 /* Tx only */
1522 if (task_type == FCOE_TASK_TYPE_WRITE) {
619c5cb6 1523 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
853e2bd2 1524 (u32)bd_tbl->bd_tbl_dma;
619c5cb6 1525 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
853e2bd2 1526 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
619c5cb6 1527 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
853e2bd2
BG		 1528 bd_tbl->bd_valid;
1529 }
1530
1531 /*Tx Write Rx Read */
1532 /* Init state to NORMAL */
619c5cb6
VZ		 1533 task->txwr_rxrd.const_ctx.init_flags = task_type <<
1534 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
1535 task->txwr_rxrd.const_ctx.init_flags |=
1536 FCOE_TASK_DEV_TYPE_DISK <<
1537 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
1538 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
1539 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
1540 /* tx flags */
1541 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
1542 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
853e2bd2
BG		 1543
1544 /* Set initial seq counter */
619c5cb6 1545 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
853e2bd2
BG		 1546
1547 /* Fill FCP_CMND IU */
1548 fcp_cmnd = (u64 *)
619c5cb6 1549 task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
853e2bd2
BG		 1550 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
1551
1552 /* swap fcp_cmnd */
1553 cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
1554
1555 for (i = 0; i < cnt; i++) {
1556 *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
1557 fcp_cmnd++;
1558 }
1559
1560 /* Rx Write Tx Read */
619c5cb6
VZ		 1561 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
1562
1563 context_id = tgt->context_id;
1564 task->rxwr_txrd.const_ctx.init_flags = context_id <<
1565 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
1566
1567 /* rx flags */
1568 /* Set state to "waiting for the first packet" */
1569 task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
1570 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
1571
1572 task->rxwr_txrd.var_ctx.rx_id = 0xffff;
853e2bd2
BG		 1573
1574 /* Rx Only */
619c5cb6
VZ		 1575 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
1576 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
1577 bd_count = bd_tbl->bd_valid;
853e2bd2 1578 if (task_type == FCOE_TASK_TYPE_READ) {
853e2bd2
BG		 1579 if (bd_count == 1) {
1580
1581 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1582
619c5cb6
VZ		 1583 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1584 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1585 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1586 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1587 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
1588 } else if (bd_count == 2) {
1589 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
1590
1591 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
1592 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
1593 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
1594
1595 fcoe_bd_tbl++;
1596 cached_sge->second_buf_addr.lo =
1597 fcoe_bd_tbl->buf_addr_lo;
1598 cached_sge->second_buf_addr.hi =
1599 fcoe_bd_tbl->buf_addr_hi;
1600 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
1601 task->txwr_rxrd.const_ctx.init_flags |= 1 <<
1602 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
853e2bd2
BG		 1603 } else {
1604
619c5cb6
VZ		 1605 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
1606 sgl->mul_sgl.cur_sge_addr.hi =
853e2bd2 1607 (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
619c5cb6 1608 sgl->mul_sgl.sgl_size = bd_count;
853e2bd2
BG		 1609 }
1610 }
1611}
1612
1613/**
1614 * bnx2fc_setup_task_ctx - allocate and map task context
1615 *
1616 * @hba: pointer to adapter structure
1617 *
1618 * allocate memory for task context, and associated BD table to be used
1619 * by firmware
1620 *
1621 */
1622int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
1623{
1624 int rc = 0;
1625 struct regpair *task_ctx_bdt;
1626 dma_addr_t addr;
1627 int i;
1628
1629 /*
1630 * Allocate task context bd table. A page size of bd table
1631 * can map 256 buffers. Each buffer contains 32 task context
1632 * entries. Hence the limit with one page is 8192 task context
1633 * entries.
1634 */
1635 hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
1636 PAGE_SIZE,
1637 &hba->task_ctx_bd_dma,
1638 GFP_KERNEL);
1639 if (!hba->task_ctx_bd_tbl) {
1640 printk(KERN_ERR PFX "unable to allocate task context BDT\n");
1641 rc = -1;
1642 goto out;
1643 }
1644 memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
1645
1646 /*
1647 * Allocate task_ctx which is an array of pointers pointing to
1648 * a page containing 32 task contexts
1649 */
1650 hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
1651 GFP_KERNEL);
1652 if (!hba->task_ctx) {
1653 printk(KERN_ERR PFX "unable to allocate task context array\n");
1654 rc = -1;
1655 goto out1;
1656 }
1657
1658 /*
1659 * Allocate task_ctx_dma which is an array of dma addresses
1660 */
1661 hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
1662 sizeof(dma_addr_t)), GFP_KERNEL);
1663 if (!hba->task_ctx_dma) {
1664 printk(KERN_ERR PFX "unable to alloc context mapping array\n");
1665 rc = -1;
1666 goto out2;
1667 }
1668
1669 task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
1670 for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
1671
1672 hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
1673 PAGE_SIZE,
1674 &hba->task_ctx_dma[i],
1675 GFP_KERNEL);
1676 if (!hba->task_ctx[i]) {
1677 printk(KERN_ERR PFX "unable to alloc task context\n");
1678 rc = -1;
1679 goto out3;
1680 }
1681 memset(hba->task_ctx[i], 0, PAGE_SIZE);
1682 addr = (u64)hba->task_ctx_dma[i];
1683 task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
1684 task_ctx_bdt->lo = cpu_to_le32((u32)addr);
1685 task_ctx_bdt++;
1686 }
1687 return 0;
1688
1689out3:
1690 for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
1691 if (hba->task_ctx[i]) {
1692
1693 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1694 hba->task_ctx[i], hba->task_ctx_dma[i]);
1695 hba->task_ctx[i] = NULL;
1696 }
1697 }
1698
1699 kfree(hba->task_ctx_dma);
1700 hba->task_ctx_dma = NULL;
1701out2:
1702 kfree(hba->task_ctx);
1703 hba->task_ctx = NULL;
1704out1:
1705 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1706 hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
1707 hba->task_ctx_bd_tbl = NULL;
1708out:
1709 return rc;
1710}
1711
1712void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
1713{
1714 int i;
1715
1716 if (hba->task_ctx_bd_tbl) {
1717 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1718 hba->task_ctx_bd_tbl,
1719 hba->task_ctx_bd_dma);
1720 hba->task_ctx_bd_tbl = NULL;
1721 }
1722
1723 if (hba->task_ctx) {
1724 for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
1725 if (hba->task_ctx[i]) {
1726 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1727 hba->task_ctx[i],
1728 hba->task_ctx_dma[i]);
1729 hba->task_ctx[i] = NULL;
1730 }
1731 }
1732 kfree(hba->task_ctx);
1733 hba->task_ctx = NULL;
1734 }
1735
1736 kfree(hba->task_ctx_dma);
1737 hba->task_ctx_dma = NULL;
1738}
1739
1740static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
1741{
1742 int i;
1743 int segment_count;
1744 int hash_table_size;
1745 u32 *pbl;
1746
1747 segment_count = hba->hash_tbl_segment_count;
1748 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
1749 sizeof(struct fcoe_hash_table_entry);
1750
1751 pbl = hba->hash_tbl_pbl;
1752 for (i = 0; i < segment_count; ++i) {
1753 dma_addr_t dma_address;
1754
1755 dma_address = le32_to_cpu(*pbl);
1756 ++pbl;
1757 dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
1758 ++pbl;
1759 dma_free_coherent(&hba->pcidev->dev,
1760 BNX2FC_HASH_TBL_CHUNK_SIZE,
1761 hba->hash_tbl_segments[i],
1762 dma_address);
1763
1764 }
1765
1766 if (hba->hash_tbl_pbl) {
1767 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1768 hba->hash_tbl_pbl,
1769 hba->hash_tbl_pbl_dma);
1770 hba->hash_tbl_pbl = NULL;
1771 }
1772}
1773
1774static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
1775{
1776 int i;
1777 int hash_table_size;
1778 int segment_count;
1779 int segment_array_size;
1780 int dma_segment_array_size;
1781 dma_addr_t *dma_segment_array;
1782 u32 *pbl;
1783
1784 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
1785 sizeof(struct fcoe_hash_table_entry);
1786
1787 segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
1788 segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
1789 hba->hash_tbl_segment_count = segment_count;
1790
1791 segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
1792 hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
1793 if (!hba->hash_tbl_segments) {
1794 printk(KERN_ERR PFX "hash table pointers alloc failed\n");
1795 return -ENOMEM;
1796 }
1797 dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
1798 dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
1799 if (!dma_segment_array) {
1800 printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
1801 return -ENOMEM;
1802 }
1803
1804 for (i = 0; i < segment_count; ++i) {
1805 hba->hash_tbl_segments[i] =
1806 dma_alloc_coherent(&hba->pcidev->dev,
1807 BNX2FC_HASH_TBL_CHUNK_SIZE,
1808 &dma_segment_array[i],
1809 GFP_KERNEL);
1810 if (!hba->hash_tbl_segments[i]) {
1811 printk(KERN_ERR PFX "hash segment alloc failed\n");
1812 while (--i >= 0) {
1813 dma_free_coherent(&hba->pcidev->dev,
1814 BNX2FC_HASH_TBL_CHUNK_SIZE,
1815 hba->hash_tbl_segments[i],
1816 dma_segment_array[i]);
1817 hba->hash_tbl_segments[i] = NULL;
1818 }
1819 kfree(dma_segment_array);
1820 return -ENOMEM;
1821 }
1822 memset(hba->hash_tbl_segments[i], 0,
1823 BNX2FC_HASH_TBL_CHUNK_SIZE);
1824 }
1825
1826 hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
1827 PAGE_SIZE,
1828 &hba->hash_tbl_pbl_dma,
1829 GFP_KERNEL);
1830 if (!hba->hash_tbl_pbl) {
1831 printk(KERN_ERR PFX "hash table pbl alloc failed\n");
1832 kfree(dma_segment_array);
1833 return -ENOMEM;
1834 }
1835 memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
1836
1837 pbl = hba->hash_tbl_pbl;
1838 for (i = 0; i < segment_count; ++i) {
1839 u64 paddr = dma_segment_array[i];
1840 *pbl = cpu_to_le32((u32) paddr);
1841 ++pbl;
1842 *pbl = cpu_to_le32((u32) (paddr >> 32));
1843 ++pbl;
1844 }
1845 pbl = hba->hash_tbl_pbl;
1846 i = 0;
1847 while (*pbl && *(pbl + 1)) {
1848 u32 lo;
1849 u32 hi;
1850 lo = *pbl;
1851 ++pbl;
1852 hi = *pbl;
1853 ++pbl;
1854 ++i;
1855 }
1856 kfree(dma_segment_array);
1857 return 0;
1858}
1859
1860/**
1861 * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
1862 *
1863 * @hba: Pointer to adapter structure
1864 *
1865 */
1866int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
1867{
1868 u64 addr;
1869 u32 mem_size;
1870 int i;
1871
1872 if (bnx2fc_allocate_hash_table(hba))
1873 return -ENOMEM;
1874
1875 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
1876 hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
1877 &hba->t2_hash_tbl_ptr_dma,
1878 GFP_KERNEL);
1879 if (!hba->t2_hash_tbl_ptr) {
1880 printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
1881 bnx2fc_free_fw_resc(hba);
1882 return -ENOMEM;
1883 }
1884 memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
1885
1886 mem_size = BNX2FC_NUM_MAX_SESS *
1887 sizeof(struct fcoe_t2_hash_table_entry);
1888 hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
1889 &hba->t2_hash_tbl_dma,
1890 GFP_KERNEL);
1891 if (!hba->t2_hash_tbl) {
1892 printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
1893 bnx2fc_free_fw_resc(hba);
1894 return -ENOMEM;
1895 }
1896 memset(hba->t2_hash_tbl, 0x00, mem_size);
1897 for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
1898 addr = (unsigned long) hba->t2_hash_tbl_dma +
1899 ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
1900 hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
1901 hba->t2_hash_tbl[i].next.hi = addr >> 32;
1902 }
1903
1904 hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
1905 PAGE_SIZE, &hba->dummy_buf_dma,
1906 GFP_KERNEL);
1907 if (!hba->dummy_buffer) {
1908 printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
1909 bnx2fc_free_fw_resc(hba);
1910 return -ENOMEM;
1911 }
1912
1913 hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
1914 PAGE_SIZE,
1915 &hba->stats_buf_dma,
1916 GFP_KERNEL);
1917 if (!hba->stats_buffer) {
1918 printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
1919 bnx2fc_free_fw_resc(hba);
1920 return -ENOMEM;
1921 }
1922 memset(hba->stats_buffer, 0x00, PAGE_SIZE);
1923
1924 return 0;
1925}
1926
1927void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
1928{
1929 u32 mem_size;
1930
1931 if (hba->stats_buffer) {
1932 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1933 hba->stats_buffer, hba->stats_buf_dma);
1934 hba->stats_buffer = NULL;
1935 }
1936
1937 if (hba->dummy_buffer) {
1938 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
1939 hba->dummy_buffer, hba->dummy_buf_dma);
1940 hba->dummy_buffer = NULL;
1941 }
1942
1943 if (hba->t2_hash_tbl_ptr) {
1944 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
1945 dma_free_coherent(&hba->pcidev->dev, mem_size,
1946 hba->t2_hash_tbl_ptr,
1947 hba->t2_hash_tbl_ptr_dma);
1948 hba->t2_hash_tbl_ptr = NULL;
1949 }
1950
1951 if (hba->t2_hash_tbl) {
1952 mem_size = BNX2FC_NUM_MAX_SESS *
1953 sizeof(struct fcoe_t2_hash_table_entry);
1954 dma_free_coherent(&hba->pcidev->dev, mem_size,
1955 hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
1956 hba->t2_hash_tbl = NULL;
1957 }
1958 bnx2fc_free_hash_table(hba);
1959}
Linux kernel - Deliverables
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