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[PATCH] libata: add ATA_QCFLAG_EH_SCHEDULED
[deliverable/linux.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
59a10b17 64static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 65static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 68static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 69static int fgb(u32 bitmap);
057ace5e 70static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 71 u8 *xfer_mode_out,
72 unsigned int *xfer_shift_out);
1da177e4
LT		 73
74static unsigned int ata_unique_id = 1;
75static struct workqueue_struct *ata_wq;
76
1623c81e
JG		 77int atapi_enabled = 0;
78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
1da177e4
LT		 81MODULE_AUTHOR("Jeff Garzik");
82MODULE_DESCRIPTION("Library module for ATA devices");
83MODULE_LICENSE("GPL");
84MODULE_VERSION(DRV_VERSION);
85
0baab86b 86
1da177e4
LT		 87/**
88 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
89 * @tf: Taskfile to convert
90 * @fis: Buffer into which data will output
91 * @pmp: Port multiplier port
92 *
93 * Converts a standard ATA taskfile to a Serial ATA
94 * FIS structure (Register - Host to Device).
95 *
96 * LOCKING:
97 * Inherited from caller.
98 */
99
057ace5e 100void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 101{
102 fis[0] = 0x27; /* Register - Host to Device FIS */
103 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
104 bit 7 indicates Command FIS */
105 fis[2] = tf->command;
106 fis[3] = tf->feature;
107
108 fis[4] = tf->lbal;
109 fis[5] = tf->lbam;
110 fis[6] = tf->lbah;
111 fis[7] = tf->device;
112
113 fis[8] = tf->hob_lbal;
114 fis[9] = tf->hob_lbam;
115 fis[10] = tf->hob_lbah;
116 fis[11] = tf->hob_feature;
117
118 fis[12] = tf->nsect;
119 fis[13] = tf->hob_nsect;
120 fis[14] = 0;
121 fis[15] = tf->ctl;
122
123 fis[16] = 0;
124 fis[17] = 0;
125 fis[18] = 0;
126 fis[19] = 0;
127}
128
129/**
130 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
131 * @fis: Buffer from which data will be input
132 * @tf: Taskfile to output
133 *
e12a1be6 134 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 135 *
136 * LOCKING:
137 * Inherited from caller.
138 */
139
057ace5e 140void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 141{
142 tf->command = fis[2]; /* status */
143 tf->feature = fis[3]; /* error */
144
145 tf->lbal = fis[4];
146 tf->lbam = fis[5];
147 tf->lbah = fis[6];
148 tf->device = fis[7];
149
150 tf->hob_lbal = fis[8];
151 tf->hob_lbam = fis[9];
152 tf->hob_lbah = fis[10];
153
154 tf->nsect = fis[12];
155 tf->hob_nsect = fis[13];
156}
157
8cbd6df1
AL		 158static const u8 ata_rw_cmds[] = {
159 /* pio multi */
160 ATA_CMD_READ_MULTI,
161 ATA_CMD_WRITE_MULTI,
162 ATA_CMD_READ_MULTI_EXT,
163 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 164 0,
165 0,
166 0,
167 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 168 /* pio */
169 ATA_CMD_PIO_READ,
170 ATA_CMD_PIO_WRITE,
171 ATA_CMD_PIO_READ_EXT,
172 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 173 0,
174 0,
175 0,
176 0,
8cbd6df1
AL		 177 /* dma */
178 ATA_CMD_READ,
179 ATA_CMD_WRITE,
180 ATA_CMD_READ_EXT,
9a3dccc4
TH		 181 ATA_CMD_WRITE_EXT,
182 0,
183 0,
184 0,
185 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 186};
1da177e4
LT		 187
188/**
8cbd6df1
AL		 189 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
190 * @qc: command to examine and configure
1da177e4 191 *
8cbd6df1
AL		 192 * Examine the device configuration and tf->flags to calculate
193 * the proper read/write commands and protocol to use.
1da177e4
LT		 194 *
195 * LOCKING:
196 * caller.
197 */
9a3dccc4 198int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 199{
8cbd6df1
AL		 200 struct ata_taskfile *tf = &qc->tf;
201 struct ata_device *dev = qc->dev;
9a3dccc4 202 u8 cmd;
1da177e4 203
9a3dccc4 204 int index, fua, lba48, write;
8cbd6df1 205
9a3dccc4 206 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 207 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
208 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 209
8cbd6df1
AL		 210 if (dev->flags & ATA_DFLAG_PIO) {
211 tf->protocol = ATA_PROT_PIO;
9a3dccc4 212 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 213 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
214 /* Unable to use DMA due to host limitation */
215 tf->protocol = ATA_PROT_PIO;
216 index = dev->multi_count ? 0 : 4;
8cbd6df1
AL		 217 } else {
218 tf->protocol = ATA_PROT_DMA;
9a3dccc4 219 index = 16;
8cbd6df1 220 }
1da177e4 221
9a3dccc4
TH		 222 cmd = ata_rw_cmds[index + fua + lba48 + write];
223 if (cmd) {
224 tf->command = cmd;
225 return 0;
226 }
227 return -1;
1da177e4
LT		 228}
229
98ac62de 230static const char * const xfer_mode_str[] = {
1da177e4
LT		 231 "UDMA/16",
232 "UDMA/25",
233 "UDMA/33",
234 "UDMA/44",
235 "UDMA/66",
236 "UDMA/100",
237 "UDMA/133",
238 "UDMA7",
239 "MWDMA0",
240 "MWDMA1",
241 "MWDMA2",
242 "PIO0",
243 "PIO1",
244 "PIO2",
245 "PIO3",
246 "PIO4",
247};
248
249/**
250 * ata_udma_string - convert UDMA bit offset to string
251 * @mask: mask of bits supported; only highest bit counts.
252 *
253 * Determine string which represents the highest speed
254 * (highest bit in @udma_mask).
255 *
256 * LOCKING:
257 * None.
258 *
259 * RETURNS:
260 * Constant C string representing highest speed listed in
261 * @udma_mask, or the constant C string "<n/a>".
262 */
263
264static const char *ata_mode_string(unsigned int mask)
265{
266 int i;
267
268 for (i = 7; i >= 0; i--)
269 if (mask & (1 << i))
270 goto out;
271 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
272 if (mask & (1 << i))
273 goto out;
274 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
275 if (mask & (1 << i))
276 goto out;
277
278 return "<n/a>";
279
280out:
281 return xfer_mode_str[i];
282}
283
284/**
285 * ata_pio_devchk - PATA device presence detection
286 * @ap: ATA channel to examine
287 * @device: Device to examine (starting at zero)
288 *
289 * This technique was originally described in
290 * Hale Landis's ATADRVR (www.ata-atapi.com), and
291 * later found its way into the ATA/ATAPI spec.
292 *
293 * Write a pattern to the ATA shadow registers,
294 * and if a device is present, it will respond by
295 * correctly storing and echoing back the
296 * ATA shadow register contents.
297 *
298 * LOCKING:
299 * caller.
300 */
301
302static unsigned int ata_pio_devchk(struct ata_port *ap,
303 unsigned int device)
304{
305 struct ata_ioports *ioaddr = &ap->ioaddr;
306 u8 nsect, lbal;
307
308 ap->ops->dev_select(ap, device);
309
310 outb(0x55, ioaddr->nsect_addr);
311 outb(0xaa, ioaddr->lbal_addr);
312
313 outb(0xaa, ioaddr->nsect_addr);
314 outb(0x55, ioaddr->lbal_addr);
315
316 outb(0x55, ioaddr->nsect_addr);
317 outb(0xaa, ioaddr->lbal_addr);
318
319 nsect = inb(ioaddr->nsect_addr);
320 lbal = inb(ioaddr->lbal_addr);
321
322 if ((nsect == 0x55) && (lbal == 0xaa))
323 return 1; /* we found a device */
324
325 return 0; /* nothing found */
326}
327
328/**
329 * ata_mmio_devchk - PATA device presence detection
330 * @ap: ATA channel to examine
331 * @device: Device to examine (starting at zero)
332 *
333 * This technique was originally described in
334 * Hale Landis's ATADRVR (www.ata-atapi.com), and
335 * later found its way into the ATA/ATAPI spec.
336 *
337 * Write a pattern to the ATA shadow registers,
338 * and if a device is present, it will respond by
339 * correctly storing and echoing back the
340 * ATA shadow register contents.
341 *
342 * LOCKING:
343 * caller.
344 */
345
346static unsigned int ata_mmio_devchk(struct ata_port *ap,
347 unsigned int device)
348{
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350 u8 nsect, lbal;
351
352 ap->ops->dev_select(ap, device);
353
354 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
355 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
356
357 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
358 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
359
360 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
361 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
362
363 nsect = readb((void __iomem *) ioaddr->nsect_addr);
364 lbal = readb((void __iomem *) ioaddr->lbal_addr);
365
366 if ((nsect == 0x55) && (lbal == 0xaa))
367 return 1; /* we found a device */
368
369 return 0; /* nothing found */
370}
371
372/**
373 * ata_devchk - PATA device presence detection
374 * @ap: ATA channel to examine
375 * @device: Device to examine (starting at zero)
376 *
377 * Dispatch ATA device presence detection, depending
378 * on whether we are using PIO or MMIO to talk to the
379 * ATA shadow registers.
380 *
381 * LOCKING:
382 * caller.
383 */
384
385static unsigned int ata_devchk(struct ata_port *ap,
386 unsigned int device)
387{
388 if (ap->flags & ATA_FLAG_MMIO)
389 return ata_mmio_devchk(ap, device);
390 return ata_pio_devchk(ap, device);
391}
392
393/**
394 * ata_dev_classify - determine device type based on ATA-spec signature
395 * @tf: ATA taskfile register set for device to be identified
396 *
397 * Determine from taskfile register contents whether a device is
398 * ATA or ATAPI, as per "Signature and persistence" section
399 * of ATA/PI spec (volume 1, sect 5.14).
400 *
401 * LOCKING:
402 * None.
403 *
404 * RETURNS:
405 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
406 * the event of failure.
407 */
408
057ace5e 409unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 410{
411 /* Apple's open source Darwin code hints that some devices only
412 * put a proper signature into the LBA mid/high registers,
413 * So, we only check those. It's sufficient for uniqueness.
414 */
415
416 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
417 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
418 DPRINTK("found ATA device by sig\n");
419 return ATA_DEV_ATA;
420 }
421
422 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
423 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
424 DPRINTK("found ATAPI device by sig\n");
425 return ATA_DEV_ATAPI;
426 }
427
428 DPRINTK("unknown device\n");
429 return ATA_DEV_UNKNOWN;
430}
431
432/**
433 * ata_dev_try_classify - Parse returned ATA device signature
434 * @ap: ATA channel to examine
435 * @device: Device to examine (starting at zero)
b4dc7623 436 * @r_err: Value of error register on completion
1da177e4
LT		 437 *
438 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
439 * an ATA/ATAPI-defined set of values is placed in the ATA
440 * shadow registers, indicating the results of device detection
441 * and diagnostics.
442 *
443 * Select the ATA device, and read the values from the ATA shadow
444 * registers. Then parse according to the Error register value,
445 * and the spec-defined values examined by ata_dev_classify().
446 *
447 * LOCKING:
448 * caller.
b4dc7623
TH		 449 *
450 * RETURNS:
451 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 452 */
453
b4dc7623
TH		 454static unsigned int
455ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 456{
1da177e4
LT		 457 struct ata_taskfile tf;
458 unsigned int class;
459 u8 err;
460
461 ap->ops->dev_select(ap, device);
462
463 memset(&tf, 0, sizeof(tf));
464
1da177e4 465 ap->ops->tf_read(ap, &tf);
0169e284 466 err = tf.feature;
b4dc7623
TH		 467 if (r_err)
468 *r_err = err;
1da177e4
LT		 469
470 /* see if device passed diags */
471 if (err == 1)
472 /* do nothing */ ;
473 else if ((device == 0) && (err == 0x81))
474 /* do nothing */ ;
475 else
b4dc7623 476 return ATA_DEV_NONE;
1da177e4 477
b4dc7623 478 /* determine if device is ATA or ATAPI */
1da177e4 479 class = ata_dev_classify(&tf);
b4dc7623 480
1da177e4 481 if (class == ATA_DEV_UNKNOWN)
b4dc7623 482 return ATA_DEV_NONE;
1da177e4 483 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 484 return ATA_DEV_NONE;
485 return class;
1da177e4
LT		 486}
487
488/**
489 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
490 * @id: IDENTIFY DEVICE results we will examine
491 * @s: string into which data is output
492 * @ofs: offset into identify device page
493 * @len: length of string to return. must be an even number.
494 *
495 * The strings in the IDENTIFY DEVICE page are broken up into
496 * 16-bit chunks. Run through the string, and output each
497 * 8-bit chunk linearly, regardless of platform.
498 *
499 * LOCKING:
500 * caller.
501 */
502
057ace5e 503void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 504 unsigned int ofs, unsigned int len)
505{
506 unsigned int c;
507
508 while (len > 0) {
509 c = id[ofs] >> 8;
510 *s = c;
511 s++;
512
513 c = id[ofs] & 0xff;
514 *s = c;
515 s++;
516
517 ofs++;
518 len -= 2;
519 }
520}
521
0baab86b
EF		 522
523/**
524 * ata_noop_dev_select - Select device 0/1 on ATA bus
525 * @ap: ATA channel to manipulate
526 * @device: ATA device (numbered from zero) to select
527 *
528 * This function performs no actual function.
529 *
530 * May be used as the dev_select() entry in ata_port_operations.
531 *
532 * LOCKING:
533 * caller.
534 */
1da177e4
LT		 535void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
536{
537}
538
0baab86b 539
1da177e4
LT		 540/**
541 * ata_std_dev_select - Select device 0/1 on ATA bus
542 * @ap: ATA channel to manipulate
543 * @device: ATA device (numbered from zero) to select
544 *
545 * Use the method defined in the ATA specification to
546 * make either device 0, or device 1, active on the
0baab86b
EF		 547 * ATA channel. Works with both PIO and MMIO.
548 *
549 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 550 *
551 * LOCKING:
552 * caller.
553 */
554
555void ata_std_dev_select (struct ata_port *ap, unsigned int device)
556{
557 u8 tmp;
558
559 if (device == 0)
560 tmp = ATA_DEVICE_OBS;
561 else
562 tmp = ATA_DEVICE_OBS | ATA_DEV1;
563
564 if (ap->flags & ATA_FLAG_MMIO) {
565 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
566 } else {
567 outb(tmp, ap->ioaddr.device_addr);
568 }
569 ata_pause(ap); /* needed; also flushes, for mmio */
570}
571
572/**
573 * ata_dev_select - Select device 0/1 on ATA bus
574 * @ap: ATA channel to manipulate
575 * @device: ATA device (numbered from zero) to select
576 * @wait: non-zero to wait for Status register BSY bit to clear
577 * @can_sleep: non-zero if context allows sleeping
578 *
579 * Use the method defined in the ATA specification to
580 * make either device 0, or device 1, active on the
581 * ATA channel.
582 *
583 * This is a high-level version of ata_std_dev_select(),
584 * which additionally provides the services of inserting
585 * the proper pauses and status polling, where needed.
586 *
587 * LOCKING:
588 * caller.
589 */
590
591void ata_dev_select(struct ata_port *ap, unsigned int device,
592 unsigned int wait, unsigned int can_sleep)
593{
594 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
595 ap->id, device, wait);
596
597 if (wait)
598 ata_wait_idle(ap);
599
600 ap->ops->dev_select(ap, device);
601
602 if (wait) {
603 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
604 msleep(150);
605 ata_wait_idle(ap);
606 }
607}
608
609/**
610 * ata_dump_id - IDENTIFY DEVICE info debugging output
611 * @dev: Device whose IDENTIFY DEVICE page we will dump
612 *
613 * Dump selected 16-bit words from a detected device's
614 * IDENTIFY PAGE page.
615 *
616 * LOCKING:
617 * caller.
618 */
619
057ace5e 620static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 621{
622 DPRINTK("49==0x%04x "
623 "53==0x%04x "
624 "63==0x%04x "
625 "64==0x%04x "
626 "75==0x%04x \n",
627 dev->id[49],
628 dev->id[53],
629 dev->id[63],
630 dev->id[64],
631 dev->id[75]);
632 DPRINTK("80==0x%04x "
633 "81==0x%04x "
634 "82==0x%04x "
635 "83==0x%04x "
636 "84==0x%04x \n",
637 dev->id[80],
638 dev->id[81],
639 dev->id[82],
640 dev->id[83],
641 dev->id[84]);
642 DPRINTK("88==0x%04x "
643 "93==0x%04x\n",
644 dev->id[88],
645 dev->id[93]);
646}
647
11e29e21
AC		 648/*
649 * Compute the PIO modes available for this device. This is not as
650 * trivial as it seems if we must consider early devices correctly.
651 *
652 * FIXME: pre IDE drive timing (do we care ?).
653 */
654
057ace5e 655static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 656{
657 u16 modes;
658
ffa29456
AC		 659 /* Usual case. Word 53 indicates word 64 is valid */
660 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 1)) {
11e29e21
AC		 661 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
662 modes <<= 3;
663 modes |= 0x7;
664 return modes;
665 }
666
ffa29456
AC		 667 /* If word 64 isn't valid then Word 51 high byte holds the PIO timing
668 number for the maximum. Turn it into a mask and return it */
669 modes = (2 << ((adev->id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF)) - 1 ;
11e29e21 670 return modes;
ffa29456
AC		 671 /* But wait.. there's more. Design your standards by committee and
672 you too can get a free iordy field to process. However its the
673 speeds not the modes that are supported... Note drivers using the
674 timing API will get this right anyway */
11e29e21
AC		 675}
676
95064379
TH		 677static inline void
678ata_queue_packet_task(struct ata_port *ap)
679{
c18d06f8
TH		 680 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
681 queue_work(ata_wq, &ap->packet_task);
95064379
TH		 682}
683
684static inline void
685ata_queue_pio_task(struct ata_port *ap)
686{
c18d06f8
TH		 687 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
688 queue_work(ata_wq, &ap->pio_task);
95064379
TH		 689}
690
691static inline void
692ata_queue_delayed_pio_task(struct ata_port *ap, unsigned long delay)
693{
c18d06f8
TH		 694 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
695 queue_delayed_work(ata_wq, &ap->pio_task, delay);
696}
697
698/**
699 * ata_flush_pio_tasks - Flush pio_task and packet_task
700 * @ap: the target ata_port
701 *
702 * After this function completes, pio_task and packet_task are
703 * guranteed not to be running or scheduled.
704 *
705 * LOCKING:
706 * Kernel thread context (may sleep)
707 */
708
709static void ata_flush_pio_tasks(struct ata_port *ap)
710{
711 int tmp = 0;
712 unsigned long flags;
713
714 DPRINTK("ENTER\n");
715
716 spin_lock_irqsave(&ap->host_set->lock, flags);
717 ap->flags |= ATA_FLAG_FLUSH_PIO_TASK;
718 spin_unlock_irqrestore(&ap->host_set->lock, flags);
719
720 DPRINTK("flush #1\n");
721 flush_workqueue(ata_wq);
722
723 /*
724 * At this point, if a task is running, it's guaranteed to see
725 * the FLUSH flag; thus, it will never queue pio tasks again.
726 * Cancel and flush.
727 */
728 tmp |= cancel_delayed_work(&ap->pio_task);
729 tmp |= cancel_delayed_work(&ap->packet_task);
730 if (!tmp) {
731 DPRINTK("flush #2\n");
732 flush_workqueue(ata_wq);
733 }
734
735 spin_lock_irqsave(&ap->host_set->lock, flags);
736 ap->flags &= ~ATA_FLAG_FLUSH_PIO_TASK;
737 spin_unlock_irqrestore(&ap->host_set->lock, flags);
738
739 DPRINTK("EXIT\n");
95064379
TH		 740}
741
77853bf2 742void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 743{
77853bf2 744 struct completion *waiting = qc->private_data;
a2a7a662 745
77853bf2 746 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 747 complete(waiting);
a2a7a662
TH		 748}
749
750/**
751 * ata_exec_internal - execute libata internal command
752 * @ap: Port to which the command is sent
753 * @dev: Device to which the command is sent
754 * @tf: Taskfile registers for the command and the result
755 * @dma_dir: Data tranfer direction of the command
756 * @buf: Data buffer of the command
757 * @buflen: Length of data buffer
758 *
759 * Executes libata internal command with timeout. @tf contains
760 * command on entry and result on return. Timeout and error
761 * conditions are reported via return value. No recovery action
762 * is taken after a command times out. It's caller's duty to
763 * clean up after timeout.
764 *
765 * LOCKING:
766 * None. Should be called with kernel context, might sleep.
767 */
768
769static unsigned
770ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
771 struct ata_taskfile *tf,
772 int dma_dir, void *buf, unsigned int buflen)
773{
774 u8 command = tf->command;
775 struct ata_queued_cmd *qc;
776 DECLARE_COMPLETION(wait);
777 unsigned long flags;
77853bf2 778 unsigned int err_mask;
a2a7a662
TH		 779
780 spin_lock_irqsave(&ap->host_set->lock, flags);
781
782 qc = ata_qc_new_init(ap, dev);
783 BUG_ON(qc == NULL);
784
785 qc->tf = *tf;
786 qc->dma_dir = dma_dir;
787 if (dma_dir != DMA_NONE) {
788 ata_sg_init_one(qc, buf, buflen);
789 qc->nsect = buflen / ATA_SECT_SIZE;
790 }
791
77853bf2 792 qc->private_data = &wait;
a2a7a662
TH		 793 qc->complete_fn = ata_qc_complete_internal;
794
9a3d9eb0
TH		 795 qc->err_mask = ata_qc_issue(qc);
796 if (qc->err_mask)
8e436af9 797 ata_qc_complete(qc);
a2a7a662
TH		 798
799 spin_unlock_irqrestore(&ap->host_set->lock, flags);
800
801 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
802 spin_lock_irqsave(&ap->host_set->lock, flags);
803
804 /* We're racing with irq here. If we lose, the
805 * following test prevents us from completing the qc
806 * again. If completion irq occurs after here but
807 * before the caller cleans up, it will result in a
808 * spurious interrupt. We can live with that.
809 */
77853bf2 810 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 811 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH		 812 ata_qc_complete(qc);
813 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
814 ap->id, command);
815 }
816
817 spin_unlock_irqrestore(&ap->host_set->lock, flags);
818 }
819
77853bf2
TH		 820 *tf = qc->tf;
821 err_mask = qc->err_mask;
822
823 ata_qc_free(qc);
824
825 return err_mask;
a2a7a662
TH		 826}
827
1bc4ccff
AC		 828/**
829 * ata_pio_need_iordy - check if iordy needed
830 * @adev: ATA device
831 *
832 * Check if the current speed of the device requires IORDY. Used
833 * by various controllers for chip configuration.
834 */
835
836unsigned int ata_pio_need_iordy(const struct ata_device *adev)
837{
838 int pio;
839 int speed = adev->pio_mode - XFER_PIO_0;
840
841 if (speed < 2)
842 return 0;
843 if (speed > 2)
844 return 1;
845
846 /* If we have no drive specific rule, then PIO 2 is non IORDY */
847
848 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
849 pio = adev->id[ATA_ID_EIDE_PIO];
850 /* Is the speed faster than the drive allows non IORDY ? */
851 if (pio) {
852 /* This is cycle times not frequency - watch the logic! */
853 if (pio > 240) /* PIO2 is 240nS per cycle */
854 return 1;
855 return 0;
856 }
857 }
858 return 0;
859}
860
1da177e4
LT		 861/**
862 * ata_dev_identify - obtain IDENTIFY x DEVICE page
863 * @ap: port on which device we wish to probe resides
864 * @device: device bus address, starting at zero
865 *
866 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
867 * command, and read back the 512-byte device information page.
868 * The device information page is fed to us via the standard
869 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
870 * using standard PIO-IN paths)
871 *
872 * After reading the device information page, we use several
873 * bits of information from it to initialize data structures
874 * that will be used during the lifetime of the ata_device.
875 * Other data from the info page is used to disqualify certain
876 * older ATA devices we do not wish to support.
877 *
878 * LOCKING:
879 * Inherited from caller. Some functions called by this function
880 * obtain the host_set lock.
881 */
882
883static void ata_dev_identify(struct ata_port *ap, unsigned int device)
884{
885 struct ata_device *dev = &ap->device[device];
8bf62ece 886 unsigned int major_version;
1da177e4
LT		 887 u16 tmp;
888 unsigned long xfer_modes;
1da177e4 889 unsigned int using_edd;
a0123703
TH		 890 struct ata_taskfile tf;
891 unsigned int err_mask;
1da177e4
LT		 892 int rc;
893
894 if (!ata_dev_present(dev)) {
895 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
896 ap->id, device);
897 return;
898 }
899
900 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
901 using_edd = 0;
902 else
903 using_edd = 1;
904
905 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
906
907 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
908 dev->class == ATA_DEV_NONE);
909
910 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
911
1da177e4 912retry:
a0123703
TH		 913 ata_tf_init(ap, &tf, device);
914
1da177e4 915 if (dev->class == ATA_DEV_ATA) {
a0123703 916 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT		 917 DPRINTK("do ATA identify\n");
918 } else {
a0123703 919 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT		 920 DPRINTK("do ATAPI identify\n");
921 }
922
a0123703 923 tf.protocol = ATA_PROT_PIO;
1da177e4 924
a0123703
TH		 925 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
926 dev->id, sizeof(dev->id));
1da177e4 927
a0123703
TH		 928 if (err_mask) {
929 if (err_mask & ~AC_ERR_DEV)
930 goto err_out;
0169e284 931
1da177e4
LT		 932 /*
933 * arg! EDD works for all test cases, but seems to return
934 * the ATA signature for some ATAPI devices. Until the
935 * reason for this is found and fixed, we fix up the mess
936 * here. If IDENTIFY DEVICE returns command aborted
937 * (as ATAPI devices do), then we issue an
938 * IDENTIFY PACKET DEVICE.
939 *
940 * ATA software reset (SRST, the default) does not appear
941 * to have this problem.
942 */
7c398335 943 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 944 u8 err = tf.feature;
1da177e4
LT		 945 if (err & ATA_ABORTED) {
946 dev->class = ATA_DEV_ATAPI;
1da177e4
LT		 947 goto retry;
948 }
949 }
950 goto err_out;
951 }
952
953 swap_buf_le16(dev->id, ATA_ID_WORDS);
954
955 /* print device capabilities */
956 printk(KERN_DEBUG "ata%u: dev %u cfg "
957 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
958 ap->id, device, dev->id[49],
959 dev->id[82], dev->id[83], dev->id[84],
960 dev->id[85], dev->id[86], dev->id[87],
961 dev->id[88]);
962
963 /*
964 * common ATA, ATAPI feature tests
965 */
966
8bf62ece
AL		 967 /* we require DMA support (bits 8 of word 49) */
968 if (!ata_id_has_dma(dev->id)) {
969 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 970 goto err_out_nosup;
971 }
972
973 /* quick-n-dirty find max transfer mode; for printk only */
974 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
975 if (!xfer_modes)
976 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 977 if (!xfer_modes)
978 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 979
980 ata_dump_id(dev);
981
982 /* ATA-specific feature tests */
983 if (dev->class == ATA_DEV_ATA) {
984 if (!ata_id_is_ata(dev->id)) /* sanity check */
985 goto err_out_nosup;
986
8bf62ece 987 /* get major version */
1da177e4 988 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 989 for (major_version = 14; major_version >= 1; major_version--)
990 if (tmp & (1 << major_version))
1da177e4
LT		 991 break;
992
8bf62ece
AL		 993 /*
994 * The exact sequence expected by certain pre-ATA4 drives is:
995 * SRST RESET
996 * IDENTIFY
997 * INITIALIZE DEVICE PARAMETERS
998 * anything else..
999 * Some drives were very specific about that exact sequence.
1000 */
59a10b17 1001 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1002 ata_dev_init_params(ap, dev);
1003
59a10b17
AL		 1004 /* current CHS translation info (id[53-58]) might be
1005 * changed. reread the identify device info.
1006 */
1007 ata_dev_reread_id(ap, dev);
1008 }
1009
8bf62ece
AL		 1010 if (ata_id_has_lba(dev->id)) {
1011 dev->flags |= ATA_DFLAG_LBA;
1012
1013 if (ata_id_has_lba48(dev->id)) {
1014 dev->flags |= ATA_DFLAG_LBA48;
1015 dev->n_sectors = ata_id_u64(dev->id, 100);
1016 } else {
1017 dev->n_sectors = ata_id_u32(dev->id, 60);
1018 }
1019
1020 /* print device info to dmesg */
1021 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1022 ap->id, device,
1023 major_version,
1024 ata_mode_string(xfer_modes),
1025 (unsigned long long)dev->n_sectors,
1026 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1027 } else {
1028 /* CHS */
1029
1030 /* Default translation */
1031 dev->cylinders = dev->id[1];
1032 dev->heads = dev->id[3];
1033 dev->sectors = dev->id[6];
1034 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1035
1036 if (ata_id_current_chs_valid(dev->id)) {
1037 /* Current CHS translation is valid. */
1038 dev->cylinders = dev->id[54];
1039 dev->heads = dev->id[55];
1040 dev->sectors = dev->id[56];
1041
1042 dev->n_sectors = ata_id_u32(dev->id, 57);
1043 }
1044
1045 /* print device info to dmesg */
1046 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1047 ap->id, device,
1048 major_version,
1049 ata_mode_string(xfer_modes),
1050 (unsigned long long)dev->n_sectors,
1051 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1052
1da177e4
LT		 1053 }
1054
1055 ap->host->max_cmd_len = 16;
1da177e4
LT		 1056 }
1057
1058 /* ATAPI-specific feature tests */
2c13b7ce 1059 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1060 if (ata_id_is_ata(dev->id)) /* sanity check */
1061 goto err_out_nosup;
1062
1063 rc = atapi_cdb_len(dev->id);
1064 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1065 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1066 goto err_out_nosup;
1067 }
1068 ap->cdb_len = (unsigned int) rc;
1069 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1070
1071 /* print device info to dmesg */
1072 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1073 ap->id, device,
1074 ata_mode_string(xfer_modes));
1075 }
1076
1077 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1078 return;
1079
1080err_out_nosup:
1081 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1082 ap->id, device);
1083err_out:
1084 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1085 DPRINTK("EXIT, err\n");
1086}
1087
6f2f3812 1088
057ace5e 1089static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1090{
1091 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1092}
1093
1094/**
c893a3ae
RD		 1095 * ata_dev_config - Run device specific handlers & check for SATA->PATA bridges
1096 * @ap: Bus
1097 * @i: Device
6f2f3812 1098 *
c893a3ae 1099 * LOCKING:
6f2f3812 1100 */
8a60a071 1101
6f2f3812
BC		 1102void ata_dev_config(struct ata_port *ap, unsigned int i)
1103{
1104 /* limit bridge transfers to udma5, 200 sectors */
1105 if (ata_dev_knobble(ap)) {
1106 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1107 ap->id, ap->device->devno);
1108 ap->udma_mask &= ATA_UDMA5;
1109 ap->host->max_sectors = ATA_MAX_SECTORS;
1110 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
9d824d07 1111 ap->device[i].flags |= ATA_DFLAG_LOCK_SECTORS;
6f2f3812
BC		 1112 }
1113
1114 if (ap->ops->dev_config)
1115 ap->ops->dev_config(ap, &ap->device[i]);
1116}
1117
1da177e4
LT		 1118/**
1119 * ata_bus_probe - Reset and probe ATA bus
1120 * @ap: Bus to probe
1121 *
0cba632b
JG		 1122 * Master ATA bus probing function. Initiates a hardware-dependent
1123 * bus reset, then attempts to identify any devices found on
1124 * the bus.
1125 *
1da177e4 1126 * LOCKING:
0cba632b 1127 * PCI/etc. bus probe sem.
1da177e4
LT		 1128 *
1129 * RETURNS:
1130 * Zero on success, non-zero on error.
1131 */
1132
1133static int ata_bus_probe(struct ata_port *ap)
1134{
1135 unsigned int i, found = 0;
1136
c19ba8af
TH		 1137 if (ap->ops->probe_reset) {
1138 unsigned int classes[ATA_MAX_DEVICES];
1139 int rc;
1140
1141 ata_port_probe(ap);
1142
1143 rc = ap->ops->probe_reset(ap, classes);
1144 if (rc == 0) {
1145 for (i = 0; i < ATA_MAX_DEVICES; i++)
1146 ap->device[i].class = classes[i];
1147 } else {
1148 printk(KERN_ERR "ata%u: probe reset failed, "
1149 "disabling port\n", ap->id);
1150 ata_port_disable(ap);
1151 }
1152 } else
1153 ap->ops->phy_reset(ap);
1154
1da177e4
LT		 1155 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1156 goto err_out;
1157
1158 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1159 ata_dev_identify(ap, i);
1160 if (ata_dev_present(&ap->device[i])) {
1161 found = 1;
6f2f3812 1162 ata_dev_config(ap,i);
1da177e4
LT		 1163 }
1164 }
1165
1166 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1167 goto err_out_disable;
1168
1169 ata_set_mode(ap);
1170 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1171 goto err_out_disable;
1172
1173 return 0;
1174
1175err_out_disable:
1176 ap->ops->port_disable(ap);
1177err_out:
1178 return -1;
1179}
1180
1181/**
0cba632b
JG		 1182 * ata_port_probe - Mark port as enabled
1183 * @ap: Port for which we indicate enablement
1da177e4 1184 *
0cba632b
JG		 1185 * Modify @ap data structure such that the system
1186 * thinks that the entire port is enabled.
1187 *
1188 * LOCKING: host_set lock, or some other form of
1189 * serialization.
1da177e4
LT		 1190 */
1191
1192void ata_port_probe(struct ata_port *ap)
1193{
1194 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1195}
1196
3be680b7
TH		 1197/**
1198 * sata_print_link_status - Print SATA link status
1199 * @ap: SATA port to printk link status about
1200 *
1201 * This function prints link speed and status of a SATA link.
1202 *
1203 * LOCKING:
1204 * None.
1205 */
1206static void sata_print_link_status(struct ata_port *ap)
1207{
1208 u32 sstatus, tmp;
1209 const char *speed;
1210
1211 if (!ap->ops->scr_read)
1212 return;
1213
1214 sstatus = scr_read(ap, SCR_STATUS);
1215
1216 if (sata_dev_present(ap)) {
1217 tmp = (sstatus >> 4) & 0xf;
1218 if (tmp & (1 << 0))
1219 speed = "1.5";
1220 else if (tmp & (1 << 1))
1221 speed = "3.0";
1222 else
1223 speed = "<unknown>";
1224 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1225 ap->id, speed, sstatus);
1226 } else {
1227 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1228 ap->id, sstatus);
1229 }
1230}
1231
1da177e4 1232/**
780a87f7
JG		 1233 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1234 * @ap: SATA port associated with target SATA PHY.
1da177e4 1235 *
780a87f7
JG		 1236 * This function issues commands to standard SATA Sxxx
1237 * PHY registers, to wake up the phy (and device), and
1238 * clear any reset condition.
1da177e4
LT		 1239 *
1240 * LOCKING:
0cba632b 1241 * PCI/etc. bus probe sem.
1da177e4
LT		 1242 *
1243 */
1244void __sata_phy_reset(struct ata_port *ap)
1245{
1246 u32 sstatus;
1247 unsigned long timeout = jiffies + (HZ * 5);
1248
1249 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1250 /* issue phy wake/reset */
1251 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1252 /* Couldn't find anything in SATA I/II specs, but
1253 * AHCI-1.1 10.4.2 says at least 1 ms. */
1254 mdelay(1);
1da177e4 1255 }
cdcca89e 1256 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1257
1258 /* wait for phy to become ready, if necessary */
1259 do {
1260 msleep(200);
1261 sstatus = scr_read(ap, SCR_STATUS);
1262 if ((sstatus & 0xf) != 1)
1263 break;
1264 } while (time_before(jiffies, timeout));
1265
3be680b7
TH		 1266 /* print link status */
1267 sata_print_link_status(ap);
656563e3 1268
3be680b7
TH		 1269 /* TODO: phy layer with polling, timeouts, etc. */
1270 if (sata_dev_present(ap))
1da177e4 1271 ata_port_probe(ap);
3be680b7 1272 else
1da177e4 1273 ata_port_disable(ap);
1da177e4
LT		 1274
1275 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1276 return;
1277
1278 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1279 ata_port_disable(ap);
1280 return;
1281 }
1282
1283 ap->cbl = ATA_CBL_SATA;
1284}
1285
1286/**
780a87f7
JG		 1287 * sata_phy_reset - Reset SATA bus.
1288 * @ap: SATA port associated with target SATA PHY.
1da177e4 1289 *
780a87f7
JG		 1290 * This function resets the SATA bus, and then probes
1291 * the bus for devices.
1da177e4
LT		 1292 *
1293 * LOCKING:
0cba632b 1294 * PCI/etc. bus probe sem.
1da177e4
LT		 1295 *
1296 */
1297void sata_phy_reset(struct ata_port *ap)
1298{
1299 __sata_phy_reset(ap);
1300 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1301 return;
1302 ata_bus_reset(ap);
1303}
1304
1305/**
780a87f7
JG		 1306 * ata_port_disable - Disable port.
1307 * @ap: Port to be disabled.
1da177e4 1308 *
780a87f7
JG		 1309 * Modify @ap data structure such that the system
1310 * thinks that the entire port is disabled, and should
1311 * never attempt to probe or communicate with devices
1312 * on this port.
1313 *
1314 * LOCKING: host_set lock, or some other form of
1315 * serialization.
1da177e4
LT		 1316 */
1317
1318void ata_port_disable(struct ata_port *ap)
1319{
1320 ap->device[0].class = ATA_DEV_NONE;
1321 ap->device[1].class = ATA_DEV_NONE;
1322 ap->flags |= ATA_FLAG_PORT_DISABLED;
1323}
1324
452503f9
AC		 1325/*
1326 * This mode timing computation functionality is ported over from
1327 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1328 */
1329/*
1330 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1331 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1332 * for PIO 5, which is a nonstandard extension and UDMA6, which
1333 * is currently supported only by Maxtor drives.
1334 */
1335
1336static const struct ata_timing ata_timing[] = {
1337
1338 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1339 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1340 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1341 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1342
1343 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1344 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1345 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1346
1347/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1348
1349 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1350 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1351 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1352
1353 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1354 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1355 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1356
1357/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1358 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1359 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1360
1361 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1362 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1363 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1364
1365/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1366
1367 { 0xFF }
1368};
1369
1370#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1371#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1372
1373static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1374{
1375 q->setup = EZ(t->setup * 1000, T);
1376 q->act8b = EZ(t->act8b * 1000, T);
1377 q->rec8b = EZ(t->rec8b * 1000, T);
1378 q->cyc8b = EZ(t->cyc8b * 1000, T);
1379 q->active = EZ(t->active * 1000, T);
1380 q->recover = EZ(t->recover * 1000, T);
1381 q->cycle = EZ(t->cycle * 1000, T);
1382 q->udma = EZ(t->udma * 1000, UT);
1383}
1384
1385void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1386 struct ata_timing *m, unsigned int what)
1387{
1388 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1389 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1390 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1391 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1392 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1393 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1394 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1395 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1396}
1397
1398static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1399{
1400 const struct ata_timing *t;
1401
1402 for (t = ata_timing; t->mode != speed; t++)
91190758 1403 if (t->mode == 0xFF)
452503f9
AC		 1404 return NULL;
1405 return t;
1406}
1407
1408int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1409 struct ata_timing *t, int T, int UT)
1410{
1411 const struct ata_timing *s;
1412 struct ata_timing p;
1413
1414 /*
1415 * Find the mode.
75b1f2f8 1416 */
452503f9
AC		 1417
1418 if (!(s = ata_timing_find_mode(speed)))
1419 return -EINVAL;
1420
75b1f2f8
AL		 1421 memcpy(t, s, sizeof(*s));
1422
452503f9
AC		 1423 /*
1424 * If the drive is an EIDE drive, it can tell us it needs extended
1425 * PIO/MW_DMA cycle timing.
1426 */
1427
1428 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1429 memset(&p, 0, sizeof(p));
1430 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1431 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1432 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1433 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1434 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1435 }
1436 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1437 }
1438
1439 /*
1440 * Convert the timing to bus clock counts.
1441 */
1442
75b1f2f8 1443 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1444
1445 /*
c893a3ae
RD		 1446 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1447 * S.M.A.R.T * and some other commands. We have to ensure that the
1448 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1449 */
1450
1451 if (speed > XFER_PIO_4) {
1452 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1453 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1454 }
1455
1456 /*
c893a3ae 1457 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1458 */
1459
1460 if (t->act8b + t->rec8b < t->cyc8b) {
1461 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1462 t->rec8b = t->cyc8b - t->act8b;
1463 }
1464
1465 if (t->active + t->recover < t->cycle) {
1466 t->active += (t->cycle - (t->active + t->recover)) / 2;
1467 t->recover = t->cycle - t->active;
1468 }
1469
1470 return 0;
1471}
1472
057ace5e 1473static const struct {
1da177e4
LT		 1474 unsigned int shift;
1475 u8 base;
1476} xfer_mode_classes[] = {
1477 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1478 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1479 { ATA_SHIFT_PIO, XFER_PIO_0 },
1480};
1481
858119e1 1482static u8 base_from_shift(unsigned int shift)
1da177e4
LT		 1483{
1484 int i;
1485
1486 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1487 if (xfer_mode_classes[i].shift == shift)
1488 return xfer_mode_classes[i].base;
1489
1490 return 0xff;
1491}
1492
1493static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1494{
1495 int ofs, idx;
1496 u8 base;
1497
1498 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1499 return;
1500
1501 if (dev->xfer_shift == ATA_SHIFT_PIO)
1502 dev->flags |= ATA_DFLAG_PIO;
1503
1504 ata_dev_set_xfermode(ap, dev);
1505
1506 base = base_from_shift(dev->xfer_shift);
1507 ofs = dev->xfer_mode - base;
1508 idx = ofs + dev->xfer_shift;
1509 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1510
1511 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1512 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1513
1514 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1515 ap->id, dev->devno, xfer_mode_str[idx]);
1516}
1517
1518static int ata_host_set_pio(struct ata_port *ap)
1519{
1520 unsigned int mask;
1521 int x, i;
1522 u8 base, xfer_mode;
1523
1524 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1525 x = fgb(mask);
1526 if (x < 0) {
1527 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1528 return -1;
1529 }
1530
1531 base = base_from_shift(ATA_SHIFT_PIO);
1532 xfer_mode = base + x;
1533
1534 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1535 (int)base, (int)xfer_mode, mask, x);
1536
1537 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1538 struct ata_device *dev = &ap->device[i];
1539 if (ata_dev_present(dev)) {
1540 dev->pio_mode = xfer_mode;
1541 dev->xfer_mode = xfer_mode;
1542 dev->xfer_shift = ATA_SHIFT_PIO;
1543 if (ap->ops->set_piomode)
1544 ap->ops->set_piomode(ap, dev);
1545 }
1546 }
1547
1548 return 0;
1549}
1550
1551static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1552 unsigned int xfer_shift)
1553{
1554 int i;
1555
1556 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1557 struct ata_device *dev = &ap->device[i];
1558 if (ata_dev_present(dev)) {
1559 dev->dma_mode = xfer_mode;
1560 dev->xfer_mode = xfer_mode;
1561 dev->xfer_shift = xfer_shift;
1562 if (ap->ops->set_dmamode)
1563 ap->ops->set_dmamode(ap, dev);
1564 }
1565 }
1566}
1567
1568/**
1569 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1570 * @ap: port on which timings will be programmed
1571 *
780a87f7
JG		 1572 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1573 *
1da177e4 1574 * LOCKING:
0cba632b 1575 * PCI/etc. bus probe sem.
1da177e4
LT		 1576 */
1577static void ata_set_mode(struct ata_port *ap)
1578{
8cbd6df1 1579 unsigned int xfer_shift;
1da177e4
LT		 1580 u8 xfer_mode;
1581 int rc;
1582
1583 /* step 1: always set host PIO timings */
1584 rc = ata_host_set_pio(ap);
1585 if (rc)
1586 goto err_out;
1587
1588 /* step 2: choose the best data xfer mode */
1589 xfer_mode = xfer_shift = 0;
1590 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1591 if (rc)
1592 goto err_out;
1593
1594 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1595 if (xfer_shift != ATA_SHIFT_PIO)
1596 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1597
1598 /* step 4: update devices' xfer mode */
1599 ata_dev_set_mode(ap, &ap->device[0]);
1600 ata_dev_set_mode(ap, &ap->device[1]);
1601
1602 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1603 return;
1604
1605 if (ap->ops->post_set_mode)
1606 ap->ops->post_set_mode(ap);
1607
1da177e4
LT		 1608 return;
1609
1610err_out:
1611 ata_port_disable(ap);
1612}
1613
1fdffbce
JG		 1614/**
1615 * ata_tf_to_host - issue ATA taskfile to host controller
1616 * @ap: port to which command is being issued
1617 * @tf: ATA taskfile register set
1618 *
1619 * Issues ATA taskfile register set to ATA host controller,
1620 * with proper synchronization with interrupt handler and
1621 * other threads.
1622 *
1623 * LOCKING:
1624 * spin_lock_irqsave(host_set lock)
1625 */
1626
1627static inline void ata_tf_to_host(struct ata_port *ap,
1628 const struct ata_taskfile *tf)
1629{
1630 ap->ops->tf_load(ap, tf);
1631 ap->ops->exec_command(ap, tf);
1632}
1633
1da177e4
LT		 1634/**
1635 * ata_busy_sleep - sleep until BSY clears, or timeout
1636 * @ap: port containing status register to be polled
1637 * @tmout_pat: impatience timeout
1638 * @tmout: overall timeout
1639 *
780a87f7
JG		 1640 * Sleep until ATA Status register bit BSY clears,
1641 * or a timeout occurs.
1642 *
1643 * LOCKING: None.
1da177e4
LT		 1644 */
1645
6f8b9958
TH		 1646unsigned int ata_busy_sleep (struct ata_port *ap,
1647 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 1648{
1649 unsigned long timer_start, timeout;
1650 u8 status;
1651
1652 status = ata_busy_wait(ap, ATA_BUSY, 300);
1653 timer_start = jiffies;
1654 timeout = timer_start + tmout_pat;
1655 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1656 msleep(50);
1657 status = ata_busy_wait(ap, ATA_BUSY, 3);
1658 }
1659
1660 if (status & ATA_BUSY)
1661 printk(KERN_WARNING "ata%u is slow to respond, "
1662 "please be patient\n", ap->id);
1663
1664 timeout = timer_start + tmout;
1665 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1666 msleep(50);
1667 status = ata_chk_status(ap);
1668 }
1669
1670 if (status & ATA_BUSY) {
1671 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1672 ap->id, tmout / HZ);
1673 return 1;
1674 }
1675
1676 return 0;
1677}
1678
1679static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1680{
1681 struct ata_ioports *ioaddr = &ap->ioaddr;
1682 unsigned int dev0 = devmask & (1 << 0);
1683 unsigned int dev1 = devmask & (1 << 1);
1684 unsigned long timeout;
1685
1686 /* if device 0 was found in ata_devchk, wait for its
1687 * BSY bit to clear
1688 */
1689 if (dev0)
1690 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1691
1692 /* if device 1 was found in ata_devchk, wait for
1693 * register access, then wait for BSY to clear
1694 */
1695 timeout = jiffies + ATA_TMOUT_BOOT;
1696 while (dev1) {
1697 u8 nsect, lbal;
1698
1699 ap->ops->dev_select(ap, 1);
1700 if (ap->flags & ATA_FLAG_MMIO) {
1701 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1702 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1703 } else {
1704 nsect = inb(ioaddr->nsect_addr);
1705 lbal = inb(ioaddr->lbal_addr);
1706 }
1707 if ((nsect == 1) && (lbal == 1))
1708 break;
1709 if (time_after(jiffies, timeout)) {
1710 dev1 = 0;
1711 break;
1712 }
1713 msleep(50); /* give drive a breather */
1714 }
1715 if (dev1)
1716 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1717
1718 /* is all this really necessary? */
1719 ap->ops->dev_select(ap, 0);
1720 if (dev1)
1721 ap->ops->dev_select(ap, 1);
1722 if (dev0)
1723 ap->ops->dev_select(ap, 0);
1724}
1725
1726/**
0cba632b
JG		 1727 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1728 * @ap: Port to reset and probe
1729 *
1730 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1731 * probe the bus. Not often used these days.
1da177e4
LT		 1732 *
1733 * LOCKING:
0cba632b 1734 * PCI/etc. bus probe sem.
e5338254 1735 * Obtains host_set lock.
1da177e4
LT		 1736 *
1737 */
1738
1739static unsigned int ata_bus_edd(struct ata_port *ap)
1740{
1741 struct ata_taskfile tf;
e5338254 1742 unsigned long flags;
1da177e4
LT		 1743
1744 /* set up execute-device-diag (bus reset) taskfile */
1745 /* also, take interrupts to a known state (disabled) */
1746 DPRINTK("execute-device-diag\n");
1747 ata_tf_init(ap, &tf, 0);
1748 tf.ctl |= ATA_NIEN;
1749 tf.command = ATA_CMD_EDD;
1750 tf.protocol = ATA_PROT_NODATA;
1751
1752 /* do bus reset */
e5338254 1753 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1754 ata_tf_to_host(ap, &tf);
e5338254 1755 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1756
1757 /* spec says at least 2ms. but who knows with those
1758 * crazy ATAPI devices...
1759 */
1760 msleep(150);
1761
1762 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1763}
1764
1765static unsigned int ata_bus_softreset(struct ata_port *ap,
1766 unsigned int devmask)
1767{
1768 struct ata_ioports *ioaddr = &ap->ioaddr;
1769
1770 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1771
1772 /* software reset. causes dev0 to be selected */
1773 if (ap->flags & ATA_FLAG_MMIO) {
1774 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1775 udelay(20); /* FIXME: flush */
1776 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1777 udelay(20); /* FIXME: flush */
1778 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1779 } else {
1780 outb(ap->ctl, ioaddr->ctl_addr);
1781 udelay(10);
1782 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1783 udelay(10);
1784 outb(ap->ctl, ioaddr->ctl_addr);
1785 }
1786
1787 /* spec mandates ">= 2ms" before checking status.
1788 * We wait 150ms, because that was the magic delay used for
1789 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1790 * between when the ATA command register is written, and then
1791 * status is checked. Because waiting for "a while" before
1792 * checking status is fine, post SRST, we perform this magic
1793 * delay here as well.
1794 */
1795 msleep(150);
1796
1797 ata_bus_post_reset(ap, devmask);
1798
1799 return 0;
1800}
1801
1802/**
1803 * ata_bus_reset - reset host port and associated ATA channel
1804 * @ap: port to reset
1805 *
1806 * This is typically the first time we actually start issuing
1807 * commands to the ATA channel. We wait for BSY to clear, then
1808 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1809 * result. Determine what devices, if any, are on the channel
1810 * by looking at the device 0/1 error register. Look at the signature
1811 * stored in each device's taskfile registers, to determine if
1812 * the device is ATA or ATAPI.
1813 *
1814 * LOCKING:
0cba632b
JG		 1815 * PCI/etc. bus probe sem.
1816 * Obtains host_set lock.
1da177e4
LT		 1817 *
1818 * SIDE EFFECTS:
1819 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1820 */
1821
1822void ata_bus_reset(struct ata_port *ap)
1823{
1824 struct ata_ioports *ioaddr = &ap->ioaddr;
1825 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1826 u8 err;
1827 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1828
1829 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1830
1831 /* determine if device 0/1 are present */
1832 if (ap->flags & ATA_FLAG_SATA_RESET)
1833 dev0 = 1;
1834 else {
1835 dev0 = ata_devchk(ap, 0);
1836 if (slave_possible)
1837 dev1 = ata_devchk(ap, 1);
1838 }
1839
1840 if (dev0)
1841 devmask |= (1 << 0);
1842 if (dev1)
1843 devmask |= (1 << 1);
1844
1845 /* select device 0 again */
1846 ap->ops->dev_select(ap, 0);
1847
1848 /* issue bus reset */
1849 if (ap->flags & ATA_FLAG_SRST)
1850 rc = ata_bus_softreset(ap, devmask);
1851 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1852 /* set up device control */
1853 if (ap->flags & ATA_FLAG_MMIO)
1854 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1855 else
1856 outb(ap->ctl, ioaddr->ctl_addr);
1857 rc = ata_bus_edd(ap);
1858 }
1859
1860 if (rc)
1861 goto err_out;
1862
1863 /*
1864 * determine by signature whether we have ATA or ATAPI devices
1865 */
b4dc7623 1866 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 1867 if ((slave_possible) && (err != 0x81))
b4dc7623 1868 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 1869
1870 /* re-enable interrupts */
1871 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
1872 ata_irq_on(ap);
1873
1874 /* is double-select really necessary? */
1875 if (ap->device[1].class != ATA_DEV_NONE)
1876 ap->ops->dev_select(ap, 1);
1877 if (ap->device[0].class != ATA_DEV_NONE)
1878 ap->ops->dev_select(ap, 0);
1879
1880 /* if no devices were detected, disable this port */
1881 if ((ap->device[0].class == ATA_DEV_NONE) &&
1882 (ap->device[1].class == ATA_DEV_NONE))
1883 goto err_out;
1884
1885 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
1886 /* set up device control for ATA_FLAG_SATA_RESET */
1887 if (ap->flags & ATA_FLAG_MMIO)
1888 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1889 else
1890 outb(ap->ctl, ioaddr->ctl_addr);
1891 }
1892
1893 DPRINTK("EXIT\n");
1894 return;
1895
1896err_out:
1897 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
1898 ap->ops->port_disable(ap);
1899
1900 DPRINTK("EXIT\n");
1901}
1902
7a7921e8
TH		 1903static int sata_phy_resume(struct ata_port *ap)
1904{
1905 unsigned long timeout = jiffies + (HZ * 5);
1906 u32 sstatus;
1907
1908 scr_write_flush(ap, SCR_CONTROL, 0x300);
1909
1910 /* Wait for phy to become ready, if necessary. */
1911 do {
1912 msleep(200);
1913 sstatus = scr_read(ap, SCR_STATUS);
1914 if ((sstatus & 0xf) != 1)
1915 return 0;
1916 } while (time_before(jiffies, timeout));
1917
1918 return -1;
1919}
1920
8a19ac89
TH		 1921/**
1922 * ata_std_probeinit - initialize probing
1923 * @ap: port to be probed
1924 *
1925 * @ap is about to be probed. Initialize it. This function is
1926 * to be used as standard callback for ata_drive_probe_reset().
1927 */
1928extern void ata_std_probeinit(struct ata_port *ap)
1929{
1930 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
1931 sata_phy_resume(ap);
1932}
1933
c2bd5804
TH		 1934/**
1935 * ata_std_softreset - reset host port via ATA SRST
1936 * @ap: port to reset
1937 * @verbose: fail verbosely
1938 * @classes: resulting classes of attached devices
1939 *
1940 * Reset host port using ATA SRST. This function is to be used
1941 * as standard callback for ata_drive_*_reset() functions.
1942 *
1943 * LOCKING:
1944 * Kernel thread context (may sleep)
1945 *
1946 * RETURNS:
1947 * 0 on success, -errno otherwise.
1948 */
1949int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
1950{
1951 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1952 unsigned int devmask = 0, err_mask;
1953 u8 err;
1954
1955 DPRINTK("ENTER\n");
1956
1957 /* determine if device 0/1 are present */
1958 if (ata_devchk(ap, 0))
1959 devmask |= (1 << 0);
1960 if (slave_possible && ata_devchk(ap, 1))
1961 devmask |= (1 << 1);
1962
1963 /* devchk reports device presence without actual device on
1964 * most SATA controllers. Check SStatus and turn devmask off
1965 * if link is offline. Note that we should continue resetting
1966 * even when it seems like there's no device.
1967 */
1968 if (ap->ops->scr_read && !sata_dev_present(ap))
1969 devmask = 0;
1970
1971 /* select device 0 again */
1972 ap->ops->dev_select(ap, 0);
1973
1974 /* issue bus reset */
1975 DPRINTK("about to softreset, devmask=%x\n", devmask);
1976 err_mask = ata_bus_softreset(ap, devmask);
1977 if (err_mask) {
1978 if (verbose)
1979 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
1980 ap->id, err_mask);
1981 else
1982 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
1983 err_mask);
1984 return -EIO;
1985 }
1986
1987 /* determine by signature whether we have ATA or ATAPI devices */
1988 classes[0] = ata_dev_try_classify(ap, 0, &err);
1989 if (slave_possible && err != 0x81)
1990 classes[1] = ata_dev_try_classify(ap, 1, &err);
1991
1992 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1993 return 0;
1994}
1995
1996/**
1997 * sata_std_hardreset - reset host port via SATA phy reset
1998 * @ap: port to reset
1999 * @verbose: fail verbosely
2000 * @class: resulting class of attached device
2001 *
2002 * SATA phy-reset host port using DET bits of SControl register.
2003 * This function is to be used as standard callback for
2004 * ata_drive_*_reset().
2005 *
2006 * LOCKING:
2007 * Kernel thread context (may sleep)
2008 *
2009 * RETURNS:
2010 * 0 on success, -errno otherwise.
2011 */
2012int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2013{
7a7921e8 2014 u32 serror;
c2bd5804
TH		 2015
2016 DPRINTK("ENTER\n");
2017
2018 /* Issue phy wake/reset */
2019 scr_write_flush(ap, SCR_CONTROL, 0x301);
2020
2021 /*
2022 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2023 * 10.4.2 says at least 1 ms.
2024 */
2025 msleep(1);
2026
7a7921e8
TH		 2027 /* Bring phy back */
2028 sata_phy_resume(ap);
c2bd5804
TH		 2029
2030 /* Clear SError */
2031 serror = scr_read(ap, SCR_ERROR);
2032 scr_write(ap, SCR_ERROR, serror);
2033
2034 /* TODO: phy layer with polling, timeouts, etc. */
2035 if (!sata_dev_present(ap)) {
2036 *class = ATA_DEV_NONE;
2037 DPRINTK("EXIT, link offline\n");
2038 return 0;
2039 }
2040
2041 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2042 if (verbose)
2043 printk(KERN_ERR "ata%u: COMRESET failed "
2044 "(device not ready)\n", ap->id);
2045 else
2046 DPRINTK("EXIT, device not ready\n");
2047 return -EIO;
2048 }
2049
2050 *class = ata_dev_try_classify(ap, 0, NULL);
2051
2052 DPRINTK("EXIT, class=%u\n", *class);
2053 return 0;
2054}
2055
2056/**
2057 * ata_std_postreset - standard postreset callback
2058 * @ap: the target ata_port
2059 * @classes: classes of attached devices
2060 *
2061 * This function is invoked after a successful reset. Note that
2062 * the device might have been reset more than once using
2063 * different reset methods before postreset is invoked.
2064 * postreset is also reponsible for setting cable type.
2065 *
2066 * This function is to be used as standard callback for
2067 * ata_drive_*_reset().
2068 *
2069 * LOCKING:
2070 * Kernel thread context (may sleep)
2071 */
2072void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2073{
2074 DPRINTK("ENTER\n");
2075
2076 /* set cable type */
2077 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2078 ap->cbl = ATA_CBL_SATA;
2079
2080 /* print link status */
2081 if (ap->cbl == ATA_CBL_SATA)
2082 sata_print_link_status(ap);
2083
2084 /* bail out if no device is present */
2085 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2086 DPRINTK("EXIT, no device\n");
2087 return;
2088 }
2089
2090 /* is double-select really necessary? */
2091 if (classes[0] != ATA_DEV_NONE)
2092 ap->ops->dev_select(ap, 1);
2093 if (classes[1] != ATA_DEV_NONE)
2094 ap->ops->dev_select(ap, 0);
2095
2096 /* re-enable interrupts & set up device control */
2097 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2098 ata_irq_on(ap);
2099
2100 DPRINTK("EXIT\n");
2101}
2102
2103/**
2104 * ata_std_probe_reset - standard probe reset method
2105 * @ap: prot to perform probe-reset
2106 * @classes: resulting classes of attached devices
2107 *
2108 * The stock off-the-shelf ->probe_reset method.
2109 *
2110 * LOCKING:
2111 * Kernel thread context (may sleep)
2112 *
2113 * RETURNS:
2114 * 0 on success, -errno otherwise.
2115 */
2116int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2117{
2118 ata_reset_fn_t hardreset;
2119
2120 hardreset = NULL;
b911fc3a 2121 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH		 2122 hardreset = sata_std_hardreset;
2123
8a19ac89 2124 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2125 ata_std_softreset, hardreset,
c2bd5804
TH		 2126 ata_std_postreset, classes);
2127}
2128
a62c0fc5
TH		 2129static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2130 ata_postreset_fn_t postreset,
2131 unsigned int *classes)
2132{
2133 int i, rc;
2134
2135 for (i = 0; i < ATA_MAX_DEVICES; i++)
2136 classes[i] = ATA_DEV_UNKNOWN;
2137
2138 rc = reset(ap, 0, classes);
2139 if (rc)
2140 return rc;
2141
2142 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2143 * is complete and convert all ATA_DEV_UNKNOWN to
2144 * ATA_DEV_NONE.
2145 */
2146 for (i = 0; i < ATA_MAX_DEVICES; i++)
2147 if (classes[i] != ATA_DEV_UNKNOWN)
2148 break;
2149
2150 if (i < ATA_MAX_DEVICES)
2151 for (i = 0; i < ATA_MAX_DEVICES; i++)
2152 if (classes[i] == ATA_DEV_UNKNOWN)
2153 classes[i] = ATA_DEV_NONE;
2154
2155 if (postreset)
2156 postreset(ap, classes);
2157
2158 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2159}
2160
2161/**
2162 * ata_drive_probe_reset - Perform probe reset with given methods
2163 * @ap: port to reset
7944ea95 2164 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2165 * @softreset: softreset method (can be NULL)
2166 * @hardreset: hardreset method (can be NULL)
2167 * @postreset: postreset method (can be NULL)
2168 * @classes: resulting classes of attached devices
2169 *
2170 * Reset the specified port and classify attached devices using
2171 * given methods. This function prefers softreset but tries all
2172 * possible reset sequences to reset and classify devices. This
2173 * function is intended to be used for constructing ->probe_reset
2174 * callback by low level drivers.
2175 *
2176 * Reset methods should follow the following rules.
2177 *
2178 * - Return 0 on sucess, -errno on failure.
2179 * - If classification is supported, fill classes[] with
2180 * recognized class codes.
2181 * - If classification is not supported, leave classes[] alone.
2182 * - If verbose is non-zero, print error message on failure;
2183 * otherwise, shut up.
2184 *
2185 * LOCKING:
2186 * Kernel thread context (may sleep)
2187 *
2188 * RETURNS:
2189 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2190 * if classification fails, and any error code from reset
2191 * methods.
2192 */
7944ea95 2193int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2194 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2195 ata_postreset_fn_t postreset, unsigned int *classes)
2196{
2197 int rc = -EINVAL;
2198
7944ea95
TH		 2199 if (probeinit)
2200 probeinit(ap);
2201
a62c0fc5
TH		 2202 if (softreset) {
2203 rc = do_probe_reset(ap, softreset, postreset, classes);
2204 if (rc == 0)
2205 return 0;
2206 }
2207
2208 if (!hardreset)
2209 return rc;
2210
2211 rc = do_probe_reset(ap, hardreset, postreset, classes);
2212 if (rc == 0 || rc != -ENODEV)
2213 return rc;
2214
2215 if (softreset)
2216 rc = do_probe_reset(ap, softreset, postreset, classes);
2217
2218 return rc;
2219}
2220
057ace5e
JG		 2221static void ata_pr_blacklisted(const struct ata_port *ap,
2222 const struct ata_device *dev)
1da177e4
LT		 2223{
2224 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2225 ap->id, dev->devno);
2226}
2227
98ac62de 2228static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2229 "WDC AC11000H",
2230 "WDC AC22100H",
2231 "WDC AC32500H",
2232 "WDC AC33100H",
2233 "WDC AC31600H",
2234 "WDC AC32100H",
2235 "WDC AC23200L",
2236 "Compaq CRD-8241B",
2237 "CRD-8400B",
2238 "CRD-8480B",
2239 "CRD-8482B",
2240 "CRD-84",
2241 "SanDisk SDP3B",
2242 "SanDisk SDP3B-64",
2243 "SANYO CD-ROM CRD",
2244 "HITACHI CDR-8",
2245 "HITACHI CDR-8335",
2246 "HITACHI CDR-8435",
2247 "Toshiba CD-ROM XM-6202B",
e922256a 2248 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2249 "CD-532E-A",
2250 "E-IDE CD-ROM CR-840",
2251 "CD-ROM Drive/F5A",
2252 "WPI CDD-820",
2253 "SAMSUNG CD-ROM SC-148C",
2254 "SAMSUNG CD-ROM SC",
2255 "SanDisk SDP3B-64",
1da177e4
LT		 2256 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2257 "_NEC DV5800A",
2258};
2259
057ace5e 2260static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2261{
2262 unsigned char model_num[40];
2263 char *s;
2264 unsigned int len;
2265 int i;
2266
2267 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2268 sizeof(model_num));
2269 s = &model_num[0];
2270 len = strnlen(s, sizeof(model_num));
2271
2272 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2273 while ((len > 0) && (s[len - 1] == ' ')) {
2274 len--;
2275 s[len] = 0;
2276 }
2277
2278 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2279 if (!strncmp(ata_dma_blacklist[i], s, len))
2280 return 1;
2281
2282 return 0;
2283}
2284
057ace5e 2285static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2286{
057ace5e 2287 const struct ata_device *master, *slave;
1da177e4
LT		 2288 unsigned int mask;
2289
2290 master = &ap->device[0];
2291 slave = &ap->device[1];
2292
2293 assert (ata_dev_present(master) || ata_dev_present(slave));
2294
2295 if (shift == ATA_SHIFT_UDMA) {
2296 mask = ap->udma_mask;
2297 if (ata_dev_present(master)) {
2298 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2299 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2300 mask = 0;
2301 ata_pr_blacklisted(ap, master);
2302 }
2303 }
2304 if (ata_dev_present(slave)) {
2305 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2306 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2307 mask = 0;
2308 ata_pr_blacklisted(ap, slave);
2309 }
2310 }
2311 }
2312 else if (shift == ATA_SHIFT_MWDMA) {
2313 mask = ap->mwdma_mask;
2314 if (ata_dev_present(master)) {
2315 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2316 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2317 mask = 0;
2318 ata_pr_blacklisted(ap, master);
2319 }
2320 }
2321 if (ata_dev_present(slave)) {
2322 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2323 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2324 mask = 0;
2325 ata_pr_blacklisted(ap, slave);
2326 }
2327 }
2328 }
2329 else if (shift == ATA_SHIFT_PIO) {
2330 mask = ap->pio_mask;
2331 if (ata_dev_present(master)) {
2332 /* spec doesn't return explicit support for
2333 * PIO0-2, so we fake it
2334 */
2335 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2336 tmp_mode <<= 3;
2337 tmp_mode |= 0x7;
2338 mask &= tmp_mode;
2339 }
2340 if (ata_dev_present(slave)) {
2341 /* spec doesn't return explicit support for
2342 * PIO0-2, so we fake it
2343 */
2344 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2345 tmp_mode <<= 3;
2346 tmp_mode |= 0x7;
2347 mask &= tmp_mode;
2348 }
2349 }
2350 else {
2351 mask = 0xffffffff; /* shut up compiler warning */
2352 BUG();
2353 }
2354
2355 return mask;
2356}
2357
2358/* find greatest bit */
2359static int fgb(u32 bitmap)
2360{
2361 unsigned int i;
2362 int x = -1;
2363
2364 for (i = 0; i < 32; i++)
2365 if (bitmap & (1 << i))
2366 x = i;
2367
2368 return x;
2369}
2370
2371/**
2372 * ata_choose_xfer_mode - attempt to find best transfer mode
2373 * @ap: Port for which an xfer mode will be selected
2374 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2375 * @xfer_shift_out: (output) bit shift that selects this mode
2376 *
0cba632b
JG		 2377 * Based on host and device capabilities, determine the
2378 * maximum transfer mode that is amenable to all.
2379 *
1da177e4 2380 * LOCKING:
0cba632b 2381 * PCI/etc. bus probe sem.
1da177e4
LT		 2382 *
2383 * RETURNS:
2384 * Zero on success, negative on error.
2385 */
2386
057ace5e 2387static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2388 u8 *xfer_mode_out,
2389 unsigned int *xfer_shift_out)
2390{
2391 unsigned int mask, shift;
2392 int x, i;
2393
2394 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2395 shift = xfer_mode_classes[i].shift;
2396 mask = ata_get_mode_mask(ap, shift);
2397
2398 x = fgb(mask);
2399 if (x >= 0) {
2400 *xfer_mode_out = xfer_mode_classes[i].base + x;
2401 *xfer_shift_out = shift;
2402 return 0;
2403 }
2404 }
2405
2406 return -1;
2407}
2408
2409/**
2410 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2411 * @ap: Port associated with device @dev
2412 * @dev: Device to which command will be sent
2413 *
780a87f7
JG		 2414 * Issue SET FEATURES - XFER MODE command to device @dev
2415 * on port @ap.
2416 *
1da177e4 2417 * LOCKING:
0cba632b 2418 * PCI/etc. bus probe sem.
1da177e4
LT		 2419 */
2420
2421static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2422{
a0123703 2423 struct ata_taskfile tf;
1da177e4
LT		 2424
2425 /* set up set-features taskfile */
2426 DPRINTK("set features - xfer mode\n");
2427
a0123703
TH		 2428 ata_tf_init(ap, &tf, dev->devno);
2429 tf.command = ATA_CMD_SET_FEATURES;
2430 tf.feature = SETFEATURES_XFER;
2431 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2432 tf.protocol = ATA_PROT_NODATA;
2433 tf.nsect = dev->xfer_mode;
1da177e4 2434
a0123703
TH		 2435 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2436 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2437 ap->id);
1da177e4 2438 ata_port_disable(ap);
a0123703 2439 }
1da177e4
LT		 2440
2441 DPRINTK("EXIT\n");
2442}
2443
59a10b17
AL		 2444/**
2445 * ata_dev_reread_id - Reread the device identify device info
2446 * @ap: port where the device is
2447 * @dev: device to reread the identify device info
2448 *
2449 * LOCKING:
2450 */
2451
2452static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2453{
a0123703 2454 struct ata_taskfile tf;
59a10b17 2455
a0123703 2456 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL		 2457
2458 if (dev->class == ATA_DEV_ATA) {
a0123703 2459 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL		 2460 DPRINTK("do ATA identify\n");
2461 } else {
a0123703 2462 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL		 2463 DPRINTK("do ATAPI identify\n");
2464 }
2465
a0123703
TH		 2466 tf.flags |= ATA_TFLAG_DEVICE;
2467 tf.protocol = ATA_PROT_PIO;
59a10b17 2468
a0123703
TH		 2469 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2470 dev->id, sizeof(dev->id)))
59a10b17
AL		 2471 goto err_out;
2472
59a10b17
AL		 2473 swap_buf_le16(dev->id, ATA_ID_WORDS);
2474
2475 ata_dump_id(dev);
2476
2477 DPRINTK("EXIT\n");
2478
2479 return;
2480err_out:
a0123703 2481 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL		 2482 ata_port_disable(ap);
2483}
2484
8bf62ece
AL		 2485/**
2486 * ata_dev_init_params - Issue INIT DEV PARAMS command
2487 * @ap: Port associated with device @dev
2488 * @dev: Device to which command will be sent
2489 *
2490 * LOCKING:
2491 */
2492
2493static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2494{
a0123703 2495 struct ata_taskfile tf;
8bf62ece
AL		 2496 u16 sectors = dev->id[6];
2497 u16 heads = dev->id[3];
2498
2499 /* Number of sectors per track 1-255. Number of heads 1-16 */
2500 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2501 return;
2502
2503 /* set up init dev params taskfile */
2504 DPRINTK("init dev params \n");
2505
a0123703
TH		 2506 ata_tf_init(ap, &tf, dev->devno);
2507 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2508 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2509 tf.protocol = ATA_PROT_NODATA;
2510 tf.nsect = sectors;
2511 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2512
a0123703
TH		 2513 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2514 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2515 ap->id);
8bf62ece 2516 ata_port_disable(ap);
a0123703 2517 }
8bf62ece
AL		 2518
2519 DPRINTK("EXIT\n");
2520}
2521
1da177e4 2522/**
0cba632b
JG		 2523 * ata_sg_clean - Unmap DMA memory associated with command
2524 * @qc: Command containing DMA memory to be released
2525 *
2526 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2527 *
2528 * LOCKING:
0cba632b 2529 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2530 */
2531
2532static void ata_sg_clean(struct ata_queued_cmd *qc)
2533{
2534 struct ata_port *ap = qc->ap;
cedc9a47 2535 struct scatterlist *sg = qc->__sg;
1da177e4 2536 int dir = qc->dma_dir;
cedc9a47 2537 void *pad_buf = NULL;
1da177e4
LT		 2538
2539 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2540 assert(sg != NULL);
2541
2542 if (qc->flags & ATA_QCFLAG_SINGLE)
2543 assert(qc->n_elem == 1);
2544
2c13b7ce 2545 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2546
cedc9a47
JG		 2547 /* if we padded the buffer out to 32-bit bound, and data
2548 * xfer direction is from-device, we must copy from the
2549 * pad buffer back into the supplied buffer
2550 */
2551 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2552 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2553
2554 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2555 if (qc->n_elem)
2556 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2557 /* restore last sg */
2558 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2559 if (pad_buf) {
2560 struct scatterlist *psg = &qc->pad_sgent;
2561 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2562 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2563 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2564 }
2565 } else {
e1410f2d
JG		 2566 if (sg_dma_len(&sg[0]) > 0)
2567 dma_unmap_single(ap->host_set->dev,
2568 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2569 dir);
cedc9a47
JG		 2570 /* restore sg */
2571 sg->length += qc->pad_len;
2572 if (pad_buf)
2573 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2574 pad_buf, qc->pad_len);
2575 }
1da177e4
LT		 2576
2577 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2578 qc->__sg = NULL;
1da177e4
LT		 2579}
2580
2581/**
2582 * ata_fill_sg - Fill PCI IDE PRD table
2583 * @qc: Metadata associated with taskfile to be transferred
2584 *
780a87f7
JG		 2585 * Fill PCI IDE PRD (scatter-gather) table with segments
2586 * associated with the current disk command.
2587 *
1da177e4 2588 * LOCKING:
780a87f7 2589 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2590 *
2591 */
2592static void ata_fill_sg(struct ata_queued_cmd *qc)
2593{
1da177e4 2594 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2595 struct scatterlist *sg;
2596 unsigned int idx;
1da177e4 2597
cedc9a47 2598 assert(qc->__sg != NULL);
1da177e4
LT		 2599 assert(qc->n_elem > 0);
2600
2601 idx = 0;
cedc9a47 2602 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2603 u32 addr, offset;
2604 u32 sg_len, len;
2605
2606 /* determine if physical DMA addr spans 64K boundary.
2607 * Note h/w doesn't support 64-bit, so we unconditionally
2608 * truncate dma_addr_t to u32.
2609 */
2610 addr = (u32) sg_dma_address(sg);
2611 sg_len = sg_dma_len(sg);
2612
2613 while (sg_len) {
2614 offset = addr & 0xffff;
2615 len = sg_len;
2616 if ((offset + sg_len) > 0x10000)
2617 len = 0x10000 - offset;
2618
2619 ap->prd[idx].addr = cpu_to_le32(addr);
2620 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2621 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2622
2623 idx++;
2624 sg_len -= len;
2625 addr += len;
2626 }
2627 }
2628
2629 if (idx)
2630 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2631}
2632/**
2633 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2634 * @qc: Metadata associated with taskfile to check
2635 *
780a87f7
JG		 2636 * Allow low-level driver to filter ATA PACKET commands, returning
2637 * a status indicating whether or not it is OK to use DMA for the
2638 * supplied PACKET command.
2639 *
1da177e4 2640 * LOCKING:
0cba632b
JG		 2641 * spin_lock_irqsave(host_set lock)
2642 *
1da177e4
LT		 2643 * RETURNS: 0 when ATAPI DMA can be used
2644 * nonzero otherwise
2645 */
2646int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2647{
2648 struct ata_port *ap = qc->ap;
2649 int rc = 0; /* Assume ATAPI DMA is OK by default */
2650
2651 if (ap->ops->check_atapi_dma)
2652 rc = ap->ops->check_atapi_dma(qc);
2653
2654 return rc;
2655}
2656/**
2657 * ata_qc_prep - Prepare taskfile for submission
2658 * @qc: Metadata associated with taskfile to be prepared
2659 *
780a87f7
JG		 2660 * Prepare ATA taskfile for submission.
2661 *
1da177e4
LT		 2662 * LOCKING:
2663 * spin_lock_irqsave(host_set lock)
2664 */
2665void ata_qc_prep(struct ata_queued_cmd *qc)
2666{
2667 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2668 return;
2669
2670 ata_fill_sg(qc);
2671}
2672
0cba632b
JG		 2673/**
2674 * ata_sg_init_one - Associate command with memory buffer
2675 * @qc: Command to be associated
2676 * @buf: Memory buffer
2677 * @buflen: Length of memory buffer, in bytes.
2678 *
2679 * Initialize the data-related elements of queued_cmd @qc
2680 * to point to a single memory buffer, @buf of byte length @buflen.
2681 *
2682 * LOCKING:
2683 * spin_lock_irqsave(host_set lock)
2684 */
2685
1da177e4
LT		 2686void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2687{
2688 struct scatterlist *sg;
2689
2690 qc->flags |= ATA_QCFLAG_SINGLE;
2691
2692 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2693 qc->__sg = &qc->sgent;
1da177e4 2694 qc->n_elem = 1;
cedc9a47 2695 qc->orig_n_elem = 1;
1da177e4
LT		 2696 qc->buf_virt = buf;
2697
cedc9a47 2698 sg = qc->__sg;
f0612bbc 2699 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2700}
2701
0cba632b
JG		 2702/**
2703 * ata_sg_init - Associate command with scatter-gather table.
2704 * @qc: Command to be associated
2705 * @sg: Scatter-gather table.
2706 * @n_elem: Number of elements in s/g table.
2707 *
2708 * Initialize the data-related elements of queued_cmd @qc
2709 * to point to a scatter-gather table @sg, containing @n_elem
2710 * elements.
2711 *
2712 * LOCKING:
2713 * spin_lock_irqsave(host_set lock)
2714 */
2715
1da177e4
LT		 2716void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2717 unsigned int n_elem)
2718{
2719 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2720 qc->__sg = sg;
1da177e4 2721 qc->n_elem = n_elem;
cedc9a47 2722 qc->orig_n_elem = n_elem;
1da177e4
LT		 2723}
2724
2725/**
0cba632b
JG		 2726 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2727 * @qc: Command with memory buffer to be mapped.
2728 *
2729 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2730 *
2731 * LOCKING:
2732 * spin_lock_irqsave(host_set lock)
2733 *
2734 * RETURNS:
0cba632b 2735 * Zero on success, negative on error.
1da177e4
LT		 2736 */
2737
2738static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2739{
2740 struct ata_port *ap = qc->ap;
2741 int dir = qc->dma_dir;
cedc9a47 2742 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2743 dma_addr_t dma_address;
2744
cedc9a47
JG		 2745 /* we must lengthen transfers to end on a 32-bit boundary */
2746 qc->pad_len = sg->length & 3;
2747 if (qc->pad_len) {
2748 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2749 struct scatterlist *psg = &qc->pad_sgent;
2750
2751 assert(qc->dev->class == ATA_DEV_ATAPI);
2752
2753 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2754
2755 if (qc->tf.flags & ATA_TFLAG_WRITE)
2756 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2757 qc->pad_len);
2758
2759 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2760 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2761 /* trim sg */
2762 sg->length -= qc->pad_len;
2763
2764 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2765 sg->length, qc->pad_len);
2766 }
2767
e1410f2d
JG		 2768 if (!sg->length) {
2769 sg_dma_address(sg) = 0;
2770 goto skip_map;
2771 }
2772
1da177e4 2773 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2774 sg->length, dir);
537a95d9
TH		 2775 if (dma_mapping_error(dma_address)) {
2776 /* restore sg */
2777 sg->length += qc->pad_len;
1da177e4 2778 return -1;
537a95d9 2779 }
1da177e4
LT		 2780
2781 sg_dma_address(sg) = dma_address;
e1410f2d 2782skip_map:
32529e01 2783 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2784
2785 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2786 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2787
2788 return 0;
2789}
2790
2791/**
0cba632b
JG		 2792 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2793 * @qc: Command with scatter-gather table to be mapped.
2794 *
2795 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2796 *
2797 * LOCKING:
2798 * spin_lock_irqsave(host_set lock)
2799 *
2800 * RETURNS:
0cba632b 2801 * Zero on success, negative on error.
1da177e4
LT		 2802 *
2803 */
2804
2805static int ata_sg_setup(struct ata_queued_cmd *qc)
2806{
2807 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2808 struct scatterlist *sg = qc->__sg;
2809 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2810 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2811
2812 VPRINTK("ENTER, ata%u\n", ap->id);
2813 assert(qc->flags & ATA_QCFLAG_SG);
2814
cedc9a47
JG		 2815 /* we must lengthen transfers to end on a 32-bit boundary */
2816 qc->pad_len = lsg->length & 3;
2817 if (qc->pad_len) {
2818 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2819 struct scatterlist *psg = &qc->pad_sgent;
2820 unsigned int offset;
2821
2822 assert(qc->dev->class == ATA_DEV_ATAPI);
2823
2824 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2825
2826 /*
2827 * psg->page/offset are used to copy to-be-written
2828 * data in this function or read data in ata_sg_clean.
2829 */
2830 offset = lsg->offset + lsg->length - qc->pad_len;
2831 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2832 psg->offset = offset_in_page(offset);
2833
2834 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2835 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2836 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2837 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2838 }
2839
2840 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2841 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2842 /* trim last sg */
2843 lsg->length -= qc->pad_len;
e1410f2d
JG		 2844 if (lsg->length == 0)
2845 trim_sg = 1;
cedc9a47
JG		 2846
2847 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2848 qc->n_elem - 1, lsg->length, qc->pad_len);
2849 }
2850
e1410f2d
JG		 2851 pre_n_elem = qc->n_elem;
2852 if (trim_sg && pre_n_elem)
2853 pre_n_elem--;
2854
2855 if (!pre_n_elem) {
2856 n_elem = 0;
2857 goto skip_map;
2858 }
2859
1da177e4 2860 dir = qc->dma_dir;
e1410f2d 2861 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2862 if (n_elem < 1) {
2863 /* restore last sg */
2864 lsg->length += qc->pad_len;
1da177e4 2865 return -1;
537a95d9 2866 }
1da177e4
LT		 2867
2868 DPRINTK("%d sg elements mapped\n", n_elem);
2869
e1410f2d 2870skip_map:
1da177e4
LT		 2871 qc->n_elem = n_elem;
2872
2873 return 0;
2874}
2875
40e8c82c
TH		 2876/**
2877 * ata_poll_qc_complete - turn irq back on and finish qc
2878 * @qc: Command to complete
8e8b77dd 2879 * @err_mask: ATA status register content
40e8c82c
TH		 2880 *
2881 * LOCKING:
2882 * None. (grabs host lock)
2883 */
2884
a22e2eb0 2885void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2886{
2887 struct ata_port *ap = qc->ap;
b8f6153e 2888 unsigned long flags;
40e8c82c 2889
b8f6153e 2890 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2891 ap->flags &= ~ATA_FLAG_NOINTR;
2892 ata_irq_on(ap);
a22e2eb0 2893 ata_qc_complete(qc);
b8f6153e 2894 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2895}
2896
1da177e4 2897/**
c893a3ae 2898 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 2899 * @ap: the target ata_port
1da177e4
LT		 2900 *
2901 * LOCKING:
0cba632b 2902 * None. (executing in kernel thread context)
1da177e4
LT		 2903 *
2904 * RETURNS:
6f0ef4fa 2905 * timeout value to use
1da177e4
LT		 2906 */
2907
2908static unsigned long ata_pio_poll(struct ata_port *ap)
2909{
c14b8331 2910 struct ata_queued_cmd *qc;
1da177e4 2911 u8 status;
14be71f4
AL		 2912 unsigned int poll_state = HSM_ST_UNKNOWN;
2913 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2914
c14b8331
AL		 2915 qc = ata_qc_from_tag(ap, ap->active_tag);
2916 assert(qc != NULL);
2917
14be71f4
AL		 2918 switch (ap->hsm_task_state) {
2919 case HSM_ST:
2920 case HSM_ST_POLL:
2921 poll_state = HSM_ST_POLL;
2922 reg_state = HSM_ST;
1da177e4 2923 break;
14be71f4
AL		 2924 case HSM_ST_LAST:
2925 case HSM_ST_LAST_POLL:
2926 poll_state = HSM_ST_LAST_POLL;
2927 reg_state = HSM_ST_LAST;
1da177e4
LT		 2928 break;
2929 default:
2930 BUG();
2931 break;
2932 }
2933
2934 status = ata_chk_status(ap);
2935 if (status & ATA_BUSY) {
2936 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 2937 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 2938 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2939 return 0;
2940 }
14be71f4 2941 ap->hsm_task_state = poll_state;
1da177e4
LT		 2942 return ATA_SHORT_PAUSE;
2943 }
2944
14be71f4 2945 ap->hsm_task_state = reg_state;
1da177e4
LT		 2946 return 0;
2947}
2948
2949/**
6f0ef4fa
RD		 2950 * ata_pio_complete - check if drive is busy or idle
2951 * @ap: the target ata_port
1da177e4
LT		 2952 *
2953 * LOCKING:
0cba632b 2954 * None. (executing in kernel thread context)
7fb6ec28
JG		 2955 *
2956 * RETURNS:
2957 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2958 */
2959
7fb6ec28 2960static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2961{
2962 struct ata_queued_cmd *qc;
2963 u8 drv_stat;
2964
2965 /*
31433ea3
AC		 2966 * This is purely heuristic. This is a fast path. Sometimes when
2967 * we enter, BSY will be cleared in a chk-status or two. If not,
2968 * the drive is probably seeking or something. Snooze for a couple
2969 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2970 * HSM_ST_POLL state.
1da177e4 2971 */
fe79e683
AL		 2972 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2973 if (drv_stat & ATA_BUSY) {
1da177e4 2974 msleep(2);
fe79e683
AL		 2975 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2976 if (drv_stat & ATA_BUSY) {
14be71f4 2977 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2978 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2979 return 0;
1da177e4
LT		 2980 }
2981 }
2982
c14b8331
AL		 2983 qc = ata_qc_from_tag(ap, ap->active_tag);
2984 assert(qc != NULL);
2985
1da177e4
LT		 2986 drv_stat = ata_wait_idle(ap);
2987 if (!ata_ok(drv_stat)) {
1c848984 2988 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 2989 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2990 return 0;
1da177e4
LT		 2991 }
2992
14be71f4 2993 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2994
a22e2eb0
AL		 2995 assert(qc->err_mask == 0);
2996 ata_poll_qc_complete(qc);
7fb6ec28
JG		 2997
2998 /* another command may start at this point */
2999
3000 return 1;
1da177e4
LT		 3001}
3002
0baab86b
EF		 3003
3004/**
c893a3ae 3005 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3006 * @buf: Buffer to swap
3007 * @buf_words: Number of 16-bit words in buffer.
3008 *
3009 * Swap halves of 16-bit words if needed to convert from
3010 * little-endian byte order to native cpu byte order, or
3011 * vice-versa.
3012 *
3013 * LOCKING:
6f0ef4fa 3014 * Inherited from caller.
0baab86b 3015 */
1da177e4
LT		 3016void swap_buf_le16(u16 *buf, unsigned int buf_words)
3017{
3018#ifdef __BIG_ENDIAN
3019 unsigned int i;
3020
3021 for (i = 0; i < buf_words; i++)
3022 buf[i] = le16_to_cpu(buf[i]);
3023#endif /* __BIG_ENDIAN */
3024}
3025
6ae4cfb5
AL		 3026/**
3027 * ata_mmio_data_xfer - Transfer data by MMIO
3028 * @ap: port to read/write
3029 * @buf: data buffer
3030 * @buflen: buffer length
344babaa 3031 * @write_data: read/write
6ae4cfb5
AL		 3032 *
3033 * Transfer data from/to the device data register by MMIO.
3034 *
3035 * LOCKING:
3036 * Inherited from caller.
6ae4cfb5
AL		 3037 */
3038
1da177e4
LT		 3039static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3040 unsigned int buflen, int write_data)
3041{
3042 unsigned int i;
3043 unsigned int words = buflen >> 1;
3044 u16 *buf16 = (u16 *) buf;
3045 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3046
6ae4cfb5 3047 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3048 if (write_data) {
3049 for (i = 0; i < words; i++)
3050 writew(le16_to_cpu(buf16[i]), mmio);
3051 } else {
3052 for (i = 0; i < words; i++)
3053 buf16[i] = cpu_to_le16(readw(mmio));
3054 }
6ae4cfb5
AL		 3055
3056 /* Transfer trailing 1 byte, if any. */
3057 if (unlikely(buflen & 0x01)) {
3058 u16 align_buf[1] = { 0 };
3059 unsigned char *trailing_buf = buf + buflen - 1;
3060
3061 if (write_data) {
3062 memcpy(align_buf, trailing_buf, 1);
3063 writew(le16_to_cpu(align_buf[0]), mmio);
3064 } else {
3065 align_buf[0] = cpu_to_le16(readw(mmio));
3066 memcpy(trailing_buf, align_buf, 1);
3067 }
3068 }
1da177e4
LT		 3069}
3070
6ae4cfb5
AL		 3071/**
3072 * ata_pio_data_xfer - Transfer data by PIO
3073 * @ap: port to read/write
3074 * @buf: data buffer
3075 * @buflen: buffer length
344babaa 3076 * @write_data: read/write
6ae4cfb5
AL		 3077 *
3078 * Transfer data from/to the device data register by PIO.
3079 *
3080 * LOCKING:
3081 * Inherited from caller.
6ae4cfb5
AL		 3082 */
3083
1da177e4
LT		 3084static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3085 unsigned int buflen, int write_data)
3086{
6ae4cfb5 3087 unsigned int words = buflen >> 1;
1da177e4 3088
6ae4cfb5 3089 /* Transfer multiple of 2 bytes */
1da177e4 3090 if (write_data)
6ae4cfb5 3091 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3092 else
6ae4cfb5
AL		 3093 insw(ap->ioaddr.data_addr, buf, words);
3094
3095 /* Transfer trailing 1 byte, if any. */
3096 if (unlikely(buflen & 0x01)) {
3097 u16 align_buf[1] = { 0 };
3098 unsigned char *trailing_buf = buf + buflen - 1;
3099
3100 if (write_data) {
3101 memcpy(align_buf, trailing_buf, 1);
3102 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3103 } else {
3104 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3105 memcpy(trailing_buf, align_buf, 1);
3106 }
3107 }
1da177e4
LT		 3108}
3109
6ae4cfb5
AL		 3110/**
3111 * ata_data_xfer - Transfer data from/to the data register.
3112 * @ap: port to read/write
3113 * @buf: data buffer
3114 * @buflen: buffer length
3115 * @do_write: read/write
3116 *
3117 * Transfer data from/to the device data register.
3118 *
3119 * LOCKING:
3120 * Inherited from caller.
6ae4cfb5
AL		 3121 */
3122
1da177e4
LT		 3123static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3124 unsigned int buflen, int do_write)
3125{
a1bd9e68
AC		 3126 /* Make the crap hardware pay the costs not the good stuff */
3127 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3128 unsigned long flags;
3129 local_irq_save(flags);
3130 if (ap->flags & ATA_FLAG_MMIO)
3131 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3132 else
3133 ata_pio_data_xfer(ap, buf, buflen, do_write);
3134 local_irq_restore(flags);
3135 } else {
3136 if (ap->flags & ATA_FLAG_MMIO)
3137 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3138 else
3139 ata_pio_data_xfer(ap, buf, buflen, do_write);
3140 }
1da177e4
LT		 3141}
3142
6ae4cfb5
AL		 3143/**
3144 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3145 * @qc: Command on going
3146 *
3147 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3148 *
3149 * LOCKING:
3150 * Inherited from caller.
3151 */
3152
1da177e4
LT		 3153static void ata_pio_sector(struct ata_queued_cmd *qc)
3154{
3155 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3156 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3157 struct ata_port *ap = qc->ap;
3158 struct page *page;
3159 unsigned int offset;
3160 unsigned char *buf;
3161
3162 if (qc->cursect == (qc->nsect - 1))
14be71f4 3163 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3164
3165 page = sg[qc->cursg].page;
3166 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3167
3168 /* get the current page and offset */
3169 page = nth_page(page, (offset >> PAGE_SHIFT));
3170 offset %= PAGE_SIZE;
3171
3172 buf = kmap(page) + offset;
3173
3174 qc->cursect++;
3175 qc->cursg_ofs++;
3176
32529e01 3177 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3178 qc->cursg++;
3179 qc->cursg_ofs = 0;
3180 }
3181
3182 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3183
3184 /* do the actual data transfer */
3185 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3186 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3187
3188 kunmap(page);
3189}
3190
6ae4cfb5
AL		 3191/**
3192 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3193 * @qc: Command on going
3194 * @bytes: number of bytes
3195 *
3196 * Transfer Transfer data from/to the ATAPI device.
3197 *
3198 * LOCKING:
3199 * Inherited from caller.
3200 *
3201 */
3202
1da177e4
LT		 3203static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3204{
3205 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3206 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3207 struct ata_port *ap = qc->ap;
3208 struct page *page;
3209 unsigned char *buf;
3210 unsigned int offset, count;
3211
563a6e1f 3212 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3213 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3214
3215next_sg:
563a6e1f 3216 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3217 /*
563a6e1f
AL		 3218 * The end of qc->sg is reached and the device expects
3219 * more data to transfer. In order not to overrun qc->sg
3220 * and fulfill length specified in the byte count register,
3221 * - for read case, discard trailing data from the device
3222 * - for write case, padding zero data to the device
3223 */
3224 u16 pad_buf[1] = { 0 };
3225 unsigned int words = bytes >> 1;
3226 unsigned int i;
3227
3228 if (words) /* warning if bytes > 1 */
7fb6ec28 3229 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3230 ap->id, bytes);
3231
3232 for (i = 0; i < words; i++)
3233 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3234
14be71f4 3235 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3236 return;
3237 }
3238
cedc9a47 3239 sg = &qc->__sg[qc->cursg];
1da177e4 3240
1da177e4
LT		 3241 page = sg->page;
3242 offset = sg->offset + qc->cursg_ofs;
3243
3244 /* get the current page and offset */
3245 page = nth_page(page, (offset >> PAGE_SHIFT));
3246 offset %= PAGE_SIZE;
3247
6952df03 3248 /* don't overrun current sg */
32529e01 3249 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3250
3251 /* don't cross page boundaries */
3252 count = min(count, (unsigned int)PAGE_SIZE - offset);
3253
3254 buf = kmap(page) + offset;
3255
3256 bytes -= count;
3257 qc->curbytes += count;
3258 qc->cursg_ofs += count;
3259
32529e01 3260 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3261 qc->cursg++;
3262 qc->cursg_ofs = 0;
3263 }
3264
3265 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3266
3267 /* do the actual data transfer */
3268 ata_data_xfer(ap, buf, count, do_write);
3269
3270 kunmap(page);
3271
563a6e1f 3272 if (bytes)
1da177e4 3273 goto next_sg;
1da177e4
LT		 3274}
3275
6ae4cfb5
AL		 3276/**
3277 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3278 * @qc: Command on going
3279 *
3280 * Transfer Transfer data from/to the ATAPI device.
3281 *
3282 * LOCKING:
3283 * Inherited from caller.
6ae4cfb5
AL		 3284 */
3285
1da177e4
LT		 3286static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3287{
3288 struct ata_port *ap = qc->ap;
3289 struct ata_device *dev = qc->dev;
3290 unsigned int ireason, bc_lo, bc_hi, bytes;
3291 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3292
3293 ap->ops->tf_read(ap, &qc->tf);
3294 ireason = qc->tf.nsect;
3295 bc_lo = qc->tf.lbam;
3296 bc_hi = qc->tf.lbah;
3297 bytes = (bc_hi << 8) | bc_lo;
3298
3299 /* shall be cleared to zero, indicating xfer of data */
3300 if (ireason & (1 << 0))
3301 goto err_out;
3302
3303 /* make sure transfer direction matches expected */
3304 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3305 if (do_write != i_write)
3306 goto err_out;
3307
3308 __atapi_pio_bytes(qc, bytes);
3309
3310 return;
3311
3312err_out:
3313 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3314 ap->id, dev->devno);
11a56d24 3315 qc->err_mask |= AC_ERR_HSM;
14be71f4 3316 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3317}
3318
3319/**
6f0ef4fa
RD		 3320 * ata_pio_block - start PIO on a block
3321 * @ap: the target ata_port
1da177e4
LT		 3322 *
3323 * LOCKING:
0cba632b 3324 * None. (executing in kernel thread context)
1da177e4
LT		 3325 */
3326
3327static void ata_pio_block(struct ata_port *ap)
3328{
3329 struct ata_queued_cmd *qc;
3330 u8 status;
3331
3332 /*
6f0ef4fa 3333 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3334 * Sometimes when we enter, BSY will be cleared in
3335 * a chk-status or two. If not, the drive is probably seeking
3336 * or something. Snooze for a couple msecs, then
3337 * chk-status again. If still busy, fall back to
14be71f4 3338 * HSM_ST_POLL state.
1da177e4
LT		 3339 */
3340 status = ata_busy_wait(ap, ATA_BUSY, 5);
3341 if (status & ATA_BUSY) {
3342 msleep(2);
3343 status = ata_busy_wait(ap, ATA_BUSY, 10);
3344 if (status & ATA_BUSY) {
14be71f4 3345 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3346 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3347 return;
3348 }
3349 }
3350
3351 qc = ata_qc_from_tag(ap, ap->active_tag);
3352 assert(qc != NULL);
3353
fe79e683
AL		 3354 /* check error */
3355 if (status & (ATA_ERR | ATA_DF)) {
3356 qc->err_mask |= AC_ERR_DEV;
3357 ap->hsm_task_state = HSM_ST_ERR;
3358 return;
3359 }
3360
3361 /* transfer data if any */
1da177e4 3362 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3363 /* DRQ=0 means no more data to transfer */
1da177e4 3364 if ((status & ATA_DRQ) == 0) {
14be71f4 3365 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3366 return;
3367 }
3368
3369 atapi_pio_bytes(qc);
3370 } else {
3371 /* handle BSY=0, DRQ=0 as error */
3372 if ((status & ATA_DRQ) == 0) {
11a56d24 3373 qc->err_mask |= AC_ERR_HSM;
14be71f4 3374 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3375 return;
3376 }
3377
3378 ata_pio_sector(qc);
3379 }
3380}
3381
3382static void ata_pio_error(struct ata_port *ap)
3383{
3384 struct ata_queued_cmd *qc;
a7dac447
JG		 3385
3386 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3387
3388 qc = ata_qc_from_tag(ap, ap->active_tag);
3389 assert(qc != NULL);
3390
1c848984
AL		 3391 /* make sure qc->err_mask is available to
3392 * know what's wrong and recover
3393 */
3394 assert(qc->err_mask);
3395
14be71f4 3396 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3397
a22e2eb0 3398 ata_poll_qc_complete(qc);
1da177e4
LT		 3399}
3400
3401static void ata_pio_task(void *_data)
3402{
3403 struct ata_port *ap = _data;
7fb6ec28
JG		 3404 unsigned long timeout;
3405 int qc_completed;
3406
3407fsm_start:
3408 timeout = 0;
3409 qc_completed = 0;
1da177e4 3410
14be71f4
AL		 3411 switch (ap->hsm_task_state) {
3412 case HSM_ST_IDLE:
1da177e4
LT		 3413 return;
3414
14be71f4 3415 case HSM_ST:
1da177e4
LT		 3416 ata_pio_block(ap);
3417 break;
3418
14be71f4 3419 case HSM_ST_LAST:
7fb6ec28 3420 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3421 break;
3422
14be71f4
AL		 3423 case HSM_ST_POLL:
3424 case HSM_ST_LAST_POLL:
1da177e4
LT		 3425 timeout = ata_pio_poll(ap);
3426 break;
3427
14be71f4
AL		 3428 case HSM_ST_TMOUT:
3429 case HSM_ST_ERR:
1da177e4
LT		 3430 ata_pio_error(ap);
3431 return;
3432 }
3433
3434 if (timeout)
95064379 3435 ata_queue_delayed_pio_task(ap, timeout);
7fb6ec28
JG		 3436 else if (!qc_completed)
3437 goto fsm_start;
1da177e4
LT		 3438}
3439
1da177e4
LT		 3440/**
3441 * ata_qc_timeout - Handle timeout of queued command
3442 * @qc: Command that timed out
3443 *
3444 * Some part of the kernel (currently, only the SCSI layer)
3445 * has noticed that the active command on port @ap has not
3446 * completed after a specified length of time. Handle this
3447 * condition by disabling DMA (if necessary) and completing
3448 * transactions, with error if necessary.
3449 *
3450 * This also handles the case of the "lost interrupt", where
3451 * for some reason (possibly hardware bug, possibly driver bug)
3452 * an interrupt was not delivered to the driver, even though the
3453 * transaction completed successfully.
3454 *
3455 * LOCKING:
0cba632b 3456 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3457 */
3458
3459static void ata_qc_timeout(struct ata_queued_cmd *qc)
3460{
3461 struct ata_port *ap = qc->ap;
b8f6153e 3462 struct ata_host_set *host_set = ap->host_set;
1da177e4 3463 u8 host_stat = 0, drv_stat;
b8f6153e 3464 unsigned long flags;
1da177e4
LT		 3465
3466 DPRINTK("ENTER\n");
3467
c18d06f8
TH		 3468 ata_flush_pio_tasks(ap);
3469 ap->hsm_task_state = HSM_ST_IDLE;
3470
b8f6153e
JG		 3471 spin_lock_irqsave(&host_set->lock, flags);
3472
1da177e4
LT		 3473 switch (qc->tf.protocol) {
3474
3475 case ATA_PROT_DMA:
3476 case ATA_PROT_ATAPI_DMA:
3477 host_stat = ap->ops->bmdma_status(ap);
3478
3479 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3480 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3481
3482 /* fall through */
3483
3484 default:
3485 ata_altstatus(ap);
3486 drv_stat = ata_chk_status(ap);
3487
3488 /* ack bmdma irq events */
3489 ap->ops->irq_clear(ap);
3490
3491 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3492 ap->id, qc->tf.command, drv_stat, host_stat);
3493
3494 /* complete taskfile transaction */
a22e2eb0 3495 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT		 3496 break;
3497 }
b8f6153e
JG		 3498
3499 spin_unlock_irqrestore(&host_set->lock, flags);
3500
a72ec4ce
TH		 3501 ata_eh_qc_complete(qc);
3502
1da177e4
LT		 3503 DPRINTK("EXIT\n");
3504}
3505
3506/**
3507 * ata_eng_timeout - Handle timeout of queued command
3508 * @ap: Port on which timed-out command is active
3509 *
3510 * Some part of the kernel (currently, only the SCSI layer)
3511 * has noticed that the active command on port @ap has not
3512 * completed after a specified length of time. Handle this
3513 * condition by disabling DMA (if necessary) and completing
3514 * transactions, with error if necessary.
3515 *
3516 * This also handles the case of the "lost interrupt", where
3517 * for some reason (possibly hardware bug, possibly driver bug)
3518 * an interrupt was not delivered to the driver, even though the
3519 * transaction completed successfully.
3520 *
3521 * LOCKING:
3522 * Inherited from SCSI layer (none, can sleep)
3523 */
3524
3525void ata_eng_timeout(struct ata_port *ap)
3526{
3527 struct ata_queued_cmd *qc;
3528
3529 DPRINTK("ENTER\n");
3530
3531 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3532 if (qc)
3533 ata_qc_timeout(qc);
3534 else {
1da177e4
LT		 3535 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3536 ap->id);
3537 goto out;
3538 }
3539
1da177e4
LT		 3540out:
3541 DPRINTK("EXIT\n");
3542}
3543
3544/**
3545 * ata_qc_new - Request an available ATA command, for queueing
3546 * @ap: Port associated with device @dev
3547 * @dev: Device from whom we request an available command structure
3548 *
3549 * LOCKING:
0cba632b 3550 * None.
1da177e4
LT		 3551 */
3552
3553static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3554{
3555 struct ata_queued_cmd *qc = NULL;
3556 unsigned int i;
3557
3558 for (i = 0; i < ATA_MAX_QUEUE; i++)
3559 if (!test_and_set_bit(i, &ap->qactive)) {
3560 qc = ata_qc_from_tag(ap, i);
3561 break;
3562 }
3563
3564 if (qc)
3565 qc->tag = i;
3566
3567 return qc;
3568}
3569
3570/**
3571 * ata_qc_new_init - Request an available ATA command, and initialize it
3572 * @ap: Port associated with device @dev
3573 * @dev: Device from whom we request an available command structure
3574 *
3575 * LOCKING:
0cba632b 3576 * None.
1da177e4
LT		 3577 */
3578
3579struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3580 struct ata_device *dev)
3581{
3582 struct ata_queued_cmd *qc;
3583
3584 qc = ata_qc_new(ap);
3585 if (qc) {
1da177e4
LT		 3586 qc->scsicmd = NULL;
3587 qc->ap = ap;
3588 qc->dev = dev;
1da177e4 3589
2c13b7ce 3590 ata_qc_reinit(qc);
1da177e4
LT		 3591 }
3592
3593 return qc;
3594}
3595
1da177e4
LT		 3596/**
3597 * ata_qc_free - free unused ata_queued_cmd
3598 * @qc: Command to complete
3599 *
3600 * Designed to free unused ata_queued_cmd object
3601 * in case something prevents using it.
3602 *
3603 * LOCKING:
0cba632b 3604 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3605 */
3606void ata_qc_free(struct ata_queued_cmd *qc)
3607{
4ba946e9
TH		 3608 struct ata_port *ap = qc->ap;
3609 unsigned int tag;
3610
1da177e4 3611 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3612
4ba946e9
TH		 3613 qc->flags = 0;
3614 tag = qc->tag;
3615 if (likely(ata_tag_valid(tag))) {
3616 if (tag == ap->active_tag)
3617 ap->active_tag = ATA_TAG_POISON;
3618 qc->tag = ATA_TAG_POISON;
3619 clear_bit(tag, &ap->qactive);
3620 }
1da177e4
LT		 3621}
3622
341963b9 3623inline void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 3624{
1da177e4
LT		 3625 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3626 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3627
3628 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3629 ata_sg_clean(qc);
3630
3f3791d3
AL		 3631 /* atapi: mark qc as inactive to prevent the interrupt handler
3632 * from completing the command twice later, before the error handler
3633 * is called. (when rc != 0 and atapi request sense is needed)
3634 */
3635 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3636
1da177e4 3637 /* call completion callback */
77853bf2 3638 qc->complete_fn(qc);
1da177e4
LT		 3639}
3640
341963b9
TH		 3641/**
3642 * ata_qc_complete - Complete an active ATA command
3643 * @qc: Command to complete
3644 * @err_mask: ATA Status register contents
3645 *
3646 * Indicate to the mid and upper layers that an ATA
3647 * command has completed, with either an ok or not-ok status.
3648 *
3649 * LOCKING:
3650 * spin_lock_irqsave(host_set lock)
3651 */
3652void ata_qc_complete(struct ata_queued_cmd *qc)
3653{
3654 if (unlikely(qc->flags & ATA_QCFLAG_EH_SCHEDULED))
3655 return;
3656
3657 __ata_qc_complete(qc);
3658}
3659
1da177e4
LT		 3660static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3661{
3662 struct ata_port *ap = qc->ap;
3663
3664 switch (qc->tf.protocol) {
3665 case ATA_PROT_DMA:
3666 case ATA_PROT_ATAPI_DMA:
3667 return 1;
3668
3669 case ATA_PROT_ATAPI:
3670 case ATA_PROT_PIO:
3671 case ATA_PROT_PIO_MULT:
3672 if (ap->flags & ATA_FLAG_PIO_DMA)
3673 return 1;
3674
3675 /* fall through */
3676
3677 default:
3678 return 0;
3679 }
3680
3681 /* never reached */
3682}
3683
3684/**
3685 * ata_qc_issue - issue taskfile to device
3686 * @qc: command to issue to device
3687 *
3688 * Prepare an ATA command to submission to device.
3689 * This includes mapping the data into a DMA-able
3690 * area, filling in the S/G table, and finally
3691 * writing the taskfile to hardware, starting the command.
3692 *
3693 * LOCKING:
3694 * spin_lock_irqsave(host_set lock)
3695 *
3696 * RETURNS:
9a3d9eb0 3697 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3698 */
3699
9a3d9eb0 3700unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 3701{
3702 struct ata_port *ap = qc->ap;
3703
3704 if (ata_should_dma_map(qc)) {
3705 if (qc->flags & ATA_QCFLAG_SG) {
3706 if (ata_sg_setup(qc))
8e436af9 3707 goto sg_err;
1da177e4
LT		 3708 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3709 if (ata_sg_setup_one(qc))
8e436af9 3710 goto sg_err;
1da177e4
LT		 3711 }
3712 } else {
3713 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3714 }
3715
3716 ap->ops->qc_prep(qc);
3717
3718 qc->ap->active_tag = qc->tag;
3719 qc->flags |= ATA_QCFLAG_ACTIVE;
3720
3721 return ap->ops->qc_issue(qc);
3722
8e436af9
TH		 3723sg_err:
3724 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 3725 return AC_ERR_SYSTEM;
1da177e4
LT		 3726}
3727
0baab86b 3728
1da177e4
LT		 3729/**
3730 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3731 * @qc: command to issue to device
3732 *
3733 * Using various libata functions and hooks, this function
3734 * starts an ATA command. ATA commands are grouped into
3735 * classes called "protocols", and issuing each type of protocol
3736 * is slightly different.
3737 *
0baab86b
EF		 3738 * May be used as the qc_issue() entry in ata_port_operations.
3739 *
1da177e4
LT		 3740 * LOCKING:
3741 * spin_lock_irqsave(host_set lock)
3742 *
3743 * RETURNS:
9a3d9eb0 3744 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3745 */
3746
9a3d9eb0 3747unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 3748{
3749 struct ata_port *ap = qc->ap;
3750
3751 ata_dev_select(ap, qc->dev->devno, 1, 0);
3752
3753 switch (qc->tf.protocol) {
3754 case ATA_PROT_NODATA:
e5338254 3755 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3756 break;
3757
3758 case ATA_PROT_DMA:
3759 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3760 ap->ops->bmdma_setup(qc); /* set up bmdma */
3761 ap->ops->bmdma_start(qc); /* initiate bmdma */
3762 break;
3763
3764 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3765 ata_qc_set_polling(qc);
e5338254 3766 ata_tf_to_host(ap, &qc->tf);
14be71f4 3767 ap->hsm_task_state = HSM_ST;
95064379 3768 ata_queue_pio_task(ap);
1da177e4
LT		 3769 break;
3770
3771 case ATA_PROT_ATAPI:
3772 ata_qc_set_polling(qc);
e5338254 3773 ata_tf_to_host(ap, &qc->tf);
95064379 3774 ata_queue_packet_task(ap);
1da177e4
LT		 3775 break;
3776
3777 case ATA_PROT_ATAPI_NODATA:
c1389503 3778 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3779 ata_tf_to_host(ap, &qc->tf);
95064379 3780 ata_queue_packet_task(ap);
1da177e4
LT		 3781 break;
3782
3783 case ATA_PROT_ATAPI_DMA:
c1389503 3784 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3785 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3786 ap->ops->bmdma_setup(qc); /* set up bmdma */
95064379 3787 ata_queue_packet_task(ap);
1da177e4
LT		 3788 break;
3789
3790 default:
3791 WARN_ON(1);
9a3d9eb0 3792 return AC_ERR_SYSTEM;
1da177e4
LT		 3793 }
3794
3795 return 0;
3796}
3797
3798/**
0baab86b 3799 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3800 * @qc: Info associated with this ATA transaction.
3801 *
3802 * LOCKING:
3803 * spin_lock_irqsave(host_set lock)
3804 */
3805
3806static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3807{
3808 struct ata_port *ap = qc->ap;
3809 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3810 u8 dmactl;
3811 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3812
3813 /* load PRD table addr. */
3814 mb(); /* make sure PRD table writes are visible to controller */
3815 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3816
3817 /* specify data direction, triple-check start bit is clear */
3818 dmactl = readb(mmio + ATA_DMA_CMD);
3819 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3820 if (!rw)
3821 dmactl |= ATA_DMA_WR;
3822 writeb(dmactl, mmio + ATA_DMA_CMD);
3823
3824 /* issue r/w command */
3825 ap->ops->exec_command(ap, &qc->tf);
3826}
3827
3828/**
b73fc89f 3829 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3830 * @qc: Info associated with this ATA transaction.
3831 *
3832 * LOCKING:
3833 * spin_lock_irqsave(host_set lock)
3834 */
3835
3836static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3837{
3838 struct ata_port *ap = qc->ap;
3839 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3840 u8 dmactl;
3841
3842 /* start host DMA transaction */
3843 dmactl = readb(mmio + ATA_DMA_CMD);
3844 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3845
3846 /* Strictly, one may wish to issue a readb() here, to
3847 * flush the mmio write. However, control also passes
3848 * to the hardware at this point, and it will interrupt
3849 * us when we are to resume control. So, in effect,
3850 * we don't care when the mmio write flushes.
3851 * Further, a read of the DMA status register _immediately_
3852 * following the write may not be what certain flaky hardware
3853 * is expected, so I think it is best to not add a readb()
3854 * without first all the MMIO ATA cards/mobos.
3855 * Or maybe I'm just being paranoid.
3856 */
3857}
3858
3859/**
3860 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3861 * @qc: Info associated with this ATA transaction.
3862 *
3863 * LOCKING:
3864 * spin_lock_irqsave(host_set lock)
3865 */
3866
3867static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3868{
3869 struct ata_port *ap = qc->ap;
3870 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3871 u8 dmactl;
3872
3873 /* load PRD table addr. */
3874 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3875
3876 /* specify data direction, triple-check start bit is clear */
3877 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3878 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3879 if (!rw)
3880 dmactl |= ATA_DMA_WR;
3881 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3882
3883 /* issue r/w command */
3884 ap->ops->exec_command(ap, &qc->tf);
3885}
3886
3887/**
3888 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3889 * @qc: Info associated with this ATA transaction.
3890 *
3891 * LOCKING:
3892 * spin_lock_irqsave(host_set lock)
3893 */
3894
3895static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3896{
3897 struct ata_port *ap = qc->ap;
3898 u8 dmactl;
3899
3900 /* start host DMA transaction */
3901 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3902 outb(dmactl | ATA_DMA_START,
3903 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3904}
3905
0baab86b
EF		 3906
3907/**
3908 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3909 * @qc: Info associated with this ATA transaction.
3910 *
3911 * Writes the ATA_DMA_START flag to the DMA command register.
3912 *
3913 * May be used as the bmdma_start() entry in ata_port_operations.
3914 *
3915 * LOCKING:
3916 * spin_lock_irqsave(host_set lock)
3917 */
1da177e4
LT		 3918void ata_bmdma_start(struct ata_queued_cmd *qc)
3919{
3920 if (qc->ap->flags & ATA_FLAG_MMIO)
3921 ata_bmdma_start_mmio(qc);
3922 else
3923 ata_bmdma_start_pio(qc);
3924}
3925
0baab86b
EF		 3926
3927/**
3928 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3929 * @qc: Info associated with this ATA transaction.
3930 *
3931 * Writes address of PRD table to device's PRD Table Address
3932 * register, sets the DMA control register, and calls
3933 * ops->exec_command() to start the transfer.
3934 *
3935 * May be used as the bmdma_setup() entry in ata_port_operations.
3936 *
3937 * LOCKING:
3938 * spin_lock_irqsave(host_set lock)
3939 */
1da177e4
LT		 3940void ata_bmdma_setup(struct ata_queued_cmd *qc)
3941{
3942 if (qc->ap->flags & ATA_FLAG_MMIO)
3943 ata_bmdma_setup_mmio(qc);
3944 else
3945 ata_bmdma_setup_pio(qc);
3946}
3947
0baab86b
EF		 3948
3949/**
3950 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3951 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3952 *
3953 * Clear interrupt and error flags in DMA status register.
3954 *
3955 * May be used as the irq_clear() entry in ata_port_operations.
3956 *
3957 * LOCKING:
3958 * spin_lock_irqsave(host_set lock)
3959 */
3960
1da177e4
LT		 3961void ata_bmdma_irq_clear(struct ata_port *ap)
3962{
3963 if (ap->flags & ATA_FLAG_MMIO) {
3964 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3965 writeb(readb(mmio), mmio);
3966 } else {
3967 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3968 outb(inb(addr), addr);
3969 }
3970
3971}
3972
0baab86b
EF		 3973
3974/**
3975 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3976 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3977 *
3978 * Read and return BMDMA status register.
3979 *
3980 * May be used as the bmdma_status() entry in ata_port_operations.
3981 *
3982 * LOCKING:
3983 * spin_lock_irqsave(host_set lock)
3984 */
3985
1da177e4
LT		 3986u8 ata_bmdma_status(struct ata_port *ap)
3987{
3988 u8 host_stat;
3989 if (ap->flags & ATA_FLAG_MMIO) {
3990 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3991 host_stat = readb(mmio + ATA_DMA_STATUS);
3992 } else
ee500aab 3993 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3994 return host_stat;
3995}
3996
0baab86b
EF		 3997
3998/**
3999 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4000 * @qc: Command we are ending DMA for
0baab86b
EF		 4001 *
4002 * Clears the ATA_DMA_START flag in the dma control register
4003 *
4004 * May be used as the bmdma_stop() entry in ata_port_operations.
4005 *
4006 * LOCKING:
4007 * spin_lock_irqsave(host_set lock)
4008 */
4009
b73fc89f 4010void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4011{
b73fc89f 4012 struct ata_port *ap = qc->ap;
1da177e4
LT		 4013 if (ap->flags & ATA_FLAG_MMIO) {
4014 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4015
4016 /* clear start/stop bit */
4017 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4018 mmio + ATA_DMA_CMD);
4019 } else {
4020 /* clear start/stop bit */
4021 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4022 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4023 }
4024
4025 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4026 ata_altstatus(ap); /* dummy read */
4027}
4028
4029/**
4030 * ata_host_intr - Handle host interrupt for given (port, task)
4031 * @ap: Port on which interrupt arrived (possibly...)
4032 * @qc: Taskfile currently active in engine
4033 *
4034 * Handle host interrupt for given queued command. Currently,
4035 * only DMA interrupts are handled. All other commands are
4036 * handled via polling with interrupts disabled (nIEN bit).
4037 *
4038 * LOCKING:
4039 * spin_lock_irqsave(host_set lock)
4040 *
4041 * RETURNS:
4042 * One if interrupt was handled, zero if not (shared irq).
4043 */
4044
4045inline unsigned int ata_host_intr (struct ata_port *ap,
4046 struct ata_queued_cmd *qc)
4047{
4048 u8 status, host_stat;
4049
4050 switch (qc->tf.protocol) {
4051
4052 case ATA_PROT_DMA:
4053 case ATA_PROT_ATAPI_DMA:
4054 case ATA_PROT_ATAPI:
4055 /* check status of DMA engine */
4056 host_stat = ap->ops->bmdma_status(ap);
4057 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4058
4059 /* if it's not our irq... */
4060 if (!(host_stat & ATA_DMA_INTR))
4061 goto idle_irq;
4062
4063 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4064 ap->ops->bmdma_stop(qc);
1da177e4
LT		 4065
4066 /* fall through */
4067
4068 case ATA_PROT_ATAPI_NODATA:
4069 case ATA_PROT_NODATA:
4070 /* check altstatus */
4071 status = ata_altstatus(ap);
4072 if (status & ATA_BUSY)
4073 goto idle_irq;
4074
4075 /* check main status, clearing INTRQ */
4076 status = ata_chk_status(ap);
4077 if (unlikely(status & ATA_BUSY))
4078 goto idle_irq;
4079 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4080 ap->id, qc->tf.protocol, status);
4081
4082 /* ack bmdma irq events */
4083 ap->ops->irq_clear(ap);
4084
4085 /* complete taskfile transaction */
a22e2eb0
AL		 4086 qc->err_mask |= ac_err_mask(status);
4087 ata_qc_complete(qc);
1da177e4
LT		 4088 break;
4089
4090 default:
4091 goto idle_irq;
4092 }
4093
4094 return 1; /* irq handled */
4095
4096idle_irq:
4097 ap->stats.idle_irq++;
4098
4099#ifdef ATA_IRQ_TRAP
4100 if ((ap->stats.idle_irq % 1000) == 0) {
4101 handled = 1;
4102 ata_irq_ack(ap, 0); /* debug trap */
4103 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4104 }
4105#endif
4106 return 0; /* irq not handled */
4107}
4108
4109/**
4110 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4111 * @irq: irq line (unused)
4112 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4113 * @regs: unused
4114 *
0cba632b
JG		 4115 * Default interrupt handler for PCI IDE devices. Calls
4116 * ata_host_intr() for each port that is not disabled.
4117 *
1da177e4 4118 * LOCKING:
0cba632b 4119 * Obtains host_set lock during operation.
1da177e4
LT		 4120 *
4121 * RETURNS:
0cba632b 4122 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4123 */
4124
4125irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4126{
4127 struct ata_host_set *host_set = dev_instance;
4128 unsigned int i;
4129 unsigned int handled = 0;
4130 unsigned long flags;
4131
4132 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4133 spin_lock_irqsave(&host_set->lock, flags);
4134
4135 for (i = 0; i < host_set->n_ports; i++) {
4136 struct ata_port *ap;
4137
4138 ap = host_set->ports[i];
c1389503
TH		 4139 if (ap &&
4140 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4141 struct ata_queued_cmd *qc;
4142
4143 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4144 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4145 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4146 handled |= ata_host_intr(ap, qc);
4147 }
4148 }
4149
4150 spin_unlock_irqrestore(&host_set->lock, flags);
4151
4152 return IRQ_RETVAL(handled);
4153}
4154
4155/**
4156 * atapi_packet_task - Write CDB bytes to hardware
4157 * @_data: Port to which ATAPI device is attached.
4158 *
4159 * When device has indicated its readiness to accept
4160 * a CDB, this function is called. Send the CDB.
4161 * If DMA is to be performed, exit immediately.
4162 * Otherwise, we are in polling mode, so poll
4163 * status under operation succeeds or fails.
4164 *
4165 * LOCKING:
4166 * Kernel thread context (may sleep)
4167 */
4168
4169static void atapi_packet_task(void *_data)
4170{
4171 struct ata_port *ap = _data;
4172 struct ata_queued_cmd *qc;
4173 u8 status;
4174
4175 qc = ata_qc_from_tag(ap, ap->active_tag);
4176 assert(qc != NULL);
4177 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4178
4179 /* sleep-wait for BSY to clear */
4180 DPRINTK("busy wait\n");
d8fe452b 4181 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
11a56d24 4182 qc->err_mask |= AC_ERR_TIMEOUT;
d8fe452b
AL		 4183 goto err_out;
4184 }
1da177e4
LT		 4185
4186 /* make sure DRQ is set */
4187 status = ata_chk_status(ap);
d8fe452b 4188 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
11a56d24 4189 qc->err_mask |= AC_ERR_HSM;
1da177e4 4190 goto err_out;
d8fe452b 4191 }
1da177e4
LT		 4192
4193 /* send SCSI cdb */
4194 DPRINTK("send cdb\n");
4195 assert(ap->cdb_len >= 12);
1da177e4 4196
c1389503
TH		 4197 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4198 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4199 unsigned long flags;
1da177e4 4200
c1389503
TH		 4201 /* Once we're done issuing command and kicking bmdma,
4202 * irq handler takes over. To not lose irq, we need
4203 * to clear NOINTR flag before sending cdb, but
4204 * interrupt handler shouldn't be invoked before we're
4205 * finished. Hence, the following locking.
4206 */
4207 spin_lock_irqsave(&ap->host_set->lock, flags);
4208 ap->flags &= ~ATA_FLAG_NOINTR;
4209 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4210 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4211 ap->ops->bmdma_start(qc); /* initiate bmdma */
4212 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4213 } else {
4214 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4215
c1389503 4216 /* PIO commands are handled by polling */
14be71f4 4217 ap->hsm_task_state = HSM_ST;
95064379 4218 ata_queue_pio_task(ap);
1da177e4
LT		 4219 }
4220
4221 return;
4222
4223err_out:
a22e2eb0 4224 ata_poll_qc_complete(qc);
1da177e4
LT		 4225}
4226
0baab86b 4227
9b847548
JA		 4228/*
4229 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4230 * without filling any other registers
4231 */
4232static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4233 u8 cmd)
4234{
4235 struct ata_taskfile tf;
4236 int err;
4237
4238 ata_tf_init(ap, &tf, dev->devno);
4239
4240 tf.command = cmd;
4241 tf.flags |= ATA_TFLAG_DEVICE;
4242 tf.protocol = ATA_PROT_NODATA;
4243
4244 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4245 if (err)
4246 printk(KERN_ERR "%s: ata command failed: %d\n",
4247 __FUNCTION__, err);
4248
4249 return err;
4250}
4251
4252static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4253{
4254 u8 cmd;
4255
4256 if (!ata_try_flush_cache(dev))
4257 return 0;
4258
4259 if (ata_id_has_flush_ext(dev->id))
4260 cmd = ATA_CMD_FLUSH_EXT;
4261 else
4262 cmd = ATA_CMD_FLUSH;
4263
4264 return ata_do_simple_cmd(ap, dev, cmd);
4265}
4266
4267static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4268{
4269 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4270}
4271
4272static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4273{
4274 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4275}
4276
4277/**
4278 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD		 4279 * @ap: port the device is connected to
4280 * @dev: the device to resume
9b847548
JA		 4281 *
4282 * Kick the drive back into action, by sending it an idle immediate
4283 * command and making sure its transfer mode matches between drive
4284 * and host.
4285 *
4286 */
4287int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4288{
4289 if (ap->flags & ATA_FLAG_SUSPENDED) {
4290 ap->flags &= ~ATA_FLAG_SUSPENDED;
4291 ata_set_mode(ap);
4292 }
4293 if (!ata_dev_present(dev))
4294 return 0;
4295 if (dev->class == ATA_DEV_ATA)
4296 ata_start_drive(ap, dev);
4297
4298 return 0;
4299}
4300
4301/**
4302 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD		 4303 * @ap: port the device is connected to
4304 * @dev: the device to suspend
9b847548
JA		 4305 *
4306 * Flush the cache on the drive, if appropriate, then issue a
4307 * standbynow command.
9b847548
JA		 4308 */
4309int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4310{
4311 if (!ata_dev_present(dev))
4312 return 0;
4313 if (dev->class == ATA_DEV_ATA)
4314 ata_flush_cache(ap, dev);
4315
4316 ata_standby_drive(ap, dev);
4317 ap->flags |= ATA_FLAG_SUSPENDED;
4318 return 0;
4319}
4320
c893a3ae
RD		 4321/**
4322 * ata_port_start - Set port up for dma.
4323 * @ap: Port to initialize
4324 *
4325 * Called just after data structures for each port are
4326 * initialized. Allocates space for PRD table.
4327 *
4328 * May be used as the port_start() entry in ata_port_operations.
4329 *
4330 * LOCKING:
4331 * Inherited from caller.
4332 */
4333
1da177e4
LT		 4334int ata_port_start (struct ata_port *ap)
4335{
4336 struct device *dev = ap->host_set->dev;
6037d6bb 4337 int rc;
1da177e4
LT		 4338
4339 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4340 if (!ap->prd)
4341 return -ENOMEM;
4342
6037d6bb
JG		 4343 rc = ata_pad_alloc(ap, dev);
4344 if (rc) {
cedc9a47 4345 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4346 return rc;
cedc9a47
JG		 4347 }
4348
1da177e4
LT		 4349 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4350
4351 return 0;
4352}
4353
0baab86b
EF		 4354
4355/**
4356 * ata_port_stop - Undo ata_port_start()
4357 * @ap: Port to shut down
4358 *
4359 * Frees the PRD table.
4360 *
4361 * May be used as the port_stop() entry in ata_port_operations.
4362 *
4363 * LOCKING:
6f0ef4fa 4364 * Inherited from caller.
0baab86b
EF		 4365 */
4366
1da177e4
LT		 4367void ata_port_stop (struct ata_port *ap)
4368{
4369 struct device *dev = ap->host_set->dev;
4370
4371 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4372 ata_pad_free(ap, dev);
1da177e4
LT		 4373}
4374
aa8f0dc6
JG		 4375void ata_host_stop (struct ata_host_set *host_set)
4376{
4377 if (host_set->mmio_base)
4378 iounmap(host_set->mmio_base);
4379}
4380
4381
1da177e4
LT		 4382/**
4383 * ata_host_remove - Unregister SCSI host structure with upper layers
4384 * @ap: Port to unregister
4385 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4386 *
4387 * LOCKING:
6f0ef4fa 4388 * Inherited from caller.
1da177e4
LT		 4389 */
4390
4391static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4392{
4393 struct Scsi_Host *sh = ap->host;
4394
4395 DPRINTK("ENTER\n");
4396
4397 if (do_unregister)
4398 scsi_remove_host(sh);
4399
4400 ap->ops->port_stop(ap);
4401}
4402
4403/**
4404 * ata_host_init - Initialize an ata_port structure
4405 * @ap: Structure to initialize
4406 * @host: associated SCSI mid-layer structure
4407 * @host_set: Collection of hosts to which @ap belongs
4408 * @ent: Probe information provided by low-level driver
4409 * @port_no: Port number associated with this ata_port
4410 *
0cba632b
JG		 4411 * Initialize a new ata_port structure, and its associated
4412 * scsi_host.
4413 *
1da177e4 4414 * LOCKING:
0cba632b 4415 * Inherited from caller.
1da177e4
LT		 4416 */
4417
4418static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4419 struct ata_host_set *host_set,
057ace5e 4420 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4421{
4422 unsigned int i;
4423
4424 host->max_id = 16;
4425 host->max_lun = 1;
4426 host->max_channel = 1;
4427 host->unique_id = ata_unique_id++;
4428 host->max_cmd_len = 12;
12413197 4429
1da177e4
LT		 4430 ap->flags = ATA_FLAG_PORT_DISABLED;
4431 ap->id = host->unique_id;
4432 ap->host = host;
4433 ap->ctl = ATA_DEVCTL_OBS;
4434 ap->host_set = host_set;
4435 ap->port_no = port_no;
4436 ap->hard_port_no =
4437 ent->legacy_mode ? ent->hard_port_no : port_no;
4438 ap->pio_mask = ent->pio_mask;
4439 ap->mwdma_mask = ent->mwdma_mask;
4440 ap->udma_mask = ent->udma_mask;
4441 ap->flags |= ent->host_flags;
4442 ap->ops = ent->port_ops;
4443 ap->cbl = ATA_CBL_NONE;
4444 ap->active_tag = ATA_TAG_POISON;
4445 ap->last_ctl = 0xFF;
4446
4447 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4448 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
a72ec4ce 4449 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT		 4450
4451 for (i = 0; i < ATA_MAX_DEVICES; i++)
4452 ap->device[i].devno = i;
4453
4454#ifdef ATA_IRQ_TRAP
4455 ap->stats.unhandled_irq = 1;
4456 ap->stats.idle_irq = 1;
4457#endif
4458
4459 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4460}
4461
4462/**
4463 * ata_host_add - Attach low-level ATA driver to system
4464 * @ent: Information provided by low-level driver
4465 * @host_set: Collections of ports to which we add
4466 * @port_no: Port number associated with this host
4467 *
0cba632b
JG		 4468 * Attach low-level ATA driver to system.
4469 *
1da177e4 4470 * LOCKING:
0cba632b 4471 * PCI/etc. bus probe sem.
1da177e4
LT		 4472 *
4473 * RETURNS:
0cba632b 4474 * New ata_port on success, for NULL on error.
1da177e4
LT		 4475 */
4476
057ace5e 4477static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4478 struct ata_host_set *host_set,
4479 unsigned int port_no)
4480{
4481 struct Scsi_Host *host;
4482 struct ata_port *ap;
4483 int rc;
4484
4485 DPRINTK("ENTER\n");
4486 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4487 if (!host)
4488 return NULL;
4489
4490 ap = (struct ata_port *) &host->hostdata[0];
4491
4492 ata_host_init(ap, host, host_set, ent, port_no);
4493
4494 rc = ap->ops->port_start(ap);
4495 if (rc)
4496 goto err_out;
4497
4498 return ap;
4499
4500err_out:
4501 scsi_host_put(host);
4502 return NULL;
4503}
4504
4505/**
0cba632b
JG		 4506 * ata_device_add - Register hardware device with ATA and SCSI layers
4507 * @ent: Probe information describing hardware device to be registered
4508 *
4509 * This function processes the information provided in the probe
4510 * information struct @ent, allocates the necessary ATA and SCSI
4511 * host information structures, initializes them, and registers
4512 * everything with requisite kernel subsystems.
4513 *
4514 * This function requests irqs, probes the ATA bus, and probes
4515 * the SCSI bus.
1da177e4
LT		 4516 *
4517 * LOCKING:
0cba632b 4518 * PCI/etc. bus probe sem.
1da177e4
LT		 4519 *
4520 * RETURNS:
0cba632b 4521 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4522 */
4523
057ace5e 4524int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4525{
4526 unsigned int count = 0, i;
4527 struct device *dev = ent->dev;
4528 struct ata_host_set *host_set;
4529
4530 DPRINTK("ENTER\n");
4531 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4532 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4533 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4534 if (!host_set)
4535 return 0;
1da177e4
LT		 4536 spin_lock_init(&host_set->lock);
4537
4538 host_set->dev = dev;
4539 host_set->n_ports = ent->n_ports;
4540 host_set->irq = ent->irq;
4541 host_set->mmio_base = ent->mmio_base;
4542 host_set->private_data = ent->private_data;
4543 host_set->ops = ent->port_ops;
4544
4545 /* register each port bound to this device */
4546 for (i = 0; i < ent->n_ports; i++) {
4547 struct ata_port *ap;
4548 unsigned long xfer_mode_mask;
4549
4550 ap = ata_host_add(ent, host_set, i);
4551 if (!ap)
4552 goto err_out;
4553
4554 host_set->ports[i] = ap;
4555 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4556 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4557 (ap->pio_mask << ATA_SHIFT_PIO);
4558
4559 /* print per-port info to dmesg */
4560 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4561 "bmdma 0x%lX irq %lu\n",
4562 ap->id,
4563 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4564 ata_mode_string(xfer_mode_mask),
4565 ap->ioaddr.cmd_addr,
4566 ap->ioaddr.ctl_addr,
4567 ap->ioaddr.bmdma_addr,
4568 ent->irq);
4569
4570 ata_chk_status(ap);
4571 host_set->ops->irq_clear(ap);
4572 count++;
4573 }
4574
57f3bda8
RD		 4575 if (!count)
4576 goto err_free_ret;
1da177e4
LT		 4577
4578 /* obtain irq, that is shared between channels */
4579 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4580 DRV_NAME, host_set))
4581 goto err_out;
4582
4583 /* perform each probe synchronously */
4584 DPRINTK("probe begin\n");
4585 for (i = 0; i < count; i++) {
4586 struct ata_port *ap;
4587 int rc;
4588
4589 ap = host_set->ports[i];
4590
c893a3ae 4591 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4592 rc = ata_bus_probe(ap);
c893a3ae 4593 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 4594
4595 if (rc) {
4596 /* FIXME: do something useful here?
4597 * Current libata behavior will
4598 * tear down everything when
4599 * the module is removed
4600 * or the h/w is unplugged.
4601 */
4602 }
4603
4604 rc = scsi_add_host(ap->host, dev);
4605 if (rc) {
4606 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4607 ap->id);
4608 /* FIXME: do something useful here */
4609 /* FIXME: handle unconditional calls to
4610 * scsi_scan_host and ata_host_remove, below,
4611 * at the very least
4612 */
4613 }
4614 }
4615
4616 /* probes are done, now scan each port's disk(s) */
c893a3ae 4617 DPRINTK("host probe begin\n");
1da177e4
LT		 4618 for (i = 0; i < count; i++) {
4619 struct ata_port *ap = host_set->ports[i];
4620
644dd0cc 4621 ata_scsi_scan_host(ap);
1da177e4
LT		 4622 }
4623
4624 dev_set_drvdata(dev, host_set);
4625
4626 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4627 return ent->n_ports; /* success */
4628
4629err_out:
4630 for (i = 0; i < count; i++) {
4631 ata_host_remove(host_set->ports[i], 1);
4632 scsi_host_put(host_set->ports[i]->host);
4633 }
57f3bda8 4634err_free_ret:
1da177e4
LT		 4635 kfree(host_set);
4636 VPRINTK("EXIT, returning 0\n");
4637 return 0;
4638}
4639
17b14451
AC		 4640/**
4641 * ata_host_set_remove - PCI layer callback for device removal
4642 * @host_set: ATA host set that was removed
4643 *
4644 * Unregister all objects associated with this host set. Free those
4645 * objects.
4646 *
4647 * LOCKING:
4648 * Inherited from calling layer (may sleep).
4649 */
4650
17b14451
AC		 4651void ata_host_set_remove(struct ata_host_set *host_set)
4652{
4653 struct ata_port *ap;
4654 unsigned int i;
4655
4656 for (i = 0; i < host_set->n_ports; i++) {
4657 ap = host_set->ports[i];
4658 scsi_remove_host(ap->host);
4659 }
4660
4661 free_irq(host_set->irq, host_set);
4662
4663 for (i = 0; i < host_set->n_ports; i++) {
4664 ap = host_set->ports[i];
4665
4666 ata_scsi_release(ap->host);
4667
4668 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4669 struct ata_ioports *ioaddr = &ap->ioaddr;
4670
4671 if (ioaddr->cmd_addr == 0x1f0)
4672 release_region(0x1f0, 8);
4673 else if (ioaddr->cmd_addr == 0x170)
4674 release_region(0x170, 8);
4675 }
4676
4677 scsi_host_put(ap->host);
4678 }
4679
4680 if (host_set->ops->host_stop)
4681 host_set->ops->host_stop(host_set);
4682
4683 kfree(host_set);
4684}
4685
1da177e4
LT		 4686/**
4687 * ata_scsi_release - SCSI layer callback hook for host unload
4688 * @host: libata host to be unloaded
4689 *
4690 * Performs all duties necessary to shut down a libata port...
4691 * Kill port kthread, disable port, and release resources.
4692 *
4693 * LOCKING:
4694 * Inherited from SCSI layer.
4695 *
4696 * RETURNS:
4697 * One.
4698 */
4699
4700int ata_scsi_release(struct Scsi_Host *host)
4701{
4702 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4703
4704 DPRINTK("ENTER\n");
4705
4706 ap->ops->port_disable(ap);
4707 ata_host_remove(ap, 0);
4708
4709 DPRINTK("EXIT\n");
4710 return 1;
4711}
4712
4713/**
4714 * ata_std_ports - initialize ioaddr with standard port offsets.
4715 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4716 *
4717 * Utility function which initializes data_addr, error_addr,
4718 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4719 * device_addr, status_addr, and command_addr to standard offsets
4720 * relative to cmd_addr.
4721 *
4722 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4723 */
0baab86b 4724
1da177e4
LT		 4725void ata_std_ports(struct ata_ioports *ioaddr)
4726{
4727 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4728 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4729 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4730 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4731 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4732 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4733 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4734 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4735 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4736 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4737}
4738
0baab86b 4739
374b1873
JG		 4740#ifdef CONFIG_PCI
4741
4742void ata_pci_host_stop (struct ata_host_set *host_set)
4743{
4744 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4745
4746 pci_iounmap(pdev, host_set->mmio_base);
4747}
4748
1da177e4
LT		 4749/**
4750 * ata_pci_remove_one - PCI layer callback for device removal
4751 * @pdev: PCI device that was removed
4752 *
4753 * PCI layer indicates to libata via this hook that
6f0ef4fa 4754 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4755 * Handle this by unregistering all objects associated
4756 * with this PCI device. Free those objects. Then finally
4757 * release PCI resources and disable device.
4758 *
4759 * LOCKING:
4760 * Inherited from PCI layer (may sleep).
4761 */
4762
4763void ata_pci_remove_one (struct pci_dev *pdev)
4764{
4765 struct device *dev = pci_dev_to_dev(pdev);
4766 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4767
17b14451 4768 ata_host_set_remove(host_set);
1da177e4
LT		 4769 pci_release_regions(pdev);
4770 pci_disable_device(pdev);
4771 dev_set_drvdata(dev, NULL);
4772}
4773
4774/* move to PCI subsystem */
057ace5e 4775int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4776{
4777 unsigned long tmp = 0;
4778
4779 switch (bits->width) {
4780 case 1: {
4781 u8 tmp8 = 0;
4782 pci_read_config_byte(pdev, bits->reg, &tmp8);
4783 tmp = tmp8;
4784 break;
4785 }
4786 case 2: {
4787 u16 tmp16 = 0;
4788 pci_read_config_word(pdev, bits->reg, &tmp16);
4789 tmp = tmp16;
4790 break;
4791 }
4792 case 4: {
4793 u32 tmp32 = 0;
4794 pci_read_config_dword(pdev, bits->reg, &tmp32);
4795 tmp = tmp32;
4796 break;
4797 }
4798
4799 default:
4800 return -EINVAL;
4801 }
4802
4803 tmp &= bits->mask;
4804
4805 return (tmp == bits->val) ? 1 : 0;
4806}
9b847548
JA		 4807
4808int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
4809{
4810 pci_save_state(pdev);
4811 pci_disable_device(pdev);
4812 pci_set_power_state(pdev, PCI_D3hot);
4813 return 0;
4814}
4815
4816int ata_pci_device_resume(struct pci_dev *pdev)
4817{
4818 pci_set_power_state(pdev, PCI_D0);
4819 pci_restore_state(pdev);
4820 pci_enable_device(pdev);
4821 pci_set_master(pdev);
4822 return 0;
4823}
1da177e4
LT		 4824#endif /* CONFIG_PCI */
4825
4826
1da177e4
LT		 4827static int __init ata_init(void)
4828{
4829 ata_wq = create_workqueue("ata");
4830 if (!ata_wq)
4831 return -ENOMEM;
4832
4833 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4834 return 0;
4835}
4836
4837static void __exit ata_exit(void)
4838{
4839 destroy_workqueue(ata_wq);
4840}
4841
4842module_init(ata_init);
4843module_exit(ata_exit);
4844
67846b30
JG		 4845static unsigned long ratelimit_time;
4846static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4847
4848int ata_ratelimit(void)
4849{
4850 int rc;
4851 unsigned long flags;
4852
4853 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4854
4855 if (time_after(jiffies, ratelimit_time)) {
4856 rc = 1;
4857 ratelimit_time = jiffies + (HZ/5);
4858 } else
4859 rc = 0;
4860
4861 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4862
4863 return rc;
4864}
4865
1da177e4
LT		 4866/*
4867 * libata is essentially a library of internal helper functions for
4868 * low-level ATA host controller drivers. As such, the API/ABI is
4869 * likely to change as new drivers are added and updated.
4870 * Do not depend on ABI/API stability.
4871 */
4872
4873EXPORT_SYMBOL_GPL(ata_std_bios_param);
4874EXPORT_SYMBOL_GPL(ata_std_ports);
4875EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4876EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4877EXPORT_SYMBOL_GPL(ata_sg_init);
4878EXPORT_SYMBOL_GPL(ata_sg_init_one);
4879EXPORT_SYMBOL_GPL(ata_qc_complete);
4880EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4881EXPORT_SYMBOL_GPL(ata_eng_timeout);
4882EXPORT_SYMBOL_GPL(ata_tf_load);
4883EXPORT_SYMBOL_GPL(ata_tf_read);
4884EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4885EXPORT_SYMBOL_GPL(ata_std_dev_select);
4886EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4887EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4888EXPORT_SYMBOL_GPL(ata_check_status);
4889EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4890EXPORT_SYMBOL_GPL(ata_exec_command);
4891EXPORT_SYMBOL_GPL(ata_port_start);
4892EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4893EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4894EXPORT_SYMBOL_GPL(ata_interrupt);
4895EXPORT_SYMBOL_GPL(ata_qc_prep);
4896EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4897EXPORT_SYMBOL_GPL(ata_bmdma_start);
4898EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4899EXPORT_SYMBOL_GPL(ata_bmdma_status);
4900EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4901EXPORT_SYMBOL_GPL(ata_port_probe);
4902EXPORT_SYMBOL_GPL(sata_phy_reset);
4903EXPORT_SYMBOL_GPL(__sata_phy_reset);
4904EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 4905EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 4906EXPORT_SYMBOL_GPL(ata_std_softreset);
4907EXPORT_SYMBOL_GPL(sata_std_hardreset);
4908EXPORT_SYMBOL_GPL(ata_std_postreset);
4909EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 4910EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
1da177e4 4911EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4912EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 4913EXPORT_SYMBOL_GPL(ata_busy_sleep);
1da177e4
LT		 4914EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4915EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
4916EXPORT_SYMBOL_GPL(ata_scsi_error);
4917EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4918EXPORT_SYMBOL_GPL(ata_scsi_release);
4919EXPORT_SYMBOL_GPL(ata_host_intr);
4920EXPORT_SYMBOL_GPL(ata_dev_classify);
4921EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4922EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4 4923EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH		 4924EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
4925EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 4926
1bc4ccff 4927EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 4928EXPORT_SYMBOL_GPL(ata_timing_compute);
4929EXPORT_SYMBOL_GPL(ata_timing_merge);
4930
1da177e4
LT		 4931#ifdef CONFIG_PCI
4932EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 4933EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 4934EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
4935EXPORT_SYMBOL_GPL(ata_pci_init_one);
4936EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 4937EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
4938EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 4939#endif /* CONFIG_PCI */
9b847548
JA		 4940
4941EXPORT_SYMBOL_GPL(ata_device_suspend);
4942EXPORT_SYMBOL_GPL(ata_device_resume);
4943EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
4944EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
Linux kernel - Deliverables
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