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[PATCH] ata_piix: kill spurious assignment in piix_sata_probe()
[deliverable/linux.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
59a10b17 64static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 65static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 68static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 69static int fgb(u32 bitmap);
057ace5e 70static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 71 u8 *xfer_mode_out,
72 unsigned int *xfer_shift_out);
1da177e4
LT		 73
74static unsigned int ata_unique_id = 1;
75static struct workqueue_struct *ata_wq;
76
1623c81e
JG		 77int atapi_enabled = 0;
78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
1da177e4
LT		 81MODULE_AUTHOR("Jeff Garzik");
82MODULE_DESCRIPTION("Library module for ATA devices");
83MODULE_LICENSE("GPL");
84MODULE_VERSION(DRV_VERSION);
85
0baab86b 86
1da177e4
LT		 87/**
88 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
89 * @tf: Taskfile to convert
90 * @fis: Buffer into which data will output
91 * @pmp: Port multiplier port
92 *
93 * Converts a standard ATA taskfile to a Serial ATA
94 * FIS structure (Register - Host to Device).
95 *
96 * LOCKING:
97 * Inherited from caller.
98 */
99
057ace5e 100void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 101{
102 fis[0] = 0x27; /* Register - Host to Device FIS */
103 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
104 bit 7 indicates Command FIS */
105 fis[2] = tf->command;
106 fis[3] = tf->feature;
107
108 fis[4] = tf->lbal;
109 fis[5] = tf->lbam;
110 fis[6] = tf->lbah;
111 fis[7] = tf->device;
112
113 fis[8] = tf->hob_lbal;
114 fis[9] = tf->hob_lbam;
115 fis[10] = tf->hob_lbah;
116 fis[11] = tf->hob_feature;
117
118 fis[12] = tf->nsect;
119 fis[13] = tf->hob_nsect;
120 fis[14] = 0;
121 fis[15] = tf->ctl;
122
123 fis[16] = 0;
124 fis[17] = 0;
125 fis[18] = 0;
126 fis[19] = 0;
127}
128
129/**
130 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
131 * @fis: Buffer from which data will be input
132 * @tf: Taskfile to output
133 *
e12a1be6 134 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 135 *
136 * LOCKING:
137 * Inherited from caller.
138 */
139
057ace5e 140void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 141{
142 tf->command = fis[2]; /* status */
143 tf->feature = fis[3]; /* error */
144
145 tf->lbal = fis[4];
146 tf->lbam = fis[5];
147 tf->lbah = fis[6];
148 tf->device = fis[7];
149
150 tf->hob_lbal = fis[8];
151 tf->hob_lbam = fis[9];
152 tf->hob_lbah = fis[10];
153
154 tf->nsect = fis[12];
155 tf->hob_nsect = fis[13];
156}
157
8cbd6df1
AL		 158static const u8 ata_rw_cmds[] = {
159 /* pio multi */
160 ATA_CMD_READ_MULTI,
161 ATA_CMD_WRITE_MULTI,
162 ATA_CMD_READ_MULTI_EXT,
163 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 164 0,
165 0,
166 0,
167 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 168 /* pio */
169 ATA_CMD_PIO_READ,
170 ATA_CMD_PIO_WRITE,
171 ATA_CMD_PIO_READ_EXT,
172 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 173 0,
174 0,
175 0,
176 0,
8cbd6df1
AL		 177 /* dma */
178 ATA_CMD_READ,
179 ATA_CMD_WRITE,
180 ATA_CMD_READ_EXT,
9a3dccc4
TH		 181 ATA_CMD_WRITE_EXT,
182 0,
183 0,
184 0,
185 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 186};
1da177e4
LT		 187
188/**
8cbd6df1
AL		 189 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
190 * @qc: command to examine and configure
1da177e4 191 *
8cbd6df1
AL		 192 * Examine the device configuration and tf->flags to calculate
193 * the proper read/write commands and protocol to use.
1da177e4
LT		 194 *
195 * LOCKING:
196 * caller.
197 */
9a3dccc4 198int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 199{
8cbd6df1
AL		 200 struct ata_taskfile *tf = &qc->tf;
201 struct ata_device *dev = qc->dev;
9a3dccc4 202 u8 cmd;
1da177e4 203
9a3dccc4 204 int index, fua, lba48, write;
8cbd6df1 205
9a3dccc4 206 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 207 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
208 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 209
8cbd6df1
AL		 210 if (dev->flags & ATA_DFLAG_PIO) {
211 tf->protocol = ATA_PROT_PIO;
9a3dccc4 212 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 213 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
214 /* Unable to use DMA due to host limitation */
215 tf->protocol = ATA_PROT_PIO;
216 index = dev->multi_count ? 0 : 4;
8cbd6df1
AL		 217 } else {
218 tf->protocol = ATA_PROT_DMA;
9a3dccc4 219 index = 16;
8cbd6df1 220 }
1da177e4 221
9a3dccc4
TH		 222 cmd = ata_rw_cmds[index + fua + lba48 + write];
223 if (cmd) {
224 tf->command = cmd;
225 return 0;
226 }
227 return -1;
1da177e4
LT		 228}
229
98ac62de 230static const char * const xfer_mode_str[] = {
1da177e4
LT		 231 "UDMA/16",
232 "UDMA/25",
233 "UDMA/33",
234 "UDMA/44",
235 "UDMA/66",
236 "UDMA/100",
237 "UDMA/133",
238 "UDMA7",
239 "MWDMA0",
240 "MWDMA1",
241 "MWDMA2",
242 "PIO0",
243 "PIO1",
244 "PIO2",
245 "PIO3",
246 "PIO4",
247};
248
249/**
250 * ata_udma_string - convert UDMA bit offset to string
251 * @mask: mask of bits supported; only highest bit counts.
252 *
253 * Determine string which represents the highest speed
254 * (highest bit in @udma_mask).
255 *
256 * LOCKING:
257 * None.
258 *
259 * RETURNS:
260 * Constant C string representing highest speed listed in
261 * @udma_mask, or the constant C string "<n/a>".
262 */
263
264static const char *ata_mode_string(unsigned int mask)
265{
266 int i;
267
268 for (i = 7; i >= 0; i--)
269 if (mask & (1 << i))
270 goto out;
271 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
272 if (mask & (1 << i))
273 goto out;
274 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
275 if (mask & (1 << i))
276 goto out;
277
278 return "<n/a>";
279
280out:
281 return xfer_mode_str[i];
282}
283
284/**
285 * ata_pio_devchk - PATA device presence detection
286 * @ap: ATA channel to examine
287 * @device: Device to examine (starting at zero)
288 *
289 * This technique was originally described in
290 * Hale Landis's ATADRVR (www.ata-atapi.com), and
291 * later found its way into the ATA/ATAPI spec.
292 *
293 * Write a pattern to the ATA shadow registers,
294 * and if a device is present, it will respond by
295 * correctly storing and echoing back the
296 * ATA shadow register contents.
297 *
298 * LOCKING:
299 * caller.
300 */
301
302static unsigned int ata_pio_devchk(struct ata_port *ap,
303 unsigned int device)
304{
305 struct ata_ioports *ioaddr = &ap->ioaddr;
306 u8 nsect, lbal;
307
308 ap->ops->dev_select(ap, device);
309
310 outb(0x55, ioaddr->nsect_addr);
311 outb(0xaa, ioaddr->lbal_addr);
312
313 outb(0xaa, ioaddr->nsect_addr);
314 outb(0x55, ioaddr->lbal_addr);
315
316 outb(0x55, ioaddr->nsect_addr);
317 outb(0xaa, ioaddr->lbal_addr);
318
319 nsect = inb(ioaddr->nsect_addr);
320 lbal = inb(ioaddr->lbal_addr);
321
322 if ((nsect == 0x55) && (lbal == 0xaa))
323 return 1; /* we found a device */
324
325 return 0; /* nothing found */
326}
327
328/**
329 * ata_mmio_devchk - PATA device presence detection
330 * @ap: ATA channel to examine
331 * @device: Device to examine (starting at zero)
332 *
333 * This technique was originally described in
334 * Hale Landis's ATADRVR (www.ata-atapi.com), and
335 * later found its way into the ATA/ATAPI spec.
336 *
337 * Write a pattern to the ATA shadow registers,
338 * and if a device is present, it will respond by
339 * correctly storing and echoing back the
340 * ATA shadow register contents.
341 *
342 * LOCKING:
343 * caller.
344 */
345
346static unsigned int ata_mmio_devchk(struct ata_port *ap,
347 unsigned int device)
348{
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350 u8 nsect, lbal;
351
352 ap->ops->dev_select(ap, device);
353
354 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
355 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
356
357 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
358 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
359
360 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
361 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
362
363 nsect = readb((void __iomem *) ioaddr->nsect_addr);
364 lbal = readb((void __iomem *) ioaddr->lbal_addr);
365
366 if ((nsect == 0x55) && (lbal == 0xaa))
367 return 1; /* we found a device */
368
369 return 0; /* nothing found */
370}
371
372/**
373 * ata_devchk - PATA device presence detection
374 * @ap: ATA channel to examine
375 * @device: Device to examine (starting at zero)
376 *
377 * Dispatch ATA device presence detection, depending
378 * on whether we are using PIO or MMIO to talk to the
379 * ATA shadow registers.
380 *
381 * LOCKING:
382 * caller.
383 */
384
385static unsigned int ata_devchk(struct ata_port *ap,
386 unsigned int device)
387{
388 if (ap->flags & ATA_FLAG_MMIO)
389 return ata_mmio_devchk(ap, device);
390 return ata_pio_devchk(ap, device);
391}
392
393/**
394 * ata_dev_classify - determine device type based on ATA-spec signature
395 * @tf: ATA taskfile register set for device to be identified
396 *
397 * Determine from taskfile register contents whether a device is
398 * ATA or ATAPI, as per "Signature and persistence" section
399 * of ATA/PI spec (volume 1, sect 5.14).
400 *
401 * LOCKING:
402 * None.
403 *
404 * RETURNS:
405 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
406 * the event of failure.
407 */
408
057ace5e 409unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 410{
411 /* Apple's open source Darwin code hints that some devices only
412 * put a proper signature into the LBA mid/high registers,
413 * So, we only check those. It's sufficient for uniqueness.
414 */
415
416 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
417 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
418 DPRINTK("found ATA device by sig\n");
419 return ATA_DEV_ATA;
420 }
421
422 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
423 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
424 DPRINTK("found ATAPI device by sig\n");
425 return ATA_DEV_ATAPI;
426 }
427
428 DPRINTK("unknown device\n");
429 return ATA_DEV_UNKNOWN;
430}
431
432/**
433 * ata_dev_try_classify - Parse returned ATA device signature
434 * @ap: ATA channel to examine
435 * @device: Device to examine (starting at zero)
b4dc7623 436 * @r_err: Value of error register on completion
1da177e4
LT		 437 *
438 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
439 * an ATA/ATAPI-defined set of values is placed in the ATA
440 * shadow registers, indicating the results of device detection
441 * and diagnostics.
442 *
443 * Select the ATA device, and read the values from the ATA shadow
444 * registers. Then parse according to the Error register value,
445 * and the spec-defined values examined by ata_dev_classify().
446 *
447 * LOCKING:
448 * caller.
b4dc7623
TH		 449 *
450 * RETURNS:
451 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 452 */
453
b4dc7623
TH		 454static unsigned int
455ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 456{
1da177e4
LT		 457 struct ata_taskfile tf;
458 unsigned int class;
459 u8 err;
460
461 ap->ops->dev_select(ap, device);
462
463 memset(&tf, 0, sizeof(tf));
464
1da177e4 465 ap->ops->tf_read(ap, &tf);
0169e284 466 err = tf.feature;
b4dc7623
TH		 467 if (r_err)
468 *r_err = err;
1da177e4
LT		 469
470 /* see if device passed diags */
471 if (err == 1)
472 /* do nothing */ ;
473 else if ((device == 0) && (err == 0x81))
474 /* do nothing */ ;
475 else
b4dc7623 476 return ATA_DEV_NONE;
1da177e4 477
b4dc7623 478 /* determine if device is ATA or ATAPI */
1da177e4 479 class = ata_dev_classify(&tf);
b4dc7623 480
1da177e4 481 if (class == ATA_DEV_UNKNOWN)
b4dc7623 482 return ATA_DEV_NONE;
1da177e4 483 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 484 return ATA_DEV_NONE;
485 return class;
1da177e4
LT		 486}
487
488/**
489 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
490 * @id: IDENTIFY DEVICE results we will examine
491 * @s: string into which data is output
492 * @ofs: offset into identify device page
493 * @len: length of string to return. must be an even number.
494 *
495 * The strings in the IDENTIFY DEVICE page are broken up into
496 * 16-bit chunks. Run through the string, and output each
497 * 8-bit chunk linearly, regardless of platform.
498 *
499 * LOCKING:
500 * caller.
501 */
502
057ace5e 503void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 504 unsigned int ofs, unsigned int len)
505{
506 unsigned int c;
507
508 while (len > 0) {
509 c = id[ofs] >> 8;
510 *s = c;
511 s++;
512
513 c = id[ofs] & 0xff;
514 *s = c;
515 s++;
516
517 ofs++;
518 len -= 2;
519 }
520}
521
0baab86b
EF		 522
523/**
524 * ata_noop_dev_select - Select device 0/1 on ATA bus
525 * @ap: ATA channel to manipulate
526 * @device: ATA device (numbered from zero) to select
527 *
528 * This function performs no actual function.
529 *
530 * May be used as the dev_select() entry in ata_port_operations.
531 *
532 * LOCKING:
533 * caller.
534 */
1da177e4
LT		 535void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
536{
537}
538
0baab86b 539
1da177e4
LT		 540/**
541 * ata_std_dev_select - Select device 0/1 on ATA bus
542 * @ap: ATA channel to manipulate
543 * @device: ATA device (numbered from zero) to select
544 *
545 * Use the method defined in the ATA specification to
546 * make either device 0, or device 1, active on the
0baab86b
EF		 547 * ATA channel. Works with both PIO and MMIO.
548 *
549 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 550 *
551 * LOCKING:
552 * caller.
553 */
554
555void ata_std_dev_select (struct ata_port *ap, unsigned int device)
556{
557 u8 tmp;
558
559 if (device == 0)
560 tmp = ATA_DEVICE_OBS;
561 else
562 tmp = ATA_DEVICE_OBS | ATA_DEV1;
563
564 if (ap->flags & ATA_FLAG_MMIO) {
565 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
566 } else {
567 outb(tmp, ap->ioaddr.device_addr);
568 }
569 ata_pause(ap); /* needed; also flushes, for mmio */
570}
571
572/**
573 * ata_dev_select - Select device 0/1 on ATA bus
574 * @ap: ATA channel to manipulate
575 * @device: ATA device (numbered from zero) to select
576 * @wait: non-zero to wait for Status register BSY bit to clear
577 * @can_sleep: non-zero if context allows sleeping
578 *
579 * Use the method defined in the ATA specification to
580 * make either device 0, or device 1, active on the
581 * ATA channel.
582 *
583 * This is a high-level version of ata_std_dev_select(),
584 * which additionally provides the services of inserting
585 * the proper pauses and status polling, where needed.
586 *
587 * LOCKING:
588 * caller.
589 */
590
591void ata_dev_select(struct ata_port *ap, unsigned int device,
592 unsigned int wait, unsigned int can_sleep)
593{
594 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
595 ap->id, device, wait);
596
597 if (wait)
598 ata_wait_idle(ap);
599
600 ap->ops->dev_select(ap, device);
601
602 if (wait) {
603 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
604 msleep(150);
605 ata_wait_idle(ap);
606 }
607}
608
609/**
610 * ata_dump_id - IDENTIFY DEVICE info debugging output
611 * @dev: Device whose IDENTIFY DEVICE page we will dump
612 *
613 * Dump selected 16-bit words from a detected device's
614 * IDENTIFY PAGE page.
615 *
616 * LOCKING:
617 * caller.
618 */
619
057ace5e 620static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 621{
622 DPRINTK("49==0x%04x "
623 "53==0x%04x "
624 "63==0x%04x "
625 "64==0x%04x "
626 "75==0x%04x \n",
627 dev->id[49],
628 dev->id[53],
629 dev->id[63],
630 dev->id[64],
631 dev->id[75]);
632 DPRINTK("80==0x%04x "
633 "81==0x%04x "
634 "82==0x%04x "
635 "83==0x%04x "
636 "84==0x%04x \n",
637 dev->id[80],
638 dev->id[81],
639 dev->id[82],
640 dev->id[83],
641 dev->id[84]);
642 DPRINTK("88==0x%04x "
643 "93==0x%04x\n",
644 dev->id[88],
645 dev->id[93]);
646}
647
11e29e21
AC		 648/*
649 * Compute the PIO modes available for this device. This is not as
650 * trivial as it seems if we must consider early devices correctly.
651 *
652 * FIXME: pre IDE drive timing (do we care ?).
653 */
654
057ace5e 655static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 656{
657 u16 modes;
658
ffa29456
AC		 659 /* Usual case. Word 53 indicates word 64 is valid */
660 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 1)) {
11e29e21
AC		 661 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
662 modes <<= 3;
663 modes |= 0x7;
664 return modes;
665 }
666
ffa29456
AC		 667 /* If word 64 isn't valid then Word 51 high byte holds the PIO timing
668 number for the maximum. Turn it into a mask and return it */
669 modes = (2 << ((adev->id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF)) - 1 ;
11e29e21 670 return modes;
ffa29456
AC		 671 /* But wait.. there's more. Design your standards by committee and
672 you too can get a free iordy field to process. However its the
673 speeds not the modes that are supported... Note drivers using the
674 timing API will get this right anyway */
11e29e21
AC		 675}
676
95064379
TH		 677static inline void
678ata_queue_packet_task(struct ata_port *ap)
679{
c18d06f8
TH		 680 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
681 queue_work(ata_wq, &ap->packet_task);
95064379
TH		 682}
683
684static inline void
685ata_queue_pio_task(struct ata_port *ap)
686{
c18d06f8
TH		 687 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
688 queue_work(ata_wq, &ap->pio_task);
95064379
TH		 689}
690
691static inline void
692ata_queue_delayed_pio_task(struct ata_port *ap, unsigned long delay)
693{
c18d06f8
TH		 694 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
695 queue_delayed_work(ata_wq, &ap->pio_task, delay);
696}
697
698/**
699 * ata_flush_pio_tasks - Flush pio_task and packet_task
700 * @ap: the target ata_port
701 *
702 * After this function completes, pio_task and packet_task are
703 * guranteed not to be running or scheduled.
704 *
705 * LOCKING:
706 * Kernel thread context (may sleep)
707 */
708
709static void ata_flush_pio_tasks(struct ata_port *ap)
710{
711 int tmp = 0;
712 unsigned long flags;
713
714 DPRINTK("ENTER\n");
715
716 spin_lock_irqsave(&ap->host_set->lock, flags);
717 ap->flags |= ATA_FLAG_FLUSH_PIO_TASK;
718 spin_unlock_irqrestore(&ap->host_set->lock, flags);
719
720 DPRINTK("flush #1\n");
721 flush_workqueue(ata_wq);
722
723 /*
724 * At this point, if a task is running, it's guaranteed to see
725 * the FLUSH flag; thus, it will never queue pio tasks again.
726 * Cancel and flush.
727 */
728 tmp |= cancel_delayed_work(&ap->pio_task);
729 tmp |= cancel_delayed_work(&ap->packet_task);
730 if (!tmp) {
731 DPRINTK("flush #2\n");
732 flush_workqueue(ata_wq);
733 }
734
735 spin_lock_irqsave(&ap->host_set->lock, flags);
736 ap->flags &= ~ATA_FLAG_FLUSH_PIO_TASK;
737 spin_unlock_irqrestore(&ap->host_set->lock, flags);
738
739 DPRINTK("EXIT\n");
95064379
TH		 740}
741
77853bf2 742void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 743{
77853bf2 744 struct completion *waiting = qc->private_data;
a2a7a662 745
77853bf2 746 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 747 complete(waiting);
a2a7a662
TH		 748}
749
750/**
751 * ata_exec_internal - execute libata internal command
752 * @ap: Port to which the command is sent
753 * @dev: Device to which the command is sent
754 * @tf: Taskfile registers for the command and the result
755 * @dma_dir: Data tranfer direction of the command
756 * @buf: Data buffer of the command
757 * @buflen: Length of data buffer
758 *
759 * Executes libata internal command with timeout. @tf contains
760 * command on entry and result on return. Timeout and error
761 * conditions are reported via return value. No recovery action
762 * is taken after a command times out. It's caller's duty to
763 * clean up after timeout.
764 *
765 * LOCKING:
766 * None. Should be called with kernel context, might sleep.
767 */
768
769static unsigned
770ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
771 struct ata_taskfile *tf,
772 int dma_dir, void *buf, unsigned int buflen)
773{
774 u8 command = tf->command;
775 struct ata_queued_cmd *qc;
776 DECLARE_COMPLETION(wait);
777 unsigned long flags;
77853bf2 778 unsigned int err_mask;
a2a7a662
TH		 779
780 spin_lock_irqsave(&ap->host_set->lock, flags);
781
782 qc = ata_qc_new_init(ap, dev);
783 BUG_ON(qc == NULL);
784
785 qc->tf = *tf;
786 qc->dma_dir = dma_dir;
787 if (dma_dir != DMA_NONE) {
788 ata_sg_init_one(qc, buf, buflen);
789 qc->nsect = buflen / ATA_SECT_SIZE;
790 }
791
77853bf2 792 qc->private_data = &wait;
a2a7a662
TH		 793 qc->complete_fn = ata_qc_complete_internal;
794
9a3d9eb0
TH		 795 qc->err_mask = ata_qc_issue(qc);
796 if (qc->err_mask)
8e436af9 797 ata_qc_complete(qc);
a2a7a662
TH		 798
799 spin_unlock_irqrestore(&ap->host_set->lock, flags);
800
801 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
802 spin_lock_irqsave(&ap->host_set->lock, flags);
803
804 /* We're racing with irq here. If we lose, the
805 * following test prevents us from completing the qc
806 * again. If completion irq occurs after here but
807 * before the caller cleans up, it will result in a
808 * spurious interrupt. We can live with that.
809 */
77853bf2 810 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 811 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH		 812 ata_qc_complete(qc);
813 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
814 ap->id, command);
815 }
816
817 spin_unlock_irqrestore(&ap->host_set->lock, flags);
818 }
819
77853bf2
TH		 820 *tf = qc->tf;
821 err_mask = qc->err_mask;
822
823 ata_qc_free(qc);
824
825 return err_mask;
a2a7a662
TH		 826}
827
1bc4ccff
AC		 828/**
829 * ata_pio_need_iordy - check if iordy needed
830 * @adev: ATA device
831 *
832 * Check if the current speed of the device requires IORDY. Used
833 * by various controllers for chip configuration.
834 */
835
836unsigned int ata_pio_need_iordy(const struct ata_device *adev)
837{
838 int pio;
839 int speed = adev->pio_mode - XFER_PIO_0;
840
841 if (speed < 2)
842 return 0;
843 if (speed > 2)
844 return 1;
845
846 /* If we have no drive specific rule, then PIO 2 is non IORDY */
847
848 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
849 pio = adev->id[ATA_ID_EIDE_PIO];
850 /* Is the speed faster than the drive allows non IORDY ? */
851 if (pio) {
852 /* This is cycle times not frequency - watch the logic! */
853 if (pio > 240) /* PIO2 is 240nS per cycle */
854 return 1;
855 return 0;
856 }
857 }
858 return 0;
859}
860
1da177e4
LT		 861/**
862 * ata_dev_identify - obtain IDENTIFY x DEVICE page
863 * @ap: port on which device we wish to probe resides
864 * @device: device bus address, starting at zero
865 *
866 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
867 * command, and read back the 512-byte device information page.
868 * The device information page is fed to us via the standard
869 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
870 * using standard PIO-IN paths)
871 *
872 * After reading the device information page, we use several
873 * bits of information from it to initialize data structures
874 * that will be used during the lifetime of the ata_device.
875 * Other data from the info page is used to disqualify certain
876 * older ATA devices we do not wish to support.
877 *
878 * LOCKING:
879 * Inherited from caller. Some functions called by this function
880 * obtain the host_set lock.
881 */
882
883static void ata_dev_identify(struct ata_port *ap, unsigned int device)
884{
885 struct ata_device *dev = &ap->device[device];
8bf62ece 886 unsigned int major_version;
1da177e4
LT		 887 u16 tmp;
888 unsigned long xfer_modes;
1da177e4 889 unsigned int using_edd;
a0123703
TH		 890 struct ata_taskfile tf;
891 unsigned int err_mask;
1da177e4
LT		 892 int rc;
893
894 if (!ata_dev_present(dev)) {
895 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
896 ap->id, device);
897 return;
898 }
899
900 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
901 using_edd = 0;
902 else
903 using_edd = 1;
904
905 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
906
a4631474
TH		 907 WARN_ON(dev->class != ATA_DEV_ATA && dev->class != ATA_DEV_ATAPI &&
908 dev->class != ATA_DEV_NONE);
1da177e4
LT		 909
910 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
911
1da177e4 912retry:
a0123703
TH		 913 ata_tf_init(ap, &tf, device);
914
1da177e4 915 if (dev->class == ATA_DEV_ATA) {
a0123703 916 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT		 917 DPRINTK("do ATA identify\n");
918 } else {
a0123703 919 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT		 920 DPRINTK("do ATAPI identify\n");
921 }
922
a0123703 923 tf.protocol = ATA_PROT_PIO;
1da177e4 924
a0123703
TH		 925 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
926 dev->id, sizeof(dev->id));
1da177e4 927
a0123703
TH		 928 if (err_mask) {
929 if (err_mask & ~AC_ERR_DEV)
930 goto err_out;
0169e284 931
1da177e4
LT		 932 /*
933 * arg! EDD works for all test cases, but seems to return
934 * the ATA signature for some ATAPI devices. Until the
935 * reason for this is found and fixed, we fix up the mess
936 * here. If IDENTIFY DEVICE returns command aborted
937 * (as ATAPI devices do), then we issue an
938 * IDENTIFY PACKET DEVICE.
939 *
940 * ATA software reset (SRST, the default) does not appear
941 * to have this problem.
942 */
7c398335 943 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 944 u8 err = tf.feature;
1da177e4
LT		 945 if (err & ATA_ABORTED) {
946 dev->class = ATA_DEV_ATAPI;
1da177e4
LT		 947 goto retry;
948 }
949 }
950 goto err_out;
951 }
952
953 swap_buf_le16(dev->id, ATA_ID_WORDS);
954
955 /* print device capabilities */
956 printk(KERN_DEBUG "ata%u: dev %u cfg "
957 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
958 ap->id, device, dev->id[49],
959 dev->id[82], dev->id[83], dev->id[84],
960 dev->id[85], dev->id[86], dev->id[87],
961 dev->id[88]);
962
963 /*
964 * common ATA, ATAPI feature tests
965 */
966
8bf62ece
AL		 967 /* we require DMA support (bits 8 of word 49) */
968 if (!ata_id_has_dma(dev->id)) {
969 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 970 goto err_out_nosup;
971 }
972
973 /* quick-n-dirty find max transfer mode; for printk only */
974 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
975 if (!xfer_modes)
976 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 977 if (!xfer_modes)
978 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 979
980 ata_dump_id(dev);
981
982 /* ATA-specific feature tests */
983 if (dev->class == ATA_DEV_ATA) {
984 if (!ata_id_is_ata(dev->id)) /* sanity check */
985 goto err_out_nosup;
986
8bf62ece 987 /* get major version */
1da177e4 988 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 989 for (major_version = 14; major_version >= 1; major_version--)
990 if (tmp & (1 << major_version))
1da177e4
LT		 991 break;
992
8bf62ece
AL		 993 /*
994 * The exact sequence expected by certain pre-ATA4 drives is:
995 * SRST RESET
996 * IDENTIFY
997 * INITIALIZE DEVICE PARAMETERS
998 * anything else..
999 * Some drives were very specific about that exact sequence.
1000 */
59a10b17 1001 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1002 ata_dev_init_params(ap, dev);
1003
59a10b17
AL		 1004 /* current CHS translation info (id[53-58]) might be
1005 * changed. reread the identify device info.
1006 */
1007 ata_dev_reread_id(ap, dev);
1008 }
1009
8bf62ece
AL		 1010 if (ata_id_has_lba(dev->id)) {
1011 dev->flags |= ATA_DFLAG_LBA;
1012
1013 if (ata_id_has_lba48(dev->id)) {
1014 dev->flags |= ATA_DFLAG_LBA48;
1015 dev->n_sectors = ata_id_u64(dev->id, 100);
1016 } else {
1017 dev->n_sectors = ata_id_u32(dev->id, 60);
1018 }
1019
1020 /* print device info to dmesg */
1021 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1022 ap->id, device,
1023 major_version,
1024 ata_mode_string(xfer_modes),
1025 (unsigned long long)dev->n_sectors,
1026 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1027 } else {
1028 /* CHS */
1029
1030 /* Default translation */
1031 dev->cylinders = dev->id[1];
1032 dev->heads = dev->id[3];
1033 dev->sectors = dev->id[6];
1034 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1035
1036 if (ata_id_current_chs_valid(dev->id)) {
1037 /* Current CHS translation is valid. */
1038 dev->cylinders = dev->id[54];
1039 dev->heads = dev->id[55];
1040 dev->sectors = dev->id[56];
1041
1042 dev->n_sectors = ata_id_u32(dev->id, 57);
1043 }
1044
1045 /* print device info to dmesg */
1046 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1047 ap->id, device,
1048 major_version,
1049 ata_mode_string(xfer_modes),
1050 (unsigned long long)dev->n_sectors,
1051 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1052
1da177e4
LT		 1053 }
1054
1055 ap->host->max_cmd_len = 16;
1da177e4
LT		 1056 }
1057
1058 /* ATAPI-specific feature tests */
2c13b7ce 1059 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1060 if (ata_id_is_ata(dev->id)) /* sanity check */
1061 goto err_out_nosup;
1062
1063 rc = atapi_cdb_len(dev->id);
1064 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1065 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1066 goto err_out_nosup;
1067 }
1068 ap->cdb_len = (unsigned int) rc;
1069 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1070
1071 /* print device info to dmesg */
1072 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1073 ap->id, device,
1074 ata_mode_string(xfer_modes));
1075 }
1076
1077 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1078 return;
1079
1080err_out_nosup:
1081 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1082 ap->id, device);
1083err_out:
1084 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1085 DPRINTK("EXIT, err\n");
1086}
1087
6f2f3812 1088
057ace5e 1089static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1090{
1091 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1092}
1093
1094/**
c893a3ae
RD		 1095 * ata_dev_config - Run device specific handlers & check for SATA->PATA bridges
1096 * @ap: Bus
1097 * @i: Device
6f2f3812 1098 *
c893a3ae 1099 * LOCKING:
6f2f3812 1100 */
8a60a071 1101
6f2f3812
BC		 1102void ata_dev_config(struct ata_port *ap, unsigned int i)
1103{
1104 /* limit bridge transfers to udma5, 200 sectors */
1105 if (ata_dev_knobble(ap)) {
1106 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1107 ap->id, ap->device->devno);
1108 ap->udma_mask &= ATA_UDMA5;
1109 ap->host->max_sectors = ATA_MAX_SECTORS;
1110 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
9d824d07 1111 ap->device[i].flags |= ATA_DFLAG_LOCK_SECTORS;
6f2f3812
BC		 1112 }
1113
1114 if (ap->ops->dev_config)
1115 ap->ops->dev_config(ap, &ap->device[i]);
1116}
1117
1da177e4
LT		 1118/**
1119 * ata_bus_probe - Reset and probe ATA bus
1120 * @ap: Bus to probe
1121 *
0cba632b
JG		 1122 * Master ATA bus probing function. Initiates a hardware-dependent
1123 * bus reset, then attempts to identify any devices found on
1124 * the bus.
1125 *
1da177e4 1126 * LOCKING:
0cba632b 1127 * PCI/etc. bus probe sem.
1da177e4
LT		 1128 *
1129 * RETURNS:
1130 * Zero on success, non-zero on error.
1131 */
1132
1133static int ata_bus_probe(struct ata_port *ap)
1134{
1135 unsigned int i, found = 0;
1136
c19ba8af
TH		 1137 if (ap->ops->probe_reset) {
1138 unsigned int classes[ATA_MAX_DEVICES];
1139 int rc;
1140
1141 ata_port_probe(ap);
1142
1143 rc = ap->ops->probe_reset(ap, classes);
1144 if (rc == 0) {
06ab7822
TH		 1145 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1146 if (classes[i] == ATA_DEV_UNKNOWN)
1147 classes[i] = ATA_DEV_NONE;
c19ba8af 1148 ap->device[i].class = classes[i];
06ab7822 1149 }
c19ba8af
TH		 1150 } else {
1151 printk(KERN_ERR "ata%u: probe reset failed, "
1152 "disabling port\n", ap->id);
1153 ata_port_disable(ap);
1154 }
1155 } else
1156 ap->ops->phy_reset(ap);
1157
1da177e4
LT		 1158 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1159 goto err_out;
1160
1161 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1162 ata_dev_identify(ap, i);
1163 if (ata_dev_present(&ap->device[i])) {
1164 found = 1;
6f2f3812 1165 ata_dev_config(ap,i);
1da177e4
LT		 1166 }
1167 }
1168
1169 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1170 goto err_out_disable;
1171
1172 ata_set_mode(ap);
1173 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1174 goto err_out_disable;
1175
1176 return 0;
1177
1178err_out_disable:
1179 ap->ops->port_disable(ap);
1180err_out:
1181 return -1;
1182}
1183
1184/**
0cba632b
JG		 1185 * ata_port_probe - Mark port as enabled
1186 * @ap: Port for which we indicate enablement
1da177e4 1187 *
0cba632b
JG		 1188 * Modify @ap data structure such that the system
1189 * thinks that the entire port is enabled.
1190 *
1191 * LOCKING: host_set lock, or some other form of
1192 * serialization.
1da177e4
LT		 1193 */
1194
1195void ata_port_probe(struct ata_port *ap)
1196{
1197 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1198}
1199
3be680b7
TH		 1200/**
1201 * sata_print_link_status - Print SATA link status
1202 * @ap: SATA port to printk link status about
1203 *
1204 * This function prints link speed and status of a SATA link.
1205 *
1206 * LOCKING:
1207 * None.
1208 */
1209static void sata_print_link_status(struct ata_port *ap)
1210{
1211 u32 sstatus, tmp;
1212 const char *speed;
1213
1214 if (!ap->ops->scr_read)
1215 return;
1216
1217 sstatus = scr_read(ap, SCR_STATUS);
1218
1219 if (sata_dev_present(ap)) {
1220 tmp = (sstatus >> 4) & 0xf;
1221 if (tmp & (1 << 0))
1222 speed = "1.5";
1223 else if (tmp & (1 << 1))
1224 speed = "3.0";
1225 else
1226 speed = "<unknown>";
1227 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1228 ap->id, speed, sstatus);
1229 } else {
1230 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1231 ap->id, sstatus);
1232 }
1233}
1234
1da177e4 1235/**
780a87f7
JG		 1236 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1237 * @ap: SATA port associated with target SATA PHY.
1da177e4 1238 *
780a87f7
JG		 1239 * This function issues commands to standard SATA Sxxx
1240 * PHY registers, to wake up the phy (and device), and
1241 * clear any reset condition.
1da177e4
LT		 1242 *
1243 * LOCKING:
0cba632b 1244 * PCI/etc. bus probe sem.
1da177e4
LT		 1245 *
1246 */
1247void __sata_phy_reset(struct ata_port *ap)
1248{
1249 u32 sstatus;
1250 unsigned long timeout = jiffies + (HZ * 5);
1251
1252 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1253 /* issue phy wake/reset */
1254 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1255 /* Couldn't find anything in SATA I/II specs, but
1256 * AHCI-1.1 10.4.2 says at least 1 ms. */
1257 mdelay(1);
1da177e4 1258 }
cdcca89e 1259 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1260
1261 /* wait for phy to become ready, if necessary */
1262 do {
1263 msleep(200);
1264 sstatus = scr_read(ap, SCR_STATUS);
1265 if ((sstatus & 0xf) != 1)
1266 break;
1267 } while (time_before(jiffies, timeout));
1268
3be680b7
TH		 1269 /* print link status */
1270 sata_print_link_status(ap);
656563e3 1271
3be680b7
TH		 1272 /* TODO: phy layer with polling, timeouts, etc. */
1273 if (sata_dev_present(ap))
1da177e4 1274 ata_port_probe(ap);
3be680b7 1275 else
1da177e4 1276 ata_port_disable(ap);
1da177e4
LT		 1277
1278 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1279 return;
1280
1281 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1282 ata_port_disable(ap);
1283 return;
1284 }
1285
1286 ap->cbl = ATA_CBL_SATA;
1287}
1288
1289/**
780a87f7
JG		 1290 * sata_phy_reset - Reset SATA bus.
1291 * @ap: SATA port associated with target SATA PHY.
1da177e4 1292 *
780a87f7
JG		 1293 * This function resets the SATA bus, and then probes
1294 * the bus for devices.
1da177e4
LT		 1295 *
1296 * LOCKING:
0cba632b 1297 * PCI/etc. bus probe sem.
1da177e4
LT		 1298 *
1299 */
1300void sata_phy_reset(struct ata_port *ap)
1301{
1302 __sata_phy_reset(ap);
1303 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1304 return;
1305 ata_bus_reset(ap);
1306}
1307
1308/**
780a87f7
JG		 1309 * ata_port_disable - Disable port.
1310 * @ap: Port to be disabled.
1da177e4 1311 *
780a87f7
JG		 1312 * Modify @ap data structure such that the system
1313 * thinks that the entire port is disabled, and should
1314 * never attempt to probe or communicate with devices
1315 * on this port.
1316 *
1317 * LOCKING: host_set lock, or some other form of
1318 * serialization.
1da177e4
LT		 1319 */
1320
1321void ata_port_disable(struct ata_port *ap)
1322{
1323 ap->device[0].class = ATA_DEV_NONE;
1324 ap->device[1].class = ATA_DEV_NONE;
1325 ap->flags |= ATA_FLAG_PORT_DISABLED;
1326}
1327
452503f9
AC		 1328/*
1329 * This mode timing computation functionality is ported over from
1330 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1331 */
1332/*
1333 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1334 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1335 * for PIO 5, which is a nonstandard extension and UDMA6, which
1336 * is currently supported only by Maxtor drives.
1337 */
1338
1339static const struct ata_timing ata_timing[] = {
1340
1341 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1342 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1343 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1344 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1345
1346 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1347 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1348 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1349
1350/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1351
1352 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1353 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1354 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1355
1356 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1357 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1358 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1359
1360/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1361 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1362 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1363
1364 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1365 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1366 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1367
1368/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1369
1370 { 0xFF }
1371};
1372
1373#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1374#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1375
1376static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1377{
1378 q->setup = EZ(t->setup * 1000, T);
1379 q->act8b = EZ(t->act8b * 1000, T);
1380 q->rec8b = EZ(t->rec8b * 1000, T);
1381 q->cyc8b = EZ(t->cyc8b * 1000, T);
1382 q->active = EZ(t->active * 1000, T);
1383 q->recover = EZ(t->recover * 1000, T);
1384 q->cycle = EZ(t->cycle * 1000, T);
1385 q->udma = EZ(t->udma * 1000, UT);
1386}
1387
1388void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1389 struct ata_timing *m, unsigned int what)
1390{
1391 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1392 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1393 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1394 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1395 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1396 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1397 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1398 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1399}
1400
1401static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1402{
1403 const struct ata_timing *t;
1404
1405 for (t = ata_timing; t->mode != speed; t++)
91190758 1406 if (t->mode == 0xFF)
452503f9
AC		 1407 return NULL;
1408 return t;
1409}
1410
1411int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1412 struct ata_timing *t, int T, int UT)
1413{
1414 const struct ata_timing *s;
1415 struct ata_timing p;
1416
1417 /*
1418 * Find the mode.
75b1f2f8 1419 */
452503f9
AC		 1420
1421 if (!(s = ata_timing_find_mode(speed)))
1422 return -EINVAL;
1423
75b1f2f8
AL		 1424 memcpy(t, s, sizeof(*s));
1425
452503f9
AC		 1426 /*
1427 * If the drive is an EIDE drive, it can tell us it needs extended
1428 * PIO/MW_DMA cycle timing.
1429 */
1430
1431 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1432 memset(&p, 0, sizeof(p));
1433 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1434 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1435 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1436 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1437 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1438 }
1439 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1440 }
1441
1442 /*
1443 * Convert the timing to bus clock counts.
1444 */
1445
75b1f2f8 1446 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1447
1448 /*
c893a3ae
RD		 1449 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1450 * S.M.A.R.T * and some other commands. We have to ensure that the
1451 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1452 */
1453
1454 if (speed > XFER_PIO_4) {
1455 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1456 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1457 }
1458
1459 /*
c893a3ae 1460 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1461 */
1462
1463 if (t->act8b + t->rec8b < t->cyc8b) {
1464 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1465 t->rec8b = t->cyc8b - t->act8b;
1466 }
1467
1468 if (t->active + t->recover < t->cycle) {
1469 t->active += (t->cycle - (t->active + t->recover)) / 2;
1470 t->recover = t->cycle - t->active;
1471 }
1472
1473 return 0;
1474}
1475
057ace5e 1476static const struct {
1da177e4
LT		 1477 unsigned int shift;
1478 u8 base;
1479} xfer_mode_classes[] = {
1480 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1481 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1482 { ATA_SHIFT_PIO, XFER_PIO_0 },
1483};
1484
858119e1 1485static u8 base_from_shift(unsigned int shift)
1da177e4
LT		 1486{
1487 int i;
1488
1489 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1490 if (xfer_mode_classes[i].shift == shift)
1491 return xfer_mode_classes[i].base;
1492
1493 return 0xff;
1494}
1495
1496static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1497{
1498 int ofs, idx;
1499 u8 base;
1500
1501 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1502 return;
1503
1504 if (dev->xfer_shift == ATA_SHIFT_PIO)
1505 dev->flags |= ATA_DFLAG_PIO;
1506
1507 ata_dev_set_xfermode(ap, dev);
1508
1509 base = base_from_shift(dev->xfer_shift);
1510 ofs = dev->xfer_mode - base;
1511 idx = ofs + dev->xfer_shift;
1512 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1513
1514 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1515 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1516
1517 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1518 ap->id, dev->devno, xfer_mode_str[idx]);
1519}
1520
1521static int ata_host_set_pio(struct ata_port *ap)
1522{
1523 unsigned int mask;
1524 int x, i;
1525 u8 base, xfer_mode;
1526
1527 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1528 x = fgb(mask);
1529 if (x < 0) {
1530 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1531 return -1;
1532 }
1533
1534 base = base_from_shift(ATA_SHIFT_PIO);
1535 xfer_mode = base + x;
1536
1537 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1538 (int)base, (int)xfer_mode, mask, x);
1539
1540 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1541 struct ata_device *dev = &ap->device[i];
1542 if (ata_dev_present(dev)) {
1543 dev->pio_mode = xfer_mode;
1544 dev->xfer_mode = xfer_mode;
1545 dev->xfer_shift = ATA_SHIFT_PIO;
1546 if (ap->ops->set_piomode)
1547 ap->ops->set_piomode(ap, dev);
1548 }
1549 }
1550
1551 return 0;
1552}
1553
1554static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1555 unsigned int xfer_shift)
1556{
1557 int i;
1558
1559 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1560 struct ata_device *dev = &ap->device[i];
1561 if (ata_dev_present(dev)) {
1562 dev->dma_mode = xfer_mode;
1563 dev->xfer_mode = xfer_mode;
1564 dev->xfer_shift = xfer_shift;
1565 if (ap->ops->set_dmamode)
1566 ap->ops->set_dmamode(ap, dev);
1567 }
1568 }
1569}
1570
1571/**
1572 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1573 * @ap: port on which timings will be programmed
1574 *
780a87f7
JG		 1575 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1576 *
1da177e4 1577 * LOCKING:
0cba632b 1578 * PCI/etc. bus probe sem.
1da177e4
LT		 1579 */
1580static void ata_set_mode(struct ata_port *ap)
1581{
8cbd6df1 1582 unsigned int xfer_shift;
1da177e4
LT		 1583 u8 xfer_mode;
1584 int rc;
1585
1586 /* step 1: always set host PIO timings */
1587 rc = ata_host_set_pio(ap);
1588 if (rc)
1589 goto err_out;
1590
1591 /* step 2: choose the best data xfer mode */
1592 xfer_mode = xfer_shift = 0;
1593 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1594 if (rc)
1595 goto err_out;
1596
1597 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1598 if (xfer_shift != ATA_SHIFT_PIO)
1599 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1600
1601 /* step 4: update devices' xfer mode */
1602 ata_dev_set_mode(ap, &ap->device[0]);
1603 ata_dev_set_mode(ap, &ap->device[1]);
1604
1605 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1606 return;
1607
1608 if (ap->ops->post_set_mode)
1609 ap->ops->post_set_mode(ap);
1610
1da177e4
LT		 1611 return;
1612
1613err_out:
1614 ata_port_disable(ap);
1615}
1616
1fdffbce
JG		 1617/**
1618 * ata_tf_to_host - issue ATA taskfile to host controller
1619 * @ap: port to which command is being issued
1620 * @tf: ATA taskfile register set
1621 *
1622 * Issues ATA taskfile register set to ATA host controller,
1623 * with proper synchronization with interrupt handler and
1624 * other threads.
1625 *
1626 * LOCKING:
1627 * spin_lock_irqsave(host_set lock)
1628 */
1629
1630static inline void ata_tf_to_host(struct ata_port *ap,
1631 const struct ata_taskfile *tf)
1632{
1633 ap->ops->tf_load(ap, tf);
1634 ap->ops->exec_command(ap, tf);
1635}
1636
1da177e4
LT		 1637/**
1638 * ata_busy_sleep - sleep until BSY clears, or timeout
1639 * @ap: port containing status register to be polled
1640 * @tmout_pat: impatience timeout
1641 * @tmout: overall timeout
1642 *
780a87f7
JG		 1643 * Sleep until ATA Status register bit BSY clears,
1644 * or a timeout occurs.
1645 *
1646 * LOCKING: None.
1da177e4
LT		 1647 */
1648
6f8b9958
TH		 1649unsigned int ata_busy_sleep (struct ata_port *ap,
1650 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 1651{
1652 unsigned long timer_start, timeout;
1653 u8 status;
1654
1655 status = ata_busy_wait(ap, ATA_BUSY, 300);
1656 timer_start = jiffies;
1657 timeout = timer_start + tmout_pat;
1658 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1659 msleep(50);
1660 status = ata_busy_wait(ap, ATA_BUSY, 3);
1661 }
1662
1663 if (status & ATA_BUSY)
1664 printk(KERN_WARNING "ata%u is slow to respond, "
1665 "please be patient\n", ap->id);
1666
1667 timeout = timer_start + tmout;
1668 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1669 msleep(50);
1670 status = ata_chk_status(ap);
1671 }
1672
1673 if (status & ATA_BUSY) {
1674 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1675 ap->id, tmout / HZ);
1676 return 1;
1677 }
1678
1679 return 0;
1680}
1681
1682static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1683{
1684 struct ata_ioports *ioaddr = &ap->ioaddr;
1685 unsigned int dev0 = devmask & (1 << 0);
1686 unsigned int dev1 = devmask & (1 << 1);
1687 unsigned long timeout;
1688
1689 /* if device 0 was found in ata_devchk, wait for its
1690 * BSY bit to clear
1691 */
1692 if (dev0)
1693 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1694
1695 /* if device 1 was found in ata_devchk, wait for
1696 * register access, then wait for BSY to clear
1697 */
1698 timeout = jiffies + ATA_TMOUT_BOOT;
1699 while (dev1) {
1700 u8 nsect, lbal;
1701
1702 ap->ops->dev_select(ap, 1);
1703 if (ap->flags & ATA_FLAG_MMIO) {
1704 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1705 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1706 } else {
1707 nsect = inb(ioaddr->nsect_addr);
1708 lbal = inb(ioaddr->lbal_addr);
1709 }
1710 if ((nsect == 1) && (lbal == 1))
1711 break;
1712 if (time_after(jiffies, timeout)) {
1713 dev1 = 0;
1714 break;
1715 }
1716 msleep(50); /* give drive a breather */
1717 }
1718 if (dev1)
1719 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1720
1721 /* is all this really necessary? */
1722 ap->ops->dev_select(ap, 0);
1723 if (dev1)
1724 ap->ops->dev_select(ap, 1);
1725 if (dev0)
1726 ap->ops->dev_select(ap, 0);
1727}
1728
1729/**
0cba632b
JG		 1730 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1731 * @ap: Port to reset and probe
1732 *
1733 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1734 * probe the bus. Not often used these days.
1da177e4
LT		 1735 *
1736 * LOCKING:
0cba632b 1737 * PCI/etc. bus probe sem.
e5338254 1738 * Obtains host_set lock.
1da177e4
LT		 1739 *
1740 */
1741
1742static unsigned int ata_bus_edd(struct ata_port *ap)
1743{
1744 struct ata_taskfile tf;
e5338254 1745 unsigned long flags;
1da177e4
LT		 1746
1747 /* set up execute-device-diag (bus reset) taskfile */
1748 /* also, take interrupts to a known state (disabled) */
1749 DPRINTK("execute-device-diag\n");
1750 ata_tf_init(ap, &tf, 0);
1751 tf.ctl |= ATA_NIEN;
1752 tf.command = ATA_CMD_EDD;
1753 tf.protocol = ATA_PROT_NODATA;
1754
1755 /* do bus reset */
e5338254 1756 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1757 ata_tf_to_host(ap, &tf);
e5338254 1758 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1759
1760 /* spec says at least 2ms. but who knows with those
1761 * crazy ATAPI devices...
1762 */
1763 msleep(150);
1764
1765 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1766}
1767
1768static unsigned int ata_bus_softreset(struct ata_port *ap,
1769 unsigned int devmask)
1770{
1771 struct ata_ioports *ioaddr = &ap->ioaddr;
1772
1773 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1774
1775 /* software reset. causes dev0 to be selected */
1776 if (ap->flags & ATA_FLAG_MMIO) {
1777 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1778 udelay(20); /* FIXME: flush */
1779 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1780 udelay(20); /* FIXME: flush */
1781 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1782 } else {
1783 outb(ap->ctl, ioaddr->ctl_addr);
1784 udelay(10);
1785 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1786 udelay(10);
1787 outb(ap->ctl, ioaddr->ctl_addr);
1788 }
1789
1790 /* spec mandates ">= 2ms" before checking status.
1791 * We wait 150ms, because that was the magic delay used for
1792 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1793 * between when the ATA command register is written, and then
1794 * status is checked. Because waiting for "a while" before
1795 * checking status is fine, post SRST, we perform this magic
1796 * delay here as well.
1797 */
1798 msleep(150);
1799
1800 ata_bus_post_reset(ap, devmask);
1801
1802 return 0;
1803}
1804
1805/**
1806 * ata_bus_reset - reset host port and associated ATA channel
1807 * @ap: port to reset
1808 *
1809 * This is typically the first time we actually start issuing
1810 * commands to the ATA channel. We wait for BSY to clear, then
1811 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1812 * result. Determine what devices, if any, are on the channel
1813 * by looking at the device 0/1 error register. Look at the signature
1814 * stored in each device's taskfile registers, to determine if
1815 * the device is ATA or ATAPI.
1816 *
1817 * LOCKING:
0cba632b
JG		 1818 * PCI/etc. bus probe sem.
1819 * Obtains host_set lock.
1da177e4
LT		 1820 *
1821 * SIDE EFFECTS:
1822 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1823 */
1824
1825void ata_bus_reset(struct ata_port *ap)
1826{
1827 struct ata_ioports *ioaddr = &ap->ioaddr;
1828 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1829 u8 err;
1830 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1831
1832 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1833
1834 /* determine if device 0/1 are present */
1835 if (ap->flags & ATA_FLAG_SATA_RESET)
1836 dev0 = 1;
1837 else {
1838 dev0 = ata_devchk(ap, 0);
1839 if (slave_possible)
1840 dev1 = ata_devchk(ap, 1);
1841 }
1842
1843 if (dev0)
1844 devmask |= (1 << 0);
1845 if (dev1)
1846 devmask |= (1 << 1);
1847
1848 /* select device 0 again */
1849 ap->ops->dev_select(ap, 0);
1850
1851 /* issue bus reset */
1852 if (ap->flags & ATA_FLAG_SRST)
1853 rc = ata_bus_softreset(ap, devmask);
1854 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1855 /* set up device control */
1856 if (ap->flags & ATA_FLAG_MMIO)
1857 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1858 else
1859 outb(ap->ctl, ioaddr->ctl_addr);
1860 rc = ata_bus_edd(ap);
1861 }
1862
1863 if (rc)
1864 goto err_out;
1865
1866 /*
1867 * determine by signature whether we have ATA or ATAPI devices
1868 */
b4dc7623 1869 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 1870 if ((slave_possible) && (err != 0x81))
b4dc7623 1871 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 1872
1873 /* re-enable interrupts */
1874 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
1875 ata_irq_on(ap);
1876
1877 /* is double-select really necessary? */
1878 if (ap->device[1].class != ATA_DEV_NONE)
1879 ap->ops->dev_select(ap, 1);
1880 if (ap->device[0].class != ATA_DEV_NONE)
1881 ap->ops->dev_select(ap, 0);
1882
1883 /* if no devices were detected, disable this port */
1884 if ((ap->device[0].class == ATA_DEV_NONE) &&
1885 (ap->device[1].class == ATA_DEV_NONE))
1886 goto err_out;
1887
1888 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
1889 /* set up device control for ATA_FLAG_SATA_RESET */
1890 if (ap->flags & ATA_FLAG_MMIO)
1891 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1892 else
1893 outb(ap->ctl, ioaddr->ctl_addr);
1894 }
1895
1896 DPRINTK("EXIT\n");
1897 return;
1898
1899err_out:
1900 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
1901 ap->ops->port_disable(ap);
1902
1903 DPRINTK("EXIT\n");
1904}
1905
7a7921e8
TH		 1906static int sata_phy_resume(struct ata_port *ap)
1907{
1908 unsigned long timeout = jiffies + (HZ * 5);
1909 u32 sstatus;
1910
1911 scr_write_flush(ap, SCR_CONTROL, 0x300);
1912
1913 /* Wait for phy to become ready, if necessary. */
1914 do {
1915 msleep(200);
1916 sstatus = scr_read(ap, SCR_STATUS);
1917 if ((sstatus & 0xf) != 1)
1918 return 0;
1919 } while (time_before(jiffies, timeout));
1920
1921 return -1;
1922}
1923
8a19ac89
TH		 1924/**
1925 * ata_std_probeinit - initialize probing
1926 * @ap: port to be probed
1927 *
1928 * @ap is about to be probed. Initialize it. This function is
1929 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 1930 *
1931 * NOTE!!! Do not use this function as probeinit if a low level
1932 * driver implements only hardreset. Just pass NULL as probeinit
1933 * in that case. Using this function is probably okay but doing
1934 * so makes reset sequence different from the original
1935 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89
TH		 1936 */
1937extern void ata_std_probeinit(struct ata_port *ap)
1938{
3a39746a 1939 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read) {
8a19ac89 1940 sata_phy_resume(ap);
3a39746a
TH		 1941 if (sata_dev_present(ap))
1942 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1943 }
8a19ac89
TH		 1944}
1945
c2bd5804
TH		 1946/**
1947 * ata_std_softreset - reset host port via ATA SRST
1948 * @ap: port to reset
1949 * @verbose: fail verbosely
1950 * @classes: resulting classes of attached devices
1951 *
1952 * Reset host port using ATA SRST. This function is to be used
1953 * as standard callback for ata_drive_*_reset() functions.
1954 *
1955 * LOCKING:
1956 * Kernel thread context (may sleep)
1957 *
1958 * RETURNS:
1959 * 0 on success, -errno otherwise.
1960 */
1961int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
1962{
1963 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1964 unsigned int devmask = 0, err_mask;
1965 u8 err;
1966
1967 DPRINTK("ENTER\n");
1968
3a39746a
TH		 1969 if (ap->ops->scr_read && !sata_dev_present(ap)) {
1970 classes[0] = ATA_DEV_NONE;
1971 goto out;
1972 }
1973
c2bd5804
TH		 1974 /* determine if device 0/1 are present */
1975 if (ata_devchk(ap, 0))
1976 devmask |= (1 << 0);
1977 if (slave_possible && ata_devchk(ap, 1))
1978 devmask |= (1 << 1);
1979
c2bd5804
TH		 1980 /* select device 0 again */
1981 ap->ops->dev_select(ap, 0);
1982
1983 /* issue bus reset */
1984 DPRINTK("about to softreset, devmask=%x\n", devmask);
1985 err_mask = ata_bus_softreset(ap, devmask);
1986 if (err_mask) {
1987 if (verbose)
1988 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
1989 ap->id, err_mask);
1990 else
1991 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
1992 err_mask);
1993 return -EIO;
1994 }
1995
1996 /* determine by signature whether we have ATA or ATAPI devices */
1997 classes[0] = ata_dev_try_classify(ap, 0, &err);
1998 if (slave_possible && err != 0x81)
1999 classes[1] = ata_dev_try_classify(ap, 1, &err);
2000
3a39746a 2001 out:
c2bd5804
TH		 2002 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2003 return 0;
2004}
2005
2006/**
2007 * sata_std_hardreset - reset host port via SATA phy reset
2008 * @ap: port to reset
2009 * @verbose: fail verbosely
2010 * @class: resulting class of attached device
2011 *
2012 * SATA phy-reset host port using DET bits of SControl register.
2013 * This function is to be used as standard callback for
2014 * ata_drive_*_reset().
2015 *
2016 * LOCKING:
2017 * Kernel thread context (may sleep)
2018 *
2019 * RETURNS:
2020 * 0 on success, -errno otherwise.
2021 */
2022int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2023{
c2bd5804
TH		 2024 DPRINTK("ENTER\n");
2025
2026 /* Issue phy wake/reset */
2027 scr_write_flush(ap, SCR_CONTROL, 0x301);
2028
2029 /*
2030 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2031 * 10.4.2 says at least 1 ms.
2032 */
2033 msleep(1);
2034
7a7921e8
TH		 2035 /* Bring phy back */
2036 sata_phy_resume(ap);
c2bd5804 2037
c2bd5804
TH		 2038 /* TODO: phy layer with polling, timeouts, etc. */
2039 if (!sata_dev_present(ap)) {
2040 *class = ATA_DEV_NONE;
2041 DPRINTK("EXIT, link offline\n");
2042 return 0;
2043 }
2044
2045 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2046 if (verbose)
2047 printk(KERN_ERR "ata%u: COMRESET failed "
2048 "(device not ready)\n", ap->id);
2049 else
2050 DPRINTK("EXIT, device not ready\n");
2051 return -EIO;
2052 }
2053
3a39746a
TH		 2054 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2055
c2bd5804
TH		 2056 *class = ata_dev_try_classify(ap, 0, NULL);
2057
2058 DPRINTK("EXIT, class=%u\n", *class);
2059 return 0;
2060}
2061
2062/**
2063 * ata_std_postreset - standard postreset callback
2064 * @ap: the target ata_port
2065 * @classes: classes of attached devices
2066 *
2067 * This function is invoked after a successful reset. Note that
2068 * the device might have been reset more than once using
2069 * different reset methods before postreset is invoked.
2070 * postreset is also reponsible for setting cable type.
2071 *
2072 * This function is to be used as standard callback for
2073 * ata_drive_*_reset().
2074 *
2075 * LOCKING:
2076 * Kernel thread context (may sleep)
2077 */
2078void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2079{
2080 DPRINTK("ENTER\n");
2081
2082 /* set cable type */
2083 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2084 ap->cbl = ATA_CBL_SATA;
2085
2086 /* print link status */
2087 if (ap->cbl == ATA_CBL_SATA)
2088 sata_print_link_status(ap);
2089
3a39746a
TH		 2090 /* re-enable interrupts */
2091 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2092 ata_irq_on(ap);
c2bd5804
TH		 2093
2094 /* is double-select really necessary? */
2095 if (classes[0] != ATA_DEV_NONE)
2096 ap->ops->dev_select(ap, 1);
2097 if (classes[1] != ATA_DEV_NONE)
2098 ap->ops->dev_select(ap, 0);
2099
3a39746a
TH		 2100 /* bail out if no device is present */
2101 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2102 DPRINTK("EXIT, no device\n");
2103 return;
2104 }
2105
2106 /* set up device control */
2107 if (ap->ioaddr.ctl_addr) {
2108 if (ap->flags & ATA_FLAG_MMIO)
2109 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2110 else
2111 outb(ap->ctl, ap->ioaddr.ctl_addr);
2112 }
c2bd5804
TH		 2113
2114 DPRINTK("EXIT\n");
2115}
2116
2117/**
2118 * ata_std_probe_reset - standard probe reset method
2119 * @ap: prot to perform probe-reset
2120 * @classes: resulting classes of attached devices
2121 *
2122 * The stock off-the-shelf ->probe_reset method.
2123 *
2124 * LOCKING:
2125 * Kernel thread context (may sleep)
2126 *
2127 * RETURNS:
2128 * 0 on success, -errno otherwise.
2129 */
2130int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2131{
2132 ata_reset_fn_t hardreset;
2133
2134 hardreset = NULL;
b911fc3a 2135 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH		 2136 hardreset = sata_std_hardreset;
2137
8a19ac89 2138 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2139 ata_std_softreset, hardreset,
c2bd5804
TH		 2140 ata_std_postreset, classes);
2141}
2142
a62c0fc5
TH		 2143static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2144 ata_postreset_fn_t postreset,
2145 unsigned int *classes)
2146{
2147 int i, rc;
2148
2149 for (i = 0; i < ATA_MAX_DEVICES; i++)
2150 classes[i] = ATA_DEV_UNKNOWN;
2151
2152 rc = reset(ap, 0, classes);
2153 if (rc)
2154 return rc;
2155
2156 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2157 * is complete and convert all ATA_DEV_UNKNOWN to
2158 * ATA_DEV_NONE.
2159 */
2160 for (i = 0; i < ATA_MAX_DEVICES; i++)
2161 if (classes[i] != ATA_DEV_UNKNOWN)
2162 break;
2163
2164 if (i < ATA_MAX_DEVICES)
2165 for (i = 0; i < ATA_MAX_DEVICES; i++)
2166 if (classes[i] == ATA_DEV_UNKNOWN)
2167 classes[i] = ATA_DEV_NONE;
2168
2169 if (postreset)
2170 postreset(ap, classes);
2171
2172 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2173}
2174
2175/**
2176 * ata_drive_probe_reset - Perform probe reset with given methods
2177 * @ap: port to reset
7944ea95 2178 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2179 * @softreset: softreset method (can be NULL)
2180 * @hardreset: hardreset method (can be NULL)
2181 * @postreset: postreset method (can be NULL)
2182 * @classes: resulting classes of attached devices
2183 *
2184 * Reset the specified port and classify attached devices using
2185 * given methods. This function prefers softreset but tries all
2186 * possible reset sequences to reset and classify devices. This
2187 * function is intended to be used for constructing ->probe_reset
2188 * callback by low level drivers.
2189 *
2190 * Reset methods should follow the following rules.
2191 *
2192 * - Return 0 on sucess, -errno on failure.
2193 * - If classification is supported, fill classes[] with
2194 * recognized class codes.
2195 * - If classification is not supported, leave classes[] alone.
2196 * - If verbose is non-zero, print error message on failure;
2197 * otherwise, shut up.
2198 *
2199 * LOCKING:
2200 * Kernel thread context (may sleep)
2201 *
2202 * RETURNS:
2203 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2204 * if classification fails, and any error code from reset
2205 * methods.
2206 */
7944ea95 2207int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2208 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2209 ata_postreset_fn_t postreset, unsigned int *classes)
2210{
2211 int rc = -EINVAL;
2212
7944ea95
TH		 2213 if (probeinit)
2214 probeinit(ap);
2215
a62c0fc5
TH		 2216 if (softreset) {
2217 rc = do_probe_reset(ap, softreset, postreset, classes);
2218 if (rc == 0)
2219 return 0;
2220 }
2221
2222 if (!hardreset)
2223 return rc;
2224
2225 rc = do_probe_reset(ap, hardreset, postreset, classes);
2226 if (rc == 0 || rc != -ENODEV)
2227 return rc;
2228
2229 if (softreset)
2230 rc = do_probe_reset(ap, softreset, postreset, classes);
2231
2232 return rc;
2233}
2234
057ace5e
JG		 2235static void ata_pr_blacklisted(const struct ata_port *ap,
2236 const struct ata_device *dev)
1da177e4
LT		 2237{
2238 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2239 ap->id, dev->devno);
2240}
2241
98ac62de 2242static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2243 "WDC AC11000H",
2244 "WDC AC22100H",
2245 "WDC AC32500H",
2246 "WDC AC33100H",
2247 "WDC AC31600H",
2248 "WDC AC32100H",
2249 "WDC AC23200L",
2250 "Compaq CRD-8241B",
2251 "CRD-8400B",
2252 "CRD-8480B",
2253 "CRD-8482B",
2254 "CRD-84",
2255 "SanDisk SDP3B",
2256 "SanDisk SDP3B-64",
2257 "SANYO CD-ROM CRD",
2258 "HITACHI CDR-8",
2259 "HITACHI CDR-8335",
2260 "HITACHI CDR-8435",
2261 "Toshiba CD-ROM XM-6202B",
e922256a 2262 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2263 "CD-532E-A",
2264 "E-IDE CD-ROM CR-840",
2265 "CD-ROM Drive/F5A",
2266 "WPI CDD-820",
2267 "SAMSUNG CD-ROM SC-148C",
2268 "SAMSUNG CD-ROM SC",
2269 "SanDisk SDP3B-64",
1da177e4
LT		 2270 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2271 "_NEC DV5800A",
2272};
2273
057ace5e 2274static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2275{
2276 unsigned char model_num[40];
2277 char *s;
2278 unsigned int len;
2279 int i;
2280
2281 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2282 sizeof(model_num));
2283 s = &model_num[0];
2284 len = strnlen(s, sizeof(model_num));
2285
2286 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2287 while ((len > 0) && (s[len - 1] == ' ')) {
2288 len--;
2289 s[len] = 0;
2290 }
2291
2292 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2293 if (!strncmp(ata_dma_blacklist[i], s, len))
2294 return 1;
2295
2296 return 0;
2297}
2298
057ace5e 2299static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2300{
057ace5e 2301 const struct ata_device *master, *slave;
1da177e4
LT		 2302 unsigned int mask;
2303
2304 master = &ap->device[0];
2305 slave = &ap->device[1];
2306
a4631474 2307 WARN_ON(!ata_dev_present(master) && !ata_dev_present(slave));
1da177e4
LT		 2308
2309 if (shift == ATA_SHIFT_UDMA) {
2310 mask = ap->udma_mask;
2311 if (ata_dev_present(master)) {
2312 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2313 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2314 mask = 0;
2315 ata_pr_blacklisted(ap, master);
2316 }
2317 }
2318 if (ata_dev_present(slave)) {
2319 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2320 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2321 mask = 0;
2322 ata_pr_blacklisted(ap, slave);
2323 }
2324 }
2325 }
2326 else if (shift == ATA_SHIFT_MWDMA) {
2327 mask = ap->mwdma_mask;
2328 if (ata_dev_present(master)) {
2329 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2330 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2331 mask = 0;
2332 ata_pr_blacklisted(ap, master);
2333 }
2334 }
2335 if (ata_dev_present(slave)) {
2336 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2337 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2338 mask = 0;
2339 ata_pr_blacklisted(ap, slave);
2340 }
2341 }
2342 }
2343 else if (shift == ATA_SHIFT_PIO) {
2344 mask = ap->pio_mask;
2345 if (ata_dev_present(master)) {
2346 /* spec doesn't return explicit support for
2347 * PIO0-2, so we fake it
2348 */
2349 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2350 tmp_mode <<= 3;
2351 tmp_mode |= 0x7;
2352 mask &= tmp_mode;
2353 }
2354 if (ata_dev_present(slave)) {
2355 /* spec doesn't return explicit support for
2356 * PIO0-2, so we fake it
2357 */
2358 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2359 tmp_mode <<= 3;
2360 tmp_mode |= 0x7;
2361 mask &= tmp_mode;
2362 }
2363 }
2364 else {
2365 mask = 0xffffffff; /* shut up compiler warning */
2366 BUG();
2367 }
2368
2369 return mask;
2370}
2371
2372/* find greatest bit */
2373static int fgb(u32 bitmap)
2374{
2375 unsigned int i;
2376 int x = -1;
2377
2378 for (i = 0; i < 32; i++)
2379 if (bitmap & (1 << i))
2380 x = i;
2381
2382 return x;
2383}
2384
2385/**
2386 * ata_choose_xfer_mode - attempt to find best transfer mode
2387 * @ap: Port for which an xfer mode will be selected
2388 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2389 * @xfer_shift_out: (output) bit shift that selects this mode
2390 *
0cba632b
JG		 2391 * Based on host and device capabilities, determine the
2392 * maximum transfer mode that is amenable to all.
2393 *
1da177e4 2394 * LOCKING:
0cba632b 2395 * PCI/etc. bus probe sem.
1da177e4
LT		 2396 *
2397 * RETURNS:
2398 * Zero on success, negative on error.
2399 */
2400
057ace5e 2401static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2402 u8 *xfer_mode_out,
2403 unsigned int *xfer_shift_out)
2404{
2405 unsigned int mask, shift;
2406 int x, i;
2407
2408 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2409 shift = xfer_mode_classes[i].shift;
2410 mask = ata_get_mode_mask(ap, shift);
2411
2412 x = fgb(mask);
2413 if (x >= 0) {
2414 *xfer_mode_out = xfer_mode_classes[i].base + x;
2415 *xfer_shift_out = shift;
2416 return 0;
2417 }
2418 }
2419
2420 return -1;
2421}
2422
2423/**
2424 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2425 * @ap: Port associated with device @dev
2426 * @dev: Device to which command will be sent
2427 *
780a87f7
JG		 2428 * Issue SET FEATURES - XFER MODE command to device @dev
2429 * on port @ap.
2430 *
1da177e4 2431 * LOCKING:
0cba632b 2432 * PCI/etc. bus probe sem.
1da177e4
LT		 2433 */
2434
2435static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2436{
a0123703 2437 struct ata_taskfile tf;
1da177e4
LT		 2438
2439 /* set up set-features taskfile */
2440 DPRINTK("set features - xfer mode\n");
2441
a0123703
TH		 2442 ata_tf_init(ap, &tf, dev->devno);
2443 tf.command = ATA_CMD_SET_FEATURES;
2444 tf.feature = SETFEATURES_XFER;
2445 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2446 tf.protocol = ATA_PROT_NODATA;
2447 tf.nsect = dev->xfer_mode;
1da177e4 2448
a0123703
TH		 2449 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2450 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2451 ap->id);
1da177e4 2452 ata_port_disable(ap);
a0123703 2453 }
1da177e4
LT		 2454
2455 DPRINTK("EXIT\n");
2456}
2457
59a10b17
AL		 2458/**
2459 * ata_dev_reread_id - Reread the device identify device info
2460 * @ap: port where the device is
2461 * @dev: device to reread the identify device info
2462 *
2463 * LOCKING:
2464 */
2465
2466static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2467{
a0123703 2468 struct ata_taskfile tf;
59a10b17 2469
a0123703 2470 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL		 2471
2472 if (dev->class == ATA_DEV_ATA) {
a0123703 2473 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL		 2474 DPRINTK("do ATA identify\n");
2475 } else {
a0123703 2476 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL		 2477 DPRINTK("do ATAPI identify\n");
2478 }
2479
a0123703
TH		 2480 tf.flags |= ATA_TFLAG_DEVICE;
2481 tf.protocol = ATA_PROT_PIO;
59a10b17 2482
a0123703
TH		 2483 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2484 dev->id, sizeof(dev->id)))
59a10b17
AL		 2485 goto err_out;
2486
59a10b17
AL		 2487 swap_buf_le16(dev->id, ATA_ID_WORDS);
2488
2489 ata_dump_id(dev);
2490
2491 DPRINTK("EXIT\n");
2492
2493 return;
2494err_out:
a0123703 2495 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL		 2496 ata_port_disable(ap);
2497}
2498
8bf62ece
AL		 2499/**
2500 * ata_dev_init_params - Issue INIT DEV PARAMS command
2501 * @ap: Port associated with device @dev
2502 * @dev: Device to which command will be sent
2503 *
2504 * LOCKING:
2505 */
2506
2507static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2508{
a0123703 2509 struct ata_taskfile tf;
8bf62ece
AL		 2510 u16 sectors = dev->id[6];
2511 u16 heads = dev->id[3];
2512
2513 /* Number of sectors per track 1-255. Number of heads 1-16 */
2514 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2515 return;
2516
2517 /* set up init dev params taskfile */
2518 DPRINTK("init dev params \n");
2519
a0123703
TH		 2520 ata_tf_init(ap, &tf, dev->devno);
2521 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2522 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2523 tf.protocol = ATA_PROT_NODATA;
2524 tf.nsect = sectors;
2525 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2526
a0123703
TH		 2527 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2528 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2529 ap->id);
8bf62ece 2530 ata_port_disable(ap);
a0123703 2531 }
8bf62ece
AL		 2532
2533 DPRINTK("EXIT\n");
2534}
2535
1da177e4 2536/**
0cba632b
JG		 2537 * ata_sg_clean - Unmap DMA memory associated with command
2538 * @qc: Command containing DMA memory to be released
2539 *
2540 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2541 *
2542 * LOCKING:
0cba632b 2543 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2544 */
2545
2546static void ata_sg_clean(struct ata_queued_cmd *qc)
2547{
2548 struct ata_port *ap = qc->ap;
cedc9a47 2549 struct scatterlist *sg = qc->__sg;
1da177e4 2550 int dir = qc->dma_dir;
cedc9a47 2551 void *pad_buf = NULL;
1da177e4 2552
a4631474
TH		 2553 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
2554 WARN_ON(sg == NULL);
1da177e4
LT		 2555
2556 if (qc->flags & ATA_QCFLAG_SINGLE)
a4631474 2557 WARN_ON(qc->n_elem != 1);
1da177e4 2558
2c13b7ce 2559 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2560
cedc9a47
JG		 2561 /* if we padded the buffer out to 32-bit bound, and data
2562 * xfer direction is from-device, we must copy from the
2563 * pad buffer back into the supplied buffer
2564 */
2565 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2566 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2567
2568 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2569 if (qc->n_elem)
2570 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2571 /* restore last sg */
2572 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2573 if (pad_buf) {
2574 struct scatterlist *psg = &qc->pad_sgent;
2575 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2576 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2577 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2578 }
2579 } else {
e1410f2d
JG		 2580 if (sg_dma_len(&sg[0]) > 0)
2581 dma_unmap_single(ap->host_set->dev,
2582 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2583 dir);
cedc9a47
JG		 2584 /* restore sg */
2585 sg->length += qc->pad_len;
2586 if (pad_buf)
2587 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2588 pad_buf, qc->pad_len);
2589 }
1da177e4
LT		 2590
2591 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2592 qc->__sg = NULL;
1da177e4
LT		 2593}
2594
2595/**
2596 * ata_fill_sg - Fill PCI IDE PRD table
2597 * @qc: Metadata associated with taskfile to be transferred
2598 *
780a87f7
JG		 2599 * Fill PCI IDE PRD (scatter-gather) table with segments
2600 * associated with the current disk command.
2601 *
1da177e4 2602 * LOCKING:
780a87f7 2603 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2604 *
2605 */
2606static void ata_fill_sg(struct ata_queued_cmd *qc)
2607{
1da177e4 2608 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2609 struct scatterlist *sg;
2610 unsigned int idx;
1da177e4 2611
a4631474
TH		 2612 WARN_ON(qc->__sg == NULL);
2613 WARN_ON(qc->n_elem == 0);
1da177e4
LT		 2614
2615 idx = 0;
cedc9a47 2616 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2617 u32 addr, offset;
2618 u32 sg_len, len;
2619
2620 /* determine if physical DMA addr spans 64K boundary.
2621 * Note h/w doesn't support 64-bit, so we unconditionally
2622 * truncate dma_addr_t to u32.
2623 */
2624 addr = (u32) sg_dma_address(sg);
2625 sg_len = sg_dma_len(sg);
2626
2627 while (sg_len) {
2628 offset = addr & 0xffff;
2629 len = sg_len;
2630 if ((offset + sg_len) > 0x10000)
2631 len = 0x10000 - offset;
2632
2633 ap->prd[idx].addr = cpu_to_le32(addr);
2634 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2635 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2636
2637 idx++;
2638 sg_len -= len;
2639 addr += len;
2640 }
2641 }
2642
2643 if (idx)
2644 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2645}
2646/**
2647 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2648 * @qc: Metadata associated with taskfile to check
2649 *
780a87f7
JG		 2650 * Allow low-level driver to filter ATA PACKET commands, returning
2651 * a status indicating whether or not it is OK to use DMA for the
2652 * supplied PACKET command.
2653 *
1da177e4 2654 * LOCKING:
0cba632b
JG		 2655 * spin_lock_irqsave(host_set lock)
2656 *
1da177e4
LT		 2657 * RETURNS: 0 when ATAPI DMA can be used
2658 * nonzero otherwise
2659 */
2660int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2661{
2662 struct ata_port *ap = qc->ap;
2663 int rc = 0; /* Assume ATAPI DMA is OK by default */
2664
2665 if (ap->ops->check_atapi_dma)
2666 rc = ap->ops->check_atapi_dma(qc);
2667
2668 return rc;
2669}
2670/**
2671 * ata_qc_prep - Prepare taskfile for submission
2672 * @qc: Metadata associated with taskfile to be prepared
2673 *
780a87f7
JG		 2674 * Prepare ATA taskfile for submission.
2675 *
1da177e4
LT		 2676 * LOCKING:
2677 * spin_lock_irqsave(host_set lock)
2678 */
2679void ata_qc_prep(struct ata_queued_cmd *qc)
2680{
2681 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2682 return;
2683
2684 ata_fill_sg(qc);
2685}
2686
0cba632b
JG		 2687/**
2688 * ata_sg_init_one - Associate command with memory buffer
2689 * @qc: Command to be associated
2690 * @buf: Memory buffer
2691 * @buflen: Length of memory buffer, in bytes.
2692 *
2693 * Initialize the data-related elements of queued_cmd @qc
2694 * to point to a single memory buffer, @buf of byte length @buflen.
2695 *
2696 * LOCKING:
2697 * spin_lock_irqsave(host_set lock)
2698 */
2699
1da177e4
LT		 2700void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2701{
2702 struct scatterlist *sg;
2703
2704 qc->flags |= ATA_QCFLAG_SINGLE;
2705
2706 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2707 qc->__sg = &qc->sgent;
1da177e4 2708 qc->n_elem = 1;
cedc9a47 2709 qc->orig_n_elem = 1;
1da177e4
LT		 2710 qc->buf_virt = buf;
2711
cedc9a47 2712 sg = qc->__sg;
f0612bbc 2713 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2714}
2715
0cba632b
JG		 2716/**
2717 * ata_sg_init - Associate command with scatter-gather table.
2718 * @qc: Command to be associated
2719 * @sg: Scatter-gather table.
2720 * @n_elem: Number of elements in s/g table.
2721 *
2722 * Initialize the data-related elements of queued_cmd @qc
2723 * to point to a scatter-gather table @sg, containing @n_elem
2724 * elements.
2725 *
2726 * LOCKING:
2727 * spin_lock_irqsave(host_set lock)
2728 */
2729
1da177e4
LT		 2730void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2731 unsigned int n_elem)
2732{
2733 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2734 qc->__sg = sg;
1da177e4 2735 qc->n_elem = n_elem;
cedc9a47 2736 qc->orig_n_elem = n_elem;
1da177e4
LT		 2737}
2738
2739/**
0cba632b
JG		 2740 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2741 * @qc: Command with memory buffer to be mapped.
2742 *
2743 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2744 *
2745 * LOCKING:
2746 * spin_lock_irqsave(host_set lock)
2747 *
2748 * RETURNS:
0cba632b 2749 * Zero on success, negative on error.
1da177e4
LT		 2750 */
2751
2752static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2753{
2754 struct ata_port *ap = qc->ap;
2755 int dir = qc->dma_dir;
cedc9a47 2756 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2757 dma_addr_t dma_address;
2758
cedc9a47
JG		 2759 /* we must lengthen transfers to end on a 32-bit boundary */
2760 qc->pad_len = sg->length & 3;
2761 if (qc->pad_len) {
2762 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2763 struct scatterlist *psg = &qc->pad_sgent;
2764
a4631474 2765 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2766
2767 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2768
2769 if (qc->tf.flags & ATA_TFLAG_WRITE)
2770 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2771 qc->pad_len);
2772
2773 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2774 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2775 /* trim sg */
2776 sg->length -= qc->pad_len;
2777
2778 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2779 sg->length, qc->pad_len);
2780 }
2781
e1410f2d
JG		 2782 if (!sg->length) {
2783 sg_dma_address(sg) = 0;
2784 goto skip_map;
2785 }
2786
1da177e4 2787 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2788 sg->length, dir);
537a95d9
TH		 2789 if (dma_mapping_error(dma_address)) {
2790 /* restore sg */
2791 sg->length += qc->pad_len;
1da177e4 2792 return -1;
537a95d9 2793 }
1da177e4
LT		 2794
2795 sg_dma_address(sg) = dma_address;
e1410f2d 2796skip_map:
32529e01 2797 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2798
2799 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2800 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2801
2802 return 0;
2803}
2804
2805/**
0cba632b
JG		 2806 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2807 * @qc: Command with scatter-gather table to be mapped.
2808 *
2809 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2810 *
2811 * LOCKING:
2812 * spin_lock_irqsave(host_set lock)
2813 *
2814 * RETURNS:
0cba632b 2815 * Zero on success, negative on error.
1da177e4
LT		 2816 *
2817 */
2818
2819static int ata_sg_setup(struct ata_queued_cmd *qc)
2820{
2821 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2822 struct scatterlist *sg = qc->__sg;
2823 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2824 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2825
2826 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 2827 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 2828
cedc9a47
JG		 2829 /* we must lengthen transfers to end on a 32-bit boundary */
2830 qc->pad_len = lsg->length & 3;
2831 if (qc->pad_len) {
2832 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2833 struct scatterlist *psg = &qc->pad_sgent;
2834 unsigned int offset;
2835
a4631474 2836 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2837
2838 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2839
2840 /*
2841 * psg->page/offset are used to copy to-be-written
2842 * data in this function or read data in ata_sg_clean.
2843 */
2844 offset = lsg->offset + lsg->length - qc->pad_len;
2845 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2846 psg->offset = offset_in_page(offset);
2847
2848 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2849 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2850 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2851 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2852 }
2853
2854 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2855 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2856 /* trim last sg */
2857 lsg->length -= qc->pad_len;
e1410f2d
JG		 2858 if (lsg->length == 0)
2859 trim_sg = 1;
cedc9a47
JG		 2860
2861 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2862 qc->n_elem - 1, lsg->length, qc->pad_len);
2863 }
2864
e1410f2d
JG		 2865 pre_n_elem = qc->n_elem;
2866 if (trim_sg && pre_n_elem)
2867 pre_n_elem--;
2868
2869 if (!pre_n_elem) {
2870 n_elem = 0;
2871 goto skip_map;
2872 }
2873
1da177e4 2874 dir = qc->dma_dir;
e1410f2d 2875 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2876 if (n_elem < 1) {
2877 /* restore last sg */
2878 lsg->length += qc->pad_len;
1da177e4 2879 return -1;
537a95d9 2880 }
1da177e4
LT		 2881
2882 DPRINTK("%d sg elements mapped\n", n_elem);
2883
e1410f2d 2884skip_map:
1da177e4
LT		 2885 qc->n_elem = n_elem;
2886
2887 return 0;
2888}
2889
40e8c82c
TH		 2890/**
2891 * ata_poll_qc_complete - turn irq back on and finish qc
2892 * @qc: Command to complete
8e8b77dd 2893 * @err_mask: ATA status register content
40e8c82c
TH		 2894 *
2895 * LOCKING:
2896 * None. (grabs host lock)
2897 */
2898
a22e2eb0 2899void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2900{
2901 struct ata_port *ap = qc->ap;
b8f6153e 2902 unsigned long flags;
40e8c82c 2903
b8f6153e 2904 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2905 ap->flags &= ~ATA_FLAG_NOINTR;
2906 ata_irq_on(ap);
a22e2eb0 2907 ata_qc_complete(qc);
b8f6153e 2908 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2909}
2910
1da177e4 2911/**
c893a3ae 2912 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 2913 * @ap: the target ata_port
1da177e4
LT		 2914 *
2915 * LOCKING:
0cba632b 2916 * None. (executing in kernel thread context)
1da177e4
LT		 2917 *
2918 * RETURNS:
6f0ef4fa 2919 * timeout value to use
1da177e4
LT		 2920 */
2921
2922static unsigned long ata_pio_poll(struct ata_port *ap)
2923{
c14b8331 2924 struct ata_queued_cmd *qc;
1da177e4 2925 u8 status;
14be71f4
AL		 2926 unsigned int poll_state = HSM_ST_UNKNOWN;
2927 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2928
c14b8331 2929 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 2930 WARN_ON(qc == NULL);
c14b8331 2931
14be71f4
AL		 2932 switch (ap->hsm_task_state) {
2933 case HSM_ST:
2934 case HSM_ST_POLL:
2935 poll_state = HSM_ST_POLL;
2936 reg_state = HSM_ST;
1da177e4 2937 break;
14be71f4
AL		 2938 case HSM_ST_LAST:
2939 case HSM_ST_LAST_POLL:
2940 poll_state = HSM_ST_LAST_POLL;
2941 reg_state = HSM_ST_LAST;
1da177e4
LT		 2942 break;
2943 default:
2944 BUG();
2945 break;
2946 }
2947
2948 status = ata_chk_status(ap);
2949 if (status & ATA_BUSY) {
2950 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 2951 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 2952 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2953 return 0;
2954 }
14be71f4 2955 ap->hsm_task_state = poll_state;
1da177e4
LT		 2956 return ATA_SHORT_PAUSE;
2957 }
2958
14be71f4 2959 ap->hsm_task_state = reg_state;
1da177e4
LT		 2960 return 0;
2961}
2962
2963/**
6f0ef4fa
RD		 2964 * ata_pio_complete - check if drive is busy or idle
2965 * @ap: the target ata_port
1da177e4
LT		 2966 *
2967 * LOCKING:
0cba632b 2968 * None. (executing in kernel thread context)
7fb6ec28
JG		 2969 *
2970 * RETURNS:
2971 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2972 */
2973
7fb6ec28 2974static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2975{
2976 struct ata_queued_cmd *qc;
2977 u8 drv_stat;
2978
2979 /*
31433ea3
AC		 2980 * This is purely heuristic. This is a fast path. Sometimes when
2981 * we enter, BSY will be cleared in a chk-status or two. If not,
2982 * the drive is probably seeking or something. Snooze for a couple
2983 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2984 * HSM_ST_POLL state.
1da177e4 2985 */
fe79e683
AL		 2986 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2987 if (drv_stat & ATA_BUSY) {
1da177e4 2988 msleep(2);
fe79e683
AL		 2989 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2990 if (drv_stat & ATA_BUSY) {
14be71f4 2991 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2992 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2993 return 0;
1da177e4
LT		 2994 }
2995 }
2996
c14b8331 2997 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 2998 WARN_ON(qc == NULL);
c14b8331 2999
1da177e4
LT		 3000 drv_stat = ata_wait_idle(ap);
3001 if (!ata_ok(drv_stat)) {
1c848984 3002 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 3003 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 3004 return 0;
1da177e4
LT		 3005 }
3006
14be71f4 3007 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3008
a4631474 3009 WARN_ON(qc->err_mask);
a22e2eb0 3010 ata_poll_qc_complete(qc);
7fb6ec28
JG		 3011
3012 /* another command may start at this point */
3013
3014 return 1;
1da177e4
LT		 3015}
3016
0baab86b
EF		 3017
3018/**
c893a3ae 3019 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3020 * @buf: Buffer to swap
3021 * @buf_words: Number of 16-bit words in buffer.
3022 *
3023 * Swap halves of 16-bit words if needed to convert from
3024 * little-endian byte order to native cpu byte order, or
3025 * vice-versa.
3026 *
3027 * LOCKING:
6f0ef4fa 3028 * Inherited from caller.
0baab86b 3029 */
1da177e4
LT		 3030void swap_buf_le16(u16 *buf, unsigned int buf_words)
3031{
3032#ifdef __BIG_ENDIAN
3033 unsigned int i;
3034
3035 for (i = 0; i < buf_words; i++)
3036 buf[i] = le16_to_cpu(buf[i]);
3037#endif /* __BIG_ENDIAN */
3038}
3039
6ae4cfb5
AL		 3040/**
3041 * ata_mmio_data_xfer - Transfer data by MMIO
3042 * @ap: port to read/write
3043 * @buf: data buffer
3044 * @buflen: buffer length
344babaa 3045 * @write_data: read/write
6ae4cfb5
AL		 3046 *
3047 * Transfer data from/to the device data register by MMIO.
3048 *
3049 * LOCKING:
3050 * Inherited from caller.
6ae4cfb5
AL		 3051 */
3052
1da177e4
LT		 3053static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3054 unsigned int buflen, int write_data)
3055{
3056 unsigned int i;
3057 unsigned int words = buflen >> 1;
3058 u16 *buf16 = (u16 *) buf;
3059 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3060
6ae4cfb5 3061 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3062 if (write_data) {
3063 for (i = 0; i < words; i++)
3064 writew(le16_to_cpu(buf16[i]), mmio);
3065 } else {
3066 for (i = 0; i < words; i++)
3067 buf16[i] = cpu_to_le16(readw(mmio));
3068 }
6ae4cfb5
AL		 3069
3070 /* Transfer trailing 1 byte, if any. */
3071 if (unlikely(buflen & 0x01)) {
3072 u16 align_buf[1] = { 0 };
3073 unsigned char *trailing_buf = buf + buflen - 1;
3074
3075 if (write_data) {
3076 memcpy(align_buf, trailing_buf, 1);
3077 writew(le16_to_cpu(align_buf[0]), mmio);
3078 } else {
3079 align_buf[0] = cpu_to_le16(readw(mmio));
3080 memcpy(trailing_buf, align_buf, 1);
3081 }
3082 }
1da177e4
LT		 3083}
3084
6ae4cfb5
AL		 3085/**
3086 * ata_pio_data_xfer - Transfer data by PIO
3087 * @ap: port to read/write
3088 * @buf: data buffer
3089 * @buflen: buffer length
344babaa 3090 * @write_data: read/write
6ae4cfb5
AL		 3091 *
3092 * Transfer data from/to the device data register by PIO.
3093 *
3094 * LOCKING:
3095 * Inherited from caller.
6ae4cfb5
AL		 3096 */
3097
1da177e4
LT		 3098static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3099 unsigned int buflen, int write_data)
3100{
6ae4cfb5 3101 unsigned int words = buflen >> 1;
1da177e4 3102
6ae4cfb5 3103 /* Transfer multiple of 2 bytes */
1da177e4 3104 if (write_data)
6ae4cfb5 3105 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3106 else
6ae4cfb5
AL		 3107 insw(ap->ioaddr.data_addr, buf, words);
3108
3109 /* Transfer trailing 1 byte, if any. */
3110 if (unlikely(buflen & 0x01)) {
3111 u16 align_buf[1] = { 0 };
3112 unsigned char *trailing_buf = buf + buflen - 1;
3113
3114 if (write_data) {
3115 memcpy(align_buf, trailing_buf, 1);
3116 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3117 } else {
3118 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3119 memcpy(trailing_buf, align_buf, 1);
3120 }
3121 }
1da177e4
LT		 3122}
3123
6ae4cfb5
AL		 3124/**
3125 * ata_data_xfer - Transfer data from/to the data register.
3126 * @ap: port to read/write
3127 * @buf: data buffer
3128 * @buflen: buffer length
3129 * @do_write: read/write
3130 *
3131 * Transfer data from/to the device data register.
3132 *
3133 * LOCKING:
3134 * Inherited from caller.
6ae4cfb5
AL		 3135 */
3136
1da177e4
LT		 3137static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3138 unsigned int buflen, int do_write)
3139{
a1bd9e68
AC		 3140 /* Make the crap hardware pay the costs not the good stuff */
3141 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3142 unsigned long flags;
3143 local_irq_save(flags);
3144 if (ap->flags & ATA_FLAG_MMIO)
3145 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3146 else
3147 ata_pio_data_xfer(ap, buf, buflen, do_write);
3148 local_irq_restore(flags);
3149 } else {
3150 if (ap->flags & ATA_FLAG_MMIO)
3151 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3152 else
3153 ata_pio_data_xfer(ap, buf, buflen, do_write);
3154 }
1da177e4
LT		 3155}
3156
6ae4cfb5
AL		 3157/**
3158 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3159 * @qc: Command on going
3160 *
3161 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3162 *
3163 * LOCKING:
3164 * Inherited from caller.
3165 */
3166
1da177e4
LT		 3167static void ata_pio_sector(struct ata_queued_cmd *qc)
3168{
3169 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3170 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3171 struct ata_port *ap = qc->ap;
3172 struct page *page;
3173 unsigned int offset;
3174 unsigned char *buf;
3175
3176 if (qc->cursect == (qc->nsect - 1))
14be71f4 3177 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3178
3179 page = sg[qc->cursg].page;
3180 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3181
3182 /* get the current page and offset */
3183 page = nth_page(page, (offset >> PAGE_SHIFT));
3184 offset %= PAGE_SIZE;
3185
3186 buf = kmap(page) + offset;
3187
3188 qc->cursect++;
3189 qc->cursg_ofs++;
3190
32529e01 3191 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3192 qc->cursg++;
3193 qc->cursg_ofs = 0;
3194 }
3195
3196 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3197
3198 /* do the actual data transfer */
3199 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3200 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3201
3202 kunmap(page);
3203}
3204
6ae4cfb5
AL		 3205/**
3206 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3207 * @qc: Command on going
3208 * @bytes: number of bytes
3209 *
3210 * Transfer Transfer data from/to the ATAPI device.
3211 *
3212 * LOCKING:
3213 * Inherited from caller.
3214 *
3215 */
3216
1da177e4
LT		 3217static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3218{
3219 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3220 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3221 struct ata_port *ap = qc->ap;
3222 struct page *page;
3223 unsigned char *buf;
3224 unsigned int offset, count;
3225
563a6e1f 3226 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3227 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3228
3229next_sg:
563a6e1f 3230 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3231 /*
563a6e1f
AL		 3232 * The end of qc->sg is reached and the device expects
3233 * more data to transfer. In order not to overrun qc->sg
3234 * and fulfill length specified in the byte count register,
3235 * - for read case, discard trailing data from the device
3236 * - for write case, padding zero data to the device
3237 */
3238 u16 pad_buf[1] = { 0 };
3239 unsigned int words = bytes >> 1;
3240 unsigned int i;
3241
3242 if (words) /* warning if bytes > 1 */
7fb6ec28 3243 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3244 ap->id, bytes);
3245
3246 for (i = 0; i < words; i++)
3247 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3248
14be71f4 3249 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3250 return;
3251 }
3252
cedc9a47 3253 sg = &qc->__sg[qc->cursg];
1da177e4 3254
1da177e4
LT		 3255 page = sg->page;
3256 offset = sg->offset + qc->cursg_ofs;
3257
3258 /* get the current page and offset */
3259 page = nth_page(page, (offset >> PAGE_SHIFT));
3260 offset %= PAGE_SIZE;
3261
6952df03 3262 /* don't overrun current sg */
32529e01 3263 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3264
3265 /* don't cross page boundaries */
3266 count = min(count, (unsigned int)PAGE_SIZE - offset);
3267
3268 buf = kmap(page) + offset;
3269
3270 bytes -= count;
3271 qc->curbytes += count;
3272 qc->cursg_ofs += count;
3273
32529e01 3274 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3275 qc->cursg++;
3276 qc->cursg_ofs = 0;
3277 }
3278
3279 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3280
3281 /* do the actual data transfer */
3282 ata_data_xfer(ap, buf, count, do_write);
3283
3284 kunmap(page);
3285
563a6e1f 3286 if (bytes)
1da177e4 3287 goto next_sg;
1da177e4
LT		 3288}
3289
6ae4cfb5
AL		 3290/**
3291 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3292 * @qc: Command on going
3293 *
3294 * Transfer Transfer data from/to the ATAPI device.
3295 *
3296 * LOCKING:
3297 * Inherited from caller.
6ae4cfb5
AL		 3298 */
3299
1da177e4
LT		 3300static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3301{
3302 struct ata_port *ap = qc->ap;
3303 struct ata_device *dev = qc->dev;
3304 unsigned int ireason, bc_lo, bc_hi, bytes;
3305 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3306
3307 ap->ops->tf_read(ap, &qc->tf);
3308 ireason = qc->tf.nsect;
3309 bc_lo = qc->tf.lbam;
3310 bc_hi = qc->tf.lbah;
3311 bytes = (bc_hi << 8) | bc_lo;
3312
3313 /* shall be cleared to zero, indicating xfer of data */
3314 if (ireason & (1 << 0))
3315 goto err_out;
3316
3317 /* make sure transfer direction matches expected */
3318 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3319 if (do_write != i_write)
3320 goto err_out;
3321
3322 __atapi_pio_bytes(qc, bytes);
3323
3324 return;
3325
3326err_out:
3327 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3328 ap->id, dev->devno);
11a56d24 3329 qc->err_mask |= AC_ERR_HSM;
14be71f4 3330 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3331}
3332
3333/**
6f0ef4fa
RD		 3334 * ata_pio_block - start PIO on a block
3335 * @ap: the target ata_port
1da177e4
LT		 3336 *
3337 * LOCKING:
0cba632b 3338 * None. (executing in kernel thread context)
1da177e4
LT		 3339 */
3340
3341static void ata_pio_block(struct ata_port *ap)
3342{
3343 struct ata_queued_cmd *qc;
3344 u8 status;
3345
3346 /*
6f0ef4fa 3347 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3348 * Sometimes when we enter, BSY will be cleared in
3349 * a chk-status or two. If not, the drive is probably seeking
3350 * or something. Snooze for a couple msecs, then
3351 * chk-status again. If still busy, fall back to
14be71f4 3352 * HSM_ST_POLL state.
1da177e4
LT		 3353 */
3354 status = ata_busy_wait(ap, ATA_BUSY, 5);
3355 if (status & ATA_BUSY) {
3356 msleep(2);
3357 status = ata_busy_wait(ap, ATA_BUSY, 10);
3358 if (status & ATA_BUSY) {
14be71f4 3359 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3360 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3361 return;
3362 }
3363 }
3364
3365 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3366 WARN_ON(qc == NULL);
1da177e4 3367
fe79e683
AL		 3368 /* check error */
3369 if (status & (ATA_ERR | ATA_DF)) {
3370 qc->err_mask |= AC_ERR_DEV;
3371 ap->hsm_task_state = HSM_ST_ERR;
3372 return;
3373 }
3374
3375 /* transfer data if any */
1da177e4 3376 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3377 /* DRQ=0 means no more data to transfer */
1da177e4 3378 if ((status & ATA_DRQ) == 0) {
14be71f4 3379 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3380 return;
3381 }
3382
3383 atapi_pio_bytes(qc);
3384 } else {
3385 /* handle BSY=0, DRQ=0 as error */
3386 if ((status & ATA_DRQ) == 0) {
11a56d24 3387 qc->err_mask |= AC_ERR_HSM;
14be71f4 3388 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3389 return;
3390 }
3391
3392 ata_pio_sector(qc);
3393 }
3394}
3395
3396static void ata_pio_error(struct ata_port *ap)
3397{
3398 struct ata_queued_cmd *qc;
a7dac447
JG		 3399
3400 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3401
3402 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3403 WARN_ON(qc == NULL);
1da177e4 3404
1c848984
AL		 3405 /* make sure qc->err_mask is available to
3406 * know what's wrong and recover
3407 */
a4631474 3408 WARN_ON(qc->err_mask == 0);
1c848984 3409
14be71f4 3410 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3411
a22e2eb0 3412 ata_poll_qc_complete(qc);
1da177e4
LT		 3413}
3414
3415static void ata_pio_task(void *_data)
3416{
3417 struct ata_port *ap = _data;
7fb6ec28
JG		 3418 unsigned long timeout;
3419 int qc_completed;
3420
3421fsm_start:
3422 timeout = 0;
3423 qc_completed = 0;
1da177e4 3424
14be71f4
AL		 3425 switch (ap->hsm_task_state) {
3426 case HSM_ST_IDLE:
1da177e4
LT		 3427 return;
3428
14be71f4 3429 case HSM_ST:
1da177e4
LT		 3430 ata_pio_block(ap);
3431 break;
3432
14be71f4 3433 case HSM_ST_LAST:
7fb6ec28 3434 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3435 break;
3436
14be71f4
AL		 3437 case HSM_ST_POLL:
3438 case HSM_ST_LAST_POLL:
1da177e4
LT		 3439 timeout = ata_pio_poll(ap);
3440 break;
3441
14be71f4
AL		 3442 case HSM_ST_TMOUT:
3443 case HSM_ST_ERR:
1da177e4
LT		 3444 ata_pio_error(ap);
3445 return;
3446 }
3447
3448 if (timeout)
95064379 3449 ata_queue_delayed_pio_task(ap, timeout);
7fb6ec28
JG		 3450 else if (!qc_completed)
3451 goto fsm_start;
1da177e4
LT		 3452}
3453
1da177e4
LT		 3454/**
3455 * ata_qc_timeout - Handle timeout of queued command
3456 * @qc: Command that timed out
3457 *
3458 * Some part of the kernel (currently, only the SCSI layer)
3459 * has noticed that the active command on port @ap has not
3460 * completed after a specified length of time. Handle this
3461 * condition by disabling DMA (if necessary) and completing
3462 * transactions, with error if necessary.
3463 *
3464 * This also handles the case of the "lost interrupt", where
3465 * for some reason (possibly hardware bug, possibly driver bug)
3466 * an interrupt was not delivered to the driver, even though the
3467 * transaction completed successfully.
3468 *
3469 * LOCKING:
0cba632b 3470 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3471 */
3472
3473static void ata_qc_timeout(struct ata_queued_cmd *qc)
3474{
3475 struct ata_port *ap = qc->ap;
b8f6153e 3476 struct ata_host_set *host_set = ap->host_set;
1da177e4 3477 u8 host_stat = 0, drv_stat;
b8f6153e 3478 unsigned long flags;
1da177e4
LT		 3479
3480 DPRINTK("ENTER\n");
3481
c18d06f8
TH		 3482 ata_flush_pio_tasks(ap);
3483 ap->hsm_task_state = HSM_ST_IDLE;
3484
b8f6153e
JG		 3485 spin_lock_irqsave(&host_set->lock, flags);
3486
1da177e4
LT		 3487 switch (qc->tf.protocol) {
3488
3489 case ATA_PROT_DMA:
3490 case ATA_PROT_ATAPI_DMA:
3491 host_stat = ap->ops->bmdma_status(ap);
3492
3493 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3494 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3495
3496 /* fall through */
3497
3498 default:
3499 ata_altstatus(ap);
3500 drv_stat = ata_chk_status(ap);
3501
3502 /* ack bmdma irq events */
3503 ap->ops->irq_clear(ap);
3504
3505 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3506 ap->id, qc->tf.command, drv_stat, host_stat);
3507
3508 /* complete taskfile transaction */
a22e2eb0 3509 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT		 3510 break;
3511 }
b8f6153e
JG		 3512
3513 spin_unlock_irqrestore(&host_set->lock, flags);
3514
a72ec4ce
TH		 3515 ata_eh_qc_complete(qc);
3516
1da177e4
LT		 3517 DPRINTK("EXIT\n");
3518}
3519
3520/**
3521 * ata_eng_timeout - Handle timeout of queued command
3522 * @ap: Port on which timed-out command is active
3523 *
3524 * Some part of the kernel (currently, only the SCSI layer)
3525 * has noticed that the active command on port @ap has not
3526 * completed after a specified length of time. Handle this
3527 * condition by disabling DMA (if necessary) and completing
3528 * transactions, with error if necessary.
3529 *
3530 * This also handles the case of the "lost interrupt", where
3531 * for some reason (possibly hardware bug, possibly driver bug)
3532 * an interrupt was not delivered to the driver, even though the
3533 * transaction completed successfully.
3534 *
3535 * LOCKING:
3536 * Inherited from SCSI layer (none, can sleep)
3537 */
3538
3539void ata_eng_timeout(struct ata_port *ap)
3540{
1da177e4
LT		 3541 DPRINTK("ENTER\n");
3542
f6379020 3543 ata_qc_timeout(ata_qc_from_tag(ap, ap->active_tag));
1da177e4 3544
1da177e4
LT		 3545 DPRINTK("EXIT\n");
3546}
3547
3548/**
3549 * ata_qc_new - Request an available ATA command, for queueing
3550 * @ap: Port associated with device @dev
3551 * @dev: Device from whom we request an available command structure
3552 *
3553 * LOCKING:
0cba632b 3554 * None.
1da177e4
LT		 3555 */
3556
3557static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3558{
3559 struct ata_queued_cmd *qc = NULL;
3560 unsigned int i;
3561
3562 for (i = 0; i < ATA_MAX_QUEUE; i++)
3563 if (!test_and_set_bit(i, &ap->qactive)) {
3564 qc = ata_qc_from_tag(ap, i);
3565 break;
3566 }
3567
3568 if (qc)
3569 qc->tag = i;
3570
3571 return qc;
3572}
3573
3574/**
3575 * ata_qc_new_init - Request an available ATA command, and initialize it
3576 * @ap: Port associated with device @dev
3577 * @dev: Device from whom we request an available command structure
3578 *
3579 * LOCKING:
0cba632b 3580 * None.
1da177e4
LT		 3581 */
3582
3583struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3584 struct ata_device *dev)
3585{
3586 struct ata_queued_cmd *qc;
3587
3588 qc = ata_qc_new(ap);
3589 if (qc) {
1da177e4
LT		 3590 qc->scsicmd = NULL;
3591 qc->ap = ap;
3592 qc->dev = dev;
1da177e4 3593
2c13b7ce 3594 ata_qc_reinit(qc);
1da177e4
LT		 3595 }
3596
3597 return qc;
3598}
3599
1da177e4
LT		 3600/**
3601 * ata_qc_free - free unused ata_queued_cmd
3602 * @qc: Command to complete
3603 *
3604 * Designed to free unused ata_queued_cmd object
3605 * in case something prevents using it.
3606 *
3607 * LOCKING:
0cba632b 3608 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3609 */
3610void ata_qc_free(struct ata_queued_cmd *qc)
3611{
4ba946e9
TH		 3612 struct ata_port *ap = qc->ap;
3613 unsigned int tag;
3614
a4631474 3615 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3616
4ba946e9
TH		 3617 qc->flags = 0;
3618 tag = qc->tag;
3619 if (likely(ata_tag_valid(tag))) {
3620 if (tag == ap->active_tag)
3621 ap->active_tag = ATA_TAG_POISON;
3622 qc->tag = ATA_TAG_POISON;
3623 clear_bit(tag, &ap->qactive);
3624 }
1da177e4
LT		 3625}
3626
76014427 3627void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 3628{
a4631474
TH		 3629 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
3630 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 3631
3632 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3633 ata_sg_clean(qc);
3634
3f3791d3
AL		 3635 /* atapi: mark qc as inactive to prevent the interrupt handler
3636 * from completing the command twice later, before the error handler
3637 * is called. (when rc != 0 and atapi request sense is needed)
3638 */
3639 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3640
1da177e4 3641 /* call completion callback */
77853bf2 3642 qc->complete_fn(qc);
1da177e4
LT		 3643}
3644
3645static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3646{
3647 struct ata_port *ap = qc->ap;
3648
3649 switch (qc->tf.protocol) {
3650 case ATA_PROT_DMA:
3651 case ATA_PROT_ATAPI_DMA:
3652 return 1;
3653
3654 case ATA_PROT_ATAPI:
3655 case ATA_PROT_PIO:
3656 case ATA_PROT_PIO_MULT:
3657 if (ap->flags & ATA_FLAG_PIO_DMA)
3658 return 1;
3659
3660 /* fall through */
3661
3662 default:
3663 return 0;
3664 }
3665
3666 /* never reached */
3667}
3668
3669/**
3670 * ata_qc_issue - issue taskfile to device
3671 * @qc: command to issue to device
3672 *
3673 * Prepare an ATA command to submission to device.
3674 * This includes mapping the data into a DMA-able
3675 * area, filling in the S/G table, and finally
3676 * writing the taskfile to hardware, starting the command.
3677 *
3678 * LOCKING:
3679 * spin_lock_irqsave(host_set lock)
3680 *
3681 * RETURNS:
9a3d9eb0 3682 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3683 */
3684
9a3d9eb0 3685unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 3686{
3687 struct ata_port *ap = qc->ap;
3688
3689 if (ata_should_dma_map(qc)) {
3690 if (qc->flags & ATA_QCFLAG_SG) {
3691 if (ata_sg_setup(qc))
8e436af9 3692 goto sg_err;
1da177e4
LT		 3693 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3694 if (ata_sg_setup_one(qc))
8e436af9 3695 goto sg_err;
1da177e4
LT		 3696 }
3697 } else {
3698 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3699 }
3700
3701 ap->ops->qc_prep(qc);
3702
3703 qc->ap->active_tag = qc->tag;
3704 qc->flags |= ATA_QCFLAG_ACTIVE;
3705
3706 return ap->ops->qc_issue(qc);
3707
8e436af9
TH		 3708sg_err:
3709 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 3710 return AC_ERR_SYSTEM;
1da177e4
LT		 3711}
3712
0baab86b 3713
1da177e4
LT		 3714/**
3715 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3716 * @qc: command to issue to device
3717 *
3718 * Using various libata functions and hooks, this function
3719 * starts an ATA command. ATA commands are grouped into
3720 * classes called "protocols", and issuing each type of protocol
3721 * is slightly different.
3722 *
0baab86b
EF		 3723 * May be used as the qc_issue() entry in ata_port_operations.
3724 *
1da177e4
LT		 3725 * LOCKING:
3726 * spin_lock_irqsave(host_set lock)
3727 *
3728 * RETURNS:
9a3d9eb0 3729 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3730 */
3731
9a3d9eb0 3732unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 3733{
3734 struct ata_port *ap = qc->ap;
3735
3736 ata_dev_select(ap, qc->dev->devno, 1, 0);
3737
3738 switch (qc->tf.protocol) {
3739 case ATA_PROT_NODATA:
e5338254 3740 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3741 break;
3742
3743 case ATA_PROT_DMA:
3744 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3745 ap->ops->bmdma_setup(qc); /* set up bmdma */
3746 ap->ops->bmdma_start(qc); /* initiate bmdma */
3747 break;
3748
3749 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3750 ata_qc_set_polling(qc);
e5338254 3751 ata_tf_to_host(ap, &qc->tf);
14be71f4 3752 ap->hsm_task_state = HSM_ST;
95064379 3753 ata_queue_pio_task(ap);
1da177e4
LT		 3754 break;
3755
3756 case ATA_PROT_ATAPI:
3757 ata_qc_set_polling(qc);
e5338254 3758 ata_tf_to_host(ap, &qc->tf);
95064379 3759 ata_queue_packet_task(ap);
1da177e4
LT		 3760 break;
3761
3762 case ATA_PROT_ATAPI_NODATA:
c1389503 3763 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3764 ata_tf_to_host(ap, &qc->tf);
95064379 3765 ata_queue_packet_task(ap);
1da177e4
LT		 3766 break;
3767
3768 case ATA_PROT_ATAPI_DMA:
c1389503 3769 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3770 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3771 ap->ops->bmdma_setup(qc); /* set up bmdma */
95064379 3772 ata_queue_packet_task(ap);
1da177e4
LT		 3773 break;
3774
3775 default:
3776 WARN_ON(1);
9a3d9eb0 3777 return AC_ERR_SYSTEM;
1da177e4
LT		 3778 }
3779
3780 return 0;
3781}
3782
3783/**
0baab86b 3784 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3785 * @qc: Info associated with this ATA transaction.
3786 *
3787 * LOCKING:
3788 * spin_lock_irqsave(host_set lock)
3789 */
3790
3791static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3792{
3793 struct ata_port *ap = qc->ap;
3794 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3795 u8 dmactl;
3796 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3797
3798 /* load PRD table addr. */
3799 mb(); /* make sure PRD table writes are visible to controller */
3800 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3801
3802 /* specify data direction, triple-check start bit is clear */
3803 dmactl = readb(mmio + ATA_DMA_CMD);
3804 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3805 if (!rw)
3806 dmactl |= ATA_DMA_WR;
3807 writeb(dmactl, mmio + ATA_DMA_CMD);
3808
3809 /* issue r/w command */
3810 ap->ops->exec_command(ap, &qc->tf);
3811}
3812
3813/**
b73fc89f 3814 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3815 * @qc: Info associated with this ATA transaction.
3816 *
3817 * LOCKING:
3818 * spin_lock_irqsave(host_set lock)
3819 */
3820
3821static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3822{
3823 struct ata_port *ap = qc->ap;
3824 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3825 u8 dmactl;
3826
3827 /* start host DMA transaction */
3828 dmactl = readb(mmio + ATA_DMA_CMD);
3829 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3830
3831 /* Strictly, one may wish to issue a readb() here, to
3832 * flush the mmio write. However, control also passes
3833 * to the hardware at this point, and it will interrupt
3834 * us when we are to resume control. So, in effect,
3835 * we don't care when the mmio write flushes.
3836 * Further, a read of the DMA status register _immediately_
3837 * following the write may not be what certain flaky hardware
3838 * is expected, so I think it is best to not add a readb()
3839 * without first all the MMIO ATA cards/mobos.
3840 * Or maybe I'm just being paranoid.
3841 */
3842}
3843
3844/**
3845 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3846 * @qc: Info associated with this ATA transaction.
3847 *
3848 * LOCKING:
3849 * spin_lock_irqsave(host_set lock)
3850 */
3851
3852static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3853{
3854 struct ata_port *ap = qc->ap;
3855 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3856 u8 dmactl;
3857
3858 /* load PRD table addr. */
3859 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3860
3861 /* specify data direction, triple-check start bit is clear */
3862 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3863 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3864 if (!rw)
3865 dmactl |= ATA_DMA_WR;
3866 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3867
3868 /* issue r/w command */
3869 ap->ops->exec_command(ap, &qc->tf);
3870}
3871
3872/**
3873 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3874 * @qc: Info associated with this ATA transaction.
3875 *
3876 * LOCKING:
3877 * spin_lock_irqsave(host_set lock)
3878 */
3879
3880static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3881{
3882 struct ata_port *ap = qc->ap;
3883 u8 dmactl;
3884
3885 /* start host DMA transaction */
3886 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3887 outb(dmactl | ATA_DMA_START,
3888 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3889}
3890
0baab86b
EF		 3891
3892/**
3893 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3894 * @qc: Info associated with this ATA transaction.
3895 *
3896 * Writes the ATA_DMA_START flag to the DMA command register.
3897 *
3898 * May be used as the bmdma_start() entry in ata_port_operations.
3899 *
3900 * LOCKING:
3901 * spin_lock_irqsave(host_set lock)
3902 */
1da177e4
LT		 3903void ata_bmdma_start(struct ata_queued_cmd *qc)
3904{
3905 if (qc->ap->flags & ATA_FLAG_MMIO)
3906 ata_bmdma_start_mmio(qc);
3907 else
3908 ata_bmdma_start_pio(qc);
3909}
3910
0baab86b
EF		 3911
3912/**
3913 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3914 * @qc: Info associated with this ATA transaction.
3915 *
3916 * Writes address of PRD table to device's PRD Table Address
3917 * register, sets the DMA control register, and calls
3918 * ops->exec_command() to start the transfer.
3919 *
3920 * May be used as the bmdma_setup() entry in ata_port_operations.
3921 *
3922 * LOCKING:
3923 * spin_lock_irqsave(host_set lock)
3924 */
1da177e4
LT		 3925void ata_bmdma_setup(struct ata_queued_cmd *qc)
3926{
3927 if (qc->ap->flags & ATA_FLAG_MMIO)
3928 ata_bmdma_setup_mmio(qc);
3929 else
3930 ata_bmdma_setup_pio(qc);
3931}
3932
0baab86b
EF		 3933
3934/**
3935 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3936 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3937 *
3938 * Clear interrupt and error flags in DMA status register.
3939 *
3940 * May be used as the irq_clear() entry in ata_port_operations.
3941 *
3942 * LOCKING:
3943 * spin_lock_irqsave(host_set lock)
3944 */
3945
1da177e4
LT		 3946void ata_bmdma_irq_clear(struct ata_port *ap)
3947{
3948 if (ap->flags & ATA_FLAG_MMIO) {
3949 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3950 writeb(readb(mmio), mmio);
3951 } else {
3952 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3953 outb(inb(addr), addr);
3954 }
3955
3956}
3957
0baab86b
EF		 3958
3959/**
3960 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3961 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3962 *
3963 * Read and return BMDMA status register.
3964 *
3965 * May be used as the bmdma_status() entry in ata_port_operations.
3966 *
3967 * LOCKING:
3968 * spin_lock_irqsave(host_set lock)
3969 */
3970
1da177e4
LT		 3971u8 ata_bmdma_status(struct ata_port *ap)
3972{
3973 u8 host_stat;
3974 if (ap->flags & ATA_FLAG_MMIO) {
3975 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3976 host_stat = readb(mmio + ATA_DMA_STATUS);
3977 } else
ee500aab 3978 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3979 return host_stat;
3980}
3981
0baab86b
EF		 3982
3983/**
3984 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 3985 * @qc: Command we are ending DMA for
0baab86b
EF		 3986 *
3987 * Clears the ATA_DMA_START flag in the dma control register
3988 *
3989 * May be used as the bmdma_stop() entry in ata_port_operations.
3990 *
3991 * LOCKING:
3992 * spin_lock_irqsave(host_set lock)
3993 */
3994
b73fc89f 3995void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 3996{
b73fc89f 3997 struct ata_port *ap = qc->ap;
1da177e4
LT		 3998 if (ap->flags & ATA_FLAG_MMIO) {
3999 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4000
4001 /* clear start/stop bit */
4002 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4003 mmio + ATA_DMA_CMD);
4004 } else {
4005 /* clear start/stop bit */
4006 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4007 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4008 }
4009
4010 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4011 ata_altstatus(ap); /* dummy read */
4012}
4013
4014/**
4015 * ata_host_intr - Handle host interrupt for given (port, task)
4016 * @ap: Port on which interrupt arrived (possibly...)
4017 * @qc: Taskfile currently active in engine
4018 *
4019 * Handle host interrupt for given queued command. Currently,
4020 * only DMA interrupts are handled. All other commands are
4021 * handled via polling with interrupts disabled (nIEN bit).
4022 *
4023 * LOCKING:
4024 * spin_lock_irqsave(host_set lock)
4025 *
4026 * RETURNS:
4027 * One if interrupt was handled, zero if not (shared irq).
4028 */
4029
4030inline unsigned int ata_host_intr (struct ata_port *ap,
4031 struct ata_queued_cmd *qc)
4032{
4033 u8 status, host_stat;
4034
4035 switch (qc->tf.protocol) {
4036
4037 case ATA_PROT_DMA:
4038 case ATA_PROT_ATAPI_DMA:
4039 case ATA_PROT_ATAPI:
4040 /* check status of DMA engine */
4041 host_stat = ap->ops->bmdma_status(ap);
4042 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4043
4044 /* if it's not our irq... */
4045 if (!(host_stat & ATA_DMA_INTR))
4046 goto idle_irq;
4047
4048 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4049 ap->ops->bmdma_stop(qc);
1da177e4
LT		 4050
4051 /* fall through */
4052
4053 case ATA_PROT_ATAPI_NODATA:
4054 case ATA_PROT_NODATA:
4055 /* check altstatus */
4056 status = ata_altstatus(ap);
4057 if (status & ATA_BUSY)
4058 goto idle_irq;
4059
4060 /* check main status, clearing INTRQ */
4061 status = ata_chk_status(ap);
4062 if (unlikely(status & ATA_BUSY))
4063 goto idle_irq;
4064 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4065 ap->id, qc->tf.protocol, status);
4066
4067 /* ack bmdma irq events */
4068 ap->ops->irq_clear(ap);
4069
4070 /* complete taskfile transaction */
a22e2eb0
AL		 4071 qc->err_mask |= ac_err_mask(status);
4072 ata_qc_complete(qc);
1da177e4
LT		 4073 break;
4074
4075 default:
4076 goto idle_irq;
4077 }
4078
4079 return 1; /* irq handled */
4080
4081idle_irq:
4082 ap->stats.idle_irq++;
4083
4084#ifdef ATA_IRQ_TRAP
4085 if ((ap->stats.idle_irq % 1000) == 0) {
4086 handled = 1;
4087 ata_irq_ack(ap, 0); /* debug trap */
4088 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4089 }
4090#endif
4091 return 0; /* irq not handled */
4092}
4093
4094/**
4095 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4096 * @irq: irq line (unused)
4097 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4098 * @regs: unused
4099 *
0cba632b
JG		 4100 * Default interrupt handler for PCI IDE devices. Calls
4101 * ata_host_intr() for each port that is not disabled.
4102 *
1da177e4 4103 * LOCKING:
0cba632b 4104 * Obtains host_set lock during operation.
1da177e4
LT		 4105 *
4106 * RETURNS:
0cba632b 4107 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4108 */
4109
4110irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4111{
4112 struct ata_host_set *host_set = dev_instance;
4113 unsigned int i;
4114 unsigned int handled = 0;
4115 unsigned long flags;
4116
4117 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4118 spin_lock_irqsave(&host_set->lock, flags);
4119
4120 for (i = 0; i < host_set->n_ports; i++) {
4121 struct ata_port *ap;
4122
4123 ap = host_set->ports[i];
c1389503
TH		 4124 if (ap &&
4125 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4126 struct ata_queued_cmd *qc;
4127
4128 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4129 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4130 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4131 handled |= ata_host_intr(ap, qc);
4132 }
4133 }
4134
4135 spin_unlock_irqrestore(&host_set->lock, flags);
4136
4137 return IRQ_RETVAL(handled);
4138}
4139
4140/**
4141 * atapi_packet_task - Write CDB bytes to hardware
4142 * @_data: Port to which ATAPI device is attached.
4143 *
4144 * When device has indicated its readiness to accept
4145 * a CDB, this function is called. Send the CDB.
4146 * If DMA is to be performed, exit immediately.
4147 * Otherwise, we are in polling mode, so poll
4148 * status under operation succeeds or fails.
4149 *
4150 * LOCKING:
4151 * Kernel thread context (may sleep)
4152 */
4153
4154static void atapi_packet_task(void *_data)
4155{
4156 struct ata_port *ap = _data;
4157 struct ata_queued_cmd *qc;
4158 u8 status;
4159
4160 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474
TH		 4161 WARN_ON(qc == NULL);
4162 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4163
4164 /* sleep-wait for BSY to clear */
4165 DPRINTK("busy wait\n");
d8fe452b 4166 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
11a56d24 4167 qc->err_mask |= AC_ERR_TIMEOUT;
d8fe452b
AL		 4168 goto err_out;
4169 }
1da177e4
LT		 4170
4171 /* make sure DRQ is set */
4172 status = ata_chk_status(ap);
d8fe452b 4173 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
11a56d24 4174 qc->err_mask |= AC_ERR_HSM;
1da177e4 4175 goto err_out;
d8fe452b 4176 }
1da177e4
LT		 4177
4178 /* send SCSI cdb */
4179 DPRINTK("send cdb\n");
a4631474 4180 WARN_ON(ap->cdb_len < 12);
1da177e4 4181
c1389503
TH		 4182 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4183 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4184 unsigned long flags;
1da177e4 4185
c1389503
TH		 4186 /* Once we're done issuing command and kicking bmdma,
4187 * irq handler takes over. To not lose irq, we need
4188 * to clear NOINTR flag before sending cdb, but
4189 * interrupt handler shouldn't be invoked before we're
4190 * finished. Hence, the following locking.
4191 */
4192 spin_lock_irqsave(&ap->host_set->lock, flags);
4193 ap->flags &= ~ATA_FLAG_NOINTR;
4194 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4195 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4196 ap->ops->bmdma_start(qc); /* initiate bmdma */
4197 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4198 } else {
4199 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4200
c1389503 4201 /* PIO commands are handled by polling */
14be71f4 4202 ap->hsm_task_state = HSM_ST;
95064379 4203 ata_queue_pio_task(ap);
1da177e4
LT		 4204 }
4205
4206 return;
4207
4208err_out:
a22e2eb0 4209 ata_poll_qc_complete(qc);
1da177e4
LT		 4210}
4211
0baab86b 4212
9b847548
JA		 4213/*
4214 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4215 * without filling any other registers
4216 */
4217static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4218 u8 cmd)
4219{
4220 struct ata_taskfile tf;
4221 int err;
4222
4223 ata_tf_init(ap, &tf, dev->devno);
4224
4225 tf.command = cmd;
4226 tf.flags |= ATA_TFLAG_DEVICE;
4227 tf.protocol = ATA_PROT_NODATA;
4228
4229 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4230 if (err)
4231 printk(KERN_ERR "%s: ata command failed: %d\n",
4232 __FUNCTION__, err);
4233
4234 return err;
4235}
4236
4237static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4238{
4239 u8 cmd;
4240
4241 if (!ata_try_flush_cache(dev))
4242 return 0;
4243
4244 if (ata_id_has_flush_ext(dev->id))
4245 cmd = ATA_CMD_FLUSH_EXT;
4246 else
4247 cmd = ATA_CMD_FLUSH;
4248
4249 return ata_do_simple_cmd(ap, dev, cmd);
4250}
4251
4252static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4253{
4254 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4255}
4256
4257static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4258{
4259 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4260}
4261
4262/**
4263 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD		 4264 * @ap: port the device is connected to
4265 * @dev: the device to resume
9b847548
JA		 4266 *
4267 * Kick the drive back into action, by sending it an idle immediate
4268 * command and making sure its transfer mode matches between drive
4269 * and host.
4270 *
4271 */
4272int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4273{
4274 if (ap->flags & ATA_FLAG_SUSPENDED) {
4275 ap->flags &= ~ATA_FLAG_SUSPENDED;
4276 ata_set_mode(ap);
4277 }
4278 if (!ata_dev_present(dev))
4279 return 0;
4280 if (dev->class == ATA_DEV_ATA)
4281 ata_start_drive(ap, dev);
4282
4283 return 0;
4284}
4285
4286/**
4287 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD		 4288 * @ap: port the device is connected to
4289 * @dev: the device to suspend
9b847548
JA		 4290 *
4291 * Flush the cache on the drive, if appropriate, then issue a
4292 * standbynow command.
9b847548
JA		 4293 */
4294int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4295{
4296 if (!ata_dev_present(dev))
4297 return 0;
4298 if (dev->class == ATA_DEV_ATA)
4299 ata_flush_cache(ap, dev);
4300
4301 ata_standby_drive(ap, dev);
4302 ap->flags |= ATA_FLAG_SUSPENDED;
4303 return 0;
4304}
4305
c893a3ae
RD		 4306/**
4307 * ata_port_start - Set port up for dma.
4308 * @ap: Port to initialize
4309 *
4310 * Called just after data structures for each port are
4311 * initialized. Allocates space for PRD table.
4312 *
4313 * May be used as the port_start() entry in ata_port_operations.
4314 *
4315 * LOCKING:
4316 * Inherited from caller.
4317 */
4318
1da177e4
LT		 4319int ata_port_start (struct ata_port *ap)
4320{
4321 struct device *dev = ap->host_set->dev;
6037d6bb 4322 int rc;
1da177e4
LT		 4323
4324 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4325 if (!ap->prd)
4326 return -ENOMEM;
4327
6037d6bb
JG		 4328 rc = ata_pad_alloc(ap, dev);
4329 if (rc) {
cedc9a47 4330 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4331 return rc;
cedc9a47
JG		 4332 }
4333
1da177e4
LT		 4334 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4335
4336 return 0;
4337}
4338
0baab86b
EF		 4339
4340/**
4341 * ata_port_stop - Undo ata_port_start()
4342 * @ap: Port to shut down
4343 *
4344 * Frees the PRD table.
4345 *
4346 * May be used as the port_stop() entry in ata_port_operations.
4347 *
4348 * LOCKING:
6f0ef4fa 4349 * Inherited from caller.
0baab86b
EF		 4350 */
4351
1da177e4
LT		 4352void ata_port_stop (struct ata_port *ap)
4353{
4354 struct device *dev = ap->host_set->dev;
4355
4356 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4357 ata_pad_free(ap, dev);
1da177e4
LT		 4358}
4359
aa8f0dc6
JG		 4360void ata_host_stop (struct ata_host_set *host_set)
4361{
4362 if (host_set->mmio_base)
4363 iounmap(host_set->mmio_base);
4364}
4365
4366
1da177e4
LT		 4367/**
4368 * ata_host_remove - Unregister SCSI host structure with upper layers
4369 * @ap: Port to unregister
4370 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4371 *
4372 * LOCKING:
6f0ef4fa 4373 * Inherited from caller.
1da177e4
LT		 4374 */
4375
4376static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4377{
4378 struct Scsi_Host *sh = ap->host;
4379
4380 DPRINTK("ENTER\n");
4381
4382 if (do_unregister)
4383 scsi_remove_host(sh);
4384
4385 ap->ops->port_stop(ap);
4386}
4387
4388/**
4389 * ata_host_init - Initialize an ata_port structure
4390 * @ap: Structure to initialize
4391 * @host: associated SCSI mid-layer structure
4392 * @host_set: Collection of hosts to which @ap belongs
4393 * @ent: Probe information provided by low-level driver
4394 * @port_no: Port number associated with this ata_port
4395 *
0cba632b
JG		 4396 * Initialize a new ata_port structure, and its associated
4397 * scsi_host.
4398 *
1da177e4 4399 * LOCKING:
0cba632b 4400 * Inherited from caller.
1da177e4
LT		 4401 */
4402
4403static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4404 struct ata_host_set *host_set,
057ace5e 4405 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4406{
4407 unsigned int i;
4408
4409 host->max_id = 16;
4410 host->max_lun = 1;
4411 host->max_channel = 1;
4412 host->unique_id = ata_unique_id++;
4413 host->max_cmd_len = 12;
12413197 4414
1da177e4
LT		 4415 ap->flags = ATA_FLAG_PORT_DISABLED;
4416 ap->id = host->unique_id;
4417 ap->host = host;
4418 ap->ctl = ATA_DEVCTL_OBS;
4419 ap->host_set = host_set;
4420 ap->port_no = port_no;
4421 ap->hard_port_no =
4422 ent->legacy_mode ? ent->hard_port_no : port_no;
4423 ap->pio_mask = ent->pio_mask;
4424 ap->mwdma_mask = ent->mwdma_mask;
4425 ap->udma_mask = ent->udma_mask;
4426 ap->flags |= ent->host_flags;
4427 ap->ops = ent->port_ops;
4428 ap->cbl = ATA_CBL_NONE;
4429 ap->active_tag = ATA_TAG_POISON;
4430 ap->last_ctl = 0xFF;
4431
4432 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4433 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
a72ec4ce 4434 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT		 4435
4436 for (i = 0; i < ATA_MAX_DEVICES; i++)
4437 ap->device[i].devno = i;
4438
4439#ifdef ATA_IRQ_TRAP
4440 ap->stats.unhandled_irq = 1;
4441 ap->stats.idle_irq = 1;
4442#endif
4443
4444 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4445}
4446
4447/**
4448 * ata_host_add - Attach low-level ATA driver to system
4449 * @ent: Information provided by low-level driver
4450 * @host_set: Collections of ports to which we add
4451 * @port_no: Port number associated with this host
4452 *
0cba632b
JG		 4453 * Attach low-level ATA driver to system.
4454 *
1da177e4 4455 * LOCKING:
0cba632b 4456 * PCI/etc. bus probe sem.
1da177e4
LT		 4457 *
4458 * RETURNS:
0cba632b 4459 * New ata_port on success, for NULL on error.
1da177e4
LT		 4460 */
4461
057ace5e 4462static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4463 struct ata_host_set *host_set,
4464 unsigned int port_no)
4465{
4466 struct Scsi_Host *host;
4467 struct ata_port *ap;
4468 int rc;
4469
4470 DPRINTK("ENTER\n");
4471 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4472 if (!host)
4473 return NULL;
4474
4475 ap = (struct ata_port *) &host->hostdata[0];
4476
4477 ata_host_init(ap, host, host_set, ent, port_no);
4478
4479 rc = ap->ops->port_start(ap);
4480 if (rc)
4481 goto err_out;
4482
4483 return ap;
4484
4485err_out:
4486 scsi_host_put(host);
4487 return NULL;
4488}
4489
4490/**
0cba632b
JG		 4491 * ata_device_add - Register hardware device with ATA and SCSI layers
4492 * @ent: Probe information describing hardware device to be registered
4493 *
4494 * This function processes the information provided in the probe
4495 * information struct @ent, allocates the necessary ATA and SCSI
4496 * host information structures, initializes them, and registers
4497 * everything with requisite kernel subsystems.
4498 *
4499 * This function requests irqs, probes the ATA bus, and probes
4500 * the SCSI bus.
1da177e4
LT		 4501 *
4502 * LOCKING:
0cba632b 4503 * PCI/etc. bus probe sem.
1da177e4
LT		 4504 *
4505 * RETURNS:
0cba632b 4506 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4507 */
4508
057ace5e 4509int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4510{
4511 unsigned int count = 0, i;
4512 struct device *dev = ent->dev;
4513 struct ata_host_set *host_set;
4514
4515 DPRINTK("ENTER\n");
4516 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4517 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4518 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4519 if (!host_set)
4520 return 0;
1da177e4
LT		 4521 spin_lock_init(&host_set->lock);
4522
4523 host_set->dev = dev;
4524 host_set->n_ports = ent->n_ports;
4525 host_set->irq = ent->irq;
4526 host_set->mmio_base = ent->mmio_base;
4527 host_set->private_data = ent->private_data;
4528 host_set->ops = ent->port_ops;
4529
4530 /* register each port bound to this device */
4531 for (i = 0; i < ent->n_ports; i++) {
4532 struct ata_port *ap;
4533 unsigned long xfer_mode_mask;
4534
4535 ap = ata_host_add(ent, host_set, i);
4536 if (!ap)
4537 goto err_out;
4538
4539 host_set->ports[i] = ap;
4540 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4541 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4542 (ap->pio_mask << ATA_SHIFT_PIO);
4543
4544 /* print per-port info to dmesg */
4545 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4546 "bmdma 0x%lX irq %lu\n",
4547 ap->id,
4548 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4549 ata_mode_string(xfer_mode_mask),
4550 ap->ioaddr.cmd_addr,
4551 ap->ioaddr.ctl_addr,
4552 ap->ioaddr.bmdma_addr,
4553 ent->irq);
4554
4555 ata_chk_status(ap);
4556 host_set->ops->irq_clear(ap);
4557 count++;
4558 }
4559
57f3bda8
RD		 4560 if (!count)
4561 goto err_free_ret;
1da177e4
LT		 4562
4563 /* obtain irq, that is shared between channels */
4564 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4565 DRV_NAME, host_set))
4566 goto err_out;
4567
4568 /* perform each probe synchronously */
4569 DPRINTK("probe begin\n");
4570 for (i = 0; i < count; i++) {
4571 struct ata_port *ap;
4572 int rc;
4573
4574 ap = host_set->ports[i];
4575
c893a3ae 4576 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4577 rc = ata_bus_probe(ap);
c893a3ae 4578 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 4579
4580 if (rc) {
4581 /* FIXME: do something useful here?
4582 * Current libata behavior will
4583 * tear down everything when
4584 * the module is removed
4585 * or the h/w is unplugged.
4586 */
4587 }
4588
4589 rc = scsi_add_host(ap->host, dev);
4590 if (rc) {
4591 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4592 ap->id);
4593 /* FIXME: do something useful here */
4594 /* FIXME: handle unconditional calls to
4595 * scsi_scan_host and ata_host_remove, below,
4596 * at the very least
4597 */
4598 }
4599 }
4600
4601 /* probes are done, now scan each port's disk(s) */
c893a3ae 4602 DPRINTK("host probe begin\n");
1da177e4
LT		 4603 for (i = 0; i < count; i++) {
4604 struct ata_port *ap = host_set->ports[i];
4605
644dd0cc 4606 ata_scsi_scan_host(ap);
1da177e4
LT		 4607 }
4608
4609 dev_set_drvdata(dev, host_set);
4610
4611 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4612 return ent->n_ports; /* success */
4613
4614err_out:
4615 for (i = 0; i < count; i++) {
4616 ata_host_remove(host_set->ports[i], 1);
4617 scsi_host_put(host_set->ports[i]->host);
4618 }
57f3bda8 4619err_free_ret:
1da177e4
LT		 4620 kfree(host_set);
4621 VPRINTK("EXIT, returning 0\n");
4622 return 0;
4623}
4624
17b14451
AC		 4625/**
4626 * ata_host_set_remove - PCI layer callback for device removal
4627 * @host_set: ATA host set that was removed
4628 *
4629 * Unregister all objects associated with this host set. Free those
4630 * objects.
4631 *
4632 * LOCKING:
4633 * Inherited from calling layer (may sleep).
4634 */
4635
17b14451
AC		 4636void ata_host_set_remove(struct ata_host_set *host_set)
4637{
4638 struct ata_port *ap;
4639 unsigned int i;
4640
4641 for (i = 0; i < host_set->n_ports; i++) {
4642 ap = host_set->ports[i];
4643 scsi_remove_host(ap->host);
4644 }
4645
4646 free_irq(host_set->irq, host_set);
4647
4648 for (i = 0; i < host_set->n_ports; i++) {
4649 ap = host_set->ports[i];
4650
4651 ata_scsi_release(ap->host);
4652
4653 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4654 struct ata_ioports *ioaddr = &ap->ioaddr;
4655
4656 if (ioaddr->cmd_addr == 0x1f0)
4657 release_region(0x1f0, 8);
4658 else if (ioaddr->cmd_addr == 0x170)
4659 release_region(0x170, 8);
4660 }
4661
4662 scsi_host_put(ap->host);
4663 }
4664
4665 if (host_set->ops->host_stop)
4666 host_set->ops->host_stop(host_set);
4667
4668 kfree(host_set);
4669}
4670
1da177e4
LT		 4671/**
4672 * ata_scsi_release - SCSI layer callback hook for host unload
4673 * @host: libata host to be unloaded
4674 *
4675 * Performs all duties necessary to shut down a libata port...
4676 * Kill port kthread, disable port, and release resources.
4677 *
4678 * LOCKING:
4679 * Inherited from SCSI layer.
4680 *
4681 * RETURNS:
4682 * One.
4683 */
4684
4685int ata_scsi_release(struct Scsi_Host *host)
4686{
4687 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4688
4689 DPRINTK("ENTER\n");
4690
4691 ap->ops->port_disable(ap);
4692 ata_host_remove(ap, 0);
4693
4694 DPRINTK("EXIT\n");
4695 return 1;
4696}
4697
4698/**
4699 * ata_std_ports - initialize ioaddr with standard port offsets.
4700 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4701 *
4702 * Utility function which initializes data_addr, error_addr,
4703 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4704 * device_addr, status_addr, and command_addr to standard offsets
4705 * relative to cmd_addr.
4706 *
4707 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4708 */
0baab86b 4709
1da177e4
LT		 4710void ata_std_ports(struct ata_ioports *ioaddr)
4711{
4712 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4713 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4714 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4715 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4716 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4717 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4718 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4719 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4720 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4721 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4722}
4723
0baab86b 4724
374b1873
JG		 4725#ifdef CONFIG_PCI
4726
4727void ata_pci_host_stop (struct ata_host_set *host_set)
4728{
4729 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4730
4731 pci_iounmap(pdev, host_set->mmio_base);
4732}
4733
1da177e4
LT		 4734/**
4735 * ata_pci_remove_one - PCI layer callback for device removal
4736 * @pdev: PCI device that was removed
4737 *
4738 * PCI layer indicates to libata via this hook that
6f0ef4fa 4739 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4740 * Handle this by unregistering all objects associated
4741 * with this PCI device. Free those objects. Then finally
4742 * release PCI resources and disable device.
4743 *
4744 * LOCKING:
4745 * Inherited from PCI layer (may sleep).
4746 */
4747
4748void ata_pci_remove_one (struct pci_dev *pdev)
4749{
4750 struct device *dev = pci_dev_to_dev(pdev);
4751 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4752
17b14451 4753 ata_host_set_remove(host_set);
1da177e4
LT		 4754 pci_release_regions(pdev);
4755 pci_disable_device(pdev);
4756 dev_set_drvdata(dev, NULL);
4757}
4758
4759/* move to PCI subsystem */
057ace5e 4760int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4761{
4762 unsigned long tmp = 0;
4763
4764 switch (bits->width) {
4765 case 1: {
4766 u8 tmp8 = 0;
4767 pci_read_config_byte(pdev, bits->reg, &tmp8);
4768 tmp = tmp8;
4769 break;
4770 }
4771 case 2: {
4772 u16 tmp16 = 0;
4773 pci_read_config_word(pdev, bits->reg, &tmp16);
4774 tmp = tmp16;
4775 break;
4776 }
4777 case 4: {
4778 u32 tmp32 = 0;
4779 pci_read_config_dword(pdev, bits->reg, &tmp32);
4780 tmp = tmp32;
4781 break;
4782 }
4783
4784 default:
4785 return -EINVAL;
4786 }
4787
4788 tmp &= bits->mask;
4789
4790 return (tmp == bits->val) ? 1 : 0;
4791}
9b847548
JA		 4792
4793int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
4794{
4795 pci_save_state(pdev);
4796 pci_disable_device(pdev);
4797 pci_set_power_state(pdev, PCI_D3hot);
4798 return 0;
4799}
4800
4801int ata_pci_device_resume(struct pci_dev *pdev)
4802{
4803 pci_set_power_state(pdev, PCI_D0);
4804 pci_restore_state(pdev);
4805 pci_enable_device(pdev);
4806 pci_set_master(pdev);
4807 return 0;
4808}
1da177e4
LT		 4809#endif /* CONFIG_PCI */
4810
4811
1da177e4
LT		 4812static int __init ata_init(void)
4813{
4814 ata_wq = create_workqueue("ata");
4815 if (!ata_wq)
4816 return -ENOMEM;
4817
4818 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4819 return 0;
4820}
4821
4822static void __exit ata_exit(void)
4823{
4824 destroy_workqueue(ata_wq);
4825}
4826
4827module_init(ata_init);
4828module_exit(ata_exit);
4829
67846b30
JG		 4830static unsigned long ratelimit_time;
4831static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4832
4833int ata_ratelimit(void)
4834{
4835 int rc;
4836 unsigned long flags;
4837
4838 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4839
4840 if (time_after(jiffies, ratelimit_time)) {
4841 rc = 1;
4842 ratelimit_time = jiffies + (HZ/5);
4843 } else
4844 rc = 0;
4845
4846 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4847
4848 return rc;
4849}
4850
1da177e4
LT		 4851/*
4852 * libata is essentially a library of internal helper functions for
4853 * low-level ATA host controller drivers. As such, the API/ABI is
4854 * likely to change as new drivers are added and updated.
4855 * Do not depend on ABI/API stability.
4856 */
4857
4858EXPORT_SYMBOL_GPL(ata_std_bios_param);
4859EXPORT_SYMBOL_GPL(ata_std_ports);
4860EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4861EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4862EXPORT_SYMBOL_GPL(ata_sg_init);
4863EXPORT_SYMBOL_GPL(ata_sg_init_one);
76014427 4864EXPORT_SYMBOL_GPL(__ata_qc_complete);
1da177e4
LT		 4865EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4866EXPORT_SYMBOL_GPL(ata_eng_timeout);
4867EXPORT_SYMBOL_GPL(ata_tf_load);
4868EXPORT_SYMBOL_GPL(ata_tf_read);
4869EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4870EXPORT_SYMBOL_GPL(ata_std_dev_select);
4871EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4872EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4873EXPORT_SYMBOL_GPL(ata_check_status);
4874EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4875EXPORT_SYMBOL_GPL(ata_exec_command);
4876EXPORT_SYMBOL_GPL(ata_port_start);
4877EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4878EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4879EXPORT_SYMBOL_GPL(ata_interrupt);
4880EXPORT_SYMBOL_GPL(ata_qc_prep);
4881EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4882EXPORT_SYMBOL_GPL(ata_bmdma_start);
4883EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4884EXPORT_SYMBOL_GPL(ata_bmdma_status);
4885EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4886EXPORT_SYMBOL_GPL(ata_port_probe);
4887EXPORT_SYMBOL_GPL(sata_phy_reset);
4888EXPORT_SYMBOL_GPL(__sata_phy_reset);
4889EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 4890EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 4891EXPORT_SYMBOL_GPL(ata_std_softreset);
4892EXPORT_SYMBOL_GPL(sata_std_hardreset);
4893EXPORT_SYMBOL_GPL(ata_std_postreset);
4894EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 4895EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
1da177e4 4896EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4897EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 4898EXPORT_SYMBOL_GPL(ata_busy_sleep);
1da177e4
LT		 4899EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4900EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
f29841e0 4901EXPORT_SYMBOL_GPL(ata_scsi_timed_out);
1da177e4
LT		 4902EXPORT_SYMBOL_GPL(ata_scsi_error);
4903EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4904EXPORT_SYMBOL_GPL(ata_scsi_release);
4905EXPORT_SYMBOL_GPL(ata_host_intr);
4906EXPORT_SYMBOL_GPL(ata_dev_classify);
4907EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4908EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4 4909EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH		 4910EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
4911EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 4912
1bc4ccff 4913EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 4914EXPORT_SYMBOL_GPL(ata_timing_compute);
4915EXPORT_SYMBOL_GPL(ata_timing_merge);
4916
1da177e4
LT		 4917#ifdef CONFIG_PCI
4918EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 4919EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 4920EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
4921EXPORT_SYMBOL_GPL(ata_pci_init_one);
4922EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 4923EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
4924EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 4925#endif /* CONFIG_PCI */
9b847548
JA		 4926
4927EXPORT_SYMBOL_GPL(ata_device_suspend);
4928EXPORT_SYMBOL_GPL(ata_device_resume);
4929EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
4930EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
Linux kernel - Deliverables
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