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[PATCH] libata: implement ata_exec_internal()
[deliverable/linux.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
64static unsigned int ata_busy_sleep (struct ata_port *ap,
65 unsigned long tmout_pat,
66 unsigned long tmout);
59a10b17 67static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 68static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 69static void ata_set_mode(struct ata_port *ap);
70static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 71static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 72static int fgb(u32 bitmap);
057ace5e 73static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 74 u8 *xfer_mode_out,
75 unsigned int *xfer_shift_out);
1da177e4
LT		 76static void __ata_qc_complete(struct ata_queued_cmd *qc);
77
78static unsigned int ata_unique_id = 1;
79static struct workqueue_struct *ata_wq;
80
1623c81e
JG		 81int atapi_enabled = 0;
82module_param(atapi_enabled, int, 0444);
83MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
84
1da177e4
LT		 85MODULE_AUTHOR("Jeff Garzik");
86MODULE_DESCRIPTION("Library module for ATA devices");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90/**
6f0ef4fa 91 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT		 92 * @ap: Port to which output is sent
93 * @tf: ATA taskfile register set
94 *
95 * Outputs ATA taskfile to standard ATA host controller.
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 102{
103 struct ata_ioports *ioaddr = &ap->ioaddr;
104 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
105
106 if (tf->ctl != ap->last_ctl) {
107 outb(tf->ctl, ioaddr->ctl_addr);
108 ap->last_ctl = tf->ctl;
109 ata_wait_idle(ap);
110 }
111
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 outb(tf->hob_feature, ioaddr->feature_addr);
114 outb(tf->hob_nsect, ioaddr->nsect_addr);
115 outb(tf->hob_lbal, ioaddr->lbal_addr);
116 outb(tf->hob_lbam, ioaddr->lbam_addr);
117 outb(tf->hob_lbah, ioaddr->lbah_addr);
118 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
119 tf->hob_feature,
120 tf->hob_nsect,
121 tf->hob_lbal,
122 tf->hob_lbam,
123 tf->hob_lbah);
124 }
125
126 if (is_addr) {
127 outb(tf->feature, ioaddr->feature_addr);
128 outb(tf->nsect, ioaddr->nsect_addr);
129 outb(tf->lbal, ioaddr->lbal_addr);
130 outb(tf->lbam, ioaddr->lbam_addr);
131 outb(tf->lbah, ioaddr->lbah_addr);
132 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
133 tf->feature,
134 tf->nsect,
135 tf->lbal,
136 tf->lbam,
137 tf->lbah);
138 }
139
140 if (tf->flags & ATA_TFLAG_DEVICE) {
141 outb(tf->device, ioaddr->device_addr);
142 VPRINTK("device 0x%X\n", tf->device);
143 }
144
145 ata_wait_idle(ap);
146}
147
148/**
149 * ata_tf_load_mmio - send taskfile registers to host controller
150 * @ap: Port to which output is sent
151 * @tf: ATA taskfile register set
152 *
153 * Outputs ATA taskfile to standard ATA host controller using MMIO.
154 *
155 * LOCKING:
156 * Inherited from caller.
157 */
158
057ace5e 159static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 160{
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
163
164 if (tf->ctl != ap->last_ctl) {
165 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
166 ap->last_ctl = tf->ctl;
167 ata_wait_idle(ap);
168 }
169
170 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
171 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
172 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
173 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
174 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
175 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
176 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
177 tf->hob_feature,
178 tf->hob_nsect,
179 tf->hob_lbal,
180 tf->hob_lbam,
181 tf->hob_lbah);
182 }
183
184 if (is_addr) {
185 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
186 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
187 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
188 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
189 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
190 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
191 tf->feature,
192 tf->nsect,
193 tf->lbal,
194 tf->lbam,
195 tf->lbah);
196 }
197
198 if (tf->flags & ATA_TFLAG_DEVICE) {
199 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
200 VPRINTK("device 0x%X\n", tf->device);
201 }
202
203 ata_wait_idle(ap);
204}
205
0baab86b
EF		 206
207/**
208 * ata_tf_load - send taskfile registers to host controller
209 * @ap: Port to which output is sent
210 * @tf: ATA taskfile register set
211 *
212 * Outputs ATA taskfile to standard ATA host controller using MMIO
213 * or PIO as indicated by the ATA_FLAG_MMIO flag.
214 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
215 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
216 * hob_lbal, hob_lbam, and hob_lbah.
217 *
218 * This function waits for idle (!BUSY and !DRQ) after writing
219 * registers. If the control register has a new value, this
220 * function also waits for idle after writing control and before
221 * writing the remaining registers.
222 *
223 * May be used as the tf_load() entry in ata_port_operations.
224 *
225 * LOCKING:
226 * Inherited from caller.
227 */
057ace5e 228void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 229{
230 if (ap->flags & ATA_FLAG_MMIO)
231 ata_tf_load_mmio(ap, tf);
232 else
233 ata_tf_load_pio(ap, tf);
234}
235
236/**
0baab86b 237 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT		 238 * @ap: port to which command is being issued
239 * @tf: ATA taskfile register set
240 *
0baab86b 241 * Issues PIO write to ATA command register, with proper
1da177e4
LT		 242 * synchronization with interrupt handler / other threads.
243 *
244 * LOCKING:
245 * spin_lock_irqsave(host_set lock)
246 */
247
057ace5e 248static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 249{
250 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
251
252 outb(tf->command, ap->ioaddr.command_addr);
253 ata_pause(ap);
254}
255
256
257/**
258 * ata_exec_command_mmio - issue ATA command to host controller
259 * @ap: port to which command is being issued
260 * @tf: ATA taskfile register set
261 *
262 * Issues MMIO write to ATA command register, with proper
263 * synchronization with interrupt handler / other threads.
264 *
265 * LOCKING:
266 * spin_lock_irqsave(host_set lock)
267 */
268
057ace5e 269static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 270{
271 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
272
273 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
274 ata_pause(ap);
275}
276
0baab86b
EF		 277
278/**
279 * ata_exec_command - issue ATA command to host controller
280 * @ap: port to which command is being issued
281 * @tf: ATA taskfile register set
282 *
283 * Issues PIO/MMIO write to ATA command register, with proper
284 * synchronization with interrupt handler / other threads.
285 *
286 * LOCKING:
287 * spin_lock_irqsave(host_set lock)
288 */
057ace5e 289void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 290{
291 if (ap->flags & ATA_FLAG_MMIO)
292 ata_exec_command_mmio(ap, tf);
293 else
294 ata_exec_command_pio(ap, tf);
295}
296
1da177e4
LT		 297/**
298 * ata_tf_to_host - issue ATA taskfile to host controller
299 * @ap: port to which command is being issued
300 * @tf: ATA taskfile register set
301 *
302 * Issues ATA taskfile register set to ATA host controller,
303 * with proper synchronization with interrupt handler and
304 * other threads.
305 *
306 * LOCKING:
1da177e4
LT		 307 * spin_lock_irqsave(host_set lock)
308 */
309
e5338254
JG		 310static inline void ata_tf_to_host(struct ata_port *ap,
311 const struct ata_taskfile *tf)
1da177e4
LT		 312{
313 ap->ops->tf_load(ap, tf);
314 ap->ops->exec_command(ap, tf);
315}
316
317/**
0baab86b 318 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT		 319 * @ap: Port from which input is read
320 * @tf: ATA taskfile register set for storing input
321 *
322 * Reads ATA taskfile registers for currently-selected device
323 * into @tf.
324 *
325 * LOCKING:
326 * Inherited from caller.
327 */
328
329static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
330{
331 struct ata_ioports *ioaddr = &ap->ioaddr;
332
ac19bff2 333 tf->command = ata_check_status(ap);
0169e284 334 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT		 335 tf->nsect = inb(ioaddr->nsect_addr);
336 tf->lbal = inb(ioaddr->lbal_addr);
337 tf->lbam = inb(ioaddr->lbam_addr);
338 tf->lbah = inb(ioaddr->lbah_addr);
339 tf->device = inb(ioaddr->device_addr);
340
341 if (tf->flags & ATA_TFLAG_LBA48) {
342 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
343 tf->hob_feature = inb(ioaddr->error_addr);
344 tf->hob_nsect = inb(ioaddr->nsect_addr);
345 tf->hob_lbal = inb(ioaddr->lbal_addr);
346 tf->hob_lbam = inb(ioaddr->lbam_addr);
347 tf->hob_lbah = inb(ioaddr->lbah_addr);
348 }
349}
350
351/**
352 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
353 * @ap: Port from which input is read
354 * @tf: ATA taskfile register set for storing input
355 *
356 * Reads ATA taskfile registers for currently-selected device
357 * into @tf via MMIO.
358 *
359 * LOCKING:
360 * Inherited from caller.
361 */
362
363static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
364{
365 struct ata_ioports *ioaddr = &ap->ioaddr;
366
ac19bff2 367 tf->command = ata_check_status(ap);
0169e284 368 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT		 369 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
370 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
371 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
372 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
373 tf->device = readb((void __iomem *)ioaddr->device_addr);
374
375 if (tf->flags & ATA_TFLAG_LBA48) {
376 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
377 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
378 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
379 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
380 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
381 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
382 }
383}
384
0baab86b
EF		 385
386/**
387 * ata_tf_read - input device's ATA taskfile shadow registers
388 * @ap: Port from which input is read
389 * @tf: ATA taskfile register set for storing input
390 *
391 * Reads ATA taskfile registers for currently-selected device
392 * into @tf.
393 *
394 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
395 * is set, also reads the hob registers.
396 *
397 * May be used as the tf_read() entry in ata_port_operations.
398 *
399 * LOCKING:
400 * Inherited from caller.
401 */
1da177e4
LT		 402void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
403{
404 if (ap->flags & ATA_FLAG_MMIO)
405 ata_tf_read_mmio(ap, tf);
406 else
407 ata_tf_read_pio(ap, tf);
408}
409
410/**
411 * ata_check_status_pio - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Reads ATA taskfile status register for currently-selected device
0baab86b 415 * and return its value. This also clears pending interrupts
1da177e4
LT		 416 * from this device
417 *
418 * LOCKING:
419 * Inherited from caller.
420 */
421static u8 ata_check_status_pio(struct ata_port *ap)
422{
423 return inb(ap->ioaddr.status_addr);
424}
425
426/**
427 * ata_check_status_mmio - Read device status reg & clear interrupt
428 * @ap: port where the device is
429 *
430 * Reads ATA taskfile status register for currently-selected device
0baab86b 431 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT		 432 * from this device
433 *
434 * LOCKING:
435 * Inherited from caller.
436 */
437static u8 ata_check_status_mmio(struct ata_port *ap)
438{
439 return readb((void __iomem *) ap->ioaddr.status_addr);
440}
441
0baab86b
EF		 442
443/**
444 * ata_check_status - Read device status reg & clear interrupt
445 * @ap: port where the device is
446 *
447 * Reads ATA taskfile status register for currently-selected device
448 * and return its value. This also clears pending interrupts
449 * from this device
450 *
451 * May be used as the check_status() entry in ata_port_operations.
452 *
453 * LOCKING:
454 * Inherited from caller.
455 */
1da177e4
LT		 456u8 ata_check_status(struct ata_port *ap)
457{
458 if (ap->flags & ATA_FLAG_MMIO)
459 return ata_check_status_mmio(ap);
460 return ata_check_status_pio(ap);
461}
462
0baab86b
EF		 463
464/**
465 * ata_altstatus - Read device alternate status reg
466 * @ap: port where the device is
467 *
468 * Reads ATA taskfile alternate status register for
469 * currently-selected device and return its value.
470 *
471 * Note: may NOT be used as the check_altstatus() entry in
472 * ata_port_operations.
473 *
474 * LOCKING:
475 * Inherited from caller.
476 */
1da177e4
LT		 477u8 ata_altstatus(struct ata_port *ap)
478{
479 if (ap->ops->check_altstatus)
480 return ap->ops->check_altstatus(ap);
481
482 if (ap->flags & ATA_FLAG_MMIO)
483 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
484 return inb(ap->ioaddr.altstatus_addr);
485}
486
0baab86b 487
1da177e4
LT		 488/**
489 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
490 * @tf: Taskfile to convert
491 * @fis: Buffer into which data will output
492 * @pmp: Port multiplier port
493 *
494 * Converts a standard ATA taskfile to a Serial ATA
495 * FIS structure (Register - Host to Device).
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
500
057ace5e 501void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 502{
503 fis[0] = 0x27; /* Register - Host to Device FIS */
504 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
505 bit 7 indicates Command FIS */
506 fis[2] = tf->command;
507 fis[3] = tf->feature;
508
509 fis[4] = tf->lbal;
510 fis[5] = tf->lbam;
511 fis[6] = tf->lbah;
512 fis[7] = tf->device;
513
514 fis[8] = tf->hob_lbal;
515 fis[9] = tf->hob_lbam;
516 fis[10] = tf->hob_lbah;
517 fis[11] = tf->hob_feature;
518
519 fis[12] = tf->nsect;
520 fis[13] = tf->hob_nsect;
521 fis[14] = 0;
522 fis[15] = tf->ctl;
523
524 fis[16] = 0;
525 fis[17] = 0;
526 fis[18] = 0;
527 fis[19] = 0;
528}
529
530/**
531 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
532 * @fis: Buffer from which data will be input
533 * @tf: Taskfile to output
534 *
e12a1be6 535 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 536 *
537 * LOCKING:
538 * Inherited from caller.
539 */
540
057ace5e 541void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 542{
543 tf->command = fis[2]; /* status */
544 tf->feature = fis[3]; /* error */
545
546 tf->lbal = fis[4];
547 tf->lbam = fis[5];
548 tf->lbah = fis[6];
549 tf->device = fis[7];
550
551 tf->hob_lbal = fis[8];
552 tf->hob_lbam = fis[9];
553 tf->hob_lbah = fis[10];
554
555 tf->nsect = fis[12];
556 tf->hob_nsect = fis[13];
557}
558
8cbd6df1
AL		 559static const u8 ata_rw_cmds[] = {
560 /* pio multi */
561 ATA_CMD_READ_MULTI,
562 ATA_CMD_WRITE_MULTI,
563 ATA_CMD_READ_MULTI_EXT,
564 ATA_CMD_WRITE_MULTI_EXT,
565 /* pio */
566 ATA_CMD_PIO_READ,
567 ATA_CMD_PIO_WRITE,
568 ATA_CMD_PIO_READ_EXT,
569 ATA_CMD_PIO_WRITE_EXT,
570 /* dma */
571 ATA_CMD_READ,
572 ATA_CMD_WRITE,
573 ATA_CMD_READ_EXT,
574 ATA_CMD_WRITE_EXT
575};
1da177e4
LT		 576
577/**
8cbd6df1
AL		 578 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
579 * @qc: command to examine and configure
1da177e4 580 *
8cbd6df1
AL		 581 * Examine the device configuration and tf->flags to calculate
582 * the proper read/write commands and protocol to use.
1da177e4
LT		 583 *
584 * LOCKING:
585 * caller.
586 */
8cbd6df1 587void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 588{
8cbd6df1
AL		 589 struct ata_taskfile *tf = &qc->tf;
590 struct ata_device *dev = qc->dev;
1da177e4 591
8cbd6df1
AL		 592 int index, lba48, write;
593
594 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
595 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 596
8cbd6df1
AL		 597 if (dev->flags & ATA_DFLAG_PIO) {
598 tf->protocol = ATA_PROT_PIO;
599 index = dev->multi_count ? 0 : 4;
600 } else {
601 tf->protocol = ATA_PROT_DMA;
602 index = 8;
603 }
1da177e4 604
8cbd6df1 605 tf->command = ata_rw_cmds[index + lba48 + write];
1da177e4
LT		 606}
607
98ac62de 608static const char * const xfer_mode_str[] = {
1da177e4
LT		 609 "UDMA/16",
610 "UDMA/25",
611 "UDMA/33",
612 "UDMA/44",
613 "UDMA/66",
614 "UDMA/100",
615 "UDMA/133",
616 "UDMA7",
617 "MWDMA0",
618 "MWDMA1",
619 "MWDMA2",
620 "PIO0",
621 "PIO1",
622 "PIO2",
623 "PIO3",
624 "PIO4",
625};
626
627/**
628 * ata_udma_string - convert UDMA bit offset to string
629 * @mask: mask of bits supported; only highest bit counts.
630 *
631 * Determine string which represents the highest speed
632 * (highest bit in @udma_mask).
633 *
634 * LOCKING:
635 * None.
636 *
637 * RETURNS:
638 * Constant C string representing highest speed listed in
639 * @udma_mask, or the constant C string "<n/a>".
640 */
641
642static const char *ata_mode_string(unsigned int mask)
643{
644 int i;
645
646 for (i = 7; i >= 0; i--)
647 if (mask & (1 << i))
648 goto out;
649 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
650 if (mask & (1 << i))
651 goto out;
652 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
653 if (mask & (1 << i))
654 goto out;
655
656 return "<n/a>";
657
658out:
659 return xfer_mode_str[i];
660}
661
662/**
663 * ata_pio_devchk - PATA device presence detection
664 * @ap: ATA channel to examine
665 * @device: Device to examine (starting at zero)
666 *
667 * This technique was originally described in
668 * Hale Landis's ATADRVR (www.ata-atapi.com), and
669 * later found its way into the ATA/ATAPI spec.
670 *
671 * Write a pattern to the ATA shadow registers,
672 * and if a device is present, it will respond by
673 * correctly storing and echoing back the
674 * ATA shadow register contents.
675 *
676 * LOCKING:
677 * caller.
678 */
679
680static unsigned int ata_pio_devchk(struct ata_port *ap,
681 unsigned int device)
682{
683 struct ata_ioports *ioaddr = &ap->ioaddr;
684 u8 nsect, lbal;
685
686 ap->ops->dev_select(ap, device);
687
688 outb(0x55, ioaddr->nsect_addr);
689 outb(0xaa, ioaddr->lbal_addr);
690
691 outb(0xaa, ioaddr->nsect_addr);
692 outb(0x55, ioaddr->lbal_addr);
693
694 outb(0x55, ioaddr->nsect_addr);
695 outb(0xaa, ioaddr->lbal_addr);
696
697 nsect = inb(ioaddr->nsect_addr);
698 lbal = inb(ioaddr->lbal_addr);
699
700 if ((nsect == 0x55) && (lbal == 0xaa))
701 return 1; /* we found a device */
702
703 return 0; /* nothing found */
704}
705
706/**
707 * ata_mmio_devchk - PATA device presence detection
708 * @ap: ATA channel to examine
709 * @device: Device to examine (starting at zero)
710 *
711 * This technique was originally described in
712 * Hale Landis's ATADRVR (www.ata-atapi.com), and
713 * later found its way into the ATA/ATAPI spec.
714 *
715 * Write a pattern to the ATA shadow registers,
716 * and if a device is present, it will respond by
717 * correctly storing and echoing back the
718 * ATA shadow register contents.
719 *
720 * LOCKING:
721 * caller.
722 */
723
724static unsigned int ata_mmio_devchk(struct ata_port *ap,
725 unsigned int device)
726{
727 struct ata_ioports *ioaddr = &ap->ioaddr;
728 u8 nsect, lbal;
729
730 ap->ops->dev_select(ap, device);
731
732 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
733 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
734
735 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
736 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
737
738 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
739 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
740
741 nsect = readb((void __iomem *) ioaddr->nsect_addr);
742 lbal = readb((void __iomem *) ioaddr->lbal_addr);
743
744 if ((nsect == 0x55) && (lbal == 0xaa))
745 return 1; /* we found a device */
746
747 return 0; /* nothing found */
748}
749
750/**
751 * ata_devchk - PATA device presence detection
752 * @ap: ATA channel to examine
753 * @device: Device to examine (starting at zero)
754 *
755 * Dispatch ATA device presence detection, depending
756 * on whether we are using PIO or MMIO to talk to the
757 * ATA shadow registers.
758 *
759 * LOCKING:
760 * caller.
761 */
762
763static unsigned int ata_devchk(struct ata_port *ap,
764 unsigned int device)
765{
766 if (ap->flags & ATA_FLAG_MMIO)
767 return ata_mmio_devchk(ap, device);
768 return ata_pio_devchk(ap, device);
769}
770
771/**
772 * ata_dev_classify - determine device type based on ATA-spec signature
773 * @tf: ATA taskfile register set for device to be identified
774 *
775 * Determine from taskfile register contents whether a device is
776 * ATA or ATAPI, as per "Signature and persistence" section
777 * of ATA/PI spec (volume 1, sect 5.14).
778 *
779 * LOCKING:
780 * None.
781 *
782 * RETURNS:
783 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
784 * the event of failure.
785 */
786
057ace5e 787unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 788{
789 /* Apple's open source Darwin code hints that some devices only
790 * put a proper signature into the LBA mid/high registers,
791 * So, we only check those. It's sufficient for uniqueness.
792 */
793
794 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
795 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
796 DPRINTK("found ATA device by sig\n");
797 return ATA_DEV_ATA;
798 }
799
800 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
801 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
802 DPRINTK("found ATAPI device by sig\n");
803 return ATA_DEV_ATAPI;
804 }
805
806 DPRINTK("unknown device\n");
807 return ATA_DEV_UNKNOWN;
808}
809
810/**
811 * ata_dev_try_classify - Parse returned ATA device signature
812 * @ap: ATA channel to examine
813 * @device: Device to examine (starting at zero)
814 *
815 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
816 * an ATA/ATAPI-defined set of values is placed in the ATA
817 * shadow registers, indicating the results of device detection
818 * and diagnostics.
819 *
820 * Select the ATA device, and read the values from the ATA shadow
821 * registers. Then parse according to the Error register value,
822 * and the spec-defined values examined by ata_dev_classify().
823 *
824 * LOCKING:
825 * caller.
826 */
827
828static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device)
829{
830 struct ata_device *dev = &ap->device[device];
831 struct ata_taskfile tf;
832 unsigned int class;
833 u8 err;
834
835 ap->ops->dev_select(ap, device);
836
837 memset(&tf, 0, sizeof(tf));
838
1da177e4 839 ap->ops->tf_read(ap, &tf);
0169e284 840 err = tf.feature;
1da177e4
LT		 841
842 dev->class = ATA_DEV_NONE;
843
844 /* see if device passed diags */
845 if (err == 1)
846 /* do nothing */ ;
847 else if ((device == 0) && (err == 0x81))
848 /* do nothing */ ;
849 else
850 return err;
851
852 /* determine if device if ATA or ATAPI */
853 class = ata_dev_classify(&tf);
854 if (class == ATA_DEV_UNKNOWN)
855 return err;
856 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
857 return err;
858
859 dev->class = class;
860
861 return err;
862}
863
864/**
865 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
866 * @id: IDENTIFY DEVICE results we will examine
867 * @s: string into which data is output
868 * @ofs: offset into identify device page
869 * @len: length of string to return. must be an even number.
870 *
871 * The strings in the IDENTIFY DEVICE page are broken up into
872 * 16-bit chunks. Run through the string, and output each
873 * 8-bit chunk linearly, regardless of platform.
874 *
875 * LOCKING:
876 * caller.
877 */
878
057ace5e 879void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 880 unsigned int ofs, unsigned int len)
881{
882 unsigned int c;
883
884 while (len > 0) {
885 c = id[ofs] >> 8;
886 *s = c;
887 s++;
888
889 c = id[ofs] & 0xff;
890 *s = c;
891 s++;
892
893 ofs++;
894 len -= 2;
895 }
896}
897
0baab86b
EF		 898
899/**
900 * ata_noop_dev_select - Select device 0/1 on ATA bus
901 * @ap: ATA channel to manipulate
902 * @device: ATA device (numbered from zero) to select
903 *
904 * This function performs no actual function.
905 *
906 * May be used as the dev_select() entry in ata_port_operations.
907 *
908 * LOCKING:
909 * caller.
910 */
1da177e4
LT		 911void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
912{
913}
914
0baab86b 915
1da177e4
LT		 916/**
917 * ata_std_dev_select - Select device 0/1 on ATA bus
918 * @ap: ATA channel to manipulate
919 * @device: ATA device (numbered from zero) to select
920 *
921 * Use the method defined in the ATA specification to
922 * make either device 0, or device 1, active on the
0baab86b
EF		 923 * ATA channel. Works with both PIO and MMIO.
924 *
925 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 926 *
927 * LOCKING:
928 * caller.
929 */
930
931void ata_std_dev_select (struct ata_port *ap, unsigned int device)
932{
933 u8 tmp;
934
935 if (device == 0)
936 tmp = ATA_DEVICE_OBS;
937 else
938 tmp = ATA_DEVICE_OBS | ATA_DEV1;
939
940 if (ap->flags & ATA_FLAG_MMIO) {
941 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
942 } else {
943 outb(tmp, ap->ioaddr.device_addr);
944 }
945 ata_pause(ap); /* needed; also flushes, for mmio */
946}
947
948/**
949 * ata_dev_select - Select device 0/1 on ATA bus
950 * @ap: ATA channel to manipulate
951 * @device: ATA device (numbered from zero) to select
952 * @wait: non-zero to wait for Status register BSY bit to clear
953 * @can_sleep: non-zero if context allows sleeping
954 *
955 * Use the method defined in the ATA specification to
956 * make either device 0, or device 1, active on the
957 * ATA channel.
958 *
959 * This is a high-level version of ata_std_dev_select(),
960 * which additionally provides the services of inserting
961 * the proper pauses and status polling, where needed.
962 *
963 * LOCKING:
964 * caller.
965 */
966
967void ata_dev_select(struct ata_port *ap, unsigned int device,
968 unsigned int wait, unsigned int can_sleep)
969{
970 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
971 ap->id, device, wait);
972
973 if (wait)
974 ata_wait_idle(ap);
975
976 ap->ops->dev_select(ap, device);
977
978 if (wait) {
979 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
980 msleep(150);
981 ata_wait_idle(ap);
982 }
983}
984
985/**
986 * ata_dump_id - IDENTIFY DEVICE info debugging output
987 * @dev: Device whose IDENTIFY DEVICE page we will dump
988 *
989 * Dump selected 16-bit words from a detected device's
990 * IDENTIFY PAGE page.
991 *
992 * LOCKING:
993 * caller.
994 */
995
057ace5e 996static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 997{
998 DPRINTK("49==0x%04x "
999 "53==0x%04x "
1000 "63==0x%04x "
1001 "64==0x%04x "
1002 "75==0x%04x \n",
1003 dev->id[49],
1004 dev->id[53],
1005 dev->id[63],
1006 dev->id[64],
1007 dev->id[75]);
1008 DPRINTK("80==0x%04x "
1009 "81==0x%04x "
1010 "82==0x%04x "
1011 "83==0x%04x "
1012 "84==0x%04x \n",
1013 dev->id[80],
1014 dev->id[81],
1015 dev->id[82],
1016 dev->id[83],
1017 dev->id[84]);
1018 DPRINTK("88==0x%04x "
1019 "93==0x%04x\n",
1020 dev->id[88],
1021 dev->id[93]);
1022}
1023
11e29e21
AC		 1024/*
1025 * Compute the PIO modes available for this device. This is not as
1026 * trivial as it seems if we must consider early devices correctly.
1027 *
1028 * FIXME: pre IDE drive timing (do we care ?).
1029 */
1030
057ace5e 1031static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 1032{
1033 u16 modes;
1034
1035 /* Usual case. Word 53 indicates word 88 is valid */
1036 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) {
1037 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1038 modes <<= 3;
1039 modes |= 0x7;
1040 return modes;
1041 }
1042
1043 /* If word 88 isn't valid then Word 51 holds the PIO timing number
1044 for the maximum. Turn it into a mask and return it */
1045 modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
1046 return modes;
1047}
1048
a2a7a662
TH		 1049struct ata_exec_internal_arg {
1050 unsigned int err_mask;
1051 struct ata_taskfile *tf;
1052 struct completion *waiting;
1053};
1054
1055int ata_qc_complete_internal(struct ata_queued_cmd *qc)
1056{
1057 struct ata_exec_internal_arg *arg = qc->private_data;
1058 struct completion *waiting = arg->waiting;
1059
1060 if (!(qc->err_mask & ~AC_ERR_DEV))
1061 qc->ap->ops->tf_read(qc->ap, arg->tf);
1062 arg->err_mask = qc->err_mask;
1063 arg->waiting = NULL;
1064 complete(waiting);
1065
1066 return 0;
1067}
1068
1069/**
1070 * ata_exec_internal - execute libata internal command
1071 * @ap: Port to which the command is sent
1072 * @dev: Device to which the command is sent
1073 * @tf: Taskfile registers for the command and the result
1074 * @dma_dir: Data tranfer direction of the command
1075 * @buf: Data buffer of the command
1076 * @buflen: Length of data buffer
1077 *
1078 * Executes libata internal command with timeout. @tf contains
1079 * command on entry and result on return. Timeout and error
1080 * conditions are reported via return value. No recovery action
1081 * is taken after a command times out. It's caller's duty to
1082 * clean up after timeout.
1083 *
1084 * LOCKING:
1085 * None. Should be called with kernel context, might sleep.
1086 */
1087
1088static unsigned
1089ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
1090 struct ata_taskfile *tf,
1091 int dma_dir, void *buf, unsigned int buflen)
1092{
1093 u8 command = tf->command;
1094 struct ata_queued_cmd *qc;
1095 DECLARE_COMPLETION(wait);
1096 unsigned long flags;
1097 struct ata_exec_internal_arg arg;
1098
1099 spin_lock_irqsave(&ap->host_set->lock, flags);
1100
1101 qc = ata_qc_new_init(ap, dev);
1102 BUG_ON(qc == NULL);
1103
1104 qc->tf = *tf;
1105 qc->dma_dir = dma_dir;
1106 if (dma_dir != DMA_NONE) {
1107 ata_sg_init_one(qc, buf, buflen);
1108 qc->nsect = buflen / ATA_SECT_SIZE;
1109 }
1110
1111 arg.waiting = &wait;
1112 arg.tf = tf;
1113 qc->private_data = &arg;
1114 qc->complete_fn = ata_qc_complete_internal;
1115
1116 if (ata_qc_issue(qc))
1117 goto issue_fail;
1118
1119 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1120
1121 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
1122 spin_lock_irqsave(&ap->host_set->lock, flags);
1123
1124 /* We're racing with irq here. If we lose, the
1125 * following test prevents us from completing the qc
1126 * again. If completion irq occurs after here but
1127 * before the caller cleans up, it will result in a
1128 * spurious interrupt. We can live with that.
1129 */
1130 if (arg.waiting) {
1131 qc->err_mask = AC_ERR_OTHER;
1132 ata_qc_complete(qc);
1133 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
1134 ap->id, command);
1135 }
1136
1137 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1138 }
1139
1140 return arg.err_mask;
1141
1142 issue_fail:
1143 ata_qc_free(qc);
1144 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1145 return AC_ERR_OTHER;
1146}
1147
64f043d8
JG		 1148static int ata_qc_wait_err(struct ata_queued_cmd *qc,
1149 struct completion *wait)
1150{
1151 int rc = 0;
1152
1153 if (wait_for_completion_timeout(wait, 30 * HZ) < 1) {
1154 /* timeout handling */
a22e2eb0 1155 qc->err_mask |= ac_err_mask(ata_chk_status(qc->ap));
64f043d8 1156
a22e2eb0 1157 if (!qc->err_mask) {
64f043d8
JG		 1158 printk(KERN_WARNING "ata%u: slow completion (cmd %x)\n",
1159 qc->ap->id, qc->tf.command);
1160 } else {
1161 printk(KERN_WARNING "ata%u: qc timeout (cmd %x)\n",
1162 qc->ap->id, qc->tf.command);
1163 rc = -EIO;
1164 }
1165
a22e2eb0 1166 ata_qc_complete(qc);
64f043d8
JG		 1167 }
1168
1169 return rc;
1170}
1171
1da177e4
LT		 1172/**
1173 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1174 * @ap: port on which device we wish to probe resides
1175 * @device: device bus address, starting at zero
1176 *
1177 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1178 * command, and read back the 512-byte device information page.
1179 * The device information page is fed to us via the standard
1180 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1181 * using standard PIO-IN paths)
1182 *
1183 * After reading the device information page, we use several
1184 * bits of information from it to initialize data structures
1185 * that will be used during the lifetime of the ata_device.
1186 * Other data from the info page is used to disqualify certain
1187 * older ATA devices we do not wish to support.
1188 *
1189 * LOCKING:
1190 * Inherited from caller. Some functions called by this function
1191 * obtain the host_set lock.
1192 */
1193
1194static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1195{
1196 struct ata_device *dev = &ap->device[device];
8bf62ece 1197 unsigned int major_version;
1da177e4
LT		 1198 u16 tmp;
1199 unsigned long xfer_modes;
1da177e4
LT		 1200 unsigned int using_edd;
1201 DECLARE_COMPLETION(wait);
1202 struct ata_queued_cmd *qc;
1203 unsigned long flags;
1204 int rc;
1205
1206 if (!ata_dev_present(dev)) {
1207 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1208 ap->id, device);
1209 return;
1210 }
1211
1212 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1213 using_edd = 0;
1214 else
1215 using_edd = 1;
1216
1217 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1218
1219 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1220 dev->class == ATA_DEV_NONE);
1221
1222 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1223
1224 qc = ata_qc_new_init(ap, dev);
1225 BUG_ON(qc == NULL);
1226
1227 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
1228 qc->dma_dir = DMA_FROM_DEVICE;
1229 qc->tf.protocol = ATA_PROT_PIO;
1230 qc->nsect = 1;
1231
1232retry:
1233 if (dev->class == ATA_DEV_ATA) {
1234 qc->tf.command = ATA_CMD_ID_ATA;
1235 DPRINTK("do ATA identify\n");
1236 } else {
1237 qc->tf.command = ATA_CMD_ID_ATAPI;
1238 DPRINTK("do ATAPI identify\n");
1239 }
1240
1241 qc->waiting = &wait;
1242 qc->complete_fn = ata_qc_complete_noop;
1243
1244 spin_lock_irqsave(&ap->host_set->lock, flags);
1245 rc = ata_qc_issue(qc);
1246 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1247
1248 if (rc)
1249 goto err_out;
1250 else
64f043d8 1251 ata_qc_wait_err(qc, &wait);
1da177e4 1252
0169e284
JG		 1253 spin_lock_irqsave(&ap->host_set->lock, flags);
1254 ap->ops->tf_read(ap, &qc->tf);
1255 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1256
1257 if (qc->tf.command & ATA_ERR) {
1da177e4
LT		 1258 /*
1259 * arg! EDD works for all test cases, but seems to return
1260 * the ATA signature for some ATAPI devices. Until the
1261 * reason for this is found and fixed, we fix up the mess
1262 * here. If IDENTIFY DEVICE returns command aborted
1263 * (as ATAPI devices do), then we issue an
1264 * IDENTIFY PACKET DEVICE.
1265 *
1266 * ATA software reset (SRST, the default) does not appear
1267 * to have this problem.
1268 */
7c398335 1269 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
0169e284 1270 u8 err = qc->tf.feature;
1da177e4
LT		 1271 if (err & ATA_ABORTED) {
1272 dev->class = ATA_DEV_ATAPI;
1273 qc->cursg = 0;
1274 qc->cursg_ofs = 0;
1275 qc->cursect = 0;
1276 qc->nsect = 1;
a22e2eb0 1277 qc->err_mask = 0;
1da177e4
LT		 1278 goto retry;
1279 }
1280 }
1281 goto err_out;
1282 }
1283
1284 swap_buf_le16(dev->id, ATA_ID_WORDS);
1285
1286 /* print device capabilities */
1287 printk(KERN_DEBUG "ata%u: dev %u cfg "
1288 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1289 ap->id, device, dev->id[49],
1290 dev->id[82], dev->id[83], dev->id[84],
1291 dev->id[85], dev->id[86], dev->id[87],
1292 dev->id[88]);
1293
1294 /*
1295 * common ATA, ATAPI feature tests
1296 */
1297
8bf62ece
AL		 1298 /* we require DMA support (bits 8 of word 49) */
1299 if (!ata_id_has_dma(dev->id)) {
1300 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1301 goto err_out_nosup;
1302 }
1303
1304 /* quick-n-dirty find max transfer mode; for printk only */
1305 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1306 if (!xfer_modes)
1307 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1308 if (!xfer_modes)
1309 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 1310
1311 ata_dump_id(dev);
1312
1313 /* ATA-specific feature tests */
1314 if (dev->class == ATA_DEV_ATA) {
1315 if (!ata_id_is_ata(dev->id)) /* sanity check */
1316 goto err_out_nosup;
1317
8bf62ece 1318 /* get major version */
1da177e4 1319 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 1320 for (major_version = 14; major_version >= 1; major_version--)
1321 if (tmp & (1 << major_version))
1da177e4
LT		 1322 break;
1323
8bf62ece
AL		 1324 /*
1325 * The exact sequence expected by certain pre-ATA4 drives is:
1326 * SRST RESET
1327 * IDENTIFY
1328 * INITIALIZE DEVICE PARAMETERS
1329 * anything else..
1330 * Some drives were very specific about that exact sequence.
1331 */
59a10b17 1332 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1333 ata_dev_init_params(ap, dev);
1334
59a10b17
AL		 1335 /* current CHS translation info (id[53-58]) might be
1336 * changed. reread the identify device info.
1337 */
1338 ata_dev_reread_id(ap, dev);
1339 }
1340
8bf62ece
AL		 1341 if (ata_id_has_lba(dev->id)) {
1342 dev->flags |= ATA_DFLAG_LBA;
1343
1344 if (ata_id_has_lba48(dev->id)) {
1345 dev->flags |= ATA_DFLAG_LBA48;
1346 dev->n_sectors = ata_id_u64(dev->id, 100);
1347 } else {
1348 dev->n_sectors = ata_id_u32(dev->id, 60);
1349 }
1350
1351 /* print device info to dmesg */
1352 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1353 ap->id, device,
1354 major_version,
1355 ata_mode_string(xfer_modes),
1356 (unsigned long long)dev->n_sectors,
1357 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1358 } else {
1359 /* CHS */
1360
1361 /* Default translation */
1362 dev->cylinders = dev->id[1];
1363 dev->heads = dev->id[3];
1364 dev->sectors = dev->id[6];
1365 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1366
1367 if (ata_id_current_chs_valid(dev->id)) {
1368 /* Current CHS translation is valid. */
1369 dev->cylinders = dev->id[54];
1370 dev->heads = dev->id[55];
1371 dev->sectors = dev->id[56];
1372
1373 dev->n_sectors = ata_id_u32(dev->id, 57);
1374 }
1375
1376 /* print device info to dmesg */
1377 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1378 ap->id, device,
1379 major_version,
1380 ata_mode_string(xfer_modes),
1381 (unsigned long long)dev->n_sectors,
1382 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1383
1da177e4
LT		 1384 }
1385
1386 ap->host->max_cmd_len = 16;
1da177e4
LT		 1387 }
1388
1389 /* ATAPI-specific feature tests */
2c13b7ce 1390 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1391 if (ata_id_is_ata(dev->id)) /* sanity check */
1392 goto err_out_nosup;
1393
1394 rc = atapi_cdb_len(dev->id);
1395 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1396 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1397 goto err_out_nosup;
1398 }
1399 ap->cdb_len = (unsigned int) rc;
1400 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1401
1402 /* print device info to dmesg */
1403 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1404 ap->id, device,
1405 ata_mode_string(xfer_modes));
1406 }
1407
1408 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1409 return;
1410
1411err_out_nosup:
1412 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1413 ap->id, device);
1414err_out:
1415 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1416 DPRINTK("EXIT, err\n");
1417}
1418
6f2f3812 1419
057ace5e 1420static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1421{
1422 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1423}
1424
1425/**
1426 * ata_dev_config - Run device specific handlers and check for
1427 * SATA->PATA bridges
8a60a071 1428 * @ap: Bus
6f2f3812
BC		 1429 * @i: Device
1430 *
1431 * LOCKING:
1432 */
8a60a071 1433
6f2f3812
BC		 1434void ata_dev_config(struct ata_port *ap, unsigned int i)
1435{
1436 /* limit bridge transfers to udma5, 200 sectors */
1437 if (ata_dev_knobble(ap)) {
1438 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1439 ap->id, ap->device->devno);
1440 ap->udma_mask &= ATA_UDMA5;
1441 ap->host->max_sectors = ATA_MAX_SECTORS;
1442 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
1443 ap->device->flags |= ATA_DFLAG_LOCK_SECTORS;
1444 }
1445
1446 if (ap->ops->dev_config)
1447 ap->ops->dev_config(ap, &ap->device[i]);
1448}
1449
1da177e4
LT		 1450/**
1451 * ata_bus_probe - Reset and probe ATA bus
1452 * @ap: Bus to probe
1453 *
0cba632b
JG		 1454 * Master ATA bus probing function. Initiates a hardware-dependent
1455 * bus reset, then attempts to identify any devices found on
1456 * the bus.
1457 *
1da177e4 1458 * LOCKING:
0cba632b 1459 * PCI/etc. bus probe sem.
1da177e4
LT		 1460 *
1461 * RETURNS:
1462 * Zero on success, non-zero on error.
1463 */
1464
1465static int ata_bus_probe(struct ata_port *ap)
1466{
1467 unsigned int i, found = 0;
1468
1469 ap->ops->phy_reset(ap);
1470 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1471 goto err_out;
1472
1473 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1474 ata_dev_identify(ap, i);
1475 if (ata_dev_present(&ap->device[i])) {
1476 found = 1;
6f2f3812 1477 ata_dev_config(ap,i);
1da177e4
LT		 1478 }
1479 }
1480
1481 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1482 goto err_out_disable;
1483
1484 ata_set_mode(ap);
1485 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1486 goto err_out_disable;
1487
1488 return 0;
1489
1490err_out_disable:
1491 ap->ops->port_disable(ap);
1492err_out:
1493 return -1;
1494}
1495
1496/**
0cba632b
JG		 1497 * ata_port_probe - Mark port as enabled
1498 * @ap: Port for which we indicate enablement
1da177e4 1499 *
0cba632b
JG		 1500 * Modify @ap data structure such that the system
1501 * thinks that the entire port is enabled.
1502 *
1503 * LOCKING: host_set lock, or some other form of
1504 * serialization.
1da177e4
LT		 1505 */
1506
1507void ata_port_probe(struct ata_port *ap)
1508{
1509 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1510}
1511
1512/**
780a87f7
JG		 1513 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1514 * @ap: SATA port associated with target SATA PHY.
1da177e4 1515 *
780a87f7
JG		 1516 * This function issues commands to standard SATA Sxxx
1517 * PHY registers, to wake up the phy (and device), and
1518 * clear any reset condition.
1da177e4
LT		 1519 *
1520 * LOCKING:
0cba632b 1521 * PCI/etc. bus probe sem.
1da177e4
LT		 1522 *
1523 */
1524void __sata_phy_reset(struct ata_port *ap)
1525{
1526 u32 sstatus;
1527 unsigned long timeout = jiffies + (HZ * 5);
1528
1529 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1530 /* issue phy wake/reset */
1531 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1532 /* Couldn't find anything in SATA I/II specs, but
1533 * AHCI-1.1 10.4.2 says at least 1 ms. */
1534 mdelay(1);
1da177e4 1535 }
cdcca89e 1536 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1537
1538 /* wait for phy to become ready, if necessary */
1539 do {
1540 msleep(200);
1541 sstatus = scr_read(ap, SCR_STATUS);
1542 if ((sstatus & 0xf) != 1)
1543 break;
1544 } while (time_before(jiffies, timeout));
1545
1546 /* TODO: phy layer with polling, timeouts, etc. */
656563e3
JG		 1547 sstatus = scr_read(ap, SCR_STATUS);
1548 if (sata_dev_present(ap)) {
1549 const char *speed;
1550 u32 tmp;
1551
1552 tmp = (sstatus >> 4) & 0xf;
1553 if (tmp & (1 << 0))
1554 speed = "1.5";
1555 else if (tmp & (1 << 1))
1556 speed = "3.0";
1557 else
1558 speed = "<unknown>";
1559 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1560 ap->id, speed, sstatus);
1da177e4 1561 ata_port_probe(ap);
656563e3
JG		 1562 } else {
1563 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1da177e4
LT		 1564 ap->id, sstatus);
1565 ata_port_disable(ap);
1566 }
1567
1568 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1569 return;
1570
1571 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1572 ata_port_disable(ap);
1573 return;
1574 }
1575
1576 ap->cbl = ATA_CBL_SATA;
1577}
1578
1579/**
780a87f7
JG		 1580 * sata_phy_reset - Reset SATA bus.
1581 * @ap: SATA port associated with target SATA PHY.
1da177e4 1582 *
780a87f7
JG		 1583 * This function resets the SATA bus, and then probes
1584 * the bus for devices.
1da177e4
LT		 1585 *
1586 * LOCKING:
0cba632b 1587 * PCI/etc. bus probe sem.
1da177e4
LT		 1588 *
1589 */
1590void sata_phy_reset(struct ata_port *ap)
1591{
1592 __sata_phy_reset(ap);
1593 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1594 return;
1595 ata_bus_reset(ap);
1596}
1597
1598/**
780a87f7
JG		 1599 * ata_port_disable - Disable port.
1600 * @ap: Port to be disabled.
1da177e4 1601 *
780a87f7
JG		 1602 * Modify @ap data structure such that the system
1603 * thinks that the entire port is disabled, and should
1604 * never attempt to probe or communicate with devices
1605 * on this port.
1606 *
1607 * LOCKING: host_set lock, or some other form of
1608 * serialization.
1da177e4
LT		 1609 */
1610
1611void ata_port_disable(struct ata_port *ap)
1612{
1613 ap->device[0].class = ATA_DEV_NONE;
1614 ap->device[1].class = ATA_DEV_NONE;
1615 ap->flags |= ATA_FLAG_PORT_DISABLED;
1616}
1617
452503f9
AC		 1618/*
1619 * This mode timing computation functionality is ported over from
1620 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1621 */
1622/*
1623 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1624 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1625 * for PIO 5, which is a nonstandard extension and UDMA6, which
1626 * is currently supported only by Maxtor drives.
1627 */
1628
1629static const struct ata_timing ata_timing[] = {
1630
1631 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1632 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1633 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1634 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1635
1636 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1637 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1638 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1639
1640/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1641
1642 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1643 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1644 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1645
1646 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1647 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1648 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1649
1650/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1651 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1652 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1653
1654 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1655 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1656 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1657
1658/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1659
1660 { 0xFF }
1661};
1662
1663#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1664#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1665
1666static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1667{
1668 q->setup = EZ(t->setup * 1000, T);
1669 q->act8b = EZ(t->act8b * 1000, T);
1670 q->rec8b = EZ(t->rec8b * 1000, T);
1671 q->cyc8b = EZ(t->cyc8b * 1000, T);
1672 q->active = EZ(t->active * 1000, T);
1673 q->recover = EZ(t->recover * 1000, T);
1674 q->cycle = EZ(t->cycle * 1000, T);
1675 q->udma = EZ(t->udma * 1000, UT);
1676}
1677
1678void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1679 struct ata_timing *m, unsigned int what)
1680{
1681 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1682 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1683 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1684 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1685 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1686 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1687 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1688 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1689}
1690
1691static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1692{
1693 const struct ata_timing *t;
1694
1695 for (t = ata_timing; t->mode != speed; t++)
91190758 1696 if (t->mode == 0xFF)
452503f9
AC		 1697 return NULL;
1698 return t;
1699}
1700
1701int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1702 struct ata_timing *t, int T, int UT)
1703{
1704 const struct ata_timing *s;
1705 struct ata_timing p;
1706
1707 /*
1708 * Find the mode.
75b1f2f8 1709 */
452503f9
AC		 1710
1711 if (!(s = ata_timing_find_mode(speed)))
1712 return -EINVAL;
1713
75b1f2f8
AL		 1714 memcpy(t, s, sizeof(*s));
1715
452503f9
AC		 1716 /*
1717 * If the drive is an EIDE drive, it can tell us it needs extended
1718 * PIO/MW_DMA cycle timing.
1719 */
1720
1721 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1722 memset(&p, 0, sizeof(p));
1723 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1724 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1725 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1726 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1727 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1728 }
1729 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1730 }
1731
1732 /*
1733 * Convert the timing to bus clock counts.
1734 */
1735
75b1f2f8 1736 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1737
1738 /*
1739 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
1740 * and some other commands. We have to ensure that the DMA cycle timing is
1741 * slower/equal than the fastest PIO timing.
1742 */
1743
1744 if (speed > XFER_PIO_4) {
1745 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1746 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1747 }
1748
1749 /*
1750 * Lenghten active & recovery time so that cycle time is correct.
1751 */
1752
1753 if (t->act8b + t->rec8b < t->cyc8b) {
1754 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1755 t->rec8b = t->cyc8b - t->act8b;
1756 }
1757
1758 if (t->active + t->recover < t->cycle) {
1759 t->active += (t->cycle - (t->active + t->recover)) / 2;
1760 t->recover = t->cycle - t->active;
1761 }
1762
1763 return 0;
1764}
1765
057ace5e 1766static const struct {
1da177e4
LT		 1767 unsigned int shift;
1768 u8 base;
1769} xfer_mode_classes[] = {
1770 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1771 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1772 { ATA_SHIFT_PIO, XFER_PIO_0 },
1773};
1774
1775static inline u8 base_from_shift(unsigned int shift)
1776{
1777 int i;
1778
1779 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1780 if (xfer_mode_classes[i].shift == shift)
1781 return xfer_mode_classes[i].base;
1782
1783 return 0xff;
1784}
1785
1786static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1787{
1788 int ofs, idx;
1789 u8 base;
1790
1791 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1792 return;
1793
1794 if (dev->xfer_shift == ATA_SHIFT_PIO)
1795 dev->flags |= ATA_DFLAG_PIO;
1796
1797 ata_dev_set_xfermode(ap, dev);
1798
1799 base = base_from_shift(dev->xfer_shift);
1800 ofs = dev->xfer_mode - base;
1801 idx = ofs + dev->xfer_shift;
1802 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1803
1804 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1805 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1806
1807 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1808 ap->id, dev->devno, xfer_mode_str[idx]);
1809}
1810
1811static int ata_host_set_pio(struct ata_port *ap)
1812{
1813 unsigned int mask;
1814 int x, i;
1815 u8 base, xfer_mode;
1816
1817 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1818 x = fgb(mask);
1819 if (x < 0) {
1820 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1821 return -1;
1822 }
1823
1824 base = base_from_shift(ATA_SHIFT_PIO);
1825 xfer_mode = base + x;
1826
1827 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1828 (int)base, (int)xfer_mode, mask, x);
1829
1830 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1831 struct ata_device *dev = &ap->device[i];
1832 if (ata_dev_present(dev)) {
1833 dev->pio_mode = xfer_mode;
1834 dev->xfer_mode = xfer_mode;
1835 dev->xfer_shift = ATA_SHIFT_PIO;
1836 if (ap->ops->set_piomode)
1837 ap->ops->set_piomode(ap, dev);
1838 }
1839 }
1840
1841 return 0;
1842}
1843
1844static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1845 unsigned int xfer_shift)
1846{
1847 int i;
1848
1849 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1850 struct ata_device *dev = &ap->device[i];
1851 if (ata_dev_present(dev)) {
1852 dev->dma_mode = xfer_mode;
1853 dev->xfer_mode = xfer_mode;
1854 dev->xfer_shift = xfer_shift;
1855 if (ap->ops->set_dmamode)
1856 ap->ops->set_dmamode(ap, dev);
1857 }
1858 }
1859}
1860
1861/**
1862 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1863 * @ap: port on which timings will be programmed
1864 *
780a87f7
JG		 1865 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1866 *
1da177e4 1867 * LOCKING:
0cba632b 1868 * PCI/etc. bus probe sem.
1da177e4
LT		 1869 *
1870 */
1871static void ata_set_mode(struct ata_port *ap)
1872{
8cbd6df1 1873 unsigned int xfer_shift;
1da177e4
LT		 1874 u8 xfer_mode;
1875 int rc;
1876
1877 /* step 1: always set host PIO timings */
1878 rc = ata_host_set_pio(ap);
1879 if (rc)
1880 goto err_out;
1881
1882 /* step 2: choose the best data xfer mode */
1883 xfer_mode = xfer_shift = 0;
1884 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1885 if (rc)
1886 goto err_out;
1887
1888 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1889 if (xfer_shift != ATA_SHIFT_PIO)
1890 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1891
1892 /* step 4: update devices' xfer mode */
1893 ata_dev_set_mode(ap, &ap->device[0]);
1894 ata_dev_set_mode(ap, &ap->device[1]);
1895
1896 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1897 return;
1898
1899 if (ap->ops->post_set_mode)
1900 ap->ops->post_set_mode(ap);
1901
1da177e4
LT		 1902 return;
1903
1904err_out:
1905 ata_port_disable(ap);
1906}
1907
1908/**
1909 * ata_busy_sleep - sleep until BSY clears, or timeout
1910 * @ap: port containing status register to be polled
1911 * @tmout_pat: impatience timeout
1912 * @tmout: overall timeout
1913 *
780a87f7
JG		 1914 * Sleep until ATA Status register bit BSY clears,
1915 * or a timeout occurs.
1916 *
1917 * LOCKING: None.
1da177e4
LT		 1918 *
1919 */
1920
1921static unsigned int ata_busy_sleep (struct ata_port *ap,
1922 unsigned long tmout_pat,
1923 unsigned long tmout)
1924{
1925 unsigned long timer_start, timeout;
1926 u8 status;
1927
1928 status = ata_busy_wait(ap, ATA_BUSY, 300);
1929 timer_start = jiffies;
1930 timeout = timer_start + tmout_pat;
1931 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1932 msleep(50);
1933 status = ata_busy_wait(ap, ATA_BUSY, 3);
1934 }
1935
1936 if (status & ATA_BUSY)
1937 printk(KERN_WARNING "ata%u is slow to respond, "
1938 "please be patient\n", ap->id);
1939
1940 timeout = timer_start + tmout;
1941 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1942 msleep(50);
1943 status = ata_chk_status(ap);
1944 }
1945
1946 if (status & ATA_BUSY) {
1947 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1948 ap->id, tmout / HZ);
1949 return 1;
1950 }
1951
1952 return 0;
1953}
1954
1955static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1956{
1957 struct ata_ioports *ioaddr = &ap->ioaddr;
1958 unsigned int dev0 = devmask & (1 << 0);
1959 unsigned int dev1 = devmask & (1 << 1);
1960 unsigned long timeout;
1961
1962 /* if device 0 was found in ata_devchk, wait for its
1963 * BSY bit to clear
1964 */
1965 if (dev0)
1966 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1967
1968 /* if device 1 was found in ata_devchk, wait for
1969 * register access, then wait for BSY to clear
1970 */
1971 timeout = jiffies + ATA_TMOUT_BOOT;
1972 while (dev1) {
1973 u8 nsect, lbal;
1974
1975 ap->ops->dev_select(ap, 1);
1976 if (ap->flags & ATA_FLAG_MMIO) {
1977 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1978 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1979 } else {
1980 nsect = inb(ioaddr->nsect_addr);
1981 lbal = inb(ioaddr->lbal_addr);
1982 }
1983 if ((nsect == 1) && (lbal == 1))
1984 break;
1985 if (time_after(jiffies, timeout)) {
1986 dev1 = 0;
1987 break;
1988 }
1989 msleep(50); /* give drive a breather */
1990 }
1991 if (dev1)
1992 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1993
1994 /* is all this really necessary? */
1995 ap->ops->dev_select(ap, 0);
1996 if (dev1)
1997 ap->ops->dev_select(ap, 1);
1998 if (dev0)
1999 ap->ops->dev_select(ap, 0);
2000}
2001
2002/**
0cba632b
JG		 2003 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
2004 * @ap: Port to reset and probe
2005 *
2006 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
2007 * probe the bus. Not often used these days.
1da177e4
LT		 2008 *
2009 * LOCKING:
0cba632b 2010 * PCI/etc. bus probe sem.
e5338254 2011 * Obtains host_set lock.
1da177e4
LT		 2012 *
2013 */
2014
2015static unsigned int ata_bus_edd(struct ata_port *ap)
2016{
2017 struct ata_taskfile tf;
e5338254 2018 unsigned long flags;
1da177e4
LT		 2019
2020 /* set up execute-device-diag (bus reset) taskfile */
2021 /* also, take interrupts to a known state (disabled) */
2022 DPRINTK("execute-device-diag\n");
2023 ata_tf_init(ap, &tf, 0);
2024 tf.ctl |= ATA_NIEN;
2025 tf.command = ATA_CMD_EDD;
2026 tf.protocol = ATA_PROT_NODATA;
2027
2028 /* do bus reset */
e5338254 2029 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 2030 ata_tf_to_host(ap, &tf);
e5338254 2031 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 2032
2033 /* spec says at least 2ms. but who knows with those
2034 * crazy ATAPI devices...
2035 */
2036 msleep(150);
2037
2038 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2039}
2040
2041static unsigned int ata_bus_softreset(struct ata_port *ap,
2042 unsigned int devmask)
2043{
2044 struct ata_ioports *ioaddr = &ap->ioaddr;
2045
2046 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2047
2048 /* software reset. causes dev0 to be selected */
2049 if (ap->flags & ATA_FLAG_MMIO) {
2050 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2051 udelay(20); /* FIXME: flush */
2052 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2053 udelay(20); /* FIXME: flush */
2054 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2055 } else {
2056 outb(ap->ctl, ioaddr->ctl_addr);
2057 udelay(10);
2058 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2059 udelay(10);
2060 outb(ap->ctl, ioaddr->ctl_addr);
2061 }
2062
2063 /* spec mandates ">= 2ms" before checking status.
2064 * We wait 150ms, because that was the magic delay used for
2065 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2066 * between when the ATA command register is written, and then
2067 * status is checked. Because waiting for "a while" before
2068 * checking status is fine, post SRST, we perform this magic
2069 * delay here as well.
2070 */
2071 msleep(150);
2072
2073 ata_bus_post_reset(ap, devmask);
2074
2075 return 0;
2076}
2077
2078/**
2079 * ata_bus_reset - reset host port and associated ATA channel
2080 * @ap: port to reset
2081 *
2082 * This is typically the first time we actually start issuing
2083 * commands to the ATA channel. We wait for BSY to clear, then
2084 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2085 * result. Determine what devices, if any, are on the channel
2086 * by looking at the device 0/1 error register. Look at the signature
2087 * stored in each device's taskfile registers, to determine if
2088 * the device is ATA or ATAPI.
2089 *
2090 * LOCKING:
0cba632b
JG		 2091 * PCI/etc. bus probe sem.
2092 * Obtains host_set lock.
1da177e4
LT		 2093 *
2094 * SIDE EFFECTS:
2095 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
2096 */
2097
2098void ata_bus_reset(struct ata_port *ap)
2099{
2100 struct ata_ioports *ioaddr = &ap->ioaddr;
2101 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2102 u8 err;
2103 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
2104
2105 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2106
2107 /* determine if device 0/1 are present */
2108 if (ap->flags & ATA_FLAG_SATA_RESET)
2109 dev0 = 1;
2110 else {
2111 dev0 = ata_devchk(ap, 0);
2112 if (slave_possible)
2113 dev1 = ata_devchk(ap, 1);
2114 }
2115
2116 if (dev0)
2117 devmask |= (1 << 0);
2118 if (dev1)
2119 devmask |= (1 << 1);
2120
2121 /* select device 0 again */
2122 ap->ops->dev_select(ap, 0);
2123
2124 /* issue bus reset */
2125 if (ap->flags & ATA_FLAG_SRST)
2126 rc = ata_bus_softreset(ap, devmask);
2127 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
2128 /* set up device control */
2129 if (ap->flags & ATA_FLAG_MMIO)
2130 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2131 else
2132 outb(ap->ctl, ioaddr->ctl_addr);
2133 rc = ata_bus_edd(ap);
2134 }
2135
2136 if (rc)
2137 goto err_out;
2138
2139 /*
2140 * determine by signature whether we have ATA or ATAPI devices
2141 */
2142 err = ata_dev_try_classify(ap, 0);
2143 if ((slave_possible) && (err != 0x81))
2144 ata_dev_try_classify(ap, 1);
2145
2146 /* re-enable interrupts */
2147 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2148 ata_irq_on(ap);
2149
2150 /* is double-select really necessary? */
2151 if (ap->device[1].class != ATA_DEV_NONE)
2152 ap->ops->dev_select(ap, 1);
2153 if (ap->device[0].class != ATA_DEV_NONE)
2154 ap->ops->dev_select(ap, 0);
2155
2156 /* if no devices were detected, disable this port */
2157 if ((ap->device[0].class == ATA_DEV_NONE) &&
2158 (ap->device[1].class == ATA_DEV_NONE))
2159 goto err_out;
2160
2161 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2162 /* set up device control for ATA_FLAG_SATA_RESET */
2163 if (ap->flags & ATA_FLAG_MMIO)
2164 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2165 else
2166 outb(ap->ctl, ioaddr->ctl_addr);
2167 }
2168
2169 DPRINTK("EXIT\n");
2170 return;
2171
2172err_out:
2173 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2174 ap->ops->port_disable(ap);
2175
2176 DPRINTK("EXIT\n");
2177}
2178
057ace5e
JG		 2179static void ata_pr_blacklisted(const struct ata_port *ap,
2180 const struct ata_device *dev)
1da177e4
LT		 2181{
2182 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2183 ap->id, dev->devno);
2184}
2185
98ac62de 2186static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2187 "WDC AC11000H",
2188 "WDC AC22100H",
2189 "WDC AC32500H",
2190 "WDC AC33100H",
2191 "WDC AC31600H",
2192 "WDC AC32100H",
2193 "WDC AC23200L",
2194 "Compaq CRD-8241B",
2195 "CRD-8400B",
2196 "CRD-8480B",
2197 "CRD-8482B",
2198 "CRD-84",
2199 "SanDisk SDP3B",
2200 "SanDisk SDP3B-64",
2201 "SANYO CD-ROM CRD",
2202 "HITACHI CDR-8",
2203 "HITACHI CDR-8335",
2204 "HITACHI CDR-8435",
2205 "Toshiba CD-ROM XM-6202B",
e922256a 2206 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2207 "CD-532E-A",
2208 "E-IDE CD-ROM CR-840",
2209 "CD-ROM Drive/F5A",
2210 "WPI CDD-820",
2211 "SAMSUNG CD-ROM SC-148C",
2212 "SAMSUNG CD-ROM SC",
2213 "SanDisk SDP3B-64",
1da177e4
LT		 2214 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2215 "_NEC DV5800A",
2216};
2217
057ace5e 2218static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2219{
2220 unsigned char model_num[40];
2221 char *s;
2222 unsigned int len;
2223 int i;
2224
2225 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2226 sizeof(model_num));
2227 s = &model_num[0];
2228 len = strnlen(s, sizeof(model_num));
2229
2230 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2231 while ((len > 0) && (s[len - 1] == ' ')) {
2232 len--;
2233 s[len] = 0;
2234 }
2235
2236 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2237 if (!strncmp(ata_dma_blacklist[i], s, len))
2238 return 1;
2239
2240 return 0;
2241}
2242
057ace5e 2243static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2244{
057ace5e 2245 const struct ata_device *master, *slave;
1da177e4
LT		 2246 unsigned int mask;
2247
2248 master = &ap->device[0];
2249 slave = &ap->device[1];
2250
2251 assert (ata_dev_present(master) || ata_dev_present(slave));
2252
2253 if (shift == ATA_SHIFT_UDMA) {
2254 mask = ap->udma_mask;
2255 if (ata_dev_present(master)) {
2256 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2257 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2258 mask = 0;
2259 ata_pr_blacklisted(ap, master);
2260 }
2261 }
2262 if (ata_dev_present(slave)) {
2263 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2264 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2265 mask = 0;
2266 ata_pr_blacklisted(ap, slave);
2267 }
2268 }
2269 }
2270 else if (shift == ATA_SHIFT_MWDMA) {
2271 mask = ap->mwdma_mask;
2272 if (ata_dev_present(master)) {
2273 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2274 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2275 mask = 0;
2276 ata_pr_blacklisted(ap, master);
2277 }
2278 }
2279 if (ata_dev_present(slave)) {
2280 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2281 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2282 mask = 0;
2283 ata_pr_blacklisted(ap, slave);
2284 }
2285 }
2286 }
2287 else if (shift == ATA_SHIFT_PIO) {
2288 mask = ap->pio_mask;
2289 if (ata_dev_present(master)) {
2290 /* spec doesn't return explicit support for
2291 * PIO0-2, so we fake it
2292 */
2293 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2294 tmp_mode <<= 3;
2295 tmp_mode |= 0x7;
2296 mask &= tmp_mode;
2297 }
2298 if (ata_dev_present(slave)) {
2299 /* spec doesn't return explicit support for
2300 * PIO0-2, so we fake it
2301 */
2302 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2303 tmp_mode <<= 3;
2304 tmp_mode |= 0x7;
2305 mask &= tmp_mode;
2306 }
2307 }
2308 else {
2309 mask = 0xffffffff; /* shut up compiler warning */
2310 BUG();
2311 }
2312
2313 return mask;
2314}
2315
2316/* find greatest bit */
2317static int fgb(u32 bitmap)
2318{
2319 unsigned int i;
2320 int x = -1;
2321
2322 for (i = 0; i < 32; i++)
2323 if (bitmap & (1 << i))
2324 x = i;
2325
2326 return x;
2327}
2328
2329/**
2330 * ata_choose_xfer_mode - attempt to find best transfer mode
2331 * @ap: Port for which an xfer mode will be selected
2332 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2333 * @xfer_shift_out: (output) bit shift that selects this mode
2334 *
0cba632b
JG		 2335 * Based on host and device capabilities, determine the
2336 * maximum transfer mode that is amenable to all.
2337 *
1da177e4 2338 * LOCKING:
0cba632b 2339 * PCI/etc. bus probe sem.
1da177e4
LT		 2340 *
2341 * RETURNS:
2342 * Zero on success, negative on error.
2343 */
2344
057ace5e 2345static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2346 u8 *xfer_mode_out,
2347 unsigned int *xfer_shift_out)
2348{
2349 unsigned int mask, shift;
2350 int x, i;
2351
2352 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2353 shift = xfer_mode_classes[i].shift;
2354 mask = ata_get_mode_mask(ap, shift);
2355
2356 x = fgb(mask);
2357 if (x >= 0) {
2358 *xfer_mode_out = xfer_mode_classes[i].base + x;
2359 *xfer_shift_out = shift;
2360 return 0;
2361 }
2362 }
2363
2364 return -1;
2365}
2366
2367/**
2368 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2369 * @ap: Port associated with device @dev
2370 * @dev: Device to which command will be sent
2371 *
780a87f7
JG		 2372 * Issue SET FEATURES - XFER MODE command to device @dev
2373 * on port @ap.
2374 *
1da177e4 2375 * LOCKING:
0cba632b 2376 * PCI/etc. bus probe sem.
1da177e4
LT		 2377 */
2378
2379static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2380{
2381 DECLARE_COMPLETION(wait);
2382 struct ata_queued_cmd *qc;
2383 int rc;
2384 unsigned long flags;
2385
2386 /* set up set-features taskfile */
2387 DPRINTK("set features - xfer mode\n");
2388
2389 qc = ata_qc_new_init(ap, dev);
2390 BUG_ON(qc == NULL);
2391
2392 qc->tf.command = ATA_CMD_SET_FEATURES;
2393 qc->tf.feature = SETFEATURES_XFER;
2394 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2395 qc->tf.protocol = ATA_PROT_NODATA;
2396 qc->tf.nsect = dev->xfer_mode;
2397
2398 qc->waiting = &wait;
2399 qc->complete_fn = ata_qc_complete_noop;
2400
2401 spin_lock_irqsave(&ap->host_set->lock, flags);
2402 rc = ata_qc_issue(qc);
2403 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2404
2405 if (rc)
2406 ata_port_disable(ap);
2407 else
64f043d8 2408 ata_qc_wait_err(qc, &wait);
1da177e4
LT		 2409
2410 DPRINTK("EXIT\n");
2411}
2412
59a10b17
AL		 2413/**
2414 * ata_dev_reread_id - Reread the device identify device info
2415 * @ap: port where the device is
2416 * @dev: device to reread the identify device info
2417 *
2418 * LOCKING:
2419 */
2420
2421static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2422{
2423 DECLARE_COMPLETION(wait);
2424 struct ata_queued_cmd *qc;
2425 unsigned long flags;
2426 int rc;
2427
2428 qc = ata_qc_new_init(ap, dev);
2429 BUG_ON(qc == NULL);
2430
2431 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
2432 qc->dma_dir = DMA_FROM_DEVICE;
2433
2434 if (dev->class == ATA_DEV_ATA) {
2435 qc->tf.command = ATA_CMD_ID_ATA;
2436 DPRINTK("do ATA identify\n");
2437 } else {
2438 qc->tf.command = ATA_CMD_ID_ATAPI;
2439 DPRINTK("do ATAPI identify\n");
2440 }
2441
2442 qc->tf.flags |= ATA_TFLAG_DEVICE;
2443 qc->tf.protocol = ATA_PROT_PIO;
2444 qc->nsect = 1;
2445
2446 qc->waiting = &wait;
2447 qc->complete_fn = ata_qc_complete_noop;
2448
2449 spin_lock_irqsave(&ap->host_set->lock, flags);
2450 rc = ata_qc_issue(qc);
2451 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2452
2453 if (rc)
2454 goto err_out;
2455
64f043d8 2456 ata_qc_wait_err(qc, &wait);
59a10b17
AL		 2457
2458 swap_buf_le16(dev->id, ATA_ID_WORDS);
2459
2460 ata_dump_id(dev);
2461
2462 DPRINTK("EXIT\n");
2463
2464 return;
2465err_out:
2466 ata_port_disable(ap);
2467}
2468
8bf62ece
AL		 2469/**
2470 * ata_dev_init_params - Issue INIT DEV PARAMS command
2471 * @ap: Port associated with device @dev
2472 * @dev: Device to which command will be sent
2473 *
2474 * LOCKING:
2475 */
2476
2477static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2478{
2479 DECLARE_COMPLETION(wait);
2480 struct ata_queued_cmd *qc;
2481 int rc;
2482 unsigned long flags;
2483 u16 sectors = dev->id[6];
2484 u16 heads = dev->id[3];
2485
2486 /* Number of sectors per track 1-255. Number of heads 1-16 */
2487 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2488 return;
2489
2490 /* set up init dev params taskfile */
2491 DPRINTK("init dev params \n");
2492
2493 qc = ata_qc_new_init(ap, dev);
2494 BUG_ON(qc == NULL);
2495
2496 qc->tf.command = ATA_CMD_INIT_DEV_PARAMS;
2497 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2498 qc->tf.protocol = ATA_PROT_NODATA;
2499 qc->tf.nsect = sectors;
2500 qc->tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
2501
2502 qc->waiting = &wait;
2503 qc->complete_fn = ata_qc_complete_noop;
2504
2505 spin_lock_irqsave(&ap->host_set->lock, flags);
2506 rc = ata_qc_issue(qc);
2507 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2508
2509 if (rc)
2510 ata_port_disable(ap);
2511 else
64f043d8 2512 ata_qc_wait_err(qc, &wait);
8bf62ece
AL		 2513
2514 DPRINTK("EXIT\n");
2515}
2516
1da177e4 2517/**
0cba632b
JG		 2518 * ata_sg_clean - Unmap DMA memory associated with command
2519 * @qc: Command containing DMA memory to be released
2520 *
2521 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2522 *
2523 * LOCKING:
0cba632b 2524 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2525 */
2526
2527static void ata_sg_clean(struct ata_queued_cmd *qc)
2528{
2529 struct ata_port *ap = qc->ap;
cedc9a47 2530 struct scatterlist *sg = qc->__sg;
1da177e4 2531 int dir = qc->dma_dir;
cedc9a47 2532 void *pad_buf = NULL;
1da177e4
LT		 2533
2534 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2535 assert(sg != NULL);
2536
2537 if (qc->flags & ATA_QCFLAG_SINGLE)
2538 assert(qc->n_elem == 1);
2539
2c13b7ce 2540 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2541
cedc9a47
JG		 2542 /* if we padded the buffer out to 32-bit bound, and data
2543 * xfer direction is from-device, we must copy from the
2544 * pad buffer back into the supplied buffer
2545 */
2546 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2547 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2548
2549 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2550 if (qc->n_elem)
2551 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2552 /* restore last sg */
2553 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2554 if (pad_buf) {
2555 struct scatterlist *psg = &qc->pad_sgent;
2556 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2557 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2558 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2559 }
2560 } else {
e1410f2d
JG		 2561 if (sg_dma_len(&sg[0]) > 0)
2562 dma_unmap_single(ap->host_set->dev,
2563 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2564 dir);
cedc9a47
JG		 2565 /* restore sg */
2566 sg->length += qc->pad_len;
2567 if (pad_buf)
2568 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2569 pad_buf, qc->pad_len);
2570 }
1da177e4
LT		 2571
2572 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2573 qc->__sg = NULL;
1da177e4
LT		 2574}
2575
2576/**
2577 * ata_fill_sg - Fill PCI IDE PRD table
2578 * @qc: Metadata associated with taskfile to be transferred
2579 *
780a87f7
JG		 2580 * Fill PCI IDE PRD (scatter-gather) table with segments
2581 * associated with the current disk command.
2582 *
1da177e4 2583 * LOCKING:
780a87f7 2584 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2585 *
2586 */
2587static void ata_fill_sg(struct ata_queued_cmd *qc)
2588{
1da177e4 2589 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2590 struct scatterlist *sg;
2591 unsigned int idx;
1da177e4 2592
cedc9a47 2593 assert(qc->__sg != NULL);
1da177e4
LT		 2594 assert(qc->n_elem > 0);
2595
2596 idx = 0;
cedc9a47 2597 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2598 u32 addr, offset;
2599 u32 sg_len, len;
2600
2601 /* determine if physical DMA addr spans 64K boundary.
2602 * Note h/w doesn't support 64-bit, so we unconditionally
2603 * truncate dma_addr_t to u32.
2604 */
2605 addr = (u32) sg_dma_address(sg);
2606 sg_len = sg_dma_len(sg);
2607
2608 while (sg_len) {
2609 offset = addr & 0xffff;
2610 len = sg_len;
2611 if ((offset + sg_len) > 0x10000)
2612 len = 0x10000 - offset;
2613
2614 ap->prd[idx].addr = cpu_to_le32(addr);
2615 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2616 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2617
2618 idx++;
2619 sg_len -= len;
2620 addr += len;
2621 }
2622 }
2623
2624 if (idx)
2625 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2626}
2627/**
2628 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2629 * @qc: Metadata associated with taskfile to check
2630 *
780a87f7
JG		 2631 * Allow low-level driver to filter ATA PACKET commands, returning
2632 * a status indicating whether or not it is OK to use DMA for the
2633 * supplied PACKET command.
2634 *
1da177e4 2635 * LOCKING:
0cba632b
JG		 2636 * spin_lock_irqsave(host_set lock)
2637 *
1da177e4
LT		 2638 * RETURNS: 0 when ATAPI DMA can be used
2639 * nonzero otherwise
2640 */
2641int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2642{
2643 struct ata_port *ap = qc->ap;
2644 int rc = 0; /* Assume ATAPI DMA is OK by default */
2645
2646 if (ap->ops->check_atapi_dma)
2647 rc = ap->ops->check_atapi_dma(qc);
2648
2649 return rc;
2650}
2651/**
2652 * ata_qc_prep - Prepare taskfile for submission
2653 * @qc: Metadata associated with taskfile to be prepared
2654 *
780a87f7
JG		 2655 * Prepare ATA taskfile for submission.
2656 *
1da177e4
LT		 2657 * LOCKING:
2658 * spin_lock_irqsave(host_set lock)
2659 */
2660void ata_qc_prep(struct ata_queued_cmd *qc)
2661{
2662 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2663 return;
2664
2665 ata_fill_sg(qc);
2666}
2667
0cba632b
JG		 2668/**
2669 * ata_sg_init_one - Associate command with memory buffer
2670 * @qc: Command to be associated
2671 * @buf: Memory buffer
2672 * @buflen: Length of memory buffer, in bytes.
2673 *
2674 * Initialize the data-related elements of queued_cmd @qc
2675 * to point to a single memory buffer, @buf of byte length @buflen.
2676 *
2677 * LOCKING:
2678 * spin_lock_irqsave(host_set lock)
2679 */
2680
1da177e4
LT		 2681void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2682{
2683 struct scatterlist *sg;
2684
2685 qc->flags |= ATA_QCFLAG_SINGLE;
2686
2687 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2688 qc->__sg = &qc->sgent;
1da177e4 2689 qc->n_elem = 1;
cedc9a47 2690 qc->orig_n_elem = 1;
1da177e4
LT		 2691 qc->buf_virt = buf;
2692
cedc9a47 2693 sg = qc->__sg;
f0612bbc 2694 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2695}
2696
0cba632b
JG		 2697/**
2698 * ata_sg_init - Associate command with scatter-gather table.
2699 * @qc: Command to be associated
2700 * @sg: Scatter-gather table.
2701 * @n_elem: Number of elements in s/g table.
2702 *
2703 * Initialize the data-related elements of queued_cmd @qc
2704 * to point to a scatter-gather table @sg, containing @n_elem
2705 * elements.
2706 *
2707 * LOCKING:
2708 * spin_lock_irqsave(host_set lock)
2709 */
2710
1da177e4
LT		 2711void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2712 unsigned int n_elem)
2713{
2714 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2715 qc->__sg = sg;
1da177e4 2716 qc->n_elem = n_elem;
cedc9a47 2717 qc->orig_n_elem = n_elem;
1da177e4
LT		 2718}
2719
2720/**
0cba632b
JG		 2721 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2722 * @qc: Command with memory buffer to be mapped.
2723 *
2724 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2725 *
2726 * LOCKING:
2727 * spin_lock_irqsave(host_set lock)
2728 *
2729 * RETURNS:
0cba632b 2730 * Zero on success, negative on error.
1da177e4
LT		 2731 */
2732
2733static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2734{
2735 struct ata_port *ap = qc->ap;
2736 int dir = qc->dma_dir;
cedc9a47 2737 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2738 dma_addr_t dma_address;
2739
cedc9a47
JG		 2740 /* we must lengthen transfers to end on a 32-bit boundary */
2741 qc->pad_len = sg->length & 3;
2742 if (qc->pad_len) {
2743 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2744 struct scatterlist *psg = &qc->pad_sgent;
2745
2746 assert(qc->dev->class == ATA_DEV_ATAPI);
2747
2748 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2749
2750 if (qc->tf.flags & ATA_TFLAG_WRITE)
2751 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2752 qc->pad_len);
2753
2754 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2755 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2756 /* trim sg */
2757 sg->length -= qc->pad_len;
2758
2759 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2760 sg->length, qc->pad_len);
2761 }
2762
e1410f2d
JG		 2763 if (!sg->length) {
2764 sg_dma_address(sg) = 0;
2765 goto skip_map;
2766 }
2767
1da177e4 2768 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2769 sg->length, dir);
537a95d9
TH		 2770 if (dma_mapping_error(dma_address)) {
2771 /* restore sg */
2772 sg->length += qc->pad_len;
1da177e4 2773 return -1;
537a95d9 2774 }
1da177e4
LT		 2775
2776 sg_dma_address(sg) = dma_address;
e1410f2d 2777skip_map:
32529e01 2778 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2779
2780 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2781 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2782
2783 return 0;
2784}
2785
2786/**
0cba632b
JG		 2787 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2788 * @qc: Command with scatter-gather table to be mapped.
2789 *
2790 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2791 *
2792 * LOCKING:
2793 * spin_lock_irqsave(host_set lock)
2794 *
2795 * RETURNS:
0cba632b 2796 * Zero on success, negative on error.
1da177e4
LT		 2797 *
2798 */
2799
2800static int ata_sg_setup(struct ata_queued_cmd *qc)
2801{
2802 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2803 struct scatterlist *sg = qc->__sg;
2804 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2805 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2806
2807 VPRINTK("ENTER, ata%u\n", ap->id);
2808 assert(qc->flags & ATA_QCFLAG_SG);
2809
cedc9a47
JG		 2810 /* we must lengthen transfers to end on a 32-bit boundary */
2811 qc->pad_len = lsg->length & 3;
2812 if (qc->pad_len) {
2813 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2814 struct scatterlist *psg = &qc->pad_sgent;
2815 unsigned int offset;
2816
2817 assert(qc->dev->class == ATA_DEV_ATAPI);
2818
2819 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2820
2821 /*
2822 * psg->page/offset are used to copy to-be-written
2823 * data in this function or read data in ata_sg_clean.
2824 */
2825 offset = lsg->offset + lsg->length - qc->pad_len;
2826 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2827 psg->offset = offset_in_page(offset);
2828
2829 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2830 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2831 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2832 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2833 }
2834
2835 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2836 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2837 /* trim last sg */
2838 lsg->length -= qc->pad_len;
e1410f2d
JG		 2839 if (lsg->length == 0)
2840 trim_sg = 1;
cedc9a47
JG		 2841
2842 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2843 qc->n_elem - 1, lsg->length, qc->pad_len);
2844 }
2845
e1410f2d
JG		 2846 pre_n_elem = qc->n_elem;
2847 if (trim_sg && pre_n_elem)
2848 pre_n_elem--;
2849
2850 if (!pre_n_elem) {
2851 n_elem = 0;
2852 goto skip_map;
2853 }
2854
1da177e4 2855 dir = qc->dma_dir;
e1410f2d 2856 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2857 if (n_elem < 1) {
2858 /* restore last sg */
2859 lsg->length += qc->pad_len;
1da177e4 2860 return -1;
537a95d9 2861 }
1da177e4
LT		 2862
2863 DPRINTK("%d sg elements mapped\n", n_elem);
2864
e1410f2d 2865skip_map:
1da177e4
LT		 2866 qc->n_elem = n_elem;
2867
2868 return 0;
2869}
2870
40e8c82c
TH		 2871/**
2872 * ata_poll_qc_complete - turn irq back on and finish qc
2873 * @qc: Command to complete
8e8b77dd 2874 * @err_mask: ATA status register content
40e8c82c
TH		 2875 *
2876 * LOCKING:
2877 * None. (grabs host lock)
2878 */
2879
a22e2eb0 2880void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2881{
2882 struct ata_port *ap = qc->ap;
b8f6153e 2883 unsigned long flags;
40e8c82c 2884
b8f6153e 2885 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2886 ap->flags &= ~ATA_FLAG_NOINTR;
2887 ata_irq_on(ap);
a22e2eb0 2888 ata_qc_complete(qc);
b8f6153e 2889 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2890}
2891
1da177e4
LT		 2892/**
2893 * ata_pio_poll -
6f0ef4fa 2894 * @ap: the target ata_port
1da177e4
LT		 2895 *
2896 * LOCKING:
0cba632b 2897 * None. (executing in kernel thread context)
1da177e4
LT		 2898 *
2899 * RETURNS:
6f0ef4fa 2900 * timeout value to use
1da177e4
LT		 2901 */
2902
2903static unsigned long ata_pio_poll(struct ata_port *ap)
2904{
c14b8331 2905 struct ata_queued_cmd *qc;
1da177e4 2906 u8 status;
14be71f4
AL		 2907 unsigned int poll_state = HSM_ST_UNKNOWN;
2908 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2909
c14b8331
AL		 2910 qc = ata_qc_from_tag(ap, ap->active_tag);
2911 assert(qc != NULL);
2912
14be71f4
AL		 2913 switch (ap->hsm_task_state) {
2914 case HSM_ST:
2915 case HSM_ST_POLL:
2916 poll_state = HSM_ST_POLL;
2917 reg_state = HSM_ST;
1da177e4 2918 break;
14be71f4
AL		 2919 case HSM_ST_LAST:
2920 case HSM_ST_LAST_POLL:
2921 poll_state = HSM_ST_LAST_POLL;
2922 reg_state = HSM_ST_LAST;
1da177e4
LT		 2923 break;
2924 default:
2925 BUG();
2926 break;
2927 }
2928
2929 status = ata_chk_status(ap);
2930 if (status & ATA_BUSY) {
2931 if (time_after(jiffies, ap->pio_task_timeout)) {
1c848984 2932 qc->err_mask |= AC_ERR_ATA_BUS;
7c398335 2933 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2934 return 0;
2935 }
14be71f4 2936 ap->hsm_task_state = poll_state;
1da177e4
LT		 2937 return ATA_SHORT_PAUSE;
2938 }
2939
14be71f4 2940 ap->hsm_task_state = reg_state;
1da177e4
LT		 2941 return 0;
2942}
2943
2944/**
6f0ef4fa
RD		 2945 * ata_pio_complete - check if drive is busy or idle
2946 * @ap: the target ata_port
1da177e4
LT		 2947 *
2948 * LOCKING:
0cba632b 2949 * None. (executing in kernel thread context)
7fb6ec28
JG		 2950 *
2951 * RETURNS:
2952 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2953 */
2954
7fb6ec28 2955static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2956{
2957 struct ata_queued_cmd *qc;
2958 u8 drv_stat;
2959
2960 /*
31433ea3
AC		 2961 * This is purely heuristic. This is a fast path. Sometimes when
2962 * we enter, BSY will be cleared in a chk-status or two. If not,
2963 * the drive is probably seeking or something. Snooze for a couple
2964 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2965 * HSM_ST_POLL state.
1da177e4 2966 */
fe79e683
AL		 2967 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2968 if (drv_stat & ATA_BUSY) {
1da177e4 2969 msleep(2);
fe79e683
AL		 2970 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2971 if (drv_stat & ATA_BUSY) {
14be71f4 2972 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2973 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2974 return 0;
1da177e4
LT		 2975 }
2976 }
2977
c14b8331
AL		 2978 qc = ata_qc_from_tag(ap, ap->active_tag);
2979 assert(qc != NULL);
2980
1da177e4
LT		 2981 drv_stat = ata_wait_idle(ap);
2982 if (!ata_ok(drv_stat)) {
1c848984 2983 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 2984 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2985 return 0;
1da177e4
LT		 2986 }
2987
14be71f4 2988 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2989
a22e2eb0
AL		 2990 assert(qc->err_mask == 0);
2991 ata_poll_qc_complete(qc);
7fb6ec28
JG		 2992
2993 /* another command may start at this point */
2994
2995 return 1;
1da177e4
LT		 2996}
2997
0baab86b
EF		 2998
2999/**
6f0ef4fa 3000 * swap_buf_le16 - swap halves of 16-words in place
0baab86b
EF		 3001 * @buf: Buffer to swap
3002 * @buf_words: Number of 16-bit words in buffer.
3003 *
3004 * Swap halves of 16-bit words if needed to convert from
3005 * little-endian byte order to native cpu byte order, or
3006 * vice-versa.
3007 *
3008 * LOCKING:
6f0ef4fa 3009 * Inherited from caller.
0baab86b 3010 */
1da177e4
LT		 3011void swap_buf_le16(u16 *buf, unsigned int buf_words)
3012{
3013#ifdef __BIG_ENDIAN
3014 unsigned int i;
3015
3016 for (i = 0; i < buf_words; i++)
3017 buf[i] = le16_to_cpu(buf[i]);
3018#endif /* __BIG_ENDIAN */
3019}
3020
6ae4cfb5
AL		 3021/**
3022 * ata_mmio_data_xfer - Transfer data by MMIO
3023 * @ap: port to read/write
3024 * @buf: data buffer
3025 * @buflen: buffer length
344babaa 3026 * @write_data: read/write
6ae4cfb5
AL		 3027 *
3028 * Transfer data from/to the device data register by MMIO.
3029 *
3030 * LOCKING:
3031 * Inherited from caller.
6ae4cfb5
AL		 3032 */
3033
1da177e4
LT		 3034static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3035 unsigned int buflen, int write_data)
3036{
3037 unsigned int i;
3038 unsigned int words = buflen >> 1;
3039 u16 *buf16 = (u16 *) buf;
3040 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3041
6ae4cfb5 3042 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3043 if (write_data) {
3044 for (i = 0; i < words; i++)
3045 writew(le16_to_cpu(buf16[i]), mmio);
3046 } else {
3047 for (i = 0; i < words; i++)
3048 buf16[i] = cpu_to_le16(readw(mmio));
3049 }
6ae4cfb5
AL		 3050
3051 /* Transfer trailing 1 byte, if any. */
3052 if (unlikely(buflen & 0x01)) {
3053 u16 align_buf[1] = { 0 };
3054 unsigned char *trailing_buf = buf + buflen - 1;
3055
3056 if (write_data) {
3057 memcpy(align_buf, trailing_buf, 1);
3058 writew(le16_to_cpu(align_buf[0]), mmio);
3059 } else {
3060 align_buf[0] = cpu_to_le16(readw(mmio));
3061 memcpy(trailing_buf, align_buf, 1);
3062 }
3063 }
1da177e4
LT		 3064}
3065
6ae4cfb5
AL		 3066/**
3067 * ata_pio_data_xfer - Transfer data by PIO
3068 * @ap: port to read/write
3069 * @buf: data buffer
3070 * @buflen: buffer length
344babaa 3071 * @write_data: read/write
6ae4cfb5
AL		 3072 *
3073 * Transfer data from/to the device data register by PIO.
3074 *
3075 * LOCKING:
3076 * Inherited from caller.
6ae4cfb5
AL		 3077 */
3078
1da177e4
LT		 3079static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3080 unsigned int buflen, int write_data)
3081{
6ae4cfb5 3082 unsigned int words = buflen >> 1;
1da177e4 3083
6ae4cfb5 3084 /* Transfer multiple of 2 bytes */
1da177e4 3085 if (write_data)
6ae4cfb5 3086 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3087 else
6ae4cfb5
AL		 3088 insw(ap->ioaddr.data_addr, buf, words);
3089
3090 /* Transfer trailing 1 byte, if any. */
3091 if (unlikely(buflen & 0x01)) {
3092 u16 align_buf[1] = { 0 };
3093 unsigned char *trailing_buf = buf + buflen - 1;
3094
3095 if (write_data) {
3096 memcpy(align_buf, trailing_buf, 1);
3097 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3098 } else {
3099 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3100 memcpy(trailing_buf, align_buf, 1);
3101 }
3102 }
1da177e4
LT		 3103}
3104
6ae4cfb5
AL		 3105/**
3106 * ata_data_xfer - Transfer data from/to the data register.
3107 * @ap: port to read/write
3108 * @buf: data buffer
3109 * @buflen: buffer length
3110 * @do_write: read/write
3111 *
3112 * Transfer data from/to the device data register.
3113 *
3114 * LOCKING:
3115 * Inherited from caller.
6ae4cfb5
AL		 3116 */
3117
1da177e4
LT		 3118static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3119 unsigned int buflen, int do_write)
3120{
3121 if (ap->flags & ATA_FLAG_MMIO)
3122 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3123 else
3124 ata_pio_data_xfer(ap, buf, buflen, do_write);
3125}
3126
6ae4cfb5
AL		 3127/**
3128 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3129 * @qc: Command on going
3130 *
3131 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3132 *
3133 * LOCKING:
3134 * Inherited from caller.
3135 */
3136
1da177e4
LT		 3137static void ata_pio_sector(struct ata_queued_cmd *qc)
3138{
3139 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3140 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3141 struct ata_port *ap = qc->ap;
3142 struct page *page;
3143 unsigned int offset;
3144 unsigned char *buf;
3145
3146 if (qc->cursect == (qc->nsect - 1))
14be71f4 3147 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3148
3149 page = sg[qc->cursg].page;
3150 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3151
3152 /* get the current page and offset */
3153 page = nth_page(page, (offset >> PAGE_SHIFT));
3154 offset %= PAGE_SIZE;
3155
3156 buf = kmap(page) + offset;
3157
3158 qc->cursect++;
3159 qc->cursg_ofs++;
3160
32529e01 3161 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3162 qc->cursg++;
3163 qc->cursg_ofs = 0;
3164 }
3165
3166 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3167
3168 /* do the actual data transfer */
3169 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3170 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3171
3172 kunmap(page);
3173}
3174
6ae4cfb5
AL		 3175/**
3176 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3177 * @qc: Command on going
3178 * @bytes: number of bytes
3179 *
3180 * Transfer Transfer data from/to the ATAPI device.
3181 *
3182 * LOCKING:
3183 * Inherited from caller.
3184 *
3185 */
3186
1da177e4
LT		 3187static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3188{
3189 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3190 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3191 struct ata_port *ap = qc->ap;
3192 struct page *page;
3193 unsigned char *buf;
3194 unsigned int offset, count;
3195
563a6e1f 3196 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3197 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3198
3199next_sg:
563a6e1f 3200 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3201 /*
563a6e1f
AL		 3202 * The end of qc->sg is reached and the device expects
3203 * more data to transfer. In order not to overrun qc->sg
3204 * and fulfill length specified in the byte count register,
3205 * - for read case, discard trailing data from the device
3206 * - for write case, padding zero data to the device
3207 */
3208 u16 pad_buf[1] = { 0 };
3209 unsigned int words = bytes >> 1;
3210 unsigned int i;
3211
3212 if (words) /* warning if bytes > 1 */
7fb6ec28 3213 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3214 ap->id, bytes);
3215
3216 for (i = 0; i < words; i++)
3217 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3218
14be71f4 3219 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3220 return;
3221 }
3222
cedc9a47 3223 sg = &qc->__sg[qc->cursg];
1da177e4 3224
1da177e4
LT		 3225 page = sg->page;
3226 offset = sg->offset + qc->cursg_ofs;
3227
3228 /* get the current page and offset */
3229 page = nth_page(page, (offset >> PAGE_SHIFT));
3230 offset %= PAGE_SIZE;
3231
6952df03 3232 /* don't overrun current sg */
32529e01 3233 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3234
3235 /* don't cross page boundaries */
3236 count = min(count, (unsigned int)PAGE_SIZE - offset);
3237
3238 buf = kmap(page) + offset;
3239
3240 bytes -= count;
3241 qc->curbytes += count;
3242 qc->cursg_ofs += count;
3243
32529e01 3244 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3245 qc->cursg++;
3246 qc->cursg_ofs = 0;
3247 }
3248
3249 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3250
3251 /* do the actual data transfer */
3252 ata_data_xfer(ap, buf, count, do_write);
3253
3254 kunmap(page);
3255
563a6e1f 3256 if (bytes)
1da177e4 3257 goto next_sg;
1da177e4
LT		 3258}
3259
6ae4cfb5
AL		 3260/**
3261 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3262 * @qc: Command on going
3263 *
3264 * Transfer Transfer data from/to the ATAPI device.
3265 *
3266 * LOCKING:
3267 * Inherited from caller.
6ae4cfb5
AL		 3268 */
3269
1da177e4
LT		 3270static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3271{
3272 struct ata_port *ap = qc->ap;
3273 struct ata_device *dev = qc->dev;
3274 unsigned int ireason, bc_lo, bc_hi, bytes;
3275 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3276
3277 ap->ops->tf_read(ap, &qc->tf);
3278 ireason = qc->tf.nsect;
3279 bc_lo = qc->tf.lbam;
3280 bc_hi = qc->tf.lbah;
3281 bytes = (bc_hi << 8) | bc_lo;
3282
3283 /* shall be cleared to zero, indicating xfer of data */
3284 if (ireason & (1 << 0))
3285 goto err_out;
3286
3287 /* make sure transfer direction matches expected */
3288 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3289 if (do_write != i_write)
3290 goto err_out;
3291
3292 __atapi_pio_bytes(qc, bytes);
3293
3294 return;
3295
3296err_out:
3297 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3298 ap->id, dev->devno);
1c848984 3299 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3300 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3301}
3302
3303/**
6f0ef4fa
RD		 3304 * ata_pio_block - start PIO on a block
3305 * @ap: the target ata_port
1da177e4
LT		 3306 *
3307 * LOCKING:
0cba632b 3308 * None. (executing in kernel thread context)
1da177e4
LT		 3309 */
3310
3311static void ata_pio_block(struct ata_port *ap)
3312{
3313 struct ata_queued_cmd *qc;
3314 u8 status;
3315
3316 /*
6f0ef4fa 3317 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3318 * Sometimes when we enter, BSY will be cleared in
3319 * a chk-status or two. If not, the drive is probably seeking
3320 * or something. Snooze for a couple msecs, then
3321 * chk-status again. If still busy, fall back to
14be71f4 3322 * HSM_ST_POLL state.
1da177e4
LT		 3323 */
3324 status = ata_busy_wait(ap, ATA_BUSY, 5);
3325 if (status & ATA_BUSY) {
3326 msleep(2);
3327 status = ata_busy_wait(ap, ATA_BUSY, 10);
3328 if (status & ATA_BUSY) {
14be71f4 3329 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3330 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3331 return;
3332 }
3333 }
3334
3335 qc = ata_qc_from_tag(ap, ap->active_tag);
3336 assert(qc != NULL);
3337
fe79e683
AL		 3338 /* check error */
3339 if (status & (ATA_ERR | ATA_DF)) {
3340 qc->err_mask |= AC_ERR_DEV;
3341 ap->hsm_task_state = HSM_ST_ERR;
3342 return;
3343 }
3344
3345 /* transfer data if any */
1da177e4 3346 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3347 /* DRQ=0 means no more data to transfer */
1da177e4 3348 if ((status & ATA_DRQ) == 0) {
14be71f4 3349 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3350 return;
3351 }
3352
3353 atapi_pio_bytes(qc);
3354 } else {
3355 /* handle BSY=0, DRQ=0 as error */
3356 if ((status & ATA_DRQ) == 0) {
1c848984 3357 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3358 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3359 return;
3360 }
3361
3362 ata_pio_sector(qc);
3363 }
3364}
3365
3366static void ata_pio_error(struct ata_port *ap)
3367{
3368 struct ata_queued_cmd *qc;
a7dac447
JG		 3369
3370 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3371
3372 qc = ata_qc_from_tag(ap, ap->active_tag);
3373 assert(qc != NULL);
3374
1c848984
AL		 3375 /* make sure qc->err_mask is available to
3376 * know what's wrong and recover
3377 */
3378 assert(qc->err_mask);
3379
14be71f4 3380 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3381
a22e2eb0 3382 ata_poll_qc_complete(qc);
1da177e4
LT		 3383}
3384
3385static void ata_pio_task(void *_data)
3386{
3387 struct ata_port *ap = _data;
7fb6ec28
JG		 3388 unsigned long timeout;
3389 int qc_completed;
3390
3391fsm_start:
3392 timeout = 0;
3393 qc_completed = 0;
1da177e4 3394
14be71f4
AL		 3395 switch (ap->hsm_task_state) {
3396 case HSM_ST_IDLE:
1da177e4
LT		 3397 return;
3398
14be71f4 3399 case HSM_ST:
1da177e4
LT		 3400 ata_pio_block(ap);
3401 break;
3402
14be71f4 3403 case HSM_ST_LAST:
7fb6ec28 3404 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3405 break;
3406
14be71f4
AL		 3407 case HSM_ST_POLL:
3408 case HSM_ST_LAST_POLL:
1da177e4
LT		 3409 timeout = ata_pio_poll(ap);
3410 break;
3411
14be71f4
AL		 3412 case HSM_ST_TMOUT:
3413 case HSM_ST_ERR:
1da177e4
LT		 3414 ata_pio_error(ap);
3415 return;
3416 }
3417
3418 if (timeout)
7fb6ec28
JG		 3419 queue_delayed_work(ata_wq, &ap->pio_task, timeout);
3420 else if (!qc_completed)
3421 goto fsm_start;
1da177e4
LT		 3422}
3423
1da177e4
LT		 3424/**
3425 * ata_qc_timeout - Handle timeout of queued command
3426 * @qc: Command that timed out
3427 *
3428 * Some part of the kernel (currently, only the SCSI layer)
3429 * has noticed that the active command on port @ap has not
3430 * completed after a specified length of time. Handle this
3431 * condition by disabling DMA (if necessary) and completing
3432 * transactions, with error if necessary.
3433 *
3434 * This also handles the case of the "lost interrupt", where
3435 * for some reason (possibly hardware bug, possibly driver bug)
3436 * an interrupt was not delivered to the driver, even though the
3437 * transaction completed successfully.
3438 *
3439 * LOCKING:
0cba632b 3440 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3441 */
3442
3443static void ata_qc_timeout(struct ata_queued_cmd *qc)
3444{
3445 struct ata_port *ap = qc->ap;
b8f6153e 3446 struct ata_host_set *host_set = ap->host_set;
1da177e4 3447 u8 host_stat = 0, drv_stat;
b8f6153e 3448 unsigned long flags;
1da177e4
LT		 3449
3450 DPRINTK("ENTER\n");
3451
b8f6153e
JG		 3452 spin_lock_irqsave(&host_set->lock, flags);
3453
1da177e4
LT		 3454 /* hack alert! We cannot use the supplied completion
3455 * function from inside the ->eh_strategy_handler() thread.
3456 * libata is the only user of ->eh_strategy_handler() in
3457 * any kernel, so the default scsi_done() assumes it is
3458 * not being called from the SCSI EH.
3459 */
3460 qc->scsidone = scsi_finish_command;
3461
3462 switch (qc->tf.protocol) {
3463
3464 case ATA_PROT_DMA:
3465 case ATA_PROT_ATAPI_DMA:
3466 host_stat = ap->ops->bmdma_status(ap);
3467
3468 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3469 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3470
3471 /* fall through */
3472
3473 default:
3474 ata_altstatus(ap);
3475 drv_stat = ata_chk_status(ap);
3476
3477 /* ack bmdma irq events */
3478 ap->ops->irq_clear(ap);
3479
3480 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3481 ap->id, qc->tf.command, drv_stat, host_stat);
3482
3483 /* complete taskfile transaction */
a22e2eb0
AL		 3484 qc->err_mask |= ac_err_mask(drv_stat);
3485 ata_qc_complete(qc);
1da177e4
LT		 3486 break;
3487 }
b8f6153e
JG		 3488
3489 spin_unlock_irqrestore(&host_set->lock, flags);
3490
1da177e4
LT		 3491 DPRINTK("EXIT\n");
3492}
3493
3494/**
3495 * ata_eng_timeout - Handle timeout of queued command
3496 * @ap: Port on which timed-out command is active
3497 *
3498 * Some part of the kernel (currently, only the SCSI layer)
3499 * has noticed that the active command on port @ap has not
3500 * completed after a specified length of time. Handle this
3501 * condition by disabling DMA (if necessary) and completing
3502 * transactions, with error if necessary.
3503 *
3504 * This also handles the case of the "lost interrupt", where
3505 * for some reason (possibly hardware bug, possibly driver bug)
3506 * an interrupt was not delivered to the driver, even though the
3507 * transaction completed successfully.
3508 *
3509 * LOCKING:
3510 * Inherited from SCSI layer (none, can sleep)
3511 */
3512
3513void ata_eng_timeout(struct ata_port *ap)
3514{
3515 struct ata_queued_cmd *qc;
3516
3517 DPRINTK("ENTER\n");
3518
3519 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3520 if (qc)
3521 ata_qc_timeout(qc);
3522 else {
1da177e4
LT		 3523 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3524 ap->id);
3525 goto out;
3526 }
3527
1da177e4
LT		 3528out:
3529 DPRINTK("EXIT\n");
3530}
3531
3532/**
3533 * ata_qc_new - Request an available ATA command, for queueing
3534 * @ap: Port associated with device @dev
3535 * @dev: Device from whom we request an available command structure
3536 *
3537 * LOCKING:
0cba632b 3538 * None.
1da177e4
LT		 3539 */
3540
3541static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3542{
3543 struct ata_queued_cmd *qc = NULL;
3544 unsigned int i;
3545
3546 for (i = 0; i < ATA_MAX_QUEUE; i++)
3547 if (!test_and_set_bit(i, &ap->qactive)) {
3548 qc = ata_qc_from_tag(ap, i);
3549 break;
3550 }
3551
3552 if (qc)
3553 qc->tag = i;
3554
3555 return qc;
3556}
3557
3558/**
3559 * ata_qc_new_init - Request an available ATA command, and initialize it
3560 * @ap: Port associated with device @dev
3561 * @dev: Device from whom we request an available command structure
3562 *
3563 * LOCKING:
0cba632b 3564 * None.
1da177e4
LT		 3565 */
3566
3567struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3568 struct ata_device *dev)
3569{
3570 struct ata_queued_cmd *qc;
3571
3572 qc = ata_qc_new(ap);
3573 if (qc) {
1da177e4
LT		 3574 qc->scsicmd = NULL;
3575 qc->ap = ap;
3576 qc->dev = dev;
1da177e4 3577
2c13b7ce 3578 ata_qc_reinit(qc);
1da177e4
LT		 3579 }
3580
3581 return qc;
3582}
3583
a22e2eb0 3584int ata_qc_complete_noop(struct ata_queued_cmd *qc)
1da177e4
LT		 3585{
3586 return 0;
3587}
3588
3589static void __ata_qc_complete(struct ata_queued_cmd *qc)
3590{
3591 struct ata_port *ap = qc->ap;
3592 unsigned int tag, do_clear = 0;
3593
3594 qc->flags = 0;
3595 tag = qc->tag;
3596 if (likely(ata_tag_valid(tag))) {
3597 if (tag == ap->active_tag)
3598 ap->active_tag = ATA_TAG_POISON;
3599 qc->tag = ATA_TAG_POISON;
3600 do_clear = 1;
3601 }
3602
3603 if (qc->waiting) {
3604 struct completion *waiting = qc->waiting;
3605 qc->waiting = NULL;
3606 complete(waiting);
3607 }
3608
3609 if (likely(do_clear))
3610 clear_bit(tag, &ap->qactive);
3611}
3612
3613/**
3614 * ata_qc_free - free unused ata_queued_cmd
3615 * @qc: Command to complete
3616 *
3617 * Designed to free unused ata_queued_cmd object
3618 * in case something prevents using it.
3619 *
3620 * LOCKING:
0cba632b 3621 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3622 */
3623void ata_qc_free(struct ata_queued_cmd *qc)
3624{
3625 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3626 assert(qc->waiting == NULL); /* nothing should be waiting */
3627
3628 __ata_qc_complete(qc);
3629}
3630
3631/**
3632 * ata_qc_complete - Complete an active ATA command
3633 * @qc: Command to complete
8e8b77dd 3634 * @err_mask: ATA Status register contents
0cba632b
JG		 3635 *
3636 * Indicate to the mid and upper layers that an ATA
3637 * command has completed, with either an ok or not-ok status.
1da177e4
LT		 3638 *
3639 * LOCKING:
0cba632b 3640 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3641 */
3642
a22e2eb0 3643void ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4
LT		 3644{
3645 int rc;
3646
3647 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3648 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3649
3650 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3651 ata_sg_clean(qc);
3652
3f3791d3
AL		 3653 /* atapi: mark qc as inactive to prevent the interrupt handler
3654 * from completing the command twice later, before the error handler
3655 * is called. (when rc != 0 and atapi request sense is needed)
3656 */
3657 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3658
1da177e4 3659 /* call completion callback */
a22e2eb0 3660 rc = qc->complete_fn(qc);
1da177e4
LT		 3661
3662 /* if callback indicates not to complete command (non-zero),
3663 * return immediately
3664 */
3665 if (rc != 0)
3666 return;
3667
3668 __ata_qc_complete(qc);
3669
3670 VPRINTK("EXIT\n");
3671}
3672
3673static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3674{
3675 struct ata_port *ap = qc->ap;
3676
3677 switch (qc->tf.protocol) {
3678 case ATA_PROT_DMA:
3679 case ATA_PROT_ATAPI_DMA:
3680 return 1;
3681
3682 case ATA_PROT_ATAPI:
3683 case ATA_PROT_PIO:
3684 case ATA_PROT_PIO_MULT:
3685 if (ap->flags & ATA_FLAG_PIO_DMA)
3686 return 1;
3687
3688 /* fall through */
3689
3690 default:
3691 return 0;
3692 }
3693
3694 /* never reached */
3695}
3696
3697/**
3698 * ata_qc_issue - issue taskfile to device
3699 * @qc: command to issue to device
3700 *
3701 * Prepare an ATA command to submission to device.
3702 * This includes mapping the data into a DMA-able
3703 * area, filling in the S/G table, and finally
3704 * writing the taskfile to hardware, starting the command.
3705 *
3706 * LOCKING:
3707 * spin_lock_irqsave(host_set lock)
3708 *
3709 * RETURNS:
3710 * Zero on success, negative on error.
3711 */
3712
3713int ata_qc_issue(struct ata_queued_cmd *qc)
3714{
3715 struct ata_port *ap = qc->ap;
3716
3717 if (ata_should_dma_map(qc)) {
3718 if (qc->flags & ATA_QCFLAG_SG) {
3719 if (ata_sg_setup(qc))
3720 goto err_out;
3721 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3722 if (ata_sg_setup_one(qc))
3723 goto err_out;
3724 }
3725 } else {
3726 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3727 }
3728
3729 ap->ops->qc_prep(qc);
3730
3731 qc->ap->active_tag = qc->tag;
3732 qc->flags |= ATA_QCFLAG_ACTIVE;
3733
3734 return ap->ops->qc_issue(qc);
3735
3736err_out:
3737 return -1;
3738}
3739
0baab86b 3740
1da177e4
LT		 3741/**
3742 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3743 * @qc: command to issue to device
3744 *
3745 * Using various libata functions and hooks, this function
3746 * starts an ATA command. ATA commands are grouped into
3747 * classes called "protocols", and issuing each type of protocol
3748 * is slightly different.
3749 *
0baab86b
EF		 3750 * May be used as the qc_issue() entry in ata_port_operations.
3751 *
1da177e4
LT		 3752 * LOCKING:
3753 * spin_lock_irqsave(host_set lock)
3754 *
3755 * RETURNS:
3756 * Zero on success, negative on error.
3757 */
3758
3759int ata_qc_issue_prot(struct ata_queued_cmd *qc)
3760{
3761 struct ata_port *ap = qc->ap;
3762
3763 ata_dev_select(ap, qc->dev->devno, 1, 0);
3764
3765 switch (qc->tf.protocol) {
3766 case ATA_PROT_NODATA:
e5338254 3767 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3768 break;
3769
3770 case ATA_PROT_DMA:
3771 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3772 ap->ops->bmdma_setup(qc); /* set up bmdma */
3773 ap->ops->bmdma_start(qc); /* initiate bmdma */
3774 break;
3775
3776 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3777 ata_qc_set_polling(qc);
e5338254 3778 ata_tf_to_host(ap, &qc->tf);
14be71f4 3779 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 3780 queue_work(ata_wq, &ap->pio_task);
3781 break;
3782
3783 case ATA_PROT_ATAPI:
3784 ata_qc_set_polling(qc);
e5338254 3785 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3786 queue_work(ata_wq, &ap->packet_task);
3787 break;
3788
3789 case ATA_PROT_ATAPI_NODATA:
c1389503 3790 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3791 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3792 queue_work(ata_wq, &ap->packet_task);
3793 break;
3794
3795 case ATA_PROT_ATAPI_DMA:
c1389503 3796 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3797 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3798 ap->ops->bmdma_setup(qc); /* set up bmdma */
3799 queue_work(ata_wq, &ap->packet_task);
3800 break;
3801
3802 default:
3803 WARN_ON(1);
3804 return -1;
3805 }
3806
3807 return 0;
3808}
3809
3810/**
0baab86b 3811 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3812 * @qc: Info associated with this ATA transaction.
3813 *
3814 * LOCKING:
3815 * spin_lock_irqsave(host_set lock)
3816 */
3817
3818static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3819{
3820 struct ata_port *ap = qc->ap;
3821 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3822 u8 dmactl;
3823 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3824
3825 /* load PRD table addr. */
3826 mb(); /* make sure PRD table writes are visible to controller */
3827 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3828
3829 /* specify data direction, triple-check start bit is clear */
3830 dmactl = readb(mmio + ATA_DMA_CMD);
3831 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3832 if (!rw)
3833 dmactl |= ATA_DMA_WR;
3834 writeb(dmactl, mmio + ATA_DMA_CMD);
3835
3836 /* issue r/w command */
3837 ap->ops->exec_command(ap, &qc->tf);
3838}
3839
3840/**
b73fc89f 3841 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3842 * @qc: Info associated with this ATA transaction.
3843 *
3844 * LOCKING:
3845 * spin_lock_irqsave(host_set lock)
3846 */
3847
3848static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3849{
3850 struct ata_port *ap = qc->ap;
3851 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3852 u8 dmactl;
3853
3854 /* start host DMA transaction */
3855 dmactl = readb(mmio + ATA_DMA_CMD);
3856 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3857
3858 /* Strictly, one may wish to issue a readb() here, to
3859 * flush the mmio write. However, control also passes
3860 * to the hardware at this point, and it will interrupt
3861 * us when we are to resume control. So, in effect,
3862 * we don't care when the mmio write flushes.
3863 * Further, a read of the DMA status register _immediately_
3864 * following the write may not be what certain flaky hardware
3865 * is expected, so I think it is best to not add a readb()
3866 * without first all the MMIO ATA cards/mobos.
3867 * Or maybe I'm just being paranoid.
3868 */
3869}
3870
3871/**
3872 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3873 * @qc: Info associated with this ATA transaction.
3874 *
3875 * LOCKING:
3876 * spin_lock_irqsave(host_set lock)
3877 */
3878
3879static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3880{
3881 struct ata_port *ap = qc->ap;
3882 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3883 u8 dmactl;
3884
3885 /* load PRD table addr. */
3886 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3887
3888 /* specify data direction, triple-check start bit is clear */
3889 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3890 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3891 if (!rw)
3892 dmactl |= ATA_DMA_WR;
3893 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3894
3895 /* issue r/w command */
3896 ap->ops->exec_command(ap, &qc->tf);
3897}
3898
3899/**
3900 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3901 * @qc: Info associated with this ATA transaction.
3902 *
3903 * LOCKING:
3904 * spin_lock_irqsave(host_set lock)
3905 */
3906
3907static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3908{
3909 struct ata_port *ap = qc->ap;
3910 u8 dmactl;
3911
3912 /* start host DMA transaction */
3913 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3914 outb(dmactl | ATA_DMA_START,
3915 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3916}
3917
0baab86b
EF		 3918
3919/**
3920 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3921 * @qc: Info associated with this ATA transaction.
3922 *
3923 * Writes the ATA_DMA_START flag to the DMA command register.
3924 *
3925 * May be used as the bmdma_start() entry in ata_port_operations.
3926 *
3927 * LOCKING:
3928 * spin_lock_irqsave(host_set lock)
3929 */
1da177e4
LT		 3930void ata_bmdma_start(struct ata_queued_cmd *qc)
3931{
3932 if (qc->ap->flags & ATA_FLAG_MMIO)
3933 ata_bmdma_start_mmio(qc);
3934 else
3935 ata_bmdma_start_pio(qc);
3936}
3937
0baab86b
EF		 3938
3939/**
3940 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3941 * @qc: Info associated with this ATA transaction.
3942 *
3943 * Writes address of PRD table to device's PRD Table Address
3944 * register, sets the DMA control register, and calls
3945 * ops->exec_command() to start the transfer.
3946 *
3947 * May be used as the bmdma_setup() entry in ata_port_operations.
3948 *
3949 * LOCKING:
3950 * spin_lock_irqsave(host_set lock)
3951 */
1da177e4
LT		 3952void ata_bmdma_setup(struct ata_queued_cmd *qc)
3953{
3954 if (qc->ap->flags & ATA_FLAG_MMIO)
3955 ata_bmdma_setup_mmio(qc);
3956 else
3957 ata_bmdma_setup_pio(qc);
3958}
3959
0baab86b
EF		 3960
3961/**
3962 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3963 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3964 *
3965 * Clear interrupt and error flags in DMA status register.
3966 *
3967 * May be used as the irq_clear() entry in ata_port_operations.
3968 *
3969 * LOCKING:
3970 * spin_lock_irqsave(host_set lock)
3971 */
3972
1da177e4
LT		 3973void ata_bmdma_irq_clear(struct ata_port *ap)
3974{
3975 if (ap->flags & ATA_FLAG_MMIO) {
3976 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3977 writeb(readb(mmio), mmio);
3978 } else {
3979 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3980 outb(inb(addr), addr);
3981 }
3982
3983}
3984
0baab86b
EF		 3985
3986/**
3987 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3988 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3989 *
3990 * Read and return BMDMA status register.
3991 *
3992 * May be used as the bmdma_status() entry in ata_port_operations.
3993 *
3994 * LOCKING:
3995 * spin_lock_irqsave(host_set lock)
3996 */
3997
1da177e4
LT		 3998u8 ata_bmdma_status(struct ata_port *ap)
3999{
4000 u8 host_stat;
4001 if (ap->flags & ATA_FLAG_MMIO) {
4002 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4003 host_stat = readb(mmio + ATA_DMA_STATUS);
4004 } else
ee500aab 4005 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 4006 return host_stat;
4007}
4008
0baab86b
EF		 4009
4010/**
4011 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4012 * @qc: Command we are ending DMA for
0baab86b
EF		 4013 *
4014 * Clears the ATA_DMA_START flag in the dma control register
4015 *
4016 * May be used as the bmdma_stop() entry in ata_port_operations.
4017 *
4018 * LOCKING:
4019 * spin_lock_irqsave(host_set lock)
4020 */
4021
b73fc89f 4022void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4023{
b73fc89f 4024 struct ata_port *ap = qc->ap;
1da177e4
LT		 4025 if (ap->flags & ATA_FLAG_MMIO) {
4026 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4027
4028 /* clear start/stop bit */
4029 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4030 mmio + ATA_DMA_CMD);
4031 } else {
4032 /* clear start/stop bit */
4033 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4034 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4035 }
4036
4037 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4038 ata_altstatus(ap); /* dummy read */
4039}
4040
4041/**
4042 * ata_host_intr - Handle host interrupt for given (port, task)
4043 * @ap: Port on which interrupt arrived (possibly...)
4044 * @qc: Taskfile currently active in engine
4045 *
4046 * Handle host interrupt for given queued command. Currently,
4047 * only DMA interrupts are handled. All other commands are
4048 * handled via polling with interrupts disabled (nIEN bit).
4049 *
4050 * LOCKING:
4051 * spin_lock_irqsave(host_set lock)
4052 *
4053 * RETURNS:
4054 * One if interrupt was handled, zero if not (shared irq).
4055 */
4056
4057inline unsigned int ata_host_intr (struct ata_port *ap,
4058 struct ata_queued_cmd *qc)
4059{
4060 u8 status, host_stat;
4061
4062 switch (qc->tf.protocol) {
4063
4064 case ATA_PROT_DMA:
4065 case ATA_PROT_ATAPI_DMA:
4066 case ATA_PROT_ATAPI:
4067 /* check status of DMA engine */
4068 host_stat = ap->ops->bmdma_status(ap);
4069 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4070
4071 /* if it's not our irq... */
4072 if (!(host_stat & ATA_DMA_INTR))
4073 goto idle_irq;
4074
4075 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4076 ap->ops->bmdma_stop(qc);
1da177e4
LT		 4077
4078 /* fall through */
4079
4080 case ATA_PROT_ATAPI_NODATA:
4081 case ATA_PROT_NODATA:
4082 /* check altstatus */
4083 status = ata_altstatus(ap);
4084 if (status & ATA_BUSY)
4085 goto idle_irq;
4086
4087 /* check main status, clearing INTRQ */
4088 status = ata_chk_status(ap);
4089 if (unlikely(status & ATA_BUSY))
4090 goto idle_irq;
4091 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4092 ap->id, qc->tf.protocol, status);
4093
4094 /* ack bmdma irq events */
4095 ap->ops->irq_clear(ap);
4096
4097 /* complete taskfile transaction */
a22e2eb0
AL		 4098 qc->err_mask |= ac_err_mask(status);
4099 ata_qc_complete(qc);
1da177e4
LT		 4100 break;
4101
4102 default:
4103 goto idle_irq;
4104 }
4105
4106 return 1; /* irq handled */
4107
4108idle_irq:
4109 ap->stats.idle_irq++;
4110
4111#ifdef ATA_IRQ_TRAP
4112 if ((ap->stats.idle_irq % 1000) == 0) {
4113 handled = 1;
4114 ata_irq_ack(ap, 0); /* debug trap */
4115 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4116 }
4117#endif
4118 return 0; /* irq not handled */
4119}
4120
4121/**
4122 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4123 * @irq: irq line (unused)
4124 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4125 * @regs: unused
4126 *
0cba632b
JG		 4127 * Default interrupt handler for PCI IDE devices. Calls
4128 * ata_host_intr() for each port that is not disabled.
4129 *
1da177e4 4130 * LOCKING:
0cba632b 4131 * Obtains host_set lock during operation.
1da177e4
LT		 4132 *
4133 * RETURNS:
0cba632b 4134 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4135 */
4136
4137irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4138{
4139 struct ata_host_set *host_set = dev_instance;
4140 unsigned int i;
4141 unsigned int handled = 0;
4142 unsigned long flags;
4143
4144 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4145 spin_lock_irqsave(&host_set->lock, flags);
4146
4147 for (i = 0; i < host_set->n_ports; i++) {
4148 struct ata_port *ap;
4149
4150 ap = host_set->ports[i];
c1389503
TH		 4151 if (ap &&
4152 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4153 struct ata_queued_cmd *qc;
4154
4155 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4156 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4157 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4158 handled |= ata_host_intr(ap, qc);
4159 }
4160 }
4161
4162 spin_unlock_irqrestore(&host_set->lock, flags);
4163
4164 return IRQ_RETVAL(handled);
4165}
4166
4167/**
4168 * atapi_packet_task - Write CDB bytes to hardware
4169 * @_data: Port to which ATAPI device is attached.
4170 *
4171 * When device has indicated its readiness to accept
4172 * a CDB, this function is called. Send the CDB.
4173 * If DMA is to be performed, exit immediately.
4174 * Otherwise, we are in polling mode, so poll
4175 * status under operation succeeds or fails.
4176 *
4177 * LOCKING:
4178 * Kernel thread context (may sleep)
4179 */
4180
4181static void atapi_packet_task(void *_data)
4182{
4183 struct ata_port *ap = _data;
4184 struct ata_queued_cmd *qc;
4185 u8 status;
4186
4187 qc = ata_qc_from_tag(ap, ap->active_tag);
4188 assert(qc != NULL);
4189 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4190
4191 /* sleep-wait for BSY to clear */
4192 DPRINTK("busy wait\n");
d8fe452b
AL		 4193 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
4194 qc->err_mask |= AC_ERR_ATA_BUS;
4195 goto err_out;
4196 }
1da177e4
LT		 4197
4198 /* make sure DRQ is set */
4199 status = ata_chk_status(ap);
d8fe452b
AL		 4200 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
4201 qc->err_mask |= AC_ERR_ATA_BUS;
1da177e4 4202 goto err_out;
d8fe452b 4203 }
1da177e4
LT		 4204
4205 /* send SCSI cdb */
4206 DPRINTK("send cdb\n");
4207 assert(ap->cdb_len >= 12);
1da177e4 4208
c1389503
TH		 4209 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4210 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4211 unsigned long flags;
1da177e4 4212
c1389503
TH		 4213 /* Once we're done issuing command and kicking bmdma,
4214 * irq handler takes over. To not lose irq, we need
4215 * to clear NOINTR flag before sending cdb, but
4216 * interrupt handler shouldn't be invoked before we're
4217 * finished. Hence, the following locking.
4218 */
4219 spin_lock_irqsave(&ap->host_set->lock, flags);
4220 ap->flags &= ~ATA_FLAG_NOINTR;
4221 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4222 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4223 ap->ops->bmdma_start(qc); /* initiate bmdma */
4224 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4225 } else {
4226 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4227
c1389503 4228 /* PIO commands are handled by polling */
14be71f4 4229 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 4230 queue_work(ata_wq, &ap->pio_task);
4231 }
4232
4233 return;
4234
4235err_out:
a22e2eb0 4236 ata_poll_qc_complete(qc);
1da177e4
LT		 4237}
4238
0baab86b
EF		 4239
4240/**
4241 * ata_port_start - Set port up for dma.
4242 * @ap: Port to initialize
4243 *
4244 * Called just after data structures for each port are
4245 * initialized. Allocates space for PRD table.
4246 *
4247 * May be used as the port_start() entry in ata_port_operations.
4248 *
4249 * LOCKING:
6f0ef4fa 4250 * Inherited from caller.
0baab86b
EF		 4251 */
4252
1da177e4
LT		 4253int ata_port_start (struct ata_port *ap)
4254{
4255 struct device *dev = ap->host_set->dev;
6037d6bb 4256 int rc;
1da177e4
LT		 4257
4258 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4259 if (!ap->prd)
4260 return -ENOMEM;
4261
6037d6bb
JG		 4262 rc = ata_pad_alloc(ap, dev);
4263 if (rc) {
cedc9a47 4264 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4265 return rc;
cedc9a47
JG		 4266 }
4267
1da177e4
LT		 4268 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4269
4270 return 0;
4271}
4272
0baab86b
EF		 4273
4274/**
4275 * ata_port_stop - Undo ata_port_start()
4276 * @ap: Port to shut down
4277 *
4278 * Frees the PRD table.
4279 *
4280 * May be used as the port_stop() entry in ata_port_operations.
4281 *
4282 * LOCKING:
6f0ef4fa 4283 * Inherited from caller.
0baab86b
EF		 4284 */
4285
1da177e4
LT		 4286void ata_port_stop (struct ata_port *ap)
4287{
4288 struct device *dev = ap->host_set->dev;
4289
4290 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4291 ata_pad_free(ap, dev);
1da177e4
LT		 4292}
4293
aa8f0dc6
JG		 4294void ata_host_stop (struct ata_host_set *host_set)
4295{
4296 if (host_set->mmio_base)
4297 iounmap(host_set->mmio_base);
4298}
4299
4300
1da177e4
LT		 4301/**
4302 * ata_host_remove - Unregister SCSI host structure with upper layers
4303 * @ap: Port to unregister
4304 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4305 *
4306 * LOCKING:
6f0ef4fa 4307 * Inherited from caller.
1da177e4
LT		 4308 */
4309
4310static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4311{
4312 struct Scsi_Host *sh = ap->host;
4313
4314 DPRINTK("ENTER\n");
4315
4316 if (do_unregister)
4317 scsi_remove_host(sh);
4318
4319 ap->ops->port_stop(ap);
4320}
4321
4322/**
4323 * ata_host_init - Initialize an ata_port structure
4324 * @ap: Structure to initialize
4325 * @host: associated SCSI mid-layer structure
4326 * @host_set: Collection of hosts to which @ap belongs
4327 * @ent: Probe information provided by low-level driver
4328 * @port_no: Port number associated with this ata_port
4329 *
0cba632b
JG		 4330 * Initialize a new ata_port structure, and its associated
4331 * scsi_host.
4332 *
1da177e4 4333 * LOCKING:
0cba632b 4334 * Inherited from caller.
1da177e4
LT		 4335 */
4336
4337static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4338 struct ata_host_set *host_set,
057ace5e 4339 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4340{
4341 unsigned int i;
4342
4343 host->max_id = 16;
4344 host->max_lun = 1;
4345 host->max_channel = 1;
4346 host->unique_id = ata_unique_id++;
4347 host->max_cmd_len = 12;
12413197 4348
1da177e4
LT		 4349 ap->flags = ATA_FLAG_PORT_DISABLED;
4350 ap->id = host->unique_id;
4351 ap->host = host;
4352 ap->ctl = ATA_DEVCTL_OBS;
4353 ap->host_set = host_set;
4354 ap->port_no = port_no;
4355 ap->hard_port_no =
4356 ent->legacy_mode ? ent->hard_port_no : port_no;
4357 ap->pio_mask = ent->pio_mask;
4358 ap->mwdma_mask = ent->mwdma_mask;
4359 ap->udma_mask = ent->udma_mask;
4360 ap->flags |= ent->host_flags;
4361 ap->ops = ent->port_ops;
4362 ap->cbl = ATA_CBL_NONE;
4363 ap->active_tag = ATA_TAG_POISON;
4364 ap->last_ctl = 0xFF;
4365
4366 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4367 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
4368
4369 for (i = 0; i < ATA_MAX_DEVICES; i++)
4370 ap->device[i].devno = i;
4371
4372#ifdef ATA_IRQ_TRAP
4373 ap->stats.unhandled_irq = 1;
4374 ap->stats.idle_irq = 1;
4375#endif
4376
4377 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4378}
4379
4380/**
4381 * ata_host_add - Attach low-level ATA driver to system
4382 * @ent: Information provided by low-level driver
4383 * @host_set: Collections of ports to which we add
4384 * @port_no: Port number associated with this host
4385 *
0cba632b
JG		 4386 * Attach low-level ATA driver to system.
4387 *
1da177e4 4388 * LOCKING:
0cba632b 4389 * PCI/etc. bus probe sem.
1da177e4
LT		 4390 *
4391 * RETURNS:
0cba632b 4392 * New ata_port on success, for NULL on error.
1da177e4
LT		 4393 */
4394
057ace5e 4395static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4396 struct ata_host_set *host_set,
4397 unsigned int port_no)
4398{
4399 struct Scsi_Host *host;
4400 struct ata_port *ap;
4401 int rc;
4402
4403 DPRINTK("ENTER\n");
4404 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4405 if (!host)
4406 return NULL;
4407
4408 ap = (struct ata_port *) &host->hostdata[0];
4409
4410 ata_host_init(ap, host, host_set, ent, port_no);
4411
4412 rc = ap->ops->port_start(ap);
4413 if (rc)
4414 goto err_out;
4415
4416 return ap;
4417
4418err_out:
4419 scsi_host_put(host);
4420 return NULL;
4421}
4422
4423/**
0cba632b
JG		 4424 * ata_device_add - Register hardware device with ATA and SCSI layers
4425 * @ent: Probe information describing hardware device to be registered
4426 *
4427 * This function processes the information provided in the probe
4428 * information struct @ent, allocates the necessary ATA and SCSI
4429 * host information structures, initializes them, and registers
4430 * everything with requisite kernel subsystems.
4431 *
4432 * This function requests irqs, probes the ATA bus, and probes
4433 * the SCSI bus.
1da177e4
LT		 4434 *
4435 * LOCKING:
0cba632b 4436 * PCI/etc. bus probe sem.
1da177e4
LT		 4437 *
4438 * RETURNS:
0cba632b 4439 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4440 */
4441
057ace5e 4442int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4443{
4444 unsigned int count = 0, i;
4445 struct device *dev = ent->dev;
4446 struct ata_host_set *host_set;
4447
4448 DPRINTK("ENTER\n");
4449 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4450 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4451 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4452 if (!host_set)
4453 return 0;
1da177e4
LT		 4454 spin_lock_init(&host_set->lock);
4455
4456 host_set->dev = dev;
4457 host_set->n_ports = ent->n_ports;
4458 host_set->irq = ent->irq;
4459 host_set->mmio_base = ent->mmio_base;
4460 host_set->private_data = ent->private_data;
4461 host_set->ops = ent->port_ops;
4462
4463 /* register each port bound to this device */
4464 for (i = 0; i < ent->n_ports; i++) {
4465 struct ata_port *ap;
4466 unsigned long xfer_mode_mask;
4467
4468 ap = ata_host_add(ent, host_set, i);
4469 if (!ap)
4470 goto err_out;
4471
4472 host_set->ports[i] = ap;
4473 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4474 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4475 (ap->pio_mask << ATA_SHIFT_PIO);
4476
4477 /* print per-port info to dmesg */
4478 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4479 "bmdma 0x%lX irq %lu\n",
4480 ap->id,
4481 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4482 ata_mode_string(xfer_mode_mask),
4483 ap->ioaddr.cmd_addr,
4484 ap->ioaddr.ctl_addr,
4485 ap->ioaddr.bmdma_addr,
4486 ent->irq);
4487
4488 ata_chk_status(ap);
4489 host_set->ops->irq_clear(ap);
4490 count++;
4491 }
4492
57f3bda8
RD		 4493 if (!count)
4494 goto err_free_ret;
1da177e4
LT		 4495
4496 /* obtain irq, that is shared between channels */
4497 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4498 DRV_NAME, host_set))
4499 goto err_out;
4500
4501 /* perform each probe synchronously */
4502 DPRINTK("probe begin\n");
4503 for (i = 0; i < count; i++) {
4504 struct ata_port *ap;
4505 int rc;
4506
4507 ap = host_set->ports[i];
4508
4509 DPRINTK("ata%u: probe begin\n", ap->id);
4510 rc = ata_bus_probe(ap);
4511 DPRINTK("ata%u: probe end\n", ap->id);
4512
4513 if (rc) {
4514 /* FIXME: do something useful here?
4515 * Current libata behavior will
4516 * tear down everything when
4517 * the module is removed
4518 * or the h/w is unplugged.
4519 */
4520 }
4521
4522 rc = scsi_add_host(ap->host, dev);
4523 if (rc) {
4524 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4525 ap->id);
4526 /* FIXME: do something useful here */
4527 /* FIXME: handle unconditional calls to
4528 * scsi_scan_host and ata_host_remove, below,
4529 * at the very least
4530 */
4531 }
4532 }
4533
4534 /* probes are done, now scan each port's disk(s) */
4535 DPRINTK("probe begin\n");
4536 for (i = 0; i < count; i++) {
4537 struct ata_port *ap = host_set->ports[i];
4538
644dd0cc 4539 ata_scsi_scan_host(ap);
1da177e4
LT		 4540 }
4541
4542 dev_set_drvdata(dev, host_set);
4543
4544 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4545 return ent->n_ports; /* success */
4546
4547err_out:
4548 for (i = 0; i < count; i++) {
4549 ata_host_remove(host_set->ports[i], 1);
4550 scsi_host_put(host_set->ports[i]->host);
4551 }
57f3bda8 4552err_free_ret:
1da177e4
LT		 4553 kfree(host_set);
4554 VPRINTK("EXIT, returning 0\n");
4555 return 0;
4556}
4557
17b14451
AC		 4558/**
4559 * ata_host_set_remove - PCI layer callback for device removal
4560 * @host_set: ATA host set that was removed
4561 *
4562 * Unregister all objects associated with this host set. Free those
4563 * objects.
4564 *
4565 * LOCKING:
4566 * Inherited from calling layer (may sleep).
4567 */
4568
17b14451
AC		 4569void ata_host_set_remove(struct ata_host_set *host_set)
4570{
4571 struct ata_port *ap;
4572 unsigned int i;
4573
4574 for (i = 0; i < host_set->n_ports; i++) {
4575 ap = host_set->ports[i];
4576 scsi_remove_host(ap->host);
4577 }
4578
4579 free_irq(host_set->irq, host_set);
4580
4581 for (i = 0; i < host_set->n_ports; i++) {
4582 ap = host_set->ports[i];
4583
4584 ata_scsi_release(ap->host);
4585
4586 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4587 struct ata_ioports *ioaddr = &ap->ioaddr;
4588
4589 if (ioaddr->cmd_addr == 0x1f0)
4590 release_region(0x1f0, 8);
4591 else if (ioaddr->cmd_addr == 0x170)
4592 release_region(0x170, 8);
4593 }
4594
4595 scsi_host_put(ap->host);
4596 }
4597
4598 if (host_set->ops->host_stop)
4599 host_set->ops->host_stop(host_set);
4600
4601 kfree(host_set);
4602}
4603
1da177e4
LT		 4604/**
4605 * ata_scsi_release - SCSI layer callback hook for host unload
4606 * @host: libata host to be unloaded
4607 *
4608 * Performs all duties necessary to shut down a libata port...
4609 * Kill port kthread, disable port, and release resources.
4610 *
4611 * LOCKING:
4612 * Inherited from SCSI layer.
4613 *
4614 * RETURNS:
4615 * One.
4616 */
4617
4618int ata_scsi_release(struct Scsi_Host *host)
4619{
4620 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4621
4622 DPRINTK("ENTER\n");
4623
4624 ap->ops->port_disable(ap);
4625 ata_host_remove(ap, 0);
4626
4627 DPRINTK("EXIT\n");
4628 return 1;
4629}
4630
4631/**
4632 * ata_std_ports - initialize ioaddr with standard port offsets.
4633 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4634 *
4635 * Utility function which initializes data_addr, error_addr,
4636 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4637 * device_addr, status_addr, and command_addr to standard offsets
4638 * relative to cmd_addr.
4639 *
4640 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4641 */
0baab86b 4642
1da177e4
LT		 4643void ata_std_ports(struct ata_ioports *ioaddr)
4644{
4645 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4646 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4647 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4648 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4649 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4650 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4651 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4652 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4653 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4654 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4655}
4656
4657static struct ata_probe_ent *
057ace5e 4658ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT		 4659{
4660 struct ata_probe_ent *probe_ent;
4661
57f3bda8 4662 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT		 4663 if (!probe_ent) {
4664 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
4665 kobject_name(&(dev->kobj)));
4666 return NULL;
4667 }
4668
1da177e4
LT		 4669 INIT_LIST_HEAD(&probe_ent->node);
4670 probe_ent->dev = dev;
4671
4672 probe_ent->sht = port->sht;
4673 probe_ent->host_flags = port->host_flags;
4674 probe_ent->pio_mask = port->pio_mask;
4675 probe_ent->mwdma_mask = port->mwdma_mask;
4676 probe_ent->udma_mask = port->udma_mask;
4677 probe_ent->port_ops = port->port_ops;
4678
4679 return probe_ent;
4680}
4681
0baab86b
EF		 4682
4683
374b1873
JG		 4684#ifdef CONFIG_PCI
4685
4686void ata_pci_host_stop (struct ata_host_set *host_set)
4687{
4688 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4689
4690 pci_iounmap(pdev, host_set->mmio_base);
4691}
4692
0baab86b
EF		 4693/**
4694 * ata_pci_init_native_mode - Initialize native-mode driver
4695 * @pdev: pci device to be initialized
4696 * @port: array[2] of pointers to port info structures.
47a86593 4697 * @ports: bitmap of ports present
0baab86b
EF		 4698 *
4699 * Utility function which allocates and initializes an
4700 * ata_probe_ent structure for a standard dual-port
4701 * PIO-based IDE controller. The returned ata_probe_ent
4702 * structure can be passed to ata_device_add(). The returned
4703 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC		 4704 *
4705 * The caller need only pass the address of the primary port, the
4706 * secondary will be deduced automatically. If the device has non
4707 * standard secondary port mappings this function can be called twice,
4708 * once for each interface.
0baab86b
EF		 4709 */
4710
1da177e4 4711struct ata_probe_ent *
47a86593 4712ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT		 4713{
4714 struct ata_probe_ent *probe_ent =
4715 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC		 4716 int p = 0;
4717
1da177e4
LT		 4718 if (!probe_ent)
4719 return NULL;
4720
1da177e4
LT		 4721 probe_ent->irq = pdev->irq;
4722 probe_ent->irq_flags = SA_SHIRQ;
e99f8b5e 4723 probe_ent->private_data = port[0]->private_data;
1da177e4 4724
47a86593
AC		 4725 if (ports & ATA_PORT_PRIMARY) {
4726 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
4727 probe_ent->port[p].altstatus_addr =
4728 probe_ent->port[p].ctl_addr =
4729 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
4730 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
4731 ata_std_ports(&probe_ent->port[p]);
4732 p++;
4733 }
1da177e4 4734
47a86593
AC		 4735 if (ports & ATA_PORT_SECONDARY) {
4736 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
4737 probe_ent->port[p].altstatus_addr =
4738 probe_ent->port[p].ctl_addr =
4739 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
4740 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
4741 ata_std_ports(&probe_ent->port[p]);
4742 p++;
4743 }
1da177e4 4744
47a86593 4745 probe_ent->n_ports = p;
1da177e4
LT		 4746 return probe_ent;
4747}
4748
0f0d5192 4749static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 4750{
47a86593 4751 struct ata_probe_ent *probe_ent;
1da177e4 4752
0f0d5192 4753 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT		 4754 if (!probe_ent)
4755 return NULL;
1da177e4 4756
1da177e4 4757 probe_ent->legacy_mode = 1;
47a86593
AC		 4758 probe_ent->n_ports = 1;
4759 probe_ent->hard_port_no = port_num;
e99f8b5e 4760 probe_ent->private_data = port->private_data;
47a86593
AC		 4761
4762 switch(port_num)
4763 {
4764 case 0:
4765 probe_ent->irq = 14;
4766 probe_ent->port[0].cmd_addr = 0x1f0;
4767 probe_ent->port[0].altstatus_addr =
4768 probe_ent->port[0].ctl_addr = 0x3f6;
4769 break;
4770 case 1:
4771 probe_ent->irq = 15;
4772 probe_ent->port[0].cmd_addr = 0x170;
4773 probe_ent->port[0].altstatus_addr =
4774 probe_ent->port[0].ctl_addr = 0x376;
4775 break;
4776 }
4777 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 4778 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT		 4779 return probe_ent;
4780}
4781
4782/**
4783 * ata_pci_init_one - Initialize/register PCI IDE host controller
4784 * @pdev: Controller to be initialized
4785 * @port_info: Information from low-level host driver
4786 * @n_ports: Number of ports attached to host controller
4787 *
0baab86b
EF		 4788 * This is a helper function which can be called from a driver's
4789 * xxx_init_one() probe function if the hardware uses traditional
4790 * IDE taskfile registers.
4791 *
4792 * This function calls pci_enable_device(), reserves its register
4793 * regions, sets the dma mask, enables bus master mode, and calls
4794 * ata_device_add()
4795 *
1da177e4
LT		 4796 * LOCKING:
4797 * Inherited from PCI layer (may sleep).
4798 *
4799 * RETURNS:
0cba632b 4800 * Zero on success, negative on errno-based value on error.
1da177e4
LT		 4801 */
4802
4803int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
4804 unsigned int n_ports)
4805{
47a86593 4806 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT		 4807 struct ata_port_info *port[2];
4808 u8 tmp8, mask;
4809 unsigned int legacy_mode = 0;
4810 int disable_dev_on_err = 1;
4811 int rc;
4812
4813 DPRINTK("ENTER\n");
4814
4815 port[0] = port_info[0];
4816 if (n_ports > 1)
4817 port[1] = port_info[1];
4818 else
4819 port[1] = port[0];
4820
4821 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
4822 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 4823 /* TODO: What if one channel is in native mode ... */
1da177e4
LT		 4824 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
4825 mask = (1 << 2) | (1 << 0);
4826 if ((tmp8 & mask) != mask)
4827 legacy_mode = (1 << 3);
4828 }
4829
4830 /* FIXME... */
47a86593
AC		 4831 if ((!legacy_mode) && (n_ports > 2)) {
4832 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
4833 n_ports = 2;
4834 /* For now */
1da177e4
LT		 4835 }
4836
47a86593
AC		 4837 /* FIXME: Really for ATA it isn't safe because the device may be
4838 multi-purpose and we want to leave it alone if it was already
4839 enabled. Secondly for shared use as Arjan says we want refcounting
4840
4841 Checking dev->is_enabled is insufficient as this is not set at
4842 boot for the primary video which is BIOS enabled
4843 */
4844
1da177e4
LT		 4845 rc = pci_enable_device(pdev);
4846 if (rc)
4847 return rc;
4848
4849 rc = pci_request_regions(pdev, DRV_NAME);
4850 if (rc) {
4851 disable_dev_on_err = 0;
4852 goto err_out;
4853 }
4854
47a86593 4855 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT		 4856 if (legacy_mode) {
4857 if (!request_region(0x1f0, 8, "libata")) {
4858 struct resource *conflict, res;
4859 res.start = 0x1f0;
4860 res.end = 0x1f0 + 8 - 1;
4861 conflict = ____request_resource(&ioport_resource, &res);
4862 if (!strcmp(conflict->name, "libata"))
4863 legacy_mode |= (1 << 0);
4864 else {
4865 disable_dev_on_err = 0;
4866 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
4867 }
4868 } else
4869 legacy_mode |= (1 << 0);
4870
4871 if (!request_region(0x170, 8, "libata")) {
4872 struct resource *conflict, res;
4873 res.start = 0x170;
4874 res.end = 0x170 + 8 - 1;
4875 conflict = ____request_resource(&ioport_resource, &res);
4876 if (!strcmp(conflict->name, "libata"))
4877 legacy_mode |= (1 << 1);
4878 else {
4879 disable_dev_on_err = 0;
4880 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
4881 }
4882 } else
4883 legacy_mode |= (1 << 1);
4884 }
4885
4886 /* we have legacy mode, but all ports are unavailable */
4887 if (legacy_mode == (1 << 3)) {
4888 rc = -EBUSY;
4889 goto err_out_regions;
4890 }
4891
4892 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
4893 if (rc)
4894 goto err_out_regions;
4895 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
4896 if (rc)
4897 goto err_out_regions;
4898
4899 if (legacy_mode) {
47a86593 4900 if (legacy_mode & (1 << 0))
0f0d5192 4901 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 4902 if (legacy_mode & (1 << 1))
0f0d5192 4903 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC		 4904 } else {
4905 if (n_ports == 2)
4906 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
4907 else
4908 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
4909 }
4910 if (!probe_ent && !probe_ent2) {
1da177e4
LT		 4911 rc = -ENOMEM;
4912 goto err_out_regions;
4913 }
4914
4915 pci_set_master(pdev);
4916
4917 /* FIXME: check ata_device_add return */
4918 if (legacy_mode) {
4919 if (legacy_mode & (1 << 0))
4920 ata_device_add(probe_ent);
4921 if (legacy_mode & (1 << 1))
4922 ata_device_add(probe_ent2);
4923 } else
4924 ata_device_add(probe_ent);
4925
4926 kfree(probe_ent);
4927 kfree(probe_ent2);
4928
4929 return 0;
4930
4931err_out_regions:
4932 if (legacy_mode & (1 << 0))
4933 release_region(0x1f0, 8);
4934 if (legacy_mode & (1 << 1))
4935 release_region(0x170, 8);
4936 pci_release_regions(pdev);
4937err_out:
4938 if (disable_dev_on_err)
4939 pci_disable_device(pdev);
4940 return rc;
4941}
4942
4943/**
4944 * ata_pci_remove_one - PCI layer callback for device removal
4945 * @pdev: PCI device that was removed
4946 *
4947 * PCI layer indicates to libata via this hook that
6f0ef4fa 4948 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4949 * Handle this by unregistering all objects associated
4950 * with this PCI device. Free those objects. Then finally
4951 * release PCI resources and disable device.
4952 *
4953 * LOCKING:
4954 * Inherited from PCI layer (may sleep).
4955 */
4956
4957void ata_pci_remove_one (struct pci_dev *pdev)
4958{
4959 struct device *dev = pci_dev_to_dev(pdev);
4960 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4961
17b14451 4962 ata_host_set_remove(host_set);
1da177e4
LT		 4963 pci_release_regions(pdev);
4964 pci_disable_device(pdev);
4965 dev_set_drvdata(dev, NULL);
4966}
4967
4968/* move to PCI subsystem */
057ace5e 4969int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4970{
4971 unsigned long tmp = 0;
4972
4973 switch (bits->width) {
4974 case 1: {
4975 u8 tmp8 = 0;
4976 pci_read_config_byte(pdev, bits->reg, &tmp8);
4977 tmp = tmp8;
4978 break;
4979 }
4980 case 2: {
4981 u16 tmp16 = 0;
4982 pci_read_config_word(pdev, bits->reg, &tmp16);
4983 tmp = tmp16;
4984 break;
4985 }
4986 case 4: {
4987 u32 tmp32 = 0;
4988 pci_read_config_dword(pdev, bits->reg, &tmp32);
4989 tmp = tmp32;
4990 break;
4991 }
4992
4993 default:
4994 return -EINVAL;
4995 }
4996
4997 tmp &= bits->mask;
4998
4999 return (tmp == bits->val) ? 1 : 0;
5000}
5001#endif /* CONFIG_PCI */
5002
5003
1da177e4
LT		 5004static int __init ata_init(void)
5005{
5006 ata_wq = create_workqueue("ata");
5007 if (!ata_wq)
5008 return -ENOMEM;
5009
5010 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5011 return 0;
5012}
5013
5014static void __exit ata_exit(void)
5015{
5016 destroy_workqueue(ata_wq);
5017}
5018
5019module_init(ata_init);
5020module_exit(ata_exit);
5021
67846b30
JG		 5022static unsigned long ratelimit_time;
5023static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5024
5025int ata_ratelimit(void)
5026{
5027 int rc;
5028 unsigned long flags;
5029
5030 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5031
5032 if (time_after(jiffies, ratelimit_time)) {
5033 rc = 1;
5034 ratelimit_time = jiffies + (HZ/5);
5035 } else
5036 rc = 0;
5037
5038 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5039
5040 return rc;
5041}
5042
1da177e4
LT		 5043/*
5044 * libata is essentially a library of internal helper functions for
5045 * low-level ATA host controller drivers. As such, the API/ABI is
5046 * likely to change as new drivers are added and updated.
5047 * Do not depend on ABI/API stability.
5048 */
5049
5050EXPORT_SYMBOL_GPL(ata_std_bios_param);
5051EXPORT_SYMBOL_GPL(ata_std_ports);
5052EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5053EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 5054EXPORT_SYMBOL_GPL(ata_sg_init);
5055EXPORT_SYMBOL_GPL(ata_sg_init_one);
5056EXPORT_SYMBOL_GPL(ata_qc_complete);
5057EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
5058EXPORT_SYMBOL_GPL(ata_eng_timeout);
5059EXPORT_SYMBOL_GPL(ata_tf_load);
5060EXPORT_SYMBOL_GPL(ata_tf_read);
5061EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5062EXPORT_SYMBOL_GPL(ata_std_dev_select);
5063EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5064EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5065EXPORT_SYMBOL_GPL(ata_check_status);
5066EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 5067EXPORT_SYMBOL_GPL(ata_exec_command);
5068EXPORT_SYMBOL_GPL(ata_port_start);
5069EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5070EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 5071EXPORT_SYMBOL_GPL(ata_interrupt);
5072EXPORT_SYMBOL_GPL(ata_qc_prep);
5073EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5074EXPORT_SYMBOL_GPL(ata_bmdma_start);
5075EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5076EXPORT_SYMBOL_GPL(ata_bmdma_status);
5077EXPORT_SYMBOL_GPL(ata_bmdma_stop);
5078EXPORT_SYMBOL_GPL(ata_port_probe);
5079EXPORT_SYMBOL_GPL(sata_phy_reset);
5080EXPORT_SYMBOL_GPL(__sata_phy_reset);
5081EXPORT_SYMBOL_GPL(ata_bus_reset);
5082EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5083EXPORT_SYMBOL_GPL(ata_ratelimit);
1da177e4
LT		 5084EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5085EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
5086EXPORT_SYMBOL_GPL(ata_scsi_error);
5087EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
5088EXPORT_SYMBOL_GPL(ata_scsi_release);
5089EXPORT_SYMBOL_GPL(ata_host_intr);
5090EXPORT_SYMBOL_GPL(ata_dev_classify);
5091EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 5092EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4
LT		 5093EXPORT_SYMBOL_GPL(ata_scsi_simulate);
5094
452503f9
AC		 5095EXPORT_SYMBOL_GPL(ata_timing_compute);
5096EXPORT_SYMBOL_GPL(ata_timing_merge);
5097
1da177e4
LT		 5098#ifdef CONFIG_PCI
5099EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5100EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5101EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5102EXPORT_SYMBOL_GPL(ata_pci_init_one);
5103EXPORT_SYMBOL_GPL(ata_pci_remove_one);
5104#endif /* CONFIG_PCI */
Linux kernel - Deliverables
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