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edac: AMD8111 & AMD8131 Kconfig fixup
[deliverable/linux.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
1da177e4
LT		 67/*
68 * Debugging.
69 */
70#if 0
71#define DEBUG_AUTOCONF(fmt...) printk(fmt)
72#else
73#define DEBUG_AUTOCONF(fmt...) do { } while (0)
74#endif
75
76#if 0
77#define DEBUG_INTR(fmt...) printk(fmt)
78#else
79#define DEBUG_INTR(fmt...) do { } while (0)
80#endif
81
82#define PASS_LIMIT 256
83
84/*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89#define is_real_interrupt(irq) ((irq) != 0)
90
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92#define CONFIG_SERIAL_DETECT_IRQ 1
93#endif
1da177e4
LT		 94#ifdef CONFIG_SERIAL_8250_MANY_PORTS
95#define CONFIG_SERIAL_MANY_PORTS 1
96#endif
97
98/*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102#define CONFIG_HUB6 1
103
a4ed1e41 104#include <asm/serial.h>
1da177e4
LT		 105/*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110#ifndef SERIAL_PORT_DFNS
111#define SERIAL_PORT_DFNS
112#endif
113
cb3592be 114static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116};
117
026d02a2 118#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 119
120#ifdef CONFIG_SERIAL_8250_RSA
121
122#define PORT_RSA_MAX 4
123static unsigned long probe_rsa[PORT_RSA_MAX];
124static unsigned int probe_rsa_count;
125#endif /* CONFIG_SERIAL_8250_RSA */
126
127struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
1da177e4 133 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
ad4c2aa6
CM		 140
141 /*
142 * Some bits in registers are cleared on a read, so they must
143 * be saved whenever the register is read but the bits will not
144 * be immediately processed.
145 */
146#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
147 unsigned char lsr_saved_flags;
148#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
149 unsigned char msr_saved_flags;
1da177e4
LT		 150
151 /*
152 * We provide a per-port pm hook.
153 */
154 void (*pm)(struct uart_port *port,
155 unsigned int state, unsigned int old);
156};
157
158struct irq_info {
25db8ad5
AC		 159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 162 struct list_head *head;
163};
164
25db8ad5
AC		 165#define NR_IRQ_HASH 32 /* Can be adjusted later */
166static struct hlist_head irq_lists[NR_IRQ_HASH];
167static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 168
169/*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_16654] = {
240 .name = "ST16654",
241 .fifo_size = 64,
242 .tx_loadsz = 32,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
244 UART_FCR_T_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 },
247 [PORT_16850] = {
248 .name = "XR16850",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_RSA] = {
255 .name = "RSA",
256 .fifo_size = 2048,
257 .tx_loadsz = 2048,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
259 .flags = UART_CAP_FIFO,
260 },
261 [PORT_NS16550A] = {
262 .name = "NS16550A",
263 .fifo_size = 16,
264 .tx_loadsz = 16,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
266 .flags = UART_CAP_FIFO | UART_NATSEMI,
267 },
268 [PORT_XSCALE] = {
269 .name = "XScale",
270 .fifo_size = 32,
271 .tx_loadsz = 32,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_CAP_UUE,
274 },
bd71c182
TK		 275 [PORT_RM9000] = {
276 .name = "RM9000",
277 .fifo_size = 16,
278 .tx_loadsz = 16,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 280 .flags = UART_CAP_FIFO,
281 },
282 [PORT_OCTEON] = {
283 .name = "OCTEON",
284 .fifo_size = 64,
285 .tx_loadsz = 64,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 287 .flags = UART_CAP_FIFO,
288 },
1da177e4
LT		 289};
290
bd71c182 291#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 292
293/* Au1x00 UART hardware has a weird register layout */
294static const u8 au_io_in_map[] = {
295 [UART_RX] = 0,
296 [UART_IER] = 2,
297 [UART_IIR] = 3,
298 [UART_LCR] = 5,
299 [UART_MCR] = 6,
300 [UART_LSR] = 7,
301 [UART_MSR] = 8,
302};
303
304static const u8 au_io_out_map[] = {
305 [UART_TX] = 1,
306 [UART_IER] = 2,
307 [UART_FCR] = 4,
308 [UART_LCR] = 5,
309 [UART_MCR] = 6,
310};
311
312/* sane hardware needs no mapping */
7d6a07d1 313static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 314{
7d6a07d1 315 if (p->iotype != UPIO_AU)
21c614a7
PA		 316 return offset;
317 return au_io_in_map[offset];
318}
319
7d6a07d1 320static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 321{
7d6a07d1 322 if (p->iotype != UPIO_AU)
21c614a7
PA		 323 return offset;
324 return au_io_out_map[offset];
325}
326
6f803cd0 327#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 328
329static const u8
330 regmap_in[8] = {
331 [UART_RX] = 0x00,
332 [UART_IER] = 0x0c,
333 [UART_IIR] = 0x14,
334 [UART_LCR] = 0x1c,
335 [UART_MCR] = 0x20,
336 [UART_LSR] = 0x24,
337 [UART_MSR] = 0x28,
338 [UART_SCR] = 0x2c
339 },
340 regmap_out[8] = {
341 [UART_TX] = 0x04,
342 [UART_IER] = 0x0c,
343 [UART_FCR] = 0x18,
344 [UART_LCR] = 0x1c,
345 [UART_MCR] = 0x20,
346 [UART_LSR] = 0x24,
347 [UART_MSR] = 0x28,
348 [UART_SCR] = 0x2c
349 };
350
7d6a07d1 351static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 352{
7d6a07d1 353 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 354 return offset;
355 return regmap_in[offset];
356}
357
7d6a07d1 358static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 359{
7d6a07d1 360 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 361 return offset;
362 return regmap_out[offset];
363}
364
21c614a7
PA		 365#else
366
367/* sane hardware needs no mapping */
368#define map_8250_in_reg(up, offset) (offset)
369#define map_8250_out_reg(up, offset) (offset)
370
371#endif
372
7d6a07d1 373static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 374{
7d6a07d1
DD		 375 offset = map_8250_in_reg(p, offset) << p->regshift;
376 outb(p->hub6 - 1 + offset, p->iobase);
377 return inb(p->iobase + 1);
378}
1da177e4 379
7d6a07d1
DD		 380static void hub6_serial_out(struct uart_port *p, int offset, int value)
381{
382 offset = map_8250_out_reg(p, offset) << p->regshift;
383 outb(p->hub6 - 1 + offset, p->iobase);
384 outb(value, p->iobase + 1);
385}
1da177e4 386
7d6a07d1
DD		 387static unsigned int mem_serial_in(struct uart_port *p, int offset)
388{
389 offset = map_8250_in_reg(p, offset) << p->regshift;
390 return readb(p->membase + offset);
391}
1da177e4 392
7d6a07d1
DD		 393static void mem_serial_out(struct uart_port *p, int offset, int value)
394{
395 offset = map_8250_out_reg(p, offset) << p->regshift;
396 writeb(value, p->membase + offset);
397}
398
399static void mem32_serial_out(struct uart_port *p, int offset, int value)
400{
401 offset = map_8250_out_reg(p, offset) << p->regshift;
402 writel(value, p->membase + offset);
403}
404
405static unsigned int mem32_serial_in(struct uart_port *p, int offset)
406{
407 offset = map_8250_in_reg(p, offset) << p->regshift;
408 return readl(p->membase + offset);
409}
1da177e4 410
21c614a7 411#ifdef CONFIG_SERIAL_8250_AU1X00
7d6a07d1
DD		 412static unsigned int au_serial_in(struct uart_port *p, int offset)
413{
414 offset = map_8250_in_reg(p, offset) << p->regshift;
415 return __raw_readl(p->membase + offset);
416}
417
418static void au_serial_out(struct uart_port *p, int offset, int value)
419{
420 offset = map_8250_out_reg(p, offset) << p->regshift;
421 __raw_writel(value, p->membase + offset);
422}
21c614a7
PA		 423#endif
424
7d6a07d1
DD		 425static unsigned int tsi_serial_in(struct uart_port *p, int offset)
426{
427 unsigned int tmp;
428 offset = map_8250_in_reg(p, offset) << p->regshift;
429 if (offset == UART_IIR) {
430 tmp = readl(p->membase + (UART_IIR & ~3));
431 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
432 } else
433 return readb(p->membase + offset);
434}
3be91ec7 435
7d6a07d1
DD		 436static void tsi_serial_out(struct uart_port *p, int offset, int value)
437{
438 offset = map_8250_out_reg(p, offset) << p->regshift;
439 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
440 writeb(value, p->membase + offset);
1da177e4
LT		 441}
442
7d6a07d1 443static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 444{
beab697a 445 int save_offset = offset;
7d6a07d1
DD		 446 offset = map_8250_out_reg(p, offset) << p->regshift;
447 /* Save the LCR value so it can be re-written when a
448 * Busy Detect interrupt occurs. */
449 if (save_offset == UART_LCR) {
450 struct uart_8250_port *up = (struct uart_8250_port *)p;
451 up->lcr = value;
452 }
453 writeb(value, p->membase + offset);
454 /* Read the IER to ensure any interrupt is cleared before
455 * returning from ISR. */
456 if (save_offset == UART_TX || save_offset == UART_IER)
457 value = p->serial_in(p, UART_IER);
458}
1da177e4 459
7d6a07d1
DD		 460static unsigned int io_serial_in(struct uart_port *p, int offset)
461{
462 offset = map_8250_in_reg(p, offset) << p->regshift;
463 return inb(p->iobase + offset);
464}
465
466static void io_serial_out(struct uart_port *p, int offset, int value)
467{
468 offset = map_8250_out_reg(p, offset) << p->regshift;
469 outb(value, p->iobase + offset);
470}
471
472static void set_io_from_upio(struct uart_port *p)
473{
474 switch (p->iotype) {
1da177e4 475 case UPIO_HUB6:
7d6a07d1
DD		 476 p->serial_in = hub6_serial_in;
477 p->serial_out = hub6_serial_out;
1da177e4
LT		 478 break;
479
480 case UPIO_MEM:
7d6a07d1
DD		 481 p->serial_in = mem_serial_in;
482 p->serial_out = mem_serial_out;
1da177e4
LT		 483 break;
484
bd71c182 485 case UPIO_RM9000:
1da177e4 486 case UPIO_MEM32:
7d6a07d1
DD		 487 p->serial_in = mem32_serial_in;
488 p->serial_out = mem32_serial_out;
1da177e4
LT		 489 break;
490
21c614a7
PA		 491#ifdef CONFIG_SERIAL_8250_AU1X00
492 case UPIO_AU:
7d6a07d1
DD		 493 p->serial_in = au_serial_in;
494 p->serial_out = au_serial_out;
21c614a7
PA		 495 break;
496#endif
3be91ec7 497 case UPIO_TSI:
7d6a07d1
DD		 498 p->serial_in = tsi_serial_in;
499 p->serial_out = tsi_serial_out;
3be91ec7 500 break;
21c614a7 501
beab697a 502 case UPIO_DWAPB:
7d6a07d1
DD		 503 p->serial_in = mem_serial_in;
504 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 505 break;
506
1da177e4 507 default:
7d6a07d1
DD		 508 p->serial_in = io_serial_in;
509 p->serial_out = io_serial_out;
510 break;
1da177e4
LT		 511 }
512}
513
40b36daa
AW		 514static void
515serial_out_sync(struct uart_8250_port *up, int offset, int value)
516{
7d6a07d1
DD		 517 struct uart_port *p = &up->port;
518 switch (p->iotype) {
40b36daa
AW		 519 case UPIO_MEM:
520 case UPIO_MEM32:
521#ifdef CONFIG_SERIAL_8250_AU1X00
522 case UPIO_AU:
523#endif
beab697a 524 case UPIO_DWAPB:
7d6a07d1
DD		 525 p->serial_out(p, offset, value);
526 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 527 break;
528 default:
7d6a07d1 529 p->serial_out(p, offset, value);
40b36daa
AW		 530 }
531}
532
7d6a07d1
DD		 533#define serial_in(up, offset) \
534 (up->port.serial_in(&(up)->port, (offset)))
535#define serial_out(up, offset, value) \
536 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 537/*
538 * We used to support using pause I/O for certain machines. We
539 * haven't supported this for a while, but just in case it's badly
540 * needed for certain old 386 machines, I've left these #define's
541 * in....
542 */
543#define serial_inp(up, offset) serial_in(up, offset)
544#define serial_outp(up, offset, value) serial_out(up, offset, value)
545
b32b19b8
JAH		 546/* Uart divisor latch read */
547static inline int _serial_dl_read(struct uart_8250_port *up)
548{
549 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
550}
551
552/* Uart divisor latch write */
553static inline void _serial_dl_write(struct uart_8250_port *up, int value)
554{
555 serial_outp(up, UART_DLL, value & 0xff);
556 serial_outp(up, UART_DLM, value >> 8 & 0xff);
557}
558
6f803cd0 559#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 560/* Au1x00 haven't got a standard divisor latch */
561static int serial_dl_read(struct uart_8250_port *up)
562{
563 if (up->port.iotype == UPIO_AU)
564 return __raw_readl(up->port.membase + 0x28);
565 else
566 return _serial_dl_read(up);
567}
568
569static void serial_dl_write(struct uart_8250_port *up, int value)
570{
571 if (up->port.iotype == UPIO_AU)
572 __raw_writel(value, up->port.membase + 0x28);
573 else
574 _serial_dl_write(up, value);
575}
6f803cd0 576#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 577static int serial_dl_read(struct uart_8250_port *up)
578{
579 return (up->port.iotype == UPIO_RM9000) ?
580 (((__raw_readl(up->port.membase + 0x10) << 8) |
581 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
582 _serial_dl_read(up);
583}
584
585static void serial_dl_write(struct uart_8250_port *up, int value)
586{
587 if (up->port.iotype == UPIO_RM9000) {
588 __raw_writel(value, up->port.membase + 0x08);
589 __raw_writel(value >> 8, up->port.membase + 0x10);
590 } else {
591 _serial_dl_write(up, value);
592 }
593}
b32b19b8
JAH		 594#else
595#define serial_dl_read(up) _serial_dl_read(up)
596#define serial_dl_write(up, value) _serial_dl_write(up, value)
597#endif
1da177e4
LT		 598
599/*
600 * For the 16C950
601 */
602static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
603{
604 serial_out(up, UART_SCR, offset);
605 serial_out(up, UART_ICR, value);
606}
607
608static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
609{
610 unsigned int value;
611
612 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
613 serial_out(up, UART_SCR, offset);
614 value = serial_in(up, UART_ICR);
615 serial_icr_write(up, UART_ACR, up->acr);
616
617 return value;
618}
619
620/*
621 * FIFO support.
622 */
b5d674ab 623static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 624{
625 if (p->capabilities & UART_CAP_FIFO) {
626 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
627 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
628 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
629 serial_outp(p, UART_FCR, 0);
630 }
631}
632
633/*
634 * IER sleep support. UARTs which have EFRs need the "extended
635 * capability" bit enabled. Note that on XR16C850s, we need to
636 * reset LCR to write to IER.
637 */
b5d674ab 638static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 639{
640 if (p->capabilities & UART_CAP_SLEEP) {
641 if (p->capabilities & UART_CAP_EFR) {
642 serial_outp(p, UART_LCR, 0xBF);
643 serial_outp(p, UART_EFR, UART_EFR_ECB);
644 serial_outp(p, UART_LCR, 0);
645 }
646 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
647 if (p->capabilities & UART_CAP_EFR) {
648 serial_outp(p, UART_LCR, 0xBF);
649 serial_outp(p, UART_EFR, 0);
650 serial_outp(p, UART_LCR, 0);
651 }
652 }
653}
654
655#ifdef CONFIG_SERIAL_8250_RSA
656/*
657 * Attempts to turn on the RSA FIFO. Returns zero on failure.
658 * We set the port uart clock rate if we succeed.
659 */
660static int __enable_rsa(struct uart_8250_port *up)
661{
662 unsigned char mode;
663 int result;
664
665 mode = serial_inp(up, UART_RSA_MSR);
666 result = mode & UART_RSA_MSR_FIFO;
667
668 if (!result) {
669 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
670 mode = serial_inp(up, UART_RSA_MSR);
671 result = mode & UART_RSA_MSR_FIFO;
672 }
673
674 if (result)
675 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
676
677 return result;
678}
679
680static void enable_rsa(struct uart_8250_port *up)
681{
682 if (up->port.type == PORT_RSA) {
683 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
684 spin_lock_irq(&up->port.lock);
685 __enable_rsa(up);
686 spin_unlock_irq(&up->port.lock);
687 }
688 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
689 serial_outp(up, UART_RSA_FRR, 0);
690 }
691}
692
693/*
694 * Attempts to turn off the RSA FIFO. Returns zero on failure.
695 * It is unknown why interrupts were disabled in here. However,
696 * the caller is expected to preserve this behaviour by grabbing
697 * the spinlock before calling this function.
698 */
699static void disable_rsa(struct uart_8250_port *up)
700{
701 unsigned char mode;
702 int result;
703
704 if (up->port.type == PORT_RSA &&
705 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
706 spin_lock_irq(&up->port.lock);
707
708 mode = serial_inp(up, UART_RSA_MSR);
709 result = !(mode & UART_RSA_MSR_FIFO);
710
711 if (!result) {
712 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
713 mode = serial_inp(up, UART_RSA_MSR);
714 result = !(mode & UART_RSA_MSR_FIFO);
715 }
716
717 if (result)
718 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
719 spin_unlock_irq(&up->port.lock);
720 }
721}
722#endif /* CONFIG_SERIAL_8250_RSA */
723
724/*
725 * This is a quickie test to see how big the FIFO is.
726 * It doesn't work at all the time, more's the pity.
727 */
728static int size_fifo(struct uart_8250_port *up)
729{
b32b19b8
JAH		 730 unsigned char old_fcr, old_mcr, old_lcr;
731 unsigned short old_dl;
1da177e4
LT		 732 int count;
733
734 old_lcr = serial_inp(up, UART_LCR);
735 serial_outp(up, UART_LCR, 0);
736 old_fcr = serial_inp(up, UART_FCR);
737 old_mcr = serial_inp(up, UART_MCR);
738 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
739 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
740 serial_outp(up, UART_MCR, UART_MCR_LOOP);
741 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 742 old_dl = serial_dl_read(up);
743 serial_dl_write(up, 0x0001);
1da177e4
LT		 744 serial_outp(up, UART_LCR, 0x03);
745 for (count = 0; count < 256; count++)
746 serial_outp(up, UART_TX, count);
747 mdelay(20);/* FIXME - schedule_timeout */
748 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
749 (count < 256); count++)
750 serial_inp(up, UART_RX);
751 serial_outp(up, UART_FCR, old_fcr);
752 serial_outp(up, UART_MCR, old_mcr);
753 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 754 serial_dl_write(up, old_dl);
1da177e4
LT		 755 serial_outp(up, UART_LCR, old_lcr);
756
757 return count;
758}
759
760/*
761 * Read UART ID using the divisor method - set DLL and DLM to zero
762 * and the revision will be in DLL and device type in DLM. We
763 * preserve the device state across this.
764 */
765static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
766{
767 unsigned char old_dll, old_dlm, old_lcr;
768 unsigned int id;
769
770 old_lcr = serial_inp(p, UART_LCR);
771 serial_outp(p, UART_LCR, UART_LCR_DLAB);
772
773 old_dll = serial_inp(p, UART_DLL);
774 old_dlm = serial_inp(p, UART_DLM);
775
776 serial_outp(p, UART_DLL, 0);
777 serial_outp(p, UART_DLM, 0);
778
779 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
780
781 serial_outp(p, UART_DLL, old_dll);
782 serial_outp(p, UART_DLM, old_dlm);
783 serial_outp(p, UART_LCR, old_lcr);
784
785 return id;
786}
787
788/*
789 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
790 * When this function is called we know it is at least a StarTech
791 * 16650 V2, but it might be one of several StarTech UARTs, or one of
792 * its clones. (We treat the broken original StarTech 16650 V1 as a
793 * 16550, and why not? Startech doesn't seem to even acknowledge its
794 * existence.)
bd71c182 795 *
1da177e4
LT		 796 * What evil have men's minds wrought...
797 */
798static void autoconfig_has_efr(struct uart_8250_port *up)
799{
800 unsigned int id1, id2, id3, rev;
801
802 /*
803 * Everything with an EFR has SLEEP
804 */
805 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
806
807 /*
808 * First we check to see if it's an Oxford Semiconductor UART.
809 *
810 * If we have to do this here because some non-National
811 * Semiconductor clone chips lock up if you try writing to the
812 * LSR register (which serial_icr_read does)
813 */
814
815 /*
816 * Check for Oxford Semiconductor 16C950.
817 *
818 * EFR [4] must be set else this test fails.
819 *
820 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
821 * claims that it's needed for 952 dual UART's (which are not
822 * recommended for new designs).
823 */
824 up->acr = 0;
825 serial_out(up, UART_LCR, 0xBF);
826 serial_out(up, UART_EFR, UART_EFR_ECB);
827 serial_out(up, UART_LCR, 0x00);
828 id1 = serial_icr_read(up, UART_ID1);
829 id2 = serial_icr_read(up, UART_ID2);
830 id3 = serial_icr_read(up, UART_ID3);
831 rev = serial_icr_read(up, UART_REV);
832
833 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
834
835 if (id1 == 0x16 && id2 == 0xC9 &&
836 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
837 up->port.type = PORT_16C950;
4ba5e35d
RK		 838
839 /*
840 * Enable work around for the Oxford Semiconductor 952 rev B
841 * chip which causes it to seriously miscalculate baud rates
842 * when DLL is 0.
843 */
844 if (id3 == 0x52 && rev == 0x01)
845 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 846 return;
847 }
bd71c182 848
1da177e4
LT		 849 /*
850 * We check for a XR16C850 by setting DLL and DLM to 0, and then
851 * reading back DLL and DLM. The chip type depends on the DLM
852 * value read back:
853 * 0x10 - XR16C850 and the DLL contains the chip revision.
854 * 0x12 - XR16C2850.
855 * 0x14 - XR16C854.
856 */
857 id1 = autoconfig_read_divisor_id(up);
858 DEBUG_AUTOCONF("850id=%04x ", id1);
859
860 id2 = id1 >> 8;
861 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 862 up->port.type = PORT_16850;
863 return;
864 }
865
866 /*
867 * It wasn't an XR16C850.
868 *
869 * We distinguish between the '654 and the '650 by counting
870 * how many bytes are in the FIFO. I'm using this for now,
871 * since that's the technique that was sent to me in the
872 * serial driver update, but I'm not convinced this works.
873 * I've had problems doing this in the past. -TYT
874 */
875 if (size_fifo(up) == 64)
876 up->port.type = PORT_16654;
877 else
878 up->port.type = PORT_16650V2;
879}
880
881/*
882 * We detected a chip without a FIFO. Only two fall into
883 * this category - the original 8250 and the 16450. The
884 * 16450 has a scratch register (accessible with LCR=0)
885 */
886static void autoconfig_8250(struct uart_8250_port *up)
887{
888 unsigned char scratch, status1, status2;
889
890 up->port.type = PORT_8250;
891
892 scratch = serial_in(up, UART_SCR);
893 serial_outp(up, UART_SCR, 0xa5);
894 status1 = serial_in(up, UART_SCR);
895 serial_outp(up, UART_SCR, 0x5a);
896 status2 = serial_in(up, UART_SCR);
897 serial_outp(up, UART_SCR, scratch);
898
899 if (status1 == 0xa5 && status2 == 0x5a)
900 up->port.type = PORT_16450;
901}
902
903static int broken_efr(struct uart_8250_port *up)
904{
905 /*
906 * Exar ST16C2550 "A2" devices incorrectly detect as
907 * having an EFR, and report an ID of 0x0201. See
908 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
909 */
910 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
911 return 1;
912
913 return 0;
914}
915
916/*
917 * We know that the chip has FIFOs. Does it have an EFR? The
918 * EFR is located in the same register position as the IIR and
919 * we know the top two bits of the IIR are currently set. The
920 * EFR should contain zero. Try to read the EFR.
921 */
922static void autoconfig_16550a(struct uart_8250_port *up)
923{
924 unsigned char status1, status2;
925 unsigned int iersave;
926
927 up->port.type = PORT_16550A;
928 up->capabilities |= UART_CAP_FIFO;
929
930 /*
931 * Check for presence of the EFR when DLAB is set.
932 * Only ST16C650V1 UARTs pass this test.
933 */
934 serial_outp(up, UART_LCR, UART_LCR_DLAB);
935 if (serial_in(up, UART_EFR) == 0) {
936 serial_outp(up, UART_EFR, 0xA8);
937 if (serial_in(up, UART_EFR) != 0) {
938 DEBUG_AUTOCONF("EFRv1 ");
939 up->port.type = PORT_16650;
940 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
941 } else {
942 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
943 }
944 serial_outp(up, UART_EFR, 0);
945 return;
946 }
947
948 /*
949 * Maybe it requires 0xbf to be written to the LCR.
950 * (other ST16C650V2 UARTs, TI16C752A, etc)
951 */
952 serial_outp(up, UART_LCR, 0xBF);
953 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
954 DEBUG_AUTOCONF("EFRv2 ");
955 autoconfig_has_efr(up);
956 return;
957 }
958
959 /*
960 * Check for a National Semiconductor SuperIO chip.
961 * Attempt to switch to bank 2, read the value of the LOOP bit
962 * from EXCR1. Switch back to bank 0, change it in MCR. Then
963 * switch back to bank 2, read it from EXCR1 again and check
964 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 965 */
966 serial_outp(up, UART_LCR, 0);
967 status1 = serial_in(up, UART_MCR);
968 serial_outp(up, UART_LCR, 0xE0);
969 status2 = serial_in(up, 0x02); /* EXCR1 */
970
971 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
972 serial_outp(up, UART_LCR, 0);
973 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
974 serial_outp(up, UART_LCR, 0xE0);
975 status2 = serial_in(up, 0x02); /* EXCR1 */
976 serial_outp(up, UART_LCR, 0);
977 serial_outp(up, UART_MCR, status1);
978
979 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 980 unsigned short quot;
981
1da177e4 982 serial_outp(up, UART_LCR, 0xE0);
857dde2e 983
b32b19b8 984 quot = serial_dl_read(up);
857dde2e
DW		 985 quot <<= 3;
986
b5b82df6 987 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 988 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
989 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
990 serial_outp(up, 0x04, status1);
bd71c182 991
b32b19b8 992 serial_dl_write(up, quot);
857dde2e 993
1da177e4 994 serial_outp(up, UART_LCR, 0);
1da177e4 995
857dde2e 996 up->port.uartclk = 921600*16;
1da177e4
LT		 997 up->port.type = PORT_NS16550A;
998 up->capabilities |= UART_NATSEMI;
999 return;
1000 }
1001 }
1002
1003 /*
1004 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1005 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1006 * Try setting it with and without DLAB set. Cheap clones
1007 * set bit 5 without DLAB set.
1008 */
1009 serial_outp(up, UART_LCR, 0);
1010 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1013 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1014 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1015 status2 = serial_in(up, UART_IIR) >> 5;
1016 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1017 serial_outp(up, UART_LCR, 0);
1018
1019 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1020
1021 if (status1 == 6 && status2 == 7) {
1022 up->port.type = PORT_16750;
1023 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1024 return;
1025 }
1026
1027 /*
1028 * Try writing and reading the UART_IER_UUE bit (b6).
1029 * If it works, this is probably one of the Xscale platform's
1030 * internal UARTs.
1031 * We're going to explicitly set the UUE bit to 0 before
1032 * trying to write and read a 1 just to make sure it's not
1033 * already a 1 and maybe locked there before we even start start.
1034 */
1035 iersave = serial_in(up, UART_IER);
1036 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1037 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1038 /*
1039 * OK it's in a known zero state, try writing and reading
1040 * without disturbing the current state of the other bits.
1041 */
1042 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1043 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1044 /*
1045 * It's an Xscale.
1046 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1047 */
1048 DEBUG_AUTOCONF("Xscale ");
1049 up->port.type = PORT_XSCALE;
1050 up->capabilities |= UART_CAP_UUE;
1051 return;
1052 }
1053 } else {
1054 /*
1055 * If we got here we couldn't force the IER_UUE bit to 0.
1056 * Log it and continue.
1057 */
1058 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1059 }
1060 serial_outp(up, UART_IER, iersave);
1061}
1062
1063/*
1064 * This routine is called by rs_init() to initialize a specific serial
1065 * port. It determines what type of UART chip this serial port is
1066 * using: 8250, 16450, 16550, 16550A. The important question is
1067 * whether or not this UART is a 16550A or not, since this will
1068 * determine whether or not we can use its FIFO features or not.
1069 */
1070static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1071{
1072 unsigned char status1, scratch, scratch2, scratch3;
1073 unsigned char save_lcr, save_mcr;
1074 unsigned long flags;
1075
1076 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1077 return;
1078
1079 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
8440838b 1080 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1081
1082 /*
1083 * We really do need global IRQs disabled here - we're going to
1084 * be frobbing the chips IRQ enable register to see if it exists.
1085 */
1086 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1087
1088 up->capabilities = 0;
4ba5e35d 1089 up->bugs = 0;
1da177e4
LT		 1090
1091 if (!(up->port.flags & UPF_BUGGY_UART)) {
1092 /*
1093 * Do a simple existence test first; if we fail this,
1094 * there's no point trying anything else.
bd71c182 1095 *
1da177e4
LT		 1096 * 0x80 is used as a nonsense port to prevent against
1097 * false positives due to ISA bus float. The
1098 * assumption is that 0x80 is a non-existent port;
1099 * which should be safe since include/asm/io.h also
1100 * makes this assumption.
1101 *
1102 * Note: this is safe as long as MCR bit 4 is clear
1103 * and the device is in "PC" mode.
1104 */
1105 scratch = serial_inp(up, UART_IER);
1106 serial_outp(up, UART_IER, 0);
1107#ifdef __i386__
1108 outb(0xff, 0x080);
1109#endif
48212008
TH		 1110 /*
1111 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1112 * 16C754B) allow only to modify them if an EFR bit is set.
1113 */
1114 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1115 serial_outp(up, UART_IER, 0x0F);
1116#ifdef __i386__
1117 outb(0, 0x080);
1118#endif
48212008 1119 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1120 serial_outp(up, UART_IER, scratch);
1121 if (scratch2 != 0 || scratch3 != 0x0F) {
1122 /*
1123 * We failed; there's nothing here
1124 */
1125 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1126 scratch2, scratch3);
1127 goto out;
1128 }
1129 }
1130
1131 save_mcr = serial_in(up, UART_MCR);
1132 save_lcr = serial_in(up, UART_LCR);
1133
bd71c182 1134 /*
1da177e4
LT		 1135 * Check to see if a UART is really there. Certain broken
1136 * internal modems based on the Rockwell chipset fail this
1137 * test, because they apparently don't implement the loopback
1138 * test mode. So this test is skipped on the COM 1 through
1139 * COM 4 ports. This *should* be safe, since no board
1140 * manufacturer would be stupid enough to design a board
1141 * that conflicts with COM 1-4 --- we hope!
1142 */
1143 if (!(up->port.flags & UPF_SKIP_TEST)) {
1144 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1145 status1 = serial_inp(up, UART_MSR) & 0xF0;
1146 serial_outp(up, UART_MCR, save_mcr);
1147 if (status1 != 0x90) {
1148 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1149 status1);
1150 goto out;
1151 }
1152 }
1153
1154 /*
1155 * We're pretty sure there's a port here. Lets find out what
1156 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1157 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1158 * determines what we test for next.
1159 *
1160 * We also initialise the EFR (if any) to zero for later. The
1161 * EFR occupies the same register location as the FCR and IIR.
1162 */
1163 serial_outp(up, UART_LCR, 0xBF);
1164 serial_outp(up, UART_EFR, 0);
1165 serial_outp(up, UART_LCR, 0);
1166
1167 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1168 scratch = serial_in(up, UART_IIR) >> 6;
1169
1170 DEBUG_AUTOCONF("iir=%d ", scratch);
1171
1172 switch (scratch) {
1173 case 0:
1174 autoconfig_8250(up);
1175 break;
1176 case 1:
1177 up->port.type = PORT_UNKNOWN;
1178 break;
1179 case 2:
1180 up->port.type = PORT_16550;
1181 break;
1182 case 3:
1183 autoconfig_16550a(up);
1184 break;
1185 }
1186
1187#ifdef CONFIG_SERIAL_8250_RSA
1188 /*
1189 * Only probe for RSA ports if we got the region.
1190 */
1191 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1192 int i;
1193
1194 for (i = 0 ; i < probe_rsa_count; ++i) {
1195 if (probe_rsa[i] == up->port.iobase &&
1196 __enable_rsa(up)) {
1197 up->port.type = PORT_RSA;
1198 break;
1199 }
1200 }
1201 }
1202#endif
21c614a7
PA		 1203
1204#ifdef CONFIG_SERIAL_8250_AU1X00
1205 /* if access method is AU, it is a 16550 with a quirk */
1206 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1207 up->bugs |= UART_BUG_NOMSR;
1208#endif
1209
1da177e4
LT		 1210 serial_outp(up, UART_LCR, save_lcr);
1211
1212 if (up->capabilities != uart_config[up->port.type].flags) {
1213 printk(KERN_WARNING
1214 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1215 serial_index(&up->port), up->capabilities,
1216 uart_config[up->port.type].flags);
1da177e4
LT		 1217 }
1218
1219 up->port.fifosize = uart_config[up->port.type].fifo_size;
1220 up->capabilities = uart_config[up->port.type].flags;
1221 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1222
1223 if (up->port.type == PORT_UNKNOWN)
1224 goto out;
1225
1226 /*
1227 * Reset the UART.
1228 */
1229#ifdef CONFIG_SERIAL_8250_RSA
1230 if (up->port.type == PORT_RSA)
1231 serial_outp(up, UART_RSA_FRR, 0);
1232#endif
1233 serial_outp(up, UART_MCR, save_mcr);
1234 serial8250_clear_fifos(up);
40b36daa 1235 serial_in(up, UART_RX);
5c8c755c
LB		 1236 if (up->capabilities & UART_CAP_UUE)
1237 serial_outp(up, UART_IER, UART_IER_UUE);
1238 else
1239 serial_outp(up, UART_IER, 0);
1da177e4 1240
bd71c182 1241 out:
1da177e4 1242 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1243 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1244}
1245
1246static void autoconfig_irq(struct uart_8250_port *up)
1247{
1248 unsigned char save_mcr, save_ier;
1249 unsigned char save_ICP = 0;
1250 unsigned int ICP = 0;
1251 unsigned long irqs;
1252 int irq;
1253
1254 if (up->port.flags & UPF_FOURPORT) {
1255 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1256 save_ICP = inb_p(ICP);
1257 outb_p(0x80, ICP);
1258 (void) inb_p(ICP);
1259 }
1260
1261 /* forget possible initially masked and pending IRQ */
1262 probe_irq_off(probe_irq_on());
1263 save_mcr = serial_inp(up, UART_MCR);
1264 save_ier = serial_inp(up, UART_IER);
1265 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1266
1da177e4
LT		 1267 irqs = probe_irq_on();
1268 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1269 udelay(10);
1270 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1271 serial_outp(up, UART_MCR,
1272 UART_MCR_DTR | UART_MCR_RTS);
1273 } else {
1274 serial_outp(up, UART_MCR,
1275 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1276 }
1277 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1278 (void)serial_inp(up, UART_LSR);
1279 (void)serial_inp(up, UART_RX);
1280 (void)serial_inp(up, UART_IIR);
1281 (void)serial_inp(up, UART_MSR);
1282 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1283 udelay(20);
1da177e4
LT		 1284 irq = probe_irq_off(irqs);
1285
1286 serial_outp(up, UART_MCR, save_mcr);
1287 serial_outp(up, UART_IER, save_ier);
1288
1289 if (up->port.flags & UPF_FOURPORT)
1290 outb_p(save_ICP, ICP);
1291
1292 up->port.irq = (irq > 0) ? irq : 0;
1293}
1294
e763b90c
RK		 1295static inline void __stop_tx(struct uart_8250_port *p)
1296{
1297 if (p->ier & UART_IER_THRI) {
1298 p->ier &= ~UART_IER_THRI;
1299 serial_out(p, UART_IER, p->ier);
1300 }
1301}
1302
b129a8cc 1303static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1304{
1305 struct uart_8250_port *up = (struct uart_8250_port *)port;
1306
e763b90c 1307 __stop_tx(up);
1da177e4
LT		 1308
1309 /*
e763b90c 1310 * We really want to stop the transmitter from sending.
1da177e4 1311 */
e763b90c 1312 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1313 up->acr |= UART_ACR_TXDIS;
1314 serial_icr_write(up, UART_ACR, up->acr);
1315 }
1316}
1317
55d3b282
RK		 1318static void transmit_chars(struct uart_8250_port *up);
1319
b129a8cc 1320static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1321{
1322 struct uart_8250_port *up = (struct uart_8250_port *)port;
1323
1324 if (!(up->ier & UART_IER_THRI)) {
1325 up->ier |= UART_IER_THRI;
1326 serial_out(up, UART_IER, up->ier);
55d3b282 1327
67f7654e 1328 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1329 unsigned char lsr, iir;
1330 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1331 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182
TK		 1332 iir = serial_in(up, UART_IIR) & 0x0f;
1333 if ((up->port.type == PORT_RM9000) ?
1334 (lsr & UART_LSR_THRE &&
1335 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1336 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
55d3b282
RK		 1337 transmit_chars(up);
1338 }
1da177e4 1339 }
e763b90c 1340
1da177e4 1341 /*
e763b90c 1342 * Re-enable the transmitter if we disabled it.
1da177e4 1343 */
e763b90c 1344 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1345 up->acr &= ~UART_ACR_TXDIS;
1346 serial_icr_write(up, UART_ACR, up->acr);
1347 }
1348}
1349
1350static void serial8250_stop_rx(struct uart_port *port)
1351{
1352 struct uart_8250_port *up = (struct uart_8250_port *)port;
1353
1354 up->ier &= ~UART_IER_RLSI;
1355 up->port.read_status_mask &= ~UART_LSR_DR;
1356 serial_out(up, UART_IER, up->ier);
1357}
1358
1359static void serial8250_enable_ms(struct uart_port *port)
1360{
1361 struct uart_8250_port *up = (struct uart_8250_port *)port;
1362
21c614a7
PA		 1363 /* no MSR capabilities */
1364 if (up->bugs & UART_BUG_NOMSR)
1365 return;
1366
1da177e4
LT		 1367 up->ier |= UART_IER_MSI;
1368 serial_out(up, UART_IER, up->ier);
1369}
1370
ea8874dc 1371static void
cc79aa9d 1372receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1373{
df4f4dd4 1374 struct tty_struct *tty = up->port.info->port.tty;
1da177e4
LT		 1375 unsigned char ch, lsr = *status;
1376 int max_count = 256;
1377 char flag;
1378
1379 do {
7500b1f6
AR		 1380 if (likely(lsr & UART_LSR_DR))
1381 ch = serial_inp(up, UART_RX);
1382 else
1383 /*
1384 * Intel 82571 has a Serial Over Lan device that will
1385 * set UART_LSR_BI without setting UART_LSR_DR when
1386 * it receives a break. To avoid reading from the
1387 * receive buffer without UART_LSR_DR bit set, we
1388 * just force the read character to be 0
1389 */
1390 ch = 0;
1391
1da177e4
LT		 1392 flag = TTY_NORMAL;
1393 up->port.icount.rx++;
1394
ad4c2aa6
CM		 1395 lsr |= up->lsr_saved_flags;
1396 up->lsr_saved_flags = 0;
1da177e4 1397
ad4c2aa6 1398 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1399 /*
1400 * For statistics only
1401 */
1402 if (lsr & UART_LSR_BI) {
1403 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1404 up->port.icount.brk++;
1405 /*
1406 * We do the SysRQ and SAK checking
1407 * here because otherwise the break
1408 * may get masked by ignore_status_mask
1409 * or read_status_mask.
1410 */
1411 if (uart_handle_break(&up->port))
1412 goto ignore_char;
1413 } else if (lsr & UART_LSR_PE)
1414 up->port.icount.parity++;
1415 else if (lsr & UART_LSR_FE)
1416 up->port.icount.frame++;
1417 if (lsr & UART_LSR_OE)
1418 up->port.icount.overrun++;
1419
1420 /*
23907eb8 1421 * Mask off conditions which should be ignored.
1da177e4
LT		 1422 */
1423 lsr &= up->port.read_status_mask;
1424
1425 if (lsr & UART_LSR_BI) {
1426 DEBUG_INTR("handling break....");
1427 flag = TTY_BREAK;
1428 } else if (lsr & UART_LSR_PE)
1429 flag = TTY_PARITY;
1430 else if (lsr & UART_LSR_FE)
1431 flag = TTY_FRAME;
1432 }
7d12e780 1433 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1434 goto ignore_char;
05ab3014
RK		 1435
1436 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1437
6f803cd0 1438ignore_char:
1da177e4 1439 lsr = serial_inp(up, UART_LSR);
7500b1f6 1440 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1441 spin_unlock(&up->port.lock);
1442 tty_flip_buffer_push(tty);
1443 spin_lock(&up->port.lock);
1444 *status = lsr;
1445}
1446
ea8874dc 1447static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1448{
1449 struct circ_buf *xmit = &up->port.info->xmit;
1450 int count;
1451
1452 if (up->port.x_char) {
1453 serial_outp(up, UART_TX, up->port.x_char);
1454 up->port.icount.tx++;
1455 up->port.x_char = 0;
1456 return;
1457 }
b129a8cc
RK		 1458 if (uart_tx_stopped(&up->port)) {
1459 serial8250_stop_tx(&up->port);
1460 return;
1461 }
1462 if (uart_circ_empty(xmit)) {
e763b90c 1463 __stop_tx(up);
1da177e4
LT		 1464 return;
1465 }
1466
1467 count = up->tx_loadsz;
1468 do {
1469 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1470 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1471 up->port.icount.tx++;
1472 if (uart_circ_empty(xmit))
1473 break;
1474 } while (--count > 0);
1475
1476 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1477 uart_write_wakeup(&up->port);
1478
1479 DEBUG_INTR("THRE...");
1480
1481 if (uart_circ_empty(xmit))
e763b90c 1482 __stop_tx(up);
1da177e4
LT		 1483}
1484
2af7cd68 1485static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1486{
2af7cd68
RK		 1487 unsigned int status = serial_in(up, UART_MSR);
1488
ad4c2aa6
CM		 1489 status |= up->msr_saved_flags;
1490 up->msr_saved_flags = 0;
fdc30b3d
TI		 1491 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1492 up->port.info != NULL) {
2af7cd68
RK		 1493 if (status & UART_MSR_TERI)
1494 up->port.icount.rng++;
1495 if (status & UART_MSR_DDSR)
1496 up->port.icount.dsr++;
1497 if (status & UART_MSR_DDCD)
1498 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1499 if (status & UART_MSR_DCTS)
1500 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1501
1502 wake_up_interruptible(&up->port.info->delta_msr_wait);
1503 }
1da177e4 1504
2af7cd68 1505 return status;
1da177e4
LT		 1506}
1507
1508/*
1509 * This handles the interrupt from one port.
1510 */
b5d674ab 1511static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1512{
45e24601 1513 unsigned int status;
4bf3631c 1514 unsigned long flags;
45e24601 1515
4bf3631c 1516 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1517
1518 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1519
1520 DEBUG_INTR("status = %x...", status);
1521
7500b1f6 1522 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1523 receive_chars(up, &status);
1da177e4
LT		 1524 check_modem_status(up);
1525 if (status & UART_LSR_THRE)
1526 transmit_chars(up);
45e24601 1527
4bf3631c 1528 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1529}
1530
1531/*
1532 * This is the serial driver's interrupt routine.
1533 *
1534 * Arjan thinks the old way was overly complex, so it got simplified.
1535 * Alan disagrees, saying that need the complexity to handle the weird
1536 * nature of ISA shared interrupts. (This is a special exception.)
1537 *
1538 * In order to handle ISA shared interrupts properly, we need to check
1539 * that all ports have been serviced, and therefore the ISA interrupt
1540 * line has been de-asserted.
1541 *
1542 * This means we need to loop through all ports. checking that they
1543 * don't have an interrupt pending.
1544 */
7d12e780 1545static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1546{
1547 struct irq_info *i = dev_id;
1548 struct list_head *l, *end = NULL;
1549 int pass_counter = 0, handled = 0;
1550
1551 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1552
1553 spin_lock(&i->lock);
1554
1555 l = i->head;
1556 do {
1557 struct uart_8250_port *up;
1558 unsigned int iir;
1559
1560 up = list_entry(l, struct uart_8250_port, list);
1561
1562 iir = serial_in(up, UART_IIR);
1563 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1564 serial8250_handle_port(up);
1da177e4
LT		 1565
1566 handled = 1;
1567
beab697a
MSJ		 1568 end = NULL;
1569 } else if (up->port.iotype == UPIO_DWAPB &&
1570 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1571 /* The DesignWare APB UART has an Busy Detect (0x07)
1572 * interrupt meaning an LCR write attempt occured while the
1573 * UART was busy. The interrupt must be cleared by reading
1574 * the UART status register (USR) and the LCR re-written. */
1575 unsigned int status;
1576 status = *(volatile u32 *)up->port.private_data;
1577 serial_out(up, UART_LCR, up->lcr);
1578
1579 handled = 1;
1580
1da177e4
LT		 1581 end = NULL;
1582 } else if (end == NULL)
1583 end = l;
1584
1585 l = l->next;
1586
1587 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1588 /* If we hit this, we're dead. */
1589 printk(KERN_ERR "serial8250: too much work for "
1590 "irq%d\n", irq);
1591 break;
1592 }
1593 } while (l != end);
1594
1595 spin_unlock(&i->lock);
1596
1597 DEBUG_INTR("end.\n");
1598
1599 return IRQ_RETVAL(handled);
1600}
1601
1602/*
1603 * To support ISA shared interrupts, we need to have one interrupt
1604 * handler that ensures that the IRQ line has been deasserted
1605 * before returning. Failing to do this will result in the IRQ
1606 * line being stuck active, and, since ISA irqs are edge triggered,
1607 * no more IRQs will be seen.
1608 */
1609static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1610{
1611 spin_lock_irq(&i->lock);
1612
1613 if (!list_empty(i->head)) {
1614 if (i->head == &up->list)
1615 i->head = i->head->next;
1616 list_del(&up->list);
1617 } else {
1618 BUG_ON(i->head != &up->list);
1619 i->head = NULL;
1620 }
1da177e4 1621 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1622 /* List empty so throw away the hash node */
1623 if (i->head == NULL) {
1624 hlist_del(&i->node);
1625 kfree(i);
1626 }
1da177e4
LT		 1627}
1628
1629static int serial_link_irq_chain(struct uart_8250_port *up)
1630{
25db8ad5
AC		 1631 struct hlist_head *h;
1632 struct hlist_node *n;
1633 struct irq_info *i;
40663cc7 1634 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1635
25db8ad5
AC		 1636 mutex_lock(&hash_mutex);
1637
1638 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1639
1640 hlist_for_each(n, h) {
1641 i = hlist_entry(n, struct irq_info, node);
1642 if (i->irq == up->port.irq)
1643 break;
1644 }
1645
1646 if (n == NULL) {
1647 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1648 if (i == NULL) {
1649 mutex_unlock(&hash_mutex);
1650 return -ENOMEM;
1651 }
1652 spin_lock_init(&i->lock);
1653 i->irq = up->port.irq;
1654 hlist_add_head(&i->node, h);
1655 }
1656 mutex_unlock(&hash_mutex);
1657
1da177e4
LT		 1658 spin_lock_irq(&i->lock);
1659
1660 if (i->head) {
1661 list_add(&up->list, i->head);
1662 spin_unlock_irq(&i->lock);
1663
1664 ret = 0;
1665 } else {
1666 INIT_LIST_HEAD(&up->list);
1667 i->head = &up->list;
1668 spin_unlock_irq(&i->lock);
1669
1670 ret = request_irq(up->port.irq, serial8250_interrupt,
1671 irq_flags, "serial", i);
1672 if (ret < 0)
1673 serial_do_unlink(i, up);
1674 }
1675
1676 return ret;
1677}
1678
1679static void serial_unlink_irq_chain(struct uart_8250_port *up)
1680{
25db8ad5
AC		 1681 struct irq_info *i;
1682 struct hlist_node *n;
1683 struct hlist_head *h;
1da177e4 1684
25db8ad5
AC		 1685 mutex_lock(&hash_mutex);
1686
1687 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1688
1689 hlist_for_each(n, h) {
1690 i = hlist_entry(n, struct irq_info, node);
1691 if (i->irq == up->port.irq)
1692 break;
1693 }
1694
1695 BUG_ON(n == NULL);
1da177e4
LT		 1696 BUG_ON(i->head == NULL);
1697
1698 if (list_empty(i->head))
1699 free_irq(up->port.irq, i);
1700
1701 serial_do_unlink(i, up);
25db8ad5 1702 mutex_unlock(&hash_mutex);
1da177e4
LT		 1703}
1704
40b36daa
AW		 1705/* Base timer interval for polling */
1706static inline int poll_timeout(int timeout)
1707{
1708 return timeout > 6 ? (timeout / 2 - 2) : 1;
1709}
1710
1da177e4
LT		 1711/*
1712 * This function is used to handle ports that do not have an
1713 * interrupt. This doesn't work very well for 16450's, but gives
1714 * barely passable results for a 16550A. (Although at the expense
1715 * of much CPU overhead).
1716 */
1717static void serial8250_timeout(unsigned long data)
1718{
1719 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1720 unsigned int iir;
1721
1722 iir = serial_in(up, UART_IIR);
45e24601 1723 if (!(iir & UART_IIR_NO_INT))
7d12e780 1724 serial8250_handle_port(up);
40b36daa
AW		 1725 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1726}
1727
1728static void serial8250_backup_timeout(unsigned long data)
1729{
1730 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1731 unsigned int iir, ier = 0, lsr;
1732 unsigned long flags;
40b36daa
AW		 1733
1734 /*
1735 * Must disable interrupts or else we risk racing with the interrupt
1736 * based handler.
1737 */
1738 if (is_real_interrupt(up->port.irq)) {
1739 ier = serial_in(up, UART_IER);
1740 serial_out(up, UART_IER, 0);
1741 }
1da177e4 1742
40b36daa
AW		 1743 iir = serial_in(up, UART_IIR);
1744
1745 /*
1746 * This should be a safe test for anyone who doesn't trust the
1747 * IIR bits on their UART, but it's specifically designed for
1748 * the "Diva" UART used on the management processor on many HP
1749 * ia64 and parisc boxes.
1750 */
ad4c2aa6
CM		 1751 spin_lock_irqsave(&up->port.lock, flags);
1752 lsr = serial_in(up, UART_LSR);
1753 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1754 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 1755 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1756 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
ad4c2aa6 1757 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1758 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1759 iir |= UART_IIR_THRI;
1760 }
1761
1762 if (!(iir & UART_IIR_NO_INT))
1763 serial8250_handle_port(up);
1764
1765 if (is_real_interrupt(up->port.irq))
1766 serial_out(up, UART_IER, ier);
1767
1768 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1769 mod_timer(&up->timer,
1770 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1771}
1772
1773static unsigned int serial8250_tx_empty(struct uart_port *port)
1774{
1775 struct uart_8250_port *up = (struct uart_8250_port *)port;
1776 unsigned long flags;
ad4c2aa6 1777 unsigned int lsr;
1da177e4
LT		 1778
1779 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1780 lsr = serial_in(up, UART_LSR);
1781 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1782 spin_unlock_irqrestore(&up->port.lock, flags);
1783
ad4c2aa6 1784 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1da177e4
LT		 1785}
1786
1787static unsigned int serial8250_get_mctrl(struct uart_port *port)
1788{
1789 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1790 unsigned int status;
1da177e4
LT		 1791 unsigned int ret;
1792
2af7cd68 1793 status = check_modem_status(up);
1da177e4
LT		 1794
1795 ret = 0;
1796 if (status & UART_MSR_DCD)
1797 ret |= TIOCM_CAR;
1798 if (status & UART_MSR_RI)
1799 ret |= TIOCM_RNG;
1800 if (status & UART_MSR_DSR)
1801 ret |= TIOCM_DSR;
1802 if (status & UART_MSR_CTS)
1803 ret |= TIOCM_CTS;
1804 return ret;
1805}
1806
1807static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1808{
1809 struct uart_8250_port *up = (struct uart_8250_port *)port;
1810 unsigned char mcr = 0;
1811
1812 if (mctrl & TIOCM_RTS)
1813 mcr |= UART_MCR_RTS;
1814 if (mctrl & TIOCM_DTR)
1815 mcr |= UART_MCR_DTR;
1816 if (mctrl & TIOCM_OUT1)
1817 mcr |= UART_MCR_OUT1;
1818 if (mctrl & TIOCM_OUT2)
1819 mcr |= UART_MCR_OUT2;
1820 if (mctrl & TIOCM_LOOP)
1821 mcr |= UART_MCR_LOOP;
1822
1823 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1824
1825 serial_out(up, UART_MCR, mcr);
1826}
1827
1828static void serial8250_break_ctl(struct uart_port *port, int break_state)
1829{
1830 struct uart_8250_port *up = (struct uart_8250_port *)port;
1831 unsigned long flags;
1832
1833 spin_lock_irqsave(&up->port.lock, flags);
1834 if (break_state == -1)
1835 up->lcr |= UART_LCR_SBC;
1836 else
1837 up->lcr &= ~UART_LCR_SBC;
1838 serial_out(up, UART_LCR, up->lcr);
1839 spin_unlock_irqrestore(&up->port.lock, flags);
1840}
1841
40b36daa
AW		 1842#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1843
1844/*
1845 * Wait for transmitter & holding register to empty
1846 */
b5d674ab 1847static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1848{
1849 unsigned int status, tmout = 10000;
1850
1851 /* Wait up to 10ms for the character(s) to be sent. */
1852 do {
1853 status = serial_in(up, UART_LSR);
1854
ad4c2aa6 1855 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1856
1857 if (--tmout == 0)
1858 break;
1859 udelay(1);
1860 } while ((status & bits) != bits);
1861
1862 /* Wait up to 1s for flow control if necessary */
1863 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1864 unsigned int tmout;
1865 for (tmout = 1000000; tmout; tmout--) {
1866 unsigned int msr = serial_in(up, UART_MSR);
1867 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1868 if (msr & UART_MSR_CTS)
1869 break;
40b36daa
AW		 1870 udelay(1);
1871 touch_nmi_watchdog();
1872 }
1873 }
1874}
1875
f2d937f3
JW		 1876#ifdef CONFIG_CONSOLE_POLL
1877/*
1878 * Console polling routines for writing and reading from the uart while
1879 * in an interrupt or debug context.
1880 */
1881
1882static int serial8250_get_poll_char(struct uart_port *port)
1883{
1884 struct uart_8250_port *up = (struct uart_8250_port *)port;
1885 unsigned char lsr = serial_inp(up, UART_LSR);
1886
1887 while (!(lsr & UART_LSR_DR))
1888 lsr = serial_inp(up, UART_LSR);
1889
1890 return serial_inp(up, UART_RX);
1891}
1892
1893
1894static void serial8250_put_poll_char(struct uart_port *port,
1895 unsigned char c)
1896{
1897 unsigned int ier;
1898 struct uart_8250_port *up = (struct uart_8250_port *)port;
1899
1900 /*
1901 * First save the IER then disable the interrupts
1902 */
1903 ier = serial_in(up, UART_IER);
1904 if (up->capabilities & UART_CAP_UUE)
1905 serial_out(up, UART_IER, UART_IER_UUE);
1906 else
1907 serial_out(up, UART_IER, 0);
1908
1909 wait_for_xmitr(up, BOTH_EMPTY);
1910 /*
1911 * Send the character out.
1912 * If a LF, also do CR...
1913 */
1914 serial_out(up, UART_TX, c);
1915 if (c == 10) {
1916 wait_for_xmitr(up, BOTH_EMPTY);
1917 serial_out(up, UART_TX, 13);
1918 }
1919
1920 /*
1921 * Finally, wait for transmitter to become empty
1922 * and restore the IER
1923 */
1924 wait_for_xmitr(up, BOTH_EMPTY);
1925 serial_out(up, UART_IER, ier);
1926}
1927
1928#endif /* CONFIG_CONSOLE_POLL */
1929
1da177e4
LT		 1930static int serial8250_startup(struct uart_port *port)
1931{
1932 struct uart_8250_port *up = (struct uart_8250_port *)port;
1933 unsigned long flags;
55d3b282 1934 unsigned char lsr, iir;
1da177e4
LT		 1935 int retval;
1936
1937 up->capabilities = uart_config[up->port.type].flags;
1938 up->mcr = 0;
1939
1940 if (up->port.type == PORT_16C950) {
1941 /* Wake up and initialize UART */
1942 up->acr = 0;
1943 serial_outp(up, UART_LCR, 0xBF);
1944 serial_outp(up, UART_EFR, UART_EFR_ECB);
1945 serial_outp(up, UART_IER, 0);
1946 serial_outp(up, UART_LCR, 0);
1947 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1948 serial_outp(up, UART_LCR, 0xBF);
1949 serial_outp(up, UART_EFR, UART_EFR_ECB);
1950 serial_outp(up, UART_LCR, 0);
1951 }
1952
1953#ifdef CONFIG_SERIAL_8250_RSA
1954 /*
1955 * If this is an RSA port, see if we can kick it up to the
1956 * higher speed clock.
1957 */
1958 enable_rsa(up);
1959#endif
1960
1961 /*
1962 * Clear the FIFO buffers and disable them.
7f927fcc 1963 * (they will be reenabled in set_termios())
1da177e4
LT		 1964 */
1965 serial8250_clear_fifos(up);
1966
1967 /*
1968 * Clear the interrupt registers.
1969 */
1970 (void) serial_inp(up, UART_LSR);
1971 (void) serial_inp(up, UART_RX);
1972 (void) serial_inp(up, UART_IIR);
1973 (void) serial_inp(up, UART_MSR);
1974
1975 /*
1976 * At this point, there's no way the LSR could still be 0xff;
1977 * if it is, then bail out, because there's likely no UART
1978 * here.
1979 */
1980 if (!(up->port.flags & UPF_BUGGY_UART) &&
1981 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1982 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1983 serial_index(&up->port));
1da177e4
LT		 1984 return -ENODEV;
1985 }
1986
1987 /*
1988 * For a XR16C850, we need to set the trigger levels
1989 */
1990 if (up->port.type == PORT_16850) {
1991 unsigned char fctr;
1992
1993 serial_outp(up, UART_LCR, 0xbf);
1994
1995 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1996 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1997 serial_outp(up, UART_TRG, UART_TRG_96);
1998 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1999 serial_outp(up, UART_TRG, UART_TRG_96);
2000
2001 serial_outp(up, UART_LCR, 0);
2002 }
2003
40b36daa 2004 if (is_real_interrupt(up->port.irq)) {
01c194d9 2005 unsigned char iir1;
40b36daa
AW		 2006 /*
2007 * Test for UARTs that do not reassert THRE when the
2008 * transmitter is idle and the interrupt has already
2009 * been cleared. Real 16550s should always reassert
2010 * this interrupt whenever the transmitter is idle and
2011 * the interrupt is enabled. Delays are necessary to
2012 * allow register changes to become visible.
2013 */
c389d27b 2014 spin_lock_irqsave(&up->port.lock, flags);
768aec0b
AV		 2015 if (up->port.flags & UPF_SHARE_IRQ)
2016 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2017
2018 wait_for_xmitr(up, UART_LSR_THRE);
2019 serial_out_sync(up, UART_IER, UART_IER_THRI);
2020 udelay(1); /* allow THRE to set */
01c194d9 2021 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2022 serial_out(up, UART_IER, 0);
2023 serial_out_sync(up, UART_IER, UART_IER_THRI);
2024 udelay(1); /* allow a working UART time to re-assert THRE */
2025 iir = serial_in(up, UART_IIR);
2026 serial_out(up, UART_IER, 0);
2027
768aec0b
AV		 2028 if (up->port.flags & UPF_SHARE_IRQ)
2029 enable_irq(up->port.irq);
c389d27b 2030 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2031
2032 /*
2033 * If the interrupt is not reasserted, setup a timer to
2034 * kick the UART on a regular basis.
2035 */
01c194d9 2036 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2037 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2038 pr_debug("ttyS%d - using backup timer\n",
2039 serial_index(port));
40b36daa
AW		 2040 }
2041 }
2042
363f66fe
WN		 2043 /*
2044 * The above check will only give an accurate result the first time
2045 * the port is opened so this value needs to be preserved.
2046 */
2047 if (up->bugs & UART_BUG_THRE) {
2048 up->timer.function = serial8250_backup_timeout;
2049 up->timer.data = (unsigned long)up;
2050 mod_timer(&up->timer, jiffies +
2051 poll_timeout(up->port.timeout) + HZ / 5);
2052 }
2053
1da177e4
LT		 2054 /*
2055 * If the "interrupt" for this port doesn't correspond with any
2056 * hardware interrupt, we use a timer-based system. The original
2057 * driver used to do this with IRQ0.
2058 */
2059 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2060 up->timer.data = (unsigned long)up;
40b36daa 2061 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 2062 } else {
2063 retval = serial_link_irq_chain(up);
2064 if (retval)
2065 return retval;
2066 }
2067
2068 /*
2069 * Now, initialize the UART
2070 */
2071 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2072
2073 spin_lock_irqsave(&up->port.lock, flags);
2074 if (up->port.flags & UPF_FOURPORT) {
2075 if (!is_real_interrupt(up->port.irq))
2076 up->port.mctrl |= TIOCM_OUT1;
2077 } else
2078 /*
2079 * Most PC uarts need OUT2 raised to enable interrupts.
2080 */
2081 if (is_real_interrupt(up->port.irq))
2082 up->port.mctrl |= TIOCM_OUT2;
2083
2084 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2085
b6adea33
MCC		 2086 /* Serial over Lan (SoL) hack:
2087 Intel 8257x Gigabit ethernet chips have a
2088 16550 emulation, to be used for Serial Over Lan.
2089 Those chips take a longer time than a normal
2090 serial device to signalize that a transmission
2091 data was queued. Due to that, the above test generally
2092 fails. One solution would be to delay the reading of
2093 iir. However, this is not reliable, since the timeout
2094 is variable. So, let's just don't test if we receive
2095 TX irq. This way, we'll never enable UART_BUG_TXEN.
2096 */
2097 if (up->port.flags & UPF_NO_TXEN_TEST)
2098 goto dont_test_tx_en;
2099
55d3b282
RK		 2100 /*
2101 * Do a quick test to see if we receive an
2102 * interrupt when we enable the TX irq.
2103 */
2104 serial_outp(up, UART_IER, UART_IER_THRI);
2105 lsr = serial_in(up, UART_LSR);
2106 iir = serial_in(up, UART_IIR);
2107 serial_outp(up, UART_IER, 0);
2108
2109 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2110 if (!(up->bugs & UART_BUG_TXEN)) {
2111 up->bugs |= UART_BUG_TXEN;
55d3b282 2112 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2113 serial_index(port));
55d3b282
RK		 2114 }
2115 } else {
67f7654e 2116 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2117 }
2118
b6adea33 2119dont_test_tx_en:
1da177e4
LT		 2120 spin_unlock_irqrestore(&up->port.lock, flags);
2121
ad4c2aa6
CM		 2122 /*
2123 * Clear the interrupt registers again for luck, and clear the
2124 * saved flags to avoid getting false values from polling
2125 * routines or the previous session.
2126 */
2127 serial_inp(up, UART_LSR);
2128 serial_inp(up, UART_RX);
2129 serial_inp(up, UART_IIR);
2130 serial_inp(up, UART_MSR);
2131 up->lsr_saved_flags = 0;
2132 up->msr_saved_flags = 0;
2133
1da177e4
LT		 2134 /*
2135 * Finally, enable interrupts. Note: Modem status interrupts
2136 * are set via set_termios(), which will be occurring imminently
2137 * anyway, so we don't enable them here.
2138 */
2139 up->ier = UART_IER_RLSI | UART_IER_RDI;
2140 serial_outp(up, UART_IER, up->ier);
2141
2142 if (up->port.flags & UPF_FOURPORT) {
2143 unsigned int icp;
2144 /*
2145 * Enable interrupts on the AST Fourport board
2146 */
2147 icp = (up->port.iobase & 0xfe0) | 0x01f;
2148 outb_p(0x80, icp);
2149 (void) inb_p(icp);
2150 }
2151
1da177e4
LT		 2152 return 0;
2153}
2154
2155static void serial8250_shutdown(struct uart_port *port)
2156{
2157 struct uart_8250_port *up = (struct uart_8250_port *)port;
2158 unsigned long flags;
2159
2160 /*
2161 * Disable interrupts from this port
2162 */
2163 up->ier = 0;
2164 serial_outp(up, UART_IER, 0);
2165
2166 spin_lock_irqsave(&up->port.lock, flags);
2167 if (up->port.flags & UPF_FOURPORT) {
2168 /* reset interrupts on the AST Fourport board */
2169 inb((up->port.iobase & 0xfe0) | 0x1f);
2170 up->port.mctrl |= TIOCM_OUT1;
2171 } else
2172 up->port.mctrl &= ~TIOCM_OUT2;
2173
2174 serial8250_set_mctrl(&up->port, up->port.mctrl);
2175 spin_unlock_irqrestore(&up->port.lock, flags);
2176
2177 /*
2178 * Disable break condition and FIFOs
2179 */
2180 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2181 serial8250_clear_fifos(up);
2182
2183#ifdef CONFIG_SERIAL_8250_RSA
2184 /*
2185 * Reset the RSA board back to 115kbps compat mode.
2186 */
2187 disable_rsa(up);
2188#endif
2189
2190 /*
2191 * Read data port to reset things, and then unlink from
2192 * the IRQ chain.
2193 */
2194 (void) serial_in(up, UART_RX);
2195
40b36daa
AW		 2196 del_timer_sync(&up->timer);
2197 up->timer.function = serial8250_timeout;
2198 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2199 serial_unlink_irq_chain(up);
2200}
2201
2202static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2203{
2204 unsigned int quot;
2205
2206 /*
2207 * Handle magic divisors for baud rates above baud_base on
2208 * SMSC SuperIO chips.
2209 */
2210 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2211 baud == (port->uartclk/4))
2212 quot = 0x8001;
2213 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2214 baud == (port->uartclk/8))
2215 quot = 0x8002;
2216 else
2217 quot = uart_get_divisor(port, baud);
2218
2219 return quot;
2220}
2221
2222static void
606d099c
AC		 2223serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2224 struct ktermios *old)
1da177e4
LT		 2225{
2226 struct uart_8250_port *up = (struct uart_8250_port *)port;
2227 unsigned char cval, fcr = 0;
2228 unsigned long flags;
2229 unsigned int baud, quot;
2230
2231 switch (termios->c_cflag & CSIZE) {
2232 case CS5:
0a8b80c5 2233 cval = UART_LCR_WLEN5;
1da177e4
LT		 2234 break;
2235 case CS6:
0a8b80c5 2236 cval = UART_LCR_WLEN6;
1da177e4
LT		 2237 break;
2238 case CS7:
0a8b80c5 2239 cval = UART_LCR_WLEN7;
1da177e4
LT		 2240 break;
2241 default:
2242 case CS8:
0a8b80c5 2243 cval = UART_LCR_WLEN8;
1da177e4
LT		 2244 break;
2245 }
2246
2247 if (termios->c_cflag & CSTOPB)
0a8b80c5 2248 cval |= UART_LCR_STOP;
1da177e4
LT		 2249 if (termios->c_cflag & PARENB)
2250 cval |= UART_LCR_PARITY;
2251 if (!(termios->c_cflag & PARODD))
2252 cval |= UART_LCR_EPAR;
2253#ifdef CMSPAR
2254 if (termios->c_cflag & CMSPAR)
2255 cval |= UART_LCR_SPAR;
2256#endif
2257
2258 /*
2259 * Ask the core to calculate the divisor for us.
2260 */
bd71c182 2261 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1da177e4
LT		 2262 quot = serial8250_get_divisor(port, baud);
2263
2264 /*
4ba5e35d 2265 * Oxford Semi 952 rev B workaround
1da177e4 2266 */
4ba5e35d 2267 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2268 quot++;
1da177e4
LT		 2269
2270 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2271 if (baud < 2400)
2272 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2273 else
2274 fcr = uart_config[up->port.type].fcr;
2275 }
2276
2277 /*
2278 * MCR-based auto flow control. When AFE is enabled, RTS will be
2279 * deasserted when the receive FIFO contains more characters than
2280 * the trigger, or the MCR RTS bit is cleared. In the case where
2281 * the remote UART is not using CTS auto flow control, we must
2282 * have sufficient FIFO entries for the latency of the remote
2283 * UART to respond. IOW, at least 32 bytes of FIFO.
2284 */
2285 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2286 up->mcr &= ~UART_MCR_AFE;
2287 if (termios->c_cflag & CRTSCTS)
2288 up->mcr |= UART_MCR_AFE;
2289 }
2290
2291 /*
2292 * Ok, we're now changing the port state. Do it with
2293 * interrupts disabled.
2294 */
2295 spin_lock_irqsave(&up->port.lock, flags);
2296
2297 /*
2298 * Update the per-port timeout.
2299 */
2300 uart_update_timeout(port, termios->c_cflag, baud);
2301
2302 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2303 if (termios->c_iflag & INPCK)
2304 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2305 if (termios->c_iflag & (BRKINT | PARMRK))
2306 up->port.read_status_mask |= UART_LSR_BI;
2307
2308 /*
2309 * Characteres to ignore
2310 */
2311 up->port.ignore_status_mask = 0;
2312 if (termios->c_iflag & IGNPAR)
2313 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2314 if (termios->c_iflag & IGNBRK) {
2315 up->port.ignore_status_mask |= UART_LSR_BI;
2316 /*
2317 * If we're ignoring parity and break indicators,
2318 * ignore overruns too (for real raw support).
2319 */
2320 if (termios->c_iflag & IGNPAR)
2321 up->port.ignore_status_mask |= UART_LSR_OE;
2322 }
2323
2324 /*
2325 * ignore all characters if CREAD is not set
2326 */
2327 if ((termios->c_cflag & CREAD) == 0)
2328 up->port.ignore_status_mask |= UART_LSR_DR;
2329
2330 /*
2331 * CTS flow control flag and modem status interrupts
2332 */
2333 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2334 if (!(up->bugs & UART_BUG_NOMSR) &&
2335 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2336 up->ier |= UART_IER_MSI;
2337 if (up->capabilities & UART_CAP_UUE)
2338 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2339
2340 serial_out(up, UART_IER, up->ier);
2341
2342 if (up->capabilities & UART_CAP_EFR) {
2343 unsigned char efr = 0;
2344 /*
2345 * TI16C752/Startech hardware flow control. FIXME:
2346 * - TI16C752 requires control thresholds to be set.
2347 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2348 */
2349 if (termios->c_cflag & CRTSCTS)
2350 efr |= UART_EFR_CTS;
2351
2352 serial_outp(up, UART_LCR, 0xBF);
2353 serial_outp(up, UART_EFR, efr);
2354 }
2355
f2eda27d 2356#ifdef CONFIG_ARCH_OMAP
255341c6 2357 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2358 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2359 if (baud == 115200) {
2360 quot = 1;
2361 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2362 } else
2363 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2364 }
2365#endif
2366
1da177e4
LT		 2367 if (up->capabilities & UART_NATSEMI) {
2368 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2369 serial_outp(up, UART_LCR, 0xe0);
2370 } else {
2371 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2372 }
2373
b32b19b8 2374 serial_dl_write(up, quot);
1da177e4
LT		 2375
2376 /*
2377 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2378 * is written without DLAB set, this mode will be disabled.
2379 */
2380 if (up->port.type == PORT_16750)
2381 serial_outp(up, UART_FCR, fcr);
2382
2383 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2384 up->lcr = cval; /* Save LCR */
2385 if (up->port.type != PORT_16750) {
2386 if (fcr & UART_FCR_ENABLE_FIFO) {
2387 /* emulated UARTs (Lucent Venus 167x) need two steps */
2388 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2389 }
2390 serial_outp(up, UART_FCR, fcr); /* set fcr */
2391 }
2392 serial8250_set_mctrl(&up->port, up->port.mctrl);
2393 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2394 /* Don't rewrite B0 */
2395 if (tty_termios_baud_rate(termios))
2396 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2397}
2398
2399static void
2400serial8250_pm(struct uart_port *port, unsigned int state,
2401 unsigned int oldstate)
2402{
2403 struct uart_8250_port *p = (struct uart_8250_port *)port;
2404
2405 serial8250_set_sleep(p, state != 0);
2406
2407 if (p->pm)
2408 p->pm(port, state, oldstate);
2409}
2410
f2eda27d
RK		 2411static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2412{
2413 if (pt->port.iotype == UPIO_AU)
2414 return 0x100000;
2415#ifdef CONFIG_ARCH_OMAP
2416 if (is_omap_port(pt))
2417 return 0x16 << pt->port.regshift;
2418#endif
2419 return 8 << pt->port.regshift;
2420}
2421
1da177e4
LT		 2422/*
2423 * Resource handling.
2424 */
2425static int serial8250_request_std_resource(struct uart_8250_port *up)
2426{
f2eda27d 2427 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2428 int ret = 0;
2429
2430 switch (up->port.iotype) {
85835f44 2431 case UPIO_AU:
0b30d668
SS		 2432 case UPIO_TSI:
2433 case UPIO_MEM32:
1da177e4 2434 case UPIO_MEM:
beab697a 2435 case UPIO_DWAPB:
1da177e4
LT		 2436 if (!up->port.mapbase)
2437 break;
2438
2439 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2440 ret = -EBUSY;
2441 break;
2442 }
2443
2444 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2445 up->port.membase = ioremap_nocache(up->port.mapbase,
2446 size);
1da177e4
LT		 2447 if (!up->port.membase) {
2448 release_mem_region(up->port.mapbase, size);
2449 ret = -ENOMEM;
2450 }
2451 }
2452 break;
2453
2454 case UPIO_HUB6:
2455 case UPIO_PORT:
2456 if (!request_region(up->port.iobase, size, "serial"))
2457 ret = -EBUSY;
2458 break;
2459 }
2460 return ret;
2461}
2462
2463static void serial8250_release_std_resource(struct uart_8250_port *up)
2464{
f2eda27d 2465 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2466
2467 switch (up->port.iotype) {
85835f44 2468 case UPIO_AU:
0b30d668
SS		 2469 case UPIO_TSI:
2470 case UPIO_MEM32:
1da177e4 2471 case UPIO_MEM:
beab697a 2472 case UPIO_DWAPB:
1da177e4
LT		 2473 if (!up->port.mapbase)
2474 break;
2475
2476 if (up->port.flags & UPF_IOREMAP) {
2477 iounmap(up->port.membase);
2478 up->port.membase = NULL;
2479 }
2480
2481 release_mem_region(up->port.mapbase, size);
2482 break;
2483
2484 case UPIO_HUB6:
2485 case UPIO_PORT:
2486 release_region(up->port.iobase, size);
2487 break;
2488 }
2489}
2490
2491static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2492{
2493 unsigned long start = UART_RSA_BASE << up->port.regshift;
2494 unsigned int size = 8 << up->port.regshift;
0b30d668 2495 int ret = -EINVAL;
1da177e4
LT		 2496
2497 switch (up->port.iotype) {
1da177e4
LT		 2498 case UPIO_HUB6:
2499 case UPIO_PORT:
2500 start += up->port.iobase;
0b30d668
SS		 2501 if (request_region(start, size, "serial-rsa"))
2502 ret = 0;
2503 else
1da177e4
LT		 2504 ret = -EBUSY;
2505 break;
2506 }
2507
2508 return ret;
2509}
2510
2511static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2512{
2513 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2514 unsigned int size = 8 << up->port.regshift;
2515
2516 switch (up->port.iotype) {
1da177e4
LT		 2517 case UPIO_HUB6:
2518 case UPIO_PORT:
2519 release_region(up->port.iobase + offset, size);
2520 break;
2521 }
2522}
2523
2524static void serial8250_release_port(struct uart_port *port)
2525{
2526 struct uart_8250_port *up = (struct uart_8250_port *)port;
2527
2528 serial8250_release_std_resource(up);
2529 if (up->port.type == PORT_RSA)
2530 serial8250_release_rsa_resource(up);
2531}
2532
2533static int serial8250_request_port(struct uart_port *port)
2534{
2535 struct uart_8250_port *up = (struct uart_8250_port *)port;
2536 int ret = 0;
2537
2538 ret = serial8250_request_std_resource(up);
2539 if (ret == 0 && up->port.type == PORT_RSA) {
2540 ret = serial8250_request_rsa_resource(up);
2541 if (ret < 0)
2542 serial8250_release_std_resource(up);
2543 }
2544
2545 return ret;
2546}
2547
2548static void serial8250_config_port(struct uart_port *port, int flags)
2549{
2550 struct uart_8250_port *up = (struct uart_8250_port *)port;
2551 int probeflags = PROBE_ANY;
2552 int ret;
2553
1da177e4
LT		 2554 /*
2555 * Find the region that we can probe for. This in turn
2556 * tells us whether we can probe for the type of port.
2557 */
2558 ret = serial8250_request_std_resource(up);
2559 if (ret < 0)
2560 return;
2561
2562 ret = serial8250_request_rsa_resource(up);
2563 if (ret < 0)
2564 probeflags &= ~PROBE_RSA;
2565
2566 if (flags & UART_CONFIG_TYPE)
2567 autoconfig(up, probeflags);
2568 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2569 autoconfig_irq(up);
2570
2571 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2572 serial8250_release_rsa_resource(up);
2573 if (up->port.type == PORT_UNKNOWN)
2574 serial8250_release_std_resource(up);
2575}
2576
2577static int
2578serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2579{
a62c4133 2580 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2581 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2582 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2583 ser->type == PORT_STARTECH)
2584 return -EINVAL;
2585 return 0;
2586}
2587
2588static const char *
2589serial8250_type(struct uart_port *port)
2590{
2591 int type = port->type;
2592
2593 if (type >= ARRAY_SIZE(uart_config))
2594 type = 0;
2595 return uart_config[type].name;
2596}
2597
2598static struct uart_ops serial8250_pops = {
2599 .tx_empty = serial8250_tx_empty,
2600 .set_mctrl = serial8250_set_mctrl,
2601 .get_mctrl = serial8250_get_mctrl,
2602 .stop_tx = serial8250_stop_tx,
2603 .start_tx = serial8250_start_tx,
2604 .stop_rx = serial8250_stop_rx,
2605 .enable_ms = serial8250_enable_ms,
2606 .break_ctl = serial8250_break_ctl,
2607 .startup = serial8250_startup,
2608 .shutdown = serial8250_shutdown,
2609 .set_termios = serial8250_set_termios,
2610 .pm = serial8250_pm,
2611 .type = serial8250_type,
2612 .release_port = serial8250_release_port,
2613 .request_port = serial8250_request_port,
2614 .config_port = serial8250_config_port,
2615 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2616#ifdef CONFIG_CONSOLE_POLL
2617 .poll_get_char = serial8250_get_poll_char,
2618 .poll_put_char = serial8250_put_poll_char,
2619#endif
1da177e4
LT		 2620};
2621
2622static struct uart_8250_port serial8250_ports[UART_NR];
2623
2624static void __init serial8250_isa_init_ports(void)
2625{
2626 struct uart_8250_port *up;
2627 static int first = 1;
2628 int i;
2629
2630 if (!first)
2631 return;
2632 first = 0;
2633
a61c2d78 2634 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2635 struct uart_8250_port *up = &serial8250_ports[i];
2636
2637 up->port.line = i;
2638 spin_lock_init(&up->port.lock);
2639
2640 init_timer(&up->timer);
2641 up->timer.function = serial8250_timeout;
2642
2643 /*
2644 * ALPHA_KLUDGE_MCR needs to be killed.
2645 */
2646 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2647 up->mcr_force = ALPHA_KLUDGE_MCR;
2648
2649 up->port.ops = &serial8250_pops;
2650 }
2651
44454bcd 2652 for (i = 0, up = serial8250_ports;
a61c2d78 2653 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2654 i++, up++) {
2655 up->port.iobase = old_serial_port[i].port;
2656 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2657 up->port.uartclk = old_serial_port[i].baud_base * 16;
2658 up->port.flags = old_serial_port[i].flags;
2659 up->port.hub6 = old_serial_port[i].hub6;
2660 up->port.membase = old_serial_port[i].iomem_base;
2661 up->port.iotype = old_serial_port[i].io_type;
2662 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2663 set_io_from_upio(&up->port);
1da177e4
LT		 2664 if (share_irqs)
2665 up->port.flags |= UPF_SHARE_IRQ;
2666 }
2667}
2668
2669static void __init
2670serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2671{
2672 int i;
2673
2674 serial8250_isa_init_ports();
2675
a61c2d78 2676 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2677 struct uart_8250_port *up = &serial8250_ports[i];
2678
2679 up->port.dev = dev;
2680 uart_add_one_port(drv, &up->port);
2681 }
2682}
2683
2684#ifdef CONFIG_SERIAL_8250_CONSOLE
2685
d358788f
RK		 2686static void serial8250_console_putchar(struct uart_port *port, int ch)
2687{
2688 struct uart_8250_port *up = (struct uart_8250_port *)port;
2689
2690 wait_for_xmitr(up, UART_LSR_THRE);
2691 serial_out(up, UART_TX, ch);
2692}
2693
1da177e4
LT		 2694/*
2695 * Print a string to the serial port trying not to disturb
2696 * any possible real use of the port...
2697 *
2698 * The console_lock must be held when we get here.
2699 */
2700static void
2701serial8250_console_write(struct console *co, const char *s, unsigned int count)
2702{
2703 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2704 unsigned long flags;
1da177e4 2705 unsigned int ier;
d8a5a8d7 2706 int locked = 1;
1da177e4 2707
78512ece
AM		 2708 touch_nmi_watchdog();
2709
68aa2c0d
AM		 2710 local_irq_save(flags);
2711 if (up->port.sysrq) {
2712 /* serial8250_handle_port() already took the lock */
2713 locked = 0;
2714 } else if (oops_in_progress) {
2715 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2716 } else
68aa2c0d 2717 spin_lock(&up->port.lock);
d8a5a8d7 2718
1da177e4 2719 /*
dc7bf130 2720 * First save the IER then disable the interrupts
1da177e4
LT		 2721 */
2722 ier = serial_in(up, UART_IER);
2723
2724 if (up->capabilities & UART_CAP_UUE)
2725 serial_out(up, UART_IER, UART_IER_UUE);
2726 else
2727 serial_out(up, UART_IER, 0);
2728
d358788f 2729 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2730
2731 /*
2732 * Finally, wait for transmitter to become empty
2733 * and restore the IER
2734 */
f91a3715 2735 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2736 serial_out(up, UART_IER, ier);
d8a5a8d7 2737
ad4c2aa6
CM		 2738 /*
2739 * The receive handling will happen properly because the
2740 * receive ready bit will still be set; it is not cleared
2741 * on read. However, modem control will not, we must
2742 * call it if we have saved something in the saved flags
2743 * while processing with interrupts off.
2744 */
2745 if (up->msr_saved_flags)
2746 check_modem_status(up);
2747
d8a5a8d7 2748 if (locked)
68aa2c0d
AM		 2749 spin_unlock(&up->port.lock);
2750 local_irq_restore(flags);
1da177e4
LT		 2751}
2752
118c0ace 2753static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2754{
2755 struct uart_port *port;
2756 int baud = 9600;
2757 int bits = 8;
2758 int parity = 'n';
2759 int flow = 'n';
2760
2761 /*
2762 * Check whether an invalid uart number has been specified, and
2763 * if so, search for the first available port that does have
2764 * console support.
2765 */
a61c2d78 2766 if (co->index >= nr_uarts)
1da177e4
LT		 2767 co->index = 0;
2768 port = &serial8250_ports[co->index].port;
2769 if (!port->iobase && !port->membase)
2770 return -ENODEV;
2771
2772 if (options)
2773 uart_parse_options(options, &baud, &parity, &bits, &flow);
2774
2775 return uart_set_options(port, co, baud, parity, bits, flow);
2776}
2777
b6b1d877 2778static int serial8250_console_early_setup(void)
18a8bd94
YL		 2779{
2780 return serial8250_find_port_for_earlycon();
2781}
2782
1da177e4
LT		 2783static struct console serial8250_console = {
2784 .name = "ttyS",
2785 .write = serial8250_console_write,
2786 .device = uart_console_device,
2787 .setup = serial8250_console_setup,
18a8bd94 2788 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2789 .flags = CON_PRINTBUFFER,
2790 .index = -1,
2791 .data = &serial8250_reg,
2792};
2793
2794static int __init serial8250_console_init(void)
2795{
05d81d22
EB		 2796 if (nr_uarts > UART_NR)
2797 nr_uarts = UART_NR;
2798
1da177e4
LT		 2799 serial8250_isa_init_ports();
2800 register_console(&serial8250_console);
2801 return 0;
2802}
2803console_initcall(serial8250_console_init);
2804
18a8bd94 2805int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2806{
2807 int line;
2808 struct uart_port *port;
2809
a61c2d78 2810 for (line = 0; line < nr_uarts; line++) {
1da177e4 2811 port = &serial8250_ports[line].port;
50aec3b5 2812 if (uart_match_port(p, port))
1da177e4
LT		 2813 return line;
2814 }
2815 return -ENODEV;
2816}
2817
1da177e4
LT		 2818#define SERIAL8250_CONSOLE &serial8250_console
2819#else
2820#define SERIAL8250_CONSOLE NULL
2821#endif
2822
2823static struct uart_driver serial8250_reg = {
2824 .owner = THIS_MODULE,
2825 .driver_name = "serial",
1da177e4
LT		 2826 .dev_name = "ttyS",
2827 .major = TTY_MAJOR,
2828 .minor = 64,
1da177e4
LT		 2829 .cons = SERIAL8250_CONSOLE,
2830};
2831
d856c666
RK		 2832/*
2833 * early_serial_setup - early registration for 8250 ports
2834 *
2835 * Setup an 8250 port structure prior to console initialisation. Use
2836 * after console initialisation will cause undefined behaviour.
2837 */
1da177e4
LT		 2838int __init early_serial_setup(struct uart_port *port)
2839{
b430428a
DD		 2840 struct uart_port *p;
2841
1da177e4
LT		 2842 if (port->line >= ARRAY_SIZE(serial8250_ports))
2843 return -ENODEV;
2844
2845 serial8250_isa_init_ports();
b430428a
DD		 2846 p = &serial8250_ports[port->line].port;
2847 p->iobase = port->iobase;
2848 p->membase = port->membase;
2849 p->irq = port->irq;
2850 p->uartclk = port->uartclk;
2851 p->fifosize = port->fifosize;
2852 p->regshift = port->regshift;
2853 p->iotype = port->iotype;
2854 p->flags = port->flags;
2855 p->mapbase = port->mapbase;
2856 p->private_data = port->private_data;
125c97d8
HD		 2857 p->type = port->type;
2858 p->line = port->line;
7d6a07d1
DD		 2859
2860 set_io_from_upio(p);
2861 if (port->serial_in)
2862 p->serial_in = port->serial_in;
2863 if (port->serial_out)
2864 p->serial_out = port->serial_out;
2865
1da177e4
LT		 2866 return 0;
2867}
2868
2869/**
2870 * serial8250_suspend_port - suspend one serial port
2871 * @line: serial line number
1da177e4
LT		 2872 *
2873 * Suspend one serial port.
2874 */
2875void serial8250_suspend_port(int line)
2876{
2877 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2878}
2879
2880/**
2881 * serial8250_resume_port - resume one serial port
2882 * @line: serial line number
1da177e4
LT		 2883 *
2884 * Resume one serial port.
2885 */
2886void serial8250_resume_port(int line)
2887{
b5b82df6
DW		 2888 struct uart_8250_port *up = &serial8250_ports[line];
2889
2890 if (up->capabilities & UART_NATSEMI) {
2891 unsigned char tmp;
2892
2893 /* Ensure it's still in high speed mode */
2894 serial_outp(up, UART_LCR, 0xE0);
2895
2896 tmp = serial_in(up, 0x04); /* EXCR2 */
2897 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2898 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2899 serial_outp(up, 0x04, tmp);
2900
2901 serial_outp(up, UART_LCR, 0);
2902 }
2903 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2904}
2905
2906/*
2907 * Register a set of serial devices attached to a platform device. The
2908 * list is terminated with a zero flags entry, which means we expect
2909 * all entries to have at least UPF_BOOT_AUTOCONF set.
2910 */
3ae5eaec 2911static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2912{
3ae5eaec 2913 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2914 struct uart_port port;
ec9f47cd 2915 int ret, i;
1da177e4
LT		 2916
2917 memset(&port, 0, sizeof(struct uart_port));
2918
ec9f47cd 2919 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2920 port.iobase = p->iobase;
2921 port.membase = p->membase;
2922 port.irq = p->irq;
2923 port.uartclk = p->uartclk;
2924 port.regshift = p->regshift;
2925 port.iotype = p->iotype;
2926 port.flags = p->flags;
2927 port.mapbase = p->mapbase;
2928 port.hub6 = p->hub6;
2929 port.private_data = p->private_data;
8e23fcc8 2930 port.type = p->type;
7d6a07d1
DD		 2931 port.serial_in = p->serial_in;
2932 port.serial_out = p->serial_out;
74a19741 2933 port.dev = &dev->dev;
1da177e4
LT		 2934 if (share_irqs)
2935 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2936 ret = serial8250_register_port(&port);
2937 if (ret < 0) {
3ae5eaec 2938 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2939 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2940 p->iobase, (unsigned long long)p->mapbase,
2941 p->irq, ret);
ec9f47cd 2942 }
1da177e4
LT		 2943 }
2944 return 0;
2945}
2946
2947/*
2948 * Remove serial ports registered against a platform device.
2949 */
3ae5eaec 2950static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2951{
2952 int i;
2953
a61c2d78 2954 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2955 struct uart_8250_port *up = &serial8250_ports[i];
2956
3ae5eaec 2957 if (up->port.dev == &dev->dev)
1da177e4
LT		 2958 serial8250_unregister_port(i);
2959 }
2960 return 0;
2961}
2962
3ae5eaec 2963static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2964{
2965 int i;
2966
1da177e4
LT		 2967 for (i = 0; i < UART_NR; i++) {
2968 struct uart_8250_port *up = &serial8250_ports[i];
2969
3ae5eaec 2970 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2971 uart_suspend_port(&serial8250_reg, &up->port);
2972 }
2973
2974 return 0;
2975}
2976
3ae5eaec 2977static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2978{
2979 int i;
2980
1da177e4
LT		 2981 for (i = 0; i < UART_NR; i++) {
2982 struct uart_8250_port *up = &serial8250_ports[i];
2983
3ae5eaec 2984 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 2985 serial8250_resume_port(i);
1da177e4
LT		 2986 }
2987
2988 return 0;
2989}
2990
3ae5eaec 2991static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2992 .probe = serial8250_probe,
2993 .remove = __devexit_p(serial8250_remove),
2994 .suspend = serial8250_suspend,
2995 .resume = serial8250_resume,
3ae5eaec
RK		 2996 .driver = {
2997 .name = "serial8250",
7493a314 2998 .owner = THIS_MODULE,
3ae5eaec 2999 },
1da177e4
LT		 3000};
3001
3002/*
3003 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3004 * in the table in include/asm/serial.h
3005 */
3006static struct platform_device *serial8250_isa_devs;
3007
3008/*
3009 * serial8250_register_port and serial8250_unregister_port allows for
3010 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3011 * modems and PCI multiport cards.
3012 */
f392ecfa 3013static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3014
3015static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3016{
3017 int i;
3018
3019 /*
3020 * First, find a port entry which matches.
3021 */
a61c2d78 3022 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3023 if (uart_match_port(&serial8250_ports[i].port, port))
3024 return &serial8250_ports[i];
3025
3026 /*
3027 * We didn't find a matching entry, so look for the first
3028 * free entry. We look for one which hasn't been previously
3029 * used (indicated by zero iobase).
3030 */
a61c2d78 3031 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3032 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3033 serial8250_ports[i].port.iobase == 0)
3034 return &serial8250_ports[i];
3035
3036 /*
3037 * That also failed. Last resort is to find any entry which
3038 * doesn't have a real port associated with it.
3039 */
a61c2d78 3040 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3041 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3042 return &serial8250_ports[i];
3043
3044 return NULL;
3045}
3046
3047/**
3048 * serial8250_register_port - register a serial port
3049 * @port: serial port template
3050 *
3051 * Configure the serial port specified by the request. If the
3052 * port exists and is in use, it is hung up and unregistered
3053 * first.
3054 *
3055 * The port is then probed and if necessary the IRQ is autodetected
3056 * If this fails an error is returned.
3057 *
3058 * On success the port is ready to use and the line number is returned.
3059 */
3060int serial8250_register_port(struct uart_port *port)
3061{
3062 struct uart_8250_port *uart;
3063 int ret = -ENOSPC;
3064
3065 if (port->uartclk == 0)
3066 return -EINVAL;
3067
f392ecfa 3068 mutex_lock(&serial_mutex);
1da177e4
LT		 3069
3070 uart = serial8250_find_match_or_unused(port);
3071 if (uart) {
3072 uart_remove_one_port(&serial8250_reg, &uart->port);
3073
74a19741
WN		 3074 uart->port.iobase = port->iobase;
3075 uart->port.membase = port->membase;
3076 uart->port.irq = port->irq;
3077 uart->port.uartclk = port->uartclk;
3078 uart->port.fifosize = port->fifosize;
3079 uart->port.regshift = port->regshift;
3080 uart->port.iotype = port->iotype;
3081 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3082 uart->port.mapbase = port->mapbase;
3083 uart->port.private_data = port->private_data;
1da177e4
LT		 3084 if (port->dev)
3085 uart->port.dev = port->dev;
8e23fcc8
DD		 3086
3087 if (port->flags & UPF_FIXED_TYPE) {
3088 uart->port.type = port->type;
3089 uart->port.fifosize = uart_config[port->type].fifo_size;
3090 uart->capabilities = uart_config[port->type].flags;
3091 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3092 }
3093
7d6a07d1
DD		 3094 set_io_from_upio(&uart->port);
3095 /* Possibly override default I/O functions. */
3096 if (port->serial_in)
3097 uart->port.serial_in = port->serial_in;
3098 if (port->serial_out)
3099 uart->port.serial_out = port->serial_out;
1da177e4
LT		 3100
3101 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3102 if (ret == 0)
3103 ret = uart->port.line;
3104 }
f392ecfa 3105 mutex_unlock(&serial_mutex);
1da177e4
LT		 3106
3107 return ret;
3108}
3109EXPORT_SYMBOL(serial8250_register_port);
3110
3111/**
3112 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3113 * @line: serial line number
3114 *
3115 * Remove one serial port. This may not be called from interrupt
3116 * context. We hand the port back to the our control.
3117 */
3118void serial8250_unregister_port(int line)
3119{
3120 struct uart_8250_port *uart = &serial8250_ports[line];
3121
f392ecfa 3122 mutex_lock(&serial_mutex);
1da177e4
LT		 3123 uart_remove_one_port(&serial8250_reg, &uart->port);
3124 if (serial8250_isa_devs) {
3125 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3126 uart->port.type = PORT_UNKNOWN;
3127 uart->port.dev = &serial8250_isa_devs->dev;
3128 uart_add_one_port(&serial8250_reg, &uart->port);
3129 } else {
3130 uart->port.dev = NULL;
3131 }
f392ecfa 3132 mutex_unlock(&serial_mutex);
1da177e4
LT		 3133}
3134EXPORT_SYMBOL(serial8250_unregister_port);
3135
3136static int __init serial8250_init(void)
3137{
25db8ad5 3138 int ret;
1da177e4 3139
a61c2d78
DJ		 3140 if (nr_uarts > UART_NR)
3141 nr_uarts = UART_NR;
3142
f1fb9bb8 3143 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3144 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3145 share_irqs ? "en" : "dis");
3146
b70ac771
DM		 3147#ifdef CONFIG_SPARC
3148 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3149#else
3150 serial8250_reg.nr = UART_NR;
1da177e4 3151 ret = uart_register_driver(&serial8250_reg);
b70ac771 3152#endif
1da177e4
LT		 3153 if (ret)
3154 goto out;
3155
7493a314
DT		 3156 serial8250_isa_devs = platform_device_alloc("serial8250",
3157 PLAT8250_DEV_LEGACY);
3158 if (!serial8250_isa_devs) {
3159 ret = -ENOMEM;
bc965a7f 3160 goto unreg_uart_drv;
1da177e4
LT		 3161 }
3162
7493a314
DT		 3163 ret = platform_device_add(serial8250_isa_devs);
3164 if (ret)
3165 goto put_dev;
3166
1da177e4
LT		 3167 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3168
bc965a7f
RK		 3169 ret = platform_driver_register(&serial8250_isa_driver);
3170 if (ret == 0)
3171 goto out;
1da177e4 3172
bc965a7f 3173 platform_device_del(serial8250_isa_devs);
25db8ad5 3174put_dev:
7493a314 3175 platform_device_put(serial8250_isa_devs);
25db8ad5 3176unreg_uart_drv:
b70ac771
DM		 3177#ifdef CONFIG_SPARC
3178 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3179#else
1da177e4 3180 uart_unregister_driver(&serial8250_reg);
b70ac771 3181#endif
25db8ad5 3182out:
1da177e4
LT		 3183 return ret;
3184}
3185
3186static void __exit serial8250_exit(void)
3187{
3188 struct platform_device *isa_dev = serial8250_isa_devs;
3189
3190 /*
3191 * This tells serial8250_unregister_port() not to re-register
3192 * the ports (thereby making serial8250_isa_driver permanently
3193 * in use.)
3194 */
3195 serial8250_isa_devs = NULL;
3196
3ae5eaec 3197 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3198 platform_device_unregister(isa_dev);
3199
b70ac771
DM		 3200#ifdef CONFIG_SPARC
3201 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3202#else
1da177e4 3203 uart_unregister_driver(&serial8250_reg);
b70ac771 3204#endif
1da177e4
LT		 3205}
3206
3207module_init(serial8250_init);
3208module_exit(serial8250_exit);
3209
3210EXPORT_SYMBOL(serial8250_suspend_port);
3211EXPORT_SYMBOL(serial8250_resume_port);
3212
3213MODULE_LICENSE("GPL");
d87a6d95 3214MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3215
3216module_param(share_irqs, uint, 0644);
3217MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3218 " (unsafe)");
3219
a61c2d78
DJ		 3220module_param(nr_uarts, uint, 0644);
3221MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3222
1da177e4
LT		 3223#ifdef CONFIG_SERIAL_8250_RSA
3224module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3225MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3226#endif
3227MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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