Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
1da177e4 LT |
25 | * This is a generic driver for ARM AMBA-type serial ports. They |
26 | * have a lot of 16550-like features, but are not register compatible. | |
27 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
28 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
29 | * required, these have to be supplied via some other means (eg, GPIO) | |
30 | * and hooked into this driver. | |
31 | */ | |
1da177e4 LT |
32 | |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
1da177e4 LT |
50 | |
51 | #include <asm/io.h> | |
c6b8fdad | 52 | #include <asm/sizes.h> |
1da177e4 LT |
53 | |
54 | #define UART_NR 14 | |
55 | ||
56 | #define SERIAL_AMBA_MAJOR 204 | |
57 | #define SERIAL_AMBA_MINOR 64 | |
58 | #define SERIAL_AMBA_NR UART_NR | |
59 | ||
60 | #define AMBA_ISR_PASS_LIMIT 256 | |
61 | ||
b63d4f0f RK |
62 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
63 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 LT |
64 | |
65 | /* | |
66 | * We wrap our port structure around the generic uart_port. | |
67 | */ | |
68 | struct uart_amba_port { | |
69 | struct uart_port port; | |
70 | struct clk *clk; | |
71 | unsigned int im; /* interrupt mask */ | |
72 | unsigned int old_status; | |
5926a295 AR |
73 | unsigned int ifls; /* vendor-specific */ |
74 | }; | |
75 | ||
76 | /* There is by now at least one vendor with differing details, so handle it */ | |
77 | struct vendor_data { | |
78 | unsigned int ifls; | |
79 | unsigned int fifosize; | |
80 | }; | |
81 | ||
82 | static struct vendor_data vendor_arm = { | |
83 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
84 | .fifosize = 16, | |
85 | }; | |
86 | ||
87 | static struct vendor_data vendor_st = { | |
88 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
89 | .fifosize = 64, | |
1da177e4 LT |
90 | }; |
91 | ||
b129a8cc | 92 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
93 | { |
94 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
95 | ||
96 | uap->im &= ~UART011_TXIM; | |
97 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
98 | } | |
99 | ||
b129a8cc | 100 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
101 | { |
102 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
103 | ||
104 | uap->im |= UART011_TXIM; | |
105 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
106 | } | |
107 | ||
108 | static void pl011_stop_rx(struct uart_port *port) | |
109 | { | |
110 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
111 | ||
112 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
113 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
114 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
115 | } | |
116 | ||
117 | static void pl011_enable_ms(struct uart_port *port) | |
118 | { | |
119 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
120 | ||
121 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
122 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
123 | } | |
124 | ||
7d12e780 | 125 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 126 | { |
ebd2c8f6 | 127 | struct tty_struct *tty = uap->port.state->port.tty; |
b63d4f0f | 128 | unsigned int status, ch, flag, max_count = 256; |
1da177e4 LT |
129 | |
130 | status = readw(uap->port.membase + UART01x_FR); | |
131 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { | |
b63d4f0f | 132 | ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX; |
1da177e4 LT |
133 | flag = TTY_NORMAL; |
134 | uap->port.icount.rx++; | |
135 | ||
136 | /* | |
137 | * Note that the error handling code is | |
138 | * out of the main execution path | |
139 | */ | |
b63d4f0f RK |
140 | if (unlikely(ch & UART_DR_ERROR)) { |
141 | if (ch & UART011_DR_BE) { | |
142 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
1da177e4 LT |
143 | uap->port.icount.brk++; |
144 | if (uart_handle_break(&uap->port)) | |
145 | goto ignore_char; | |
b63d4f0f | 146 | } else if (ch & UART011_DR_PE) |
1da177e4 | 147 | uap->port.icount.parity++; |
b63d4f0f | 148 | else if (ch & UART011_DR_FE) |
1da177e4 | 149 | uap->port.icount.frame++; |
b63d4f0f | 150 | if (ch & UART011_DR_OE) |
1da177e4 LT |
151 | uap->port.icount.overrun++; |
152 | ||
b63d4f0f | 153 | ch &= uap->port.read_status_mask; |
1da177e4 | 154 | |
b63d4f0f | 155 | if (ch & UART011_DR_BE) |
1da177e4 | 156 | flag = TTY_BREAK; |
b63d4f0f | 157 | else if (ch & UART011_DR_PE) |
1da177e4 | 158 | flag = TTY_PARITY; |
b63d4f0f | 159 | else if (ch & UART011_DR_FE) |
1da177e4 LT |
160 | flag = TTY_FRAME; |
161 | } | |
162 | ||
7d12e780 | 163 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) |
1da177e4 LT |
164 | goto ignore_char; |
165 | ||
b63d4f0f | 166 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); |
05ab3014 | 167 | |
1da177e4 LT |
168 | ignore_char: |
169 | status = readw(uap->port.membase + UART01x_FR); | |
170 | } | |
2389b272 | 171 | spin_unlock(&uap->port.lock); |
1da177e4 | 172 | tty_flip_buffer_push(tty); |
2389b272 | 173 | spin_lock(&uap->port.lock); |
1da177e4 LT |
174 | } |
175 | ||
176 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
177 | { | |
ebd2c8f6 | 178 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
179 | int count; |
180 | ||
181 | if (uap->port.x_char) { | |
182 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
183 | uap->port.icount.tx++; | |
184 | uap->port.x_char = 0; | |
185 | return; | |
186 | } | |
187 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 188 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
189 | return; |
190 | } | |
191 | ||
192 | count = uap->port.fifosize >> 1; | |
193 | do { | |
194 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
195 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
196 | uap->port.icount.tx++; | |
197 | if (uart_circ_empty(xmit)) | |
198 | break; | |
199 | } while (--count > 0); | |
200 | ||
201 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
202 | uart_write_wakeup(&uap->port); | |
203 | ||
204 | if (uart_circ_empty(xmit)) | |
b129a8cc | 205 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
206 | } |
207 | ||
208 | static void pl011_modem_status(struct uart_amba_port *uap) | |
209 | { | |
210 | unsigned int status, delta; | |
211 | ||
212 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
213 | ||
214 | delta = status ^ uap->old_status; | |
215 | uap->old_status = status; | |
216 | ||
217 | if (!delta) | |
218 | return; | |
219 | ||
220 | if (delta & UART01x_FR_DCD) | |
221 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
222 | ||
223 | if (delta & UART01x_FR_DSR) | |
224 | uap->port.icount.dsr++; | |
225 | ||
226 | if (delta & UART01x_FR_CTS) | |
227 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
228 | ||
ebd2c8f6 | 229 | wake_up_interruptible(&uap->port.state->delta_msr_wait); |
1da177e4 LT |
230 | } |
231 | ||
7d12e780 | 232 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
233 | { |
234 | struct uart_amba_port *uap = dev_id; | |
235 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; | |
236 | int handled = 0; | |
237 | ||
238 | spin_lock(&uap->port.lock); | |
239 | ||
240 | status = readw(uap->port.membase + UART011_MIS); | |
241 | if (status) { | |
242 | do { | |
243 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
244 | UART011_RXIS), | |
245 | uap->port.membase + UART011_ICR); | |
246 | ||
247 | if (status & (UART011_RTIS|UART011_RXIS)) | |
1da177e4 | 248 | pl011_rx_chars(uap); |
1da177e4 LT |
249 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
250 | UART011_CTSMIS|UART011_RIMIS)) | |
251 | pl011_modem_status(uap); | |
252 | if (status & UART011_TXIS) | |
253 | pl011_tx_chars(uap); | |
254 | ||
255 | if (pass_counter-- == 0) | |
256 | break; | |
257 | ||
258 | status = readw(uap->port.membase + UART011_MIS); | |
259 | } while (status != 0); | |
260 | handled = 1; | |
261 | } | |
262 | ||
263 | spin_unlock(&uap->port.lock); | |
264 | ||
265 | return IRQ_RETVAL(handled); | |
266 | } | |
267 | ||
268 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
269 | { | |
270 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
271 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
272 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
273 | } | |
274 | ||
275 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
276 | { | |
277 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
278 | unsigned int result = 0; | |
279 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
280 | ||
5159f407 | 281 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
282 | if (status & uartbit) \ |
283 | result |= tiocmbit | |
284 | ||
5159f407 JS |
285 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
286 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
287 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
288 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
289 | #undef TIOCMBIT | |
1da177e4 LT |
290 | return result; |
291 | } | |
292 | ||
293 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
294 | { | |
295 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
296 | unsigned int cr; | |
297 | ||
298 | cr = readw(uap->port.membase + UART011_CR); | |
299 | ||
5159f407 | 300 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
301 | if (mctrl & tiocmbit) \ |
302 | cr |= uartbit; \ | |
303 | else \ | |
304 | cr &= ~uartbit | |
305 | ||
5159f407 JS |
306 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
307 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
308 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
309 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
310 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
311 | #undef TIOCMBIT | |
1da177e4 LT |
312 | |
313 | writew(cr, uap->port.membase + UART011_CR); | |
314 | } | |
315 | ||
316 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
317 | { | |
318 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
319 | unsigned long flags; | |
320 | unsigned int lcr_h; | |
321 | ||
322 | spin_lock_irqsave(&uap->port.lock, flags); | |
323 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
324 | if (break_state == -1) | |
325 | lcr_h |= UART01x_LCRH_BRK; | |
326 | else | |
327 | lcr_h &= ~UART01x_LCRH_BRK; | |
328 | writew(lcr_h, uap->port.membase + UART011_LCRH); | |
329 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
330 | } | |
331 | ||
84b5ae15 JW |
332 | #ifdef CONFIG_CONSOLE_POLL |
333 | static int pl010_get_poll_char(struct uart_port *port) | |
334 | { | |
335 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
336 | unsigned int status; | |
337 | ||
338 | do { | |
339 | status = readw(uap->port.membase + UART01x_FR); | |
340 | } while (status & UART01x_FR_RXFE); | |
341 | ||
342 | return readw(uap->port.membase + UART01x_DR); | |
343 | } | |
344 | ||
345 | static void pl010_put_poll_char(struct uart_port *port, | |
346 | unsigned char ch) | |
347 | { | |
348 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
349 | ||
350 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
351 | barrier(); | |
352 | ||
353 | writew(ch, uap->port.membase + UART01x_DR); | |
354 | } | |
355 | ||
356 | #endif /* CONFIG_CONSOLE_POLL */ | |
357 | ||
1da177e4 LT |
358 | static int pl011_startup(struct uart_port *port) |
359 | { | |
360 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
361 | unsigned int cr; | |
362 | int retval; | |
363 | ||
364 | /* | |
365 | * Try to enable the clock producer. | |
366 | */ | |
367 | retval = clk_enable(uap->clk); | |
368 | if (retval) | |
369 | goto out; | |
370 | ||
371 | uap->port.uartclk = clk_get_rate(uap->clk); | |
372 | ||
373 | /* | |
374 | * Allocate the IRQ | |
375 | */ | |
376 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
377 | if (retval) | |
378 | goto clk_dis; | |
379 | ||
5926a295 | 380 | writew(uap->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
381 | |
382 | /* | |
383 | * Provoke TX FIFO interrupt into asserting. | |
384 | */ | |
385 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
386 | writew(cr, uap->port.membase + UART011_CR); | |
387 | writew(0, uap->port.membase + UART011_FBRD); | |
388 | writew(1, uap->port.membase + UART011_IBRD); | |
389 | writew(0, uap->port.membase + UART011_LCRH); | |
390 | writew(0, uap->port.membase + UART01x_DR); | |
391 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
392 | barrier(); | |
393 | ||
394 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
395 | writew(cr, uap->port.membase + UART011_CR); | |
396 | ||
397 | /* | |
398 | * initialise the old status of the modem signals | |
399 | */ | |
400 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
401 | ||
402 | /* | |
403 | * Finally, enable interrupts | |
404 | */ | |
405 | spin_lock_irq(&uap->port.lock); | |
406 | uap->im = UART011_RXIM | UART011_RTIM; | |
407 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
408 | spin_unlock_irq(&uap->port.lock); | |
409 | ||
410 | return 0; | |
411 | ||
412 | clk_dis: | |
413 | clk_disable(uap->clk); | |
414 | out: | |
415 | return retval; | |
416 | } | |
417 | ||
418 | static void pl011_shutdown(struct uart_port *port) | |
419 | { | |
420 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
421 | unsigned long val; | |
422 | ||
423 | /* | |
424 | * disable all interrupts | |
425 | */ | |
426 | spin_lock_irq(&uap->port.lock); | |
427 | uap->im = 0; | |
428 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
429 | writew(0xffff, uap->port.membase + UART011_ICR); | |
430 | spin_unlock_irq(&uap->port.lock); | |
431 | ||
432 | /* | |
433 | * Free the interrupt | |
434 | */ | |
435 | free_irq(uap->port.irq, uap); | |
436 | ||
437 | /* | |
438 | * disable the port | |
439 | */ | |
440 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); | |
441 | ||
442 | /* | |
443 | * disable break condition and fifos | |
444 | */ | |
445 | val = readw(uap->port.membase + UART011_LCRH); | |
446 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
447 | writew(val, uap->port.membase + UART011_LCRH); | |
448 | ||
449 | /* | |
450 | * Shut down the clock producer | |
451 | */ | |
452 | clk_disable(uap->clk); | |
453 | } | |
454 | ||
455 | static void | |
606d099c AC |
456 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
457 | struct ktermios *old) | |
1da177e4 LT |
458 | { |
459 | unsigned int lcr_h, old_cr; | |
460 | unsigned long flags; | |
461 | unsigned int baud, quot; | |
462 | ||
463 | /* | |
464 | * Ask the core to calculate the divisor for us. | |
465 | */ | |
466 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
467 | quot = port->uartclk * 4 / baud; | |
468 | ||
469 | switch (termios->c_cflag & CSIZE) { | |
470 | case CS5: | |
471 | lcr_h = UART01x_LCRH_WLEN_5; | |
472 | break; | |
473 | case CS6: | |
474 | lcr_h = UART01x_LCRH_WLEN_6; | |
475 | break; | |
476 | case CS7: | |
477 | lcr_h = UART01x_LCRH_WLEN_7; | |
478 | break; | |
479 | default: // CS8 | |
480 | lcr_h = UART01x_LCRH_WLEN_8; | |
481 | break; | |
482 | } | |
483 | if (termios->c_cflag & CSTOPB) | |
484 | lcr_h |= UART01x_LCRH_STP2; | |
485 | if (termios->c_cflag & PARENB) { | |
486 | lcr_h |= UART01x_LCRH_PEN; | |
487 | if (!(termios->c_cflag & PARODD)) | |
488 | lcr_h |= UART01x_LCRH_EPS; | |
489 | } | |
490 | if (port->fifosize > 1) | |
491 | lcr_h |= UART01x_LCRH_FEN; | |
492 | ||
493 | spin_lock_irqsave(&port->lock, flags); | |
494 | ||
495 | /* | |
496 | * Update the per-port timeout. | |
497 | */ | |
498 | uart_update_timeout(port, termios->c_cflag, baud); | |
499 | ||
b63d4f0f | 500 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 501 | if (termios->c_iflag & INPCK) |
b63d4f0f | 502 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 503 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 504 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
505 | |
506 | /* | |
507 | * Characters to ignore | |
508 | */ | |
509 | port->ignore_status_mask = 0; | |
510 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 511 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 512 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 513 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
514 | /* |
515 | * If we're ignoring parity and break indicators, | |
516 | * ignore overruns too (for real raw support). | |
517 | */ | |
518 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 519 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
520 | } |
521 | ||
522 | /* | |
523 | * Ignore all characters if CREAD is not set. | |
524 | */ | |
525 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 526 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
527 | |
528 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
529 | pl011_enable_ms(port); | |
530 | ||
531 | /* first, disable everything */ | |
532 | old_cr = readw(port->membase + UART011_CR); | |
533 | writew(0, port->membase + UART011_CR); | |
534 | ||
535 | /* Set baud rate */ | |
536 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
537 | writew(quot >> 6, port->membase + UART011_IBRD); | |
538 | ||
539 | /* | |
540 | * ----------v----------v----------v----------v----- | |
541 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
542 | * ----------^----------^----------^----------^----- | |
543 | */ | |
544 | writew(lcr_h, port->membase + UART011_LCRH); | |
545 | writew(old_cr, port->membase + UART011_CR); | |
546 | ||
547 | spin_unlock_irqrestore(&port->lock, flags); | |
548 | } | |
549 | ||
550 | static const char *pl011_type(struct uart_port *port) | |
551 | { | |
552 | return port->type == PORT_AMBA ? "AMBA/PL011" : NULL; | |
553 | } | |
554 | ||
555 | /* | |
556 | * Release the memory region(s) being used by 'port' | |
557 | */ | |
558 | static void pl010_release_port(struct uart_port *port) | |
559 | { | |
560 | release_mem_region(port->mapbase, SZ_4K); | |
561 | } | |
562 | ||
563 | /* | |
564 | * Request the memory region(s) being used by 'port' | |
565 | */ | |
566 | static int pl010_request_port(struct uart_port *port) | |
567 | { | |
568 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
569 | != NULL ? 0 : -EBUSY; | |
570 | } | |
571 | ||
572 | /* | |
573 | * Configure/autoconfigure the port. | |
574 | */ | |
575 | static void pl010_config_port(struct uart_port *port, int flags) | |
576 | { | |
577 | if (flags & UART_CONFIG_TYPE) { | |
578 | port->type = PORT_AMBA; | |
579 | pl010_request_port(port); | |
580 | } | |
581 | } | |
582 | ||
583 | /* | |
584 | * verify the new serial_struct (for TIOCSSERIAL). | |
585 | */ | |
586 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
587 | { | |
588 | int ret = 0; | |
589 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
590 | ret = -EINVAL; | |
a62c4133 | 591 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
592 | ret = -EINVAL; |
593 | if (ser->baud_base < 9600) | |
594 | ret = -EINVAL; | |
595 | return ret; | |
596 | } | |
597 | ||
598 | static struct uart_ops amba_pl011_pops = { | |
599 | .tx_empty = pl01x_tx_empty, | |
600 | .set_mctrl = pl011_set_mctrl, | |
601 | .get_mctrl = pl01x_get_mctrl, | |
602 | .stop_tx = pl011_stop_tx, | |
603 | .start_tx = pl011_start_tx, | |
604 | .stop_rx = pl011_stop_rx, | |
605 | .enable_ms = pl011_enable_ms, | |
606 | .break_ctl = pl011_break_ctl, | |
607 | .startup = pl011_startup, | |
608 | .shutdown = pl011_shutdown, | |
609 | .set_termios = pl011_set_termios, | |
610 | .type = pl011_type, | |
611 | .release_port = pl010_release_port, | |
612 | .request_port = pl010_request_port, | |
613 | .config_port = pl010_config_port, | |
614 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
615 | #ifdef CONFIG_CONSOLE_POLL |
616 | .poll_get_char = pl010_get_poll_char, | |
617 | .poll_put_char = pl010_put_poll_char, | |
618 | #endif | |
1da177e4 LT |
619 | }; |
620 | ||
621 | static struct uart_amba_port *amba_ports[UART_NR]; | |
622 | ||
623 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
624 | ||
d358788f | 625 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 626 | { |
d358788f | 627 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 628 | |
d358788f RK |
629 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
630 | barrier(); | |
1da177e4 LT |
631 | writew(ch, uap->port.membase + UART01x_DR); |
632 | } | |
633 | ||
634 | static void | |
635 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
636 | { | |
637 | struct uart_amba_port *uap = amba_ports[co->index]; | |
638 | unsigned int status, old_cr, new_cr; | |
1da177e4 LT |
639 | |
640 | clk_enable(uap->clk); | |
641 | ||
642 | /* | |
643 | * First save the CR then disable the interrupts | |
644 | */ | |
645 | old_cr = readw(uap->port.membase + UART011_CR); | |
646 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
647 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
648 | writew(new_cr, uap->port.membase + UART011_CR); | |
649 | ||
d358788f | 650 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
651 | |
652 | /* | |
653 | * Finally, wait for transmitter to become empty | |
654 | * and restore the TCR | |
655 | */ | |
656 | do { | |
657 | status = readw(uap->port.membase + UART01x_FR); | |
658 | } while (status & UART01x_FR_BUSY); | |
659 | writew(old_cr, uap->port.membase + UART011_CR); | |
660 | ||
661 | clk_disable(uap->clk); | |
662 | } | |
663 | ||
664 | static void __init | |
665 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
666 | int *parity, int *bits) | |
667 | { | |
668 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
669 | unsigned int lcr_h, ibrd, fbrd; | |
670 | ||
671 | lcr_h = readw(uap->port.membase + UART011_LCRH); | |
672 | ||
673 | *parity = 'n'; | |
674 | if (lcr_h & UART01x_LCRH_PEN) { | |
675 | if (lcr_h & UART01x_LCRH_EPS) | |
676 | *parity = 'e'; | |
677 | else | |
678 | *parity = 'o'; | |
679 | } | |
680 | ||
681 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
682 | *bits = 7; | |
683 | else | |
684 | *bits = 8; | |
685 | ||
686 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
687 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
688 | ||
689 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
690 | } | |
691 | } | |
692 | ||
693 | static int __init pl011_console_setup(struct console *co, char *options) | |
694 | { | |
695 | struct uart_amba_port *uap; | |
696 | int baud = 38400; | |
697 | int bits = 8; | |
698 | int parity = 'n'; | |
699 | int flow = 'n'; | |
700 | ||
701 | /* | |
702 | * Check whether an invalid uart number has been specified, and | |
703 | * if so, search for the first available port that does have | |
704 | * console support. | |
705 | */ | |
706 | if (co->index >= UART_NR) | |
707 | co->index = 0; | |
708 | uap = amba_ports[co->index]; | |
d28122a5 RK |
709 | if (!uap) |
710 | return -ENODEV; | |
1da177e4 LT |
711 | |
712 | uap->port.uartclk = clk_get_rate(uap->clk); | |
713 | ||
714 | if (options) | |
715 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
716 | else | |
717 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
718 | ||
719 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
720 | } | |
721 | ||
2d93486c | 722 | static struct uart_driver amba_reg; |
1da177e4 LT |
723 | static struct console amba_console = { |
724 | .name = "ttyAMA", | |
725 | .write = pl011_console_write, | |
726 | .device = uart_console_device, | |
727 | .setup = pl011_console_setup, | |
728 | .flags = CON_PRINTBUFFER, | |
729 | .index = -1, | |
730 | .data = &amba_reg, | |
731 | }; | |
732 | ||
733 | #define AMBA_CONSOLE (&amba_console) | |
734 | #else | |
735 | #define AMBA_CONSOLE NULL | |
736 | #endif | |
737 | ||
738 | static struct uart_driver amba_reg = { | |
739 | .owner = THIS_MODULE, | |
740 | .driver_name = "ttyAMA", | |
741 | .dev_name = "ttyAMA", | |
742 | .major = SERIAL_AMBA_MAJOR, | |
743 | .minor = SERIAL_AMBA_MINOR, | |
744 | .nr = UART_NR, | |
745 | .cons = AMBA_CONSOLE, | |
746 | }; | |
747 | ||
03fbdb15 | 748 | static int pl011_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 LT |
749 | { |
750 | struct uart_amba_port *uap; | |
5926a295 | 751 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
752 | void __iomem *base; |
753 | int i, ret; | |
754 | ||
755 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
756 | if (amba_ports[i] == NULL) | |
757 | break; | |
758 | ||
759 | if (i == ARRAY_SIZE(amba_ports)) { | |
760 | ret = -EBUSY; | |
761 | goto out; | |
762 | } | |
763 | ||
dd00cc48 | 764 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
765 | if (uap == NULL) { |
766 | ret = -ENOMEM; | |
767 | goto out; | |
768 | } | |
769 | ||
dc890c2d | 770 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
771 | if (!base) { |
772 | ret = -ENOMEM; | |
773 | goto free; | |
774 | } | |
775 | ||
ee569c43 | 776 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
777 | if (IS_ERR(uap->clk)) { |
778 | ret = PTR_ERR(uap->clk); | |
779 | goto unmap; | |
780 | } | |
781 | ||
5926a295 | 782 | uap->ifls = vendor->ifls; |
1da177e4 LT |
783 | uap->port.dev = &dev->dev; |
784 | uap->port.mapbase = dev->res.start; | |
785 | uap->port.membase = base; | |
786 | uap->port.iotype = UPIO_MEM; | |
787 | uap->port.irq = dev->irq[0]; | |
5926a295 | 788 | uap->port.fifosize = vendor->fifosize; |
1da177e4 LT |
789 | uap->port.ops = &amba_pl011_pops; |
790 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
791 | uap->port.line = i; | |
792 | ||
793 | amba_ports[i] = uap; | |
794 | ||
795 | amba_set_drvdata(dev, uap); | |
796 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
797 | if (ret) { | |
798 | amba_set_drvdata(dev, NULL); | |
799 | amba_ports[i] = NULL; | |
1da177e4 LT |
800 | clk_put(uap->clk); |
801 | unmap: | |
802 | iounmap(base); | |
803 | free: | |
804 | kfree(uap); | |
805 | } | |
806 | out: | |
807 | return ret; | |
808 | } | |
809 | ||
810 | static int pl011_remove(struct amba_device *dev) | |
811 | { | |
812 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
813 | int i; | |
814 | ||
815 | amba_set_drvdata(dev, NULL); | |
816 | ||
817 | uart_remove_one_port(&amba_reg, &uap->port); | |
818 | ||
819 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
820 | if (amba_ports[i] == uap) | |
821 | amba_ports[i] = NULL; | |
822 | ||
823 | iounmap(uap->port.membase); | |
1da177e4 LT |
824 | clk_put(uap->clk); |
825 | kfree(uap); | |
826 | return 0; | |
827 | } | |
828 | ||
b736b89f LC |
829 | #ifdef CONFIG_PM |
830 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
831 | { | |
832 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
833 | ||
834 | if (!uap) | |
835 | return -EINVAL; | |
836 | ||
837 | return uart_suspend_port(&amba_reg, &uap->port); | |
838 | } | |
839 | ||
840 | static int pl011_resume(struct amba_device *dev) | |
841 | { | |
842 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
843 | ||
844 | if (!uap) | |
845 | return -EINVAL; | |
846 | ||
847 | return uart_resume_port(&amba_reg, &uap->port); | |
848 | } | |
849 | #endif | |
850 | ||
1da177e4 LT |
851 | static struct amba_id pl011_ids[] __initdata = { |
852 | { | |
853 | .id = 0x00041011, | |
854 | .mask = 0x000fffff, | |
5926a295 AR |
855 | .data = &vendor_arm, |
856 | }, | |
857 | { | |
858 | .id = 0x00380802, | |
859 | .mask = 0x00ffffff, | |
860 | .data = &vendor_st, | |
1da177e4 LT |
861 | }, |
862 | { 0, 0 }, | |
863 | }; | |
864 | ||
865 | static struct amba_driver pl011_driver = { | |
866 | .drv = { | |
867 | .name = "uart-pl011", | |
868 | }, | |
869 | .id_table = pl011_ids, | |
870 | .probe = pl011_probe, | |
871 | .remove = pl011_remove, | |
b736b89f LC |
872 | #ifdef CONFIG_PM |
873 | .suspend = pl011_suspend, | |
874 | .resume = pl011_resume, | |
875 | #endif | |
1da177e4 LT |
876 | }; |
877 | ||
878 | static int __init pl011_init(void) | |
879 | { | |
880 | int ret; | |
881 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
882 | ||
883 | ret = uart_register_driver(&amba_reg); | |
884 | if (ret == 0) { | |
885 | ret = amba_driver_register(&pl011_driver); | |
886 | if (ret) | |
887 | uart_unregister_driver(&amba_reg); | |
888 | } | |
889 | return ret; | |
890 | } | |
891 | ||
892 | static void __exit pl011_exit(void) | |
893 | { | |
894 | amba_driver_unregister(&pl011_driver); | |
895 | uart_unregister_driver(&amba_reg); | |
896 | } | |
897 | ||
4dd9e742 AR |
898 | /* |
899 | * While this can be a module, if builtin it's most likely the console | |
900 | * So let's leave module_exit but move module_init to an earlier place | |
901 | */ | |
902 | arch_initcall(pl011_init); | |
1da177e4 LT |
903 | module_exit(pl011_exit); |
904 | ||
905 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
906 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
907 | MODULE_LICENSE("GPL"); |