Commit | Line | Data |
---|---|---|
1e6c9c28 | 1 | /* |
c2f5ccfb | 2 | * linux/drivers/char/atmel_serial.c |
1e6c9c28 | 3 | * |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
93a3ddc2 | 36 | #include <linux/atmel_pdc.h> |
fa3218d8 | 37 | #include <linux/atmel_serial.h> |
1e6c9c28 AV |
38 | |
39 | #include <asm/io.h> | |
40 | ||
afefc415 | 41 | #include <asm/mach/serial_at91.h> |
1e6c9c28 | 42 | #include <asm/arch/board.h> |
93a3ddc2 | 43 | |
acca9b83 | 44 | #ifdef CONFIG_ARM |
c2f5ccfb | 45 | #include <asm/arch/cpu.h> |
20e65276 | 46 | #include <asm/arch/gpio.h> |
acca9b83 | 47 | #endif |
1e6c9c28 | 48 | |
749c4e60 | 49 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
50 | #define SUPPORT_SYSRQ |
51 | #endif | |
52 | ||
53 | #include <linux/serial_core.h> | |
54 | ||
749c4e60 | 55 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
56 | |
57 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
58 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
59 | * UART. */ | |
7192f92c | 60 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 61 | #define MINOR_START 154 |
7192f92c | 62 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
63 | |
64 | #else | |
65 | ||
66 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
67 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 68 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 69 | #define MINOR_START 64 |
7192f92c | 70 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
71 | |
72 | #endif | |
73 | ||
7192f92c | 74 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 75 | |
b843aa21 | 76 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
77 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
78 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
79 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
80 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
81 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
82 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
83 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
84 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
85 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
86 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
87 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
88 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
89 | ||
1e6c9c28 | 90 | /* PDC registers */ |
544fc728 HS |
91 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
92 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
93 | ||
94 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
95 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
96 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
97 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
98 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
99 | ||
100 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
101 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
1e6c9c28 | 102 | |
71f2e2b8 HS |
103 | static int (*atmel_open_hook)(struct uart_port *); |
104 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 105 | |
afefc415 AV |
106 | /* |
107 | * We wrap our port structure around the generic uart_port. | |
108 | */ | |
7192f92c | 109 | struct atmel_uart_port { |
afefc415 AV |
110 | struct uart_port uart; /* uart */ |
111 | struct clk *clk; /* uart clock */ | |
112 | unsigned short suspended; /* is port suspended? */ | |
9e6077bd | 113 | int break_active; /* break being received */ |
afefc415 AV |
114 | }; |
115 | ||
7192f92c | 116 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 117 | |
1e6c9c28 | 118 | #ifdef SUPPORT_SYSRQ |
7192f92c | 119 | static struct console atmel_console; |
1e6c9c28 AV |
120 | #endif |
121 | ||
122 | /* | |
123 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
124 | */ | |
7192f92c | 125 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 126 | { |
7192f92c | 127 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
128 | } |
129 | ||
130 | /* | |
131 | * Set state of the modem control output lines | |
132 | */ | |
7192f92c | 133 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
134 | { |
135 | unsigned int control = 0; | |
afefc415 | 136 | unsigned int mode; |
1e6c9c28 | 137 | |
c2f5ccfb | 138 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 139 | if (cpu_is_at91rm9200()) { |
afefc415 | 140 | /* |
b843aa21 RB |
141 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
142 | * to PA21. We need to drive the pin manually. | |
afefc415 | 143 | */ |
72729910 | 144 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 145 | if (mctrl & TIOCM_RTS) |
20e65276 | 146 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 147 | else |
20e65276 | 148 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 149 | } |
1e6c9c28 | 150 | } |
acca9b83 | 151 | #endif |
1e6c9c28 AV |
152 | |
153 | if (mctrl & TIOCM_RTS) | |
7192f92c | 154 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 155 | else |
7192f92c | 156 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
157 | |
158 | if (mctrl & TIOCM_DTR) | |
7192f92c | 159 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 160 | else |
7192f92c | 161 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 162 | |
afefc415 AV |
163 | UART_PUT_CR(port, control); |
164 | ||
165 | /* Local loopback mode? */ | |
7192f92c | 166 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 167 | if (mctrl & TIOCM_LOOP) |
7192f92c | 168 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 169 | else |
7192f92c | 170 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 171 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
172 | } |
173 | ||
174 | /* | |
175 | * Get state of the modem control input lines | |
176 | */ | |
7192f92c | 177 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
178 | { |
179 | unsigned int status, ret = 0; | |
180 | ||
181 | status = UART_GET_CSR(port); | |
182 | ||
183 | /* | |
184 | * The control signals are active low. | |
185 | */ | |
7192f92c | 186 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 187 | ret |= TIOCM_CD; |
7192f92c | 188 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 189 | ret |= TIOCM_CTS; |
7192f92c | 190 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 191 | ret |= TIOCM_DSR; |
7192f92c | 192 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
193 | ret |= TIOCM_RI; |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
198 | /* | |
199 | * Stop transmitting. | |
200 | */ | |
7192f92c | 201 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 202 | { |
7192f92c | 203 | UART_PUT_IDR(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
204 | } |
205 | ||
206 | /* | |
207 | * Start transmitting. | |
208 | */ | |
7192f92c | 209 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 210 | { |
7192f92c | 211 | UART_PUT_IER(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
212 | } |
213 | ||
214 | /* | |
215 | * Stop receiving - port is in process of being closed. | |
216 | */ | |
7192f92c | 217 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 218 | { |
7192f92c | 219 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
1e6c9c28 AV |
220 | } |
221 | ||
222 | /* | |
223 | * Enable modem status interrupts | |
224 | */ | |
7192f92c | 225 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 226 | { |
b843aa21 RB |
227 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
228 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
229 | } |
230 | ||
231 | /* | |
232 | * Control the transmission of a break signal | |
233 | */ | |
7192f92c | 234 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
235 | { |
236 | if (break_state != 0) | |
7192f92c | 237 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 238 | else |
7192f92c | 239 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
240 | } |
241 | ||
242 | /* | |
243 | * Characters received (called from interrupt handler) | |
244 | */ | |
7d12e780 | 245 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 246 | { |
b843aa21 | 247 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; |
1e6c9c28 AV |
248 | struct tty_struct *tty = port->info->tty; |
249 | unsigned int status, ch, flg; | |
250 | ||
afefc415 | 251 | status = UART_GET_CSR(port); |
7192f92c | 252 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
253 | ch = UART_GET_CHAR(port); |
254 | ||
1e6c9c28 AV |
255 | port->icount.rx++; |
256 | ||
257 | flg = TTY_NORMAL; | |
258 | ||
259 | /* | |
260 | * note that the error handling code is | |
261 | * out of the main execution path | |
262 | */ | |
9e6077bd HS |
263 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
264 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
265 | || atmel_port->break_active)) { | |
b843aa21 RB |
266 | /* clear error */ |
267 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
9e6077bd HS |
268 | if (status & ATMEL_US_RXBRK |
269 | && !atmel_port->break_active) { | |
b843aa21 RB |
270 | /* ignore side-effect */ |
271 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
afefc415 | 272 | port->icount.brk++; |
9e6077bd HS |
273 | atmel_port->break_active = 1; |
274 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
afefc415 AV |
275 | if (uart_handle_break(port)) |
276 | goto ignore_char; | |
9e6077bd HS |
277 | } else { |
278 | /* | |
279 | * This is either the end-of-break | |
280 | * condition or we've received at | |
281 | * least one character without RXBRK | |
282 | * being set. In both cases, the next | |
283 | * RXBRK will indicate start-of-break. | |
284 | */ | |
285 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
286 | status &= ~ATMEL_US_RXBRK; | |
287 | atmel_port->break_active = 0; | |
afefc415 | 288 | } |
7192f92c | 289 | if (status & ATMEL_US_PARE) |
1e6c9c28 | 290 | port->icount.parity++; |
7192f92c | 291 | if (status & ATMEL_US_FRAME) |
1e6c9c28 | 292 | port->icount.frame++; |
7192f92c | 293 | if (status & ATMEL_US_OVRE) |
1e6c9c28 AV |
294 | port->icount.overrun++; |
295 | ||
afefc415 AV |
296 | status &= port->read_status_mask; |
297 | ||
7192f92c | 298 | if (status & ATMEL_US_RXBRK) |
afefc415 | 299 | flg = TTY_BREAK; |
7192f92c | 300 | else if (status & ATMEL_US_PARE) |
1e6c9c28 | 301 | flg = TTY_PARITY; |
7192f92c | 302 | else if (status & ATMEL_US_FRAME) |
1e6c9c28 | 303 | flg = TTY_FRAME; |
1e6c9c28 AV |
304 | } |
305 | ||
7d12e780 | 306 | if (uart_handle_sysrq_char(port, ch)) |
1e6c9c28 AV |
307 | goto ignore_char; |
308 | ||
7192f92c | 309 | uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg); |
1e6c9c28 | 310 | |
b843aa21 | 311 | ignore_char: |
afefc415 | 312 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
313 | } |
314 | ||
315 | tty_flip_buffer_push(tty); | |
316 | } | |
317 | ||
318 | /* | |
319 | * Transmit characters (called from interrupt handler) | |
320 | */ | |
7192f92c | 321 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
322 | { |
323 | struct circ_buf *xmit = &port->info->xmit; | |
324 | ||
325 | if (port->x_char) { | |
326 | UART_PUT_CHAR(port, port->x_char); | |
327 | port->icount.tx++; | |
328 | port->x_char = 0; | |
329 | return; | |
330 | } | |
331 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
7192f92c | 332 | atmel_stop_tx(port); |
1e6c9c28 AV |
333 | return; |
334 | } | |
335 | ||
7192f92c | 336 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
337 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
338 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
339 | port->icount.tx++; | |
340 | if (uart_circ_empty(xmit)) | |
341 | break; | |
342 | } | |
343 | ||
344 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
345 | uart_write_wakeup(port); | |
346 | ||
347 | if (uart_circ_empty(xmit)) | |
7192f92c | 348 | atmel_stop_tx(port); |
1e6c9c28 AV |
349 | } |
350 | ||
b843aa21 RB |
351 | /* |
352 | * receive interrupt handler. | |
353 | */ | |
354 | static void | |
355 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
356 | { | |
357 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; | |
358 | ||
359 | /* Interrupt receive */ | |
360 | if (pending & ATMEL_US_RXRDY) | |
361 | atmel_rx_chars(port); | |
362 | else if (pending & ATMEL_US_RXBRK) { | |
363 | /* | |
364 | * End of break detected. If it came along with a | |
365 | * character, atmel_rx_chars will handle it. | |
366 | */ | |
367 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
368 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
369 | atmel_port->break_active = 0; | |
370 | } | |
371 | } | |
372 | ||
373 | /* | |
374 | * transmit interrupt handler. | |
375 | */ | |
376 | static void | |
377 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
378 | { | |
379 | /* Interrupt transmit */ | |
380 | if (pending & ATMEL_US_TXRDY) | |
381 | atmel_tx_chars(port); | |
382 | } | |
383 | ||
384 | /* | |
385 | * status flags interrupt handler. | |
386 | */ | |
387 | static void | |
388 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
389 | unsigned int status) | |
390 | { | |
391 | /* TODO: All reads to CSR will clear these interrupts! */ | |
392 | if (pending & ATMEL_US_RIIC) | |
393 | port->icount.rng++; | |
394 | if (pending & ATMEL_US_DSRIC) | |
395 | port->icount.dsr++; | |
396 | if (pending & ATMEL_US_DCDIC) | |
397 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
398 | if (pending & ATMEL_US_CTSIC) | |
399 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
400 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | |
401 | | ATMEL_US_CTSIC)) | |
402 | wake_up_interruptible(&port->info->delta_msr_wait); | |
403 | } | |
404 | ||
1e6c9c28 AV |
405 | /* |
406 | * Interrupt handler | |
407 | */ | |
7d12e780 | 408 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
409 | { |
410 | struct uart_port *port = dev_id; | |
411 | unsigned int status, pending, pass_counter = 0; | |
412 | ||
413 | status = UART_GET_CSR(port); | |
afefc415 AV |
414 | pending = status & UART_GET_IMR(port); |
415 | while (pending) { | |
b843aa21 RB |
416 | atmel_handle_receive(port, pending); |
417 | atmel_handle_status(port, pending, status); | |
418 | atmel_handle_transmit(port, pending); | |
afefc415 | 419 | |
7192f92c | 420 | if (pass_counter++ > ATMEL_ISR_PASS_LIMIT) |
afefc415 | 421 | break; |
1e6c9c28 | 422 | |
afefc415 AV |
423 | status = UART_GET_CSR(port); |
424 | pending = status & UART_GET_IMR(port); | |
1e6c9c28 AV |
425 | } |
426 | return IRQ_HANDLED; | |
427 | } | |
428 | ||
429 | /* | |
430 | * Perform initialization and enable port for reception | |
431 | */ | |
7192f92c | 432 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 AV |
433 | { |
434 | int retval; | |
435 | ||
436 | /* | |
437 | * Ensure that no interrupts are enabled otherwise when | |
438 | * request_irq() is called we could get stuck trying to | |
439 | * handle an unexpected interrupt | |
440 | */ | |
441 | UART_PUT_IDR(port, -1); | |
442 | ||
443 | /* | |
444 | * Allocate the IRQ | |
445 | */ | |
b843aa21 RB |
446 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
447 | "atmel_serial", port); | |
1e6c9c28 | 448 | if (retval) { |
7192f92c | 449 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
450 | return retval; |
451 | } | |
452 | ||
453 | /* | |
454 | * If there is a specific "open" function (to register | |
455 | * control line interrupts) | |
456 | */ | |
71f2e2b8 HS |
457 | if (atmel_open_hook) { |
458 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
459 | if (retval) { |
460 | free_irq(port->irq, port); | |
461 | return retval; | |
462 | } | |
463 | } | |
464 | ||
1e6c9c28 AV |
465 | /* |
466 | * Finally, enable the serial port | |
467 | */ | |
7192f92c | 468 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
469 | /* enable xmit & rcvr */ |
470 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 471 | |
b843aa21 RB |
472 | /* enable receive only */ |
473 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
afefc415 | 474 | |
1e6c9c28 AV |
475 | return 0; |
476 | } | |
477 | ||
478 | /* | |
479 | * Disable the port | |
480 | */ | |
7192f92c | 481 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 AV |
482 | { |
483 | /* | |
484 | * Disable all interrupts, port and break condition. | |
485 | */ | |
7192f92c | 486 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
487 | UART_PUT_IDR(port, -1); |
488 | ||
489 | /* | |
490 | * Free the interrupt | |
491 | */ | |
492 | free_irq(port->irq, port); | |
493 | ||
494 | /* | |
495 | * If there is a specific "close" function (to unregister | |
496 | * control line interrupts) | |
497 | */ | |
71f2e2b8 HS |
498 | if (atmel_close_hook) |
499 | atmel_close_hook(port); | |
1e6c9c28 AV |
500 | } |
501 | ||
502 | /* | |
503 | * Power / Clock management. | |
504 | */ | |
b843aa21 RB |
505 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
506 | unsigned int oldstate) | |
1e6c9c28 | 507 | { |
b843aa21 | 508 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; |
afefc415 | 509 | |
1e6c9c28 | 510 | switch (state) { |
b843aa21 RB |
511 | case 0: |
512 | /* | |
513 | * Enable the peripheral clock for this serial port. | |
514 | * This is called on uart_open() or a resume event. | |
515 | */ | |
516 | clk_enable(atmel_port->clk); | |
517 | break; | |
518 | case 3: | |
519 | /* | |
520 | * Disable the peripheral clock for this serial port. | |
521 | * This is called on uart_close() or a suspend event. | |
522 | */ | |
523 | clk_disable(atmel_port->clk); | |
524 | break; | |
525 | default: | |
526 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
527 | } |
528 | } | |
529 | ||
530 | /* | |
531 | * Change the port parameters | |
532 | */ | |
b843aa21 RB |
533 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
534 | struct ktermios *old) | |
1e6c9c28 AV |
535 | { |
536 | unsigned long flags; | |
537 | unsigned int mode, imr, quot, baud; | |
538 | ||
03abeac0 | 539 | /* Get current mode register */ |
b843aa21 RB |
540 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
541 | | ATMEL_US_NBSTOP | ATMEL_US_PAR); | |
03abeac0 | 542 | |
b843aa21 | 543 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
544 | quot = uart_get_divisor(port, baud); |
545 | ||
b843aa21 | 546 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
547 | quot /= 8; |
548 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
549 | } | |
1e6c9c28 AV |
550 | |
551 | /* byte size */ | |
552 | switch (termios->c_cflag & CSIZE) { | |
553 | case CS5: | |
7192f92c | 554 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
555 | break; |
556 | case CS6: | |
7192f92c | 557 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
558 | break; |
559 | case CS7: | |
7192f92c | 560 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
561 | break; |
562 | default: | |
7192f92c | 563 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
564 | break; |
565 | } | |
566 | ||
567 | /* stop bits */ | |
568 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 569 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
570 | |
571 | /* parity */ | |
572 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
573 | /* Mark or Space parity */ |
574 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 575 | if (termios->c_cflag & PARODD) |
7192f92c | 576 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 577 | else |
7192f92c | 578 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 579 | } else if (termios->c_cflag & PARODD) |
7192f92c | 580 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 581 | else |
7192f92c | 582 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 583 | } else |
7192f92c | 584 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
585 | |
586 | spin_lock_irqsave(&port->lock, flags); | |
587 | ||
7192f92c | 588 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 589 | if (termios->c_iflag & INPCK) |
7192f92c | 590 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 591 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 592 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
593 | |
594 | /* | |
595 | * Characters to ignore | |
596 | */ | |
597 | port->ignore_status_mask = 0; | |
598 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 599 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 600 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 601 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
602 | /* |
603 | * If we're ignoring parity and break indicators, | |
604 | * ignore overruns too (for real raw support). | |
605 | */ | |
606 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 607 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 608 | } |
b843aa21 | 609 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
610 | |
611 | /* update the per-port timeout */ | |
612 | uart_update_timeout(port, termios->c_cflag, baud); | |
613 | ||
b843aa21 RB |
614 | /* save/disable interrupts and drain transmitter */ |
615 | imr = UART_GET_IMR(port); | |
616 | UART_PUT_IDR(port, -1); | |
617 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
829dd811 | 618 | cpu_relax(); |
1e6c9c28 AV |
619 | |
620 | /* disable receiver and transmitter */ | |
7192f92c | 621 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
622 | |
623 | /* set the parity, stop bits and data size */ | |
624 | UART_PUT_MR(port, mode); | |
625 | ||
626 | /* set the baud rate */ | |
627 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
628 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
629 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
630 | |
631 | /* restore interrupts */ | |
632 | UART_PUT_IER(port, imr); | |
633 | ||
634 | /* CTS flow-control and modem-status interrupts */ | |
635 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
636 | port->ops->enable_ms(port); | |
637 | ||
638 | spin_unlock_irqrestore(&port->lock, flags); | |
639 | } | |
640 | ||
641 | /* | |
642 | * Return string describing the specified port | |
643 | */ | |
7192f92c | 644 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 645 | { |
9ab4f88b | 646 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
647 | } |
648 | ||
649 | /* | |
650 | * Release the memory region(s) being used by 'port'. | |
651 | */ | |
7192f92c | 652 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 653 | { |
afefc415 AV |
654 | struct platform_device *pdev = to_platform_device(port->dev); |
655 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
656 | ||
657 | release_mem_region(port->mapbase, size); | |
658 | ||
659 | if (port->flags & UPF_IOREMAP) { | |
660 | iounmap(port->membase); | |
661 | port->membase = NULL; | |
662 | } | |
1e6c9c28 AV |
663 | } |
664 | ||
665 | /* | |
666 | * Request the memory region(s) being used by 'port'. | |
667 | */ | |
7192f92c | 668 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 669 | { |
afefc415 AV |
670 | struct platform_device *pdev = to_platform_device(port->dev); |
671 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
672 | ||
7192f92c | 673 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
674 | return -EBUSY; |
675 | ||
676 | if (port->flags & UPF_IOREMAP) { | |
677 | port->membase = ioremap(port->mapbase, size); | |
678 | if (port->membase == NULL) { | |
679 | release_mem_region(port->mapbase, size); | |
680 | return -ENOMEM; | |
681 | } | |
682 | } | |
1e6c9c28 | 683 | |
afefc415 | 684 | return 0; |
1e6c9c28 AV |
685 | } |
686 | ||
687 | /* | |
688 | * Configure/autoconfigure the port. | |
689 | */ | |
7192f92c | 690 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
691 | { |
692 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 693 | port->type = PORT_ATMEL; |
7192f92c | 694 | atmel_request_port(port); |
1e6c9c28 AV |
695 | } |
696 | } | |
697 | ||
698 | /* | |
699 | * Verify the new serial_struct (for TIOCSSERIAL). | |
700 | */ | |
7192f92c | 701 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
702 | { |
703 | int ret = 0; | |
9ab4f88b | 704 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
705 | ret = -EINVAL; |
706 | if (port->irq != ser->irq) | |
707 | ret = -EINVAL; | |
708 | if (ser->io_type != SERIAL_IO_MEM) | |
709 | ret = -EINVAL; | |
710 | if (port->uartclk / 16 != ser->baud_base) | |
711 | ret = -EINVAL; | |
712 | if ((void *)port->mapbase != ser->iomem_base) | |
713 | ret = -EINVAL; | |
714 | if (port->iobase != ser->port) | |
715 | ret = -EINVAL; | |
716 | if (ser->hub6 != 0) | |
717 | ret = -EINVAL; | |
718 | return ret; | |
719 | } | |
720 | ||
7192f92c HS |
721 | static struct uart_ops atmel_pops = { |
722 | .tx_empty = atmel_tx_empty, | |
723 | .set_mctrl = atmel_set_mctrl, | |
724 | .get_mctrl = atmel_get_mctrl, | |
725 | .stop_tx = atmel_stop_tx, | |
726 | .start_tx = atmel_start_tx, | |
727 | .stop_rx = atmel_stop_rx, | |
728 | .enable_ms = atmel_enable_ms, | |
729 | .break_ctl = atmel_break_ctl, | |
730 | .startup = atmel_startup, | |
731 | .shutdown = atmel_shutdown, | |
732 | .set_termios = atmel_set_termios, | |
733 | .type = atmel_type, | |
734 | .release_port = atmel_release_port, | |
735 | .request_port = atmel_request_port, | |
736 | .config_port = atmel_config_port, | |
737 | .verify_port = atmel_verify_port, | |
738 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
739 | }; |
740 | ||
afefc415 AV |
741 | /* |
742 | * Configure the port from the platform device resource info. | |
743 | */ | |
b843aa21 RB |
744 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, |
745 | struct platform_device *pdev) | |
1e6c9c28 | 746 | { |
7192f92c | 747 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 748 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
749 | |
750 | port->iotype = UPIO_MEM; | |
a14d5273 | 751 | port->flags = UPF_BOOT_AUTOCONF; |
7192f92c | 752 | port->ops = &atmel_pops; |
a14d5273 | 753 | port->fifosize = 1; |
afefc415 AV |
754 | port->line = pdev->id; |
755 | port->dev = &pdev->dev; | |
756 | ||
757 | port->mapbase = pdev->resource[0].start; | |
758 | port->irq = pdev->resource[1].start; | |
759 | ||
75d35213 HS |
760 | if (data->regs) |
761 | /* Already mapped by setup code */ | |
762 | port->membase = data->regs; | |
afefc415 AV |
763 | else { |
764 | port->flags |= UPF_IOREMAP; | |
765 | port->membase = NULL; | |
766 | } | |
1e6c9c28 | 767 | |
b843aa21 RB |
768 | /* for console, the clock could already be configured */ |
769 | if (!atmel_port->clk) { | |
7192f92c HS |
770 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
771 | clk_enable(atmel_port->clk); | |
772 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 773 | } |
1e6c9c28 AV |
774 | } |
775 | ||
afefc415 AV |
776 | /* |
777 | * Register board-specific modem-control line handlers. | |
778 | */ | |
71f2e2b8 | 779 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
780 | { |
781 | if (fns->enable_ms) | |
7192f92c | 782 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 783 | if (fns->get_mctrl) |
7192f92c | 784 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 785 | if (fns->set_mctrl) |
7192f92c | 786 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
787 | atmel_open_hook = fns->open; |
788 | atmel_close_hook = fns->close; | |
7192f92c HS |
789 | atmel_pops.pm = fns->pm; |
790 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
791 | } |
792 | ||
749c4e60 | 793 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 794 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 795 | { |
7192f92c | 796 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 797 | cpu_relax(); |
d358788f RK |
798 | UART_PUT_CHAR(port, ch); |
799 | } | |
1e6c9c28 AV |
800 | |
801 | /* | |
802 | * Interrupts are disabled on entering | |
803 | */ | |
7192f92c | 804 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 805 | { |
7192f92c | 806 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 807 | unsigned int status, imr; |
1e6c9c28 AV |
808 | |
809 | /* | |
b843aa21 | 810 | * First, save IMR and then disable interrupts |
1e6c9c28 | 811 | */ |
b843aa21 | 812 | imr = UART_GET_IMR(port); |
7192f92c | 813 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 814 | |
7192f92c | 815 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
816 | |
817 | /* | |
b843aa21 RB |
818 | * Finally, wait for transmitter to become empty |
819 | * and restore IMR | |
1e6c9c28 AV |
820 | */ |
821 | do { | |
822 | status = UART_GET_CSR(port); | |
7192f92c | 823 | } while (!(status & ATMEL_US_TXRDY)); |
b843aa21 RB |
824 | /* set interrupts back the way they were */ |
825 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
826 | } |
827 | ||
828 | /* | |
b843aa21 RB |
829 | * If the port was already initialised (eg, by a boot loader), |
830 | * try to determine the current setup. | |
1e6c9c28 | 831 | */ |
b843aa21 RB |
832 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
833 | int *parity, int *bits) | |
1e6c9c28 AV |
834 | { |
835 | unsigned int mr, quot; | |
836 | ||
837 | // TODO: CR is a write-only register | |
838 | // unsigned int cr; | |
839 | // | |
7192f92c HS |
840 | // cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN); |
841 | // if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) { | |
1e6c9c28 AV |
842 | // /* ok, the port was enabled */ |
843 | // } | |
844 | ||
7192f92c HS |
845 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
846 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
847 | *bits = 8; |
848 | else | |
849 | *bits = 7; | |
850 | ||
7192f92c HS |
851 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
852 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 853 | *parity = 'e'; |
7192f92c | 854 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
855 | *parity = 'o'; |
856 | ||
4d5e392c HS |
857 | /* |
858 | * The serial core only rounds down when matching this to a | |
859 | * supported baud rate. Make sure we don't end up slightly | |
860 | * lower than one of those, as it would make us fall through | |
861 | * to a much lower baud rate than we really want. | |
862 | */ | |
1e6c9c28 | 863 | quot = UART_GET_BRGR(port); |
4d5e392c | 864 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
865 | } |
866 | ||
7192f92c | 867 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 868 | { |
7192f92c | 869 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
870 | int baud = 115200; |
871 | int bits = 8; | |
872 | int parity = 'n'; | |
873 | int flow = 'n'; | |
874 | ||
b843aa21 RB |
875 | if (port->membase == NULL) { |
876 | /* Port not initialized yet - delay setup */ | |
afefc415 | 877 | return -ENODEV; |
b843aa21 | 878 | } |
1e6c9c28 | 879 | |
b843aa21 | 880 | UART_PUT_IDR(port, -1); |
7192f92c HS |
881 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
882 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
883 | |
884 | if (options) | |
885 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
886 | else | |
7192f92c | 887 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
888 | |
889 | return uart_set_options(port, co, baud, parity, bits, flow); | |
890 | } | |
891 | ||
7192f92c | 892 | static struct uart_driver atmel_uart; |
1e6c9c28 | 893 | |
7192f92c HS |
894 | static struct console atmel_console = { |
895 | .name = ATMEL_DEVICENAME, | |
896 | .write = atmel_console_write, | |
1e6c9c28 | 897 | .device = uart_console_device, |
7192f92c | 898 | .setup = atmel_console_setup, |
1e6c9c28 AV |
899 | .flags = CON_PRINTBUFFER, |
900 | .index = -1, | |
7192f92c | 901 | .data = &atmel_uart, |
1e6c9c28 AV |
902 | }; |
903 | ||
7192f92c | 904 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 905 | |
afefc415 AV |
906 | /* |
907 | * Early console initialization (before VM subsystem initialized). | |
908 | */ | |
7192f92c | 909 | static int __init atmel_console_init(void) |
1e6c9c28 | 910 | { |
73e2798b | 911 | if (atmel_default_console_device) { |
b843aa21 RB |
912 | add_preferred_console(ATMEL_DEVICENAME, |
913 | atmel_default_console_device->id, NULL); | |
914 | atmel_init_port(&atmel_ports[atmel_default_console_device->id], | |
915 | atmel_default_console_device); | |
7192f92c | 916 | register_console(&atmel_console); |
afefc415 | 917 | } |
1e6c9c28 | 918 | |
1e6c9c28 AV |
919 | return 0; |
920 | } | |
b843aa21 | 921 | |
7192f92c | 922 | console_initcall(atmel_console_init); |
1e6c9c28 | 923 | |
afefc415 AV |
924 | /* |
925 | * Late console initialization. | |
926 | */ | |
7192f92c | 927 | static int __init atmel_late_console_init(void) |
afefc415 | 928 | { |
b843aa21 RB |
929 | if (atmel_default_console_device |
930 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 931 | register_console(&atmel_console); |
afefc415 AV |
932 | |
933 | return 0; | |
934 | } | |
b843aa21 | 935 | |
7192f92c | 936 | core_initcall(atmel_late_console_init); |
afefc415 | 937 | |
1e6c9c28 | 938 | #else |
7192f92c | 939 | #define ATMEL_CONSOLE_DEVICE NULL |
1e6c9c28 AV |
940 | #endif |
941 | ||
7192f92c | 942 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
943 | .owner = THIS_MODULE, |
944 | .driver_name = "atmel_serial", | |
945 | .dev_name = ATMEL_DEVICENAME, | |
946 | .major = SERIAL_ATMEL_MAJOR, | |
947 | .minor = MINOR_START, | |
948 | .nr = ATMEL_MAX_UART, | |
949 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
950 | }; |
951 | ||
afefc415 | 952 | #ifdef CONFIG_PM |
b843aa21 RB |
953 | static int atmel_serial_suspend(struct platform_device *pdev, |
954 | pm_message_t state) | |
1e6c9c28 | 955 | { |
afefc415 | 956 | struct uart_port *port = platform_get_drvdata(pdev); |
b843aa21 | 957 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; |
afefc415 | 958 | |
b843aa21 RB |
959 | if (device_may_wakeup(&pdev->dev) |
960 | && !at91_suspend_entering_slow_clock()) | |
afefc415 AV |
961 | enable_irq_wake(port->irq); |
962 | else { | |
7192f92c HS |
963 | uart_suspend_port(&atmel_uart, port); |
964 | atmel_port->suspended = 1; | |
afefc415 | 965 | } |
1e6c9c28 | 966 | |
afefc415 AV |
967 | return 0; |
968 | } | |
1e6c9c28 | 969 | |
7192f92c | 970 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
971 | { |
972 | struct uart_port *port = platform_get_drvdata(pdev); | |
b843aa21 | 973 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; |
1e6c9c28 | 974 | |
7192f92c HS |
975 | if (atmel_port->suspended) { |
976 | uart_resume_port(&atmel_uart, port); | |
977 | atmel_port->suspended = 0; | |
b843aa21 | 978 | } else |
9b938166 | 979 | disable_irq_wake(port->irq); |
1e6c9c28 AV |
980 | |
981 | return 0; | |
982 | } | |
afefc415 | 983 | #else |
7192f92c HS |
984 | #define atmel_serial_suspend NULL |
985 | #define atmel_serial_resume NULL | |
afefc415 | 986 | #endif |
1e6c9c28 | 987 | |
7192f92c | 988 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 989 | { |
7192f92c | 990 | struct atmel_uart_port *port; |
afefc415 | 991 | int ret; |
1e6c9c28 | 992 | |
7192f92c HS |
993 | port = &atmel_ports[pdev->id]; |
994 | atmel_init_port(port, pdev); | |
1e6c9c28 | 995 | |
7192f92c | 996 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
afefc415 AV |
997 | if (!ret) { |
998 | device_init_wakeup(&pdev->dev, 1); | |
999 | platform_set_drvdata(pdev, port); | |
1000 | } | |
1001 | ||
1002 | return ret; | |
1003 | } | |
1004 | ||
7192f92c | 1005 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1006 | { |
1007 | struct uart_port *port = platform_get_drvdata(pdev); | |
b843aa21 | 1008 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *)port; |
afefc415 AV |
1009 | int ret = 0; |
1010 | ||
7192f92c HS |
1011 | clk_disable(atmel_port->clk); |
1012 | clk_put(atmel_port->clk); | |
afefc415 AV |
1013 | |
1014 | device_init_wakeup(&pdev->dev, 0); | |
1015 | platform_set_drvdata(pdev, NULL); | |
1016 | ||
1017 | if (port) { | |
7192f92c | 1018 | ret = uart_remove_one_port(&atmel_uart, port); |
afefc415 AV |
1019 | kfree(port); |
1020 | } | |
1021 | ||
1022 | return ret; | |
1023 | } | |
1024 | ||
7192f92c HS |
1025 | static struct platform_driver atmel_serial_driver = { |
1026 | .probe = atmel_serial_probe, | |
1027 | .remove = __devexit_p(atmel_serial_remove), | |
1028 | .suspend = atmel_serial_suspend, | |
1029 | .resume = atmel_serial_resume, | |
afefc415 | 1030 | .driver = { |
1e8ea802 | 1031 | .name = "atmel_usart", |
afefc415 AV |
1032 | .owner = THIS_MODULE, |
1033 | }, | |
1034 | }; | |
1035 | ||
7192f92c | 1036 | static int __init atmel_serial_init(void) |
afefc415 AV |
1037 | { |
1038 | int ret; | |
1039 | ||
7192f92c | 1040 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1041 | if (ret) |
1042 | return ret; | |
1043 | ||
7192f92c | 1044 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1045 | if (ret) |
7192f92c | 1046 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1047 | |
1048 | return ret; | |
1049 | } | |
1050 | ||
7192f92c | 1051 | static void __exit atmel_serial_exit(void) |
afefc415 | 1052 | { |
7192f92c HS |
1053 | platform_driver_unregister(&atmel_serial_driver); |
1054 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1055 | } |
1056 | ||
7192f92c HS |
1057 | module_init(atmel_serial_init); |
1058 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1059 | |
1060 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1061 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1062 | MODULE_LICENSE("GPL"); |