Commit | Line | Data |
---|---|---|
1e6c9c28 | 1 | /* |
c2f5ccfb | 2 | * linux/drivers/char/atmel_serial.c |
1e6c9c28 | 3 | * |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
93a3ddc2 | 36 | #include <linux/atmel_pdc.h> |
1e6c9c28 AV |
37 | |
38 | #include <asm/io.h> | |
39 | ||
afefc415 | 40 | #include <asm/mach/serial_at91.h> |
1e6c9c28 | 41 | #include <asm/arch/board.h> |
93a3ddc2 | 42 | |
acca9b83 | 43 | #ifdef CONFIG_ARM |
c2f5ccfb | 44 | #include <asm/arch/cpu.h> |
20e65276 | 45 | #include <asm/arch/gpio.h> |
acca9b83 | 46 | #endif |
1e6c9c28 | 47 | |
5b34821a HS |
48 | #include "atmel_serial.h" |
49 | ||
749c4e60 | 50 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
51 | #define SUPPORT_SYSRQ |
52 | #endif | |
53 | ||
54 | #include <linux/serial_core.h> | |
55 | ||
749c4e60 | 56 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
57 | |
58 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
59 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
60 | * UART. */ | |
7192f92c | 61 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 62 | #define MINOR_START 154 |
7192f92c | 63 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
64 | |
65 | #else | |
66 | ||
67 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
68 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 69 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 70 | #define MINOR_START 64 |
7192f92c | 71 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
72 | |
73 | #endif | |
74 | ||
7192f92c | 75 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 76 | |
544fc728 HS |
77 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
78 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
79 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
80 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
81 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
82 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
83 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
84 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
85 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
86 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
87 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
88 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
89 | ||
90 | // #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only | |
1e6c9c28 AV |
91 | |
92 | /* PDC registers */ | |
544fc728 HS |
93 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
94 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
95 | ||
96 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
97 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
98 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
99 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
100 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
101 | ||
102 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
103 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
104 | //#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR) | |
105 | //#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR) | |
1e6c9c28 | 106 | |
71f2e2b8 HS |
107 | static int (*atmel_open_hook)(struct uart_port *); |
108 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 109 | |
afefc415 AV |
110 | /* |
111 | * We wrap our port structure around the generic uart_port. | |
112 | */ | |
7192f92c | 113 | struct atmel_uart_port { |
afefc415 AV |
114 | struct uart_port uart; /* uart */ |
115 | struct clk *clk; /* uart clock */ | |
116 | unsigned short suspended; /* is port suspended? */ | |
9e6077bd | 117 | int break_active; /* break being received */ |
afefc415 AV |
118 | }; |
119 | ||
7192f92c | 120 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 121 | |
1e6c9c28 | 122 | #ifdef SUPPORT_SYSRQ |
7192f92c | 123 | static struct console atmel_console; |
1e6c9c28 AV |
124 | #endif |
125 | ||
126 | /* | |
127 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
128 | */ | |
7192f92c | 129 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 130 | { |
7192f92c | 131 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
132 | } |
133 | ||
134 | /* | |
135 | * Set state of the modem control output lines | |
136 | */ | |
7192f92c | 137 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
138 | { |
139 | unsigned int control = 0; | |
afefc415 | 140 | unsigned int mode; |
1e6c9c28 | 141 | |
c2f5ccfb | 142 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 143 | if (cpu_is_at91rm9200()) { |
afefc415 AV |
144 | /* |
145 | * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21. | |
146 | * We need to drive the pin manually. | |
147 | */ | |
72729910 | 148 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 149 | if (mctrl & TIOCM_RTS) |
20e65276 | 150 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 151 | else |
20e65276 | 152 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 153 | } |
1e6c9c28 | 154 | } |
acca9b83 | 155 | #endif |
1e6c9c28 AV |
156 | |
157 | if (mctrl & TIOCM_RTS) | |
7192f92c | 158 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 159 | else |
7192f92c | 160 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
161 | |
162 | if (mctrl & TIOCM_DTR) | |
7192f92c | 163 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 164 | else |
7192f92c | 165 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 166 | |
afefc415 AV |
167 | UART_PUT_CR(port, control); |
168 | ||
169 | /* Local loopback mode? */ | |
7192f92c | 170 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 171 | if (mctrl & TIOCM_LOOP) |
7192f92c | 172 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 173 | else |
7192f92c | 174 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 175 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
176 | } |
177 | ||
178 | /* | |
179 | * Get state of the modem control input lines | |
180 | */ | |
7192f92c | 181 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
182 | { |
183 | unsigned int status, ret = 0; | |
184 | ||
185 | status = UART_GET_CSR(port); | |
186 | ||
187 | /* | |
188 | * The control signals are active low. | |
189 | */ | |
7192f92c | 190 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 191 | ret |= TIOCM_CD; |
7192f92c | 192 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 193 | ret |= TIOCM_CTS; |
7192f92c | 194 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 195 | ret |= TIOCM_DSR; |
7192f92c | 196 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
197 | ret |= TIOCM_RI; |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
202 | /* | |
203 | * Stop transmitting. | |
204 | */ | |
7192f92c | 205 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 206 | { |
7192f92c | 207 | UART_PUT_IDR(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
208 | } |
209 | ||
210 | /* | |
211 | * Start transmitting. | |
212 | */ | |
7192f92c | 213 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 214 | { |
7192f92c | 215 | UART_PUT_IER(port, ATMEL_US_TXRDY); |
1e6c9c28 AV |
216 | } |
217 | ||
218 | /* | |
219 | * Stop receiving - port is in process of being closed. | |
220 | */ | |
7192f92c | 221 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 222 | { |
7192f92c | 223 | UART_PUT_IDR(port, ATMEL_US_RXRDY); |
1e6c9c28 AV |
224 | } |
225 | ||
226 | /* | |
227 | * Enable modem status interrupts | |
228 | */ | |
7192f92c | 229 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 230 | { |
7192f92c | 231 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC); |
1e6c9c28 AV |
232 | } |
233 | ||
234 | /* | |
235 | * Control the transmission of a break signal | |
236 | */ | |
7192f92c | 237 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
238 | { |
239 | if (break_state != 0) | |
7192f92c | 240 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 241 | else |
7192f92c | 242 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
243 | } |
244 | ||
245 | /* | |
246 | * Characters received (called from interrupt handler) | |
247 | */ | |
7d12e780 | 248 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 249 | { |
9e6077bd | 250 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
251 | struct tty_struct *tty = port->info->tty; |
252 | unsigned int status, ch, flg; | |
253 | ||
afefc415 | 254 | status = UART_GET_CSR(port); |
7192f92c | 255 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
256 | ch = UART_GET_CHAR(port); |
257 | ||
1e6c9c28 AV |
258 | port->icount.rx++; |
259 | ||
260 | flg = TTY_NORMAL; | |
261 | ||
262 | /* | |
263 | * note that the error handling code is | |
264 | * out of the main execution path | |
265 | */ | |
9e6077bd HS |
266 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
267 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
268 | || atmel_port->break_active)) { | |
7192f92c | 269 | UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */ |
9e6077bd HS |
270 | if (status & ATMEL_US_RXBRK |
271 | && !atmel_port->break_active) { | |
7192f92c | 272 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */ |
afefc415 | 273 | port->icount.brk++; |
9e6077bd HS |
274 | atmel_port->break_active = 1; |
275 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
afefc415 AV |
276 | if (uart_handle_break(port)) |
277 | goto ignore_char; | |
9e6077bd HS |
278 | } else { |
279 | /* | |
280 | * This is either the end-of-break | |
281 | * condition or we've received at | |
282 | * least one character without RXBRK | |
283 | * being set. In both cases, the next | |
284 | * RXBRK will indicate start-of-break. | |
285 | */ | |
286 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
287 | status &= ~ATMEL_US_RXBRK; | |
288 | atmel_port->break_active = 0; | |
afefc415 | 289 | } |
7192f92c | 290 | if (status & ATMEL_US_PARE) |
1e6c9c28 | 291 | port->icount.parity++; |
7192f92c | 292 | if (status & ATMEL_US_FRAME) |
1e6c9c28 | 293 | port->icount.frame++; |
7192f92c | 294 | if (status & ATMEL_US_OVRE) |
1e6c9c28 AV |
295 | port->icount.overrun++; |
296 | ||
afefc415 AV |
297 | status &= port->read_status_mask; |
298 | ||
7192f92c | 299 | if (status & ATMEL_US_RXBRK) |
afefc415 | 300 | flg = TTY_BREAK; |
7192f92c | 301 | else if (status & ATMEL_US_PARE) |
1e6c9c28 | 302 | flg = TTY_PARITY; |
7192f92c | 303 | else if (status & ATMEL_US_FRAME) |
1e6c9c28 | 304 | flg = TTY_FRAME; |
1e6c9c28 AV |
305 | } |
306 | ||
7d12e780 | 307 | if (uart_handle_sysrq_char(port, ch)) |
1e6c9c28 AV |
308 | goto ignore_char; |
309 | ||
7192f92c | 310 | uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg); |
1e6c9c28 AV |
311 | |
312 | ignore_char: | |
afefc415 | 313 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
314 | } |
315 | ||
316 | tty_flip_buffer_push(tty); | |
317 | } | |
318 | ||
319 | /* | |
320 | * Transmit characters (called from interrupt handler) | |
321 | */ | |
7192f92c | 322 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
323 | { |
324 | struct circ_buf *xmit = &port->info->xmit; | |
325 | ||
326 | if (port->x_char) { | |
327 | UART_PUT_CHAR(port, port->x_char); | |
328 | port->icount.tx++; | |
329 | port->x_char = 0; | |
330 | return; | |
331 | } | |
332 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
7192f92c | 333 | atmel_stop_tx(port); |
1e6c9c28 AV |
334 | return; |
335 | } | |
336 | ||
7192f92c | 337 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
338 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
339 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
340 | port->icount.tx++; | |
341 | if (uart_circ_empty(xmit)) | |
342 | break; | |
343 | } | |
344 | ||
345 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
346 | uart_write_wakeup(port); | |
347 | ||
348 | if (uart_circ_empty(xmit)) | |
7192f92c | 349 | atmel_stop_tx(port); |
1e6c9c28 AV |
350 | } |
351 | ||
352 | /* | |
353 | * Interrupt handler | |
354 | */ | |
7d12e780 | 355 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
356 | { |
357 | struct uart_port *port = dev_id; | |
7192f92c | 358 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 AV |
359 | unsigned int status, pending, pass_counter = 0; |
360 | ||
361 | status = UART_GET_CSR(port); | |
afefc415 AV |
362 | pending = status & UART_GET_IMR(port); |
363 | while (pending) { | |
364 | /* Interrupt receive */ | |
7192f92c | 365 | if (pending & ATMEL_US_RXRDY) |
7d12e780 | 366 | atmel_rx_chars(port); |
9e6077bd HS |
367 | else if (pending & ATMEL_US_RXBRK) { |
368 | /* | |
369 | * End of break detected. If it came along | |
370 | * with a character, atmel_rx_chars will | |
371 | * handle it. | |
372 | */ | |
373 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
374 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
375 | atmel_port->break_active = 0; | |
376 | } | |
afefc415 AV |
377 | |
378 | // TODO: All reads to CSR will clear these interrupts! | |
7192f92c HS |
379 | if (pending & ATMEL_US_RIIC) port->icount.rng++; |
380 | if (pending & ATMEL_US_DSRIC) port->icount.dsr++; | |
381 | if (pending & ATMEL_US_DCDIC) | |
382 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
383 | if (pending & ATMEL_US_CTSIC) | |
384 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
385 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC)) | |
afefc415 AV |
386 | wake_up_interruptible(&port->info->delta_msr_wait); |
387 | ||
388 | /* Interrupt transmit */ | |
7192f92c HS |
389 | if (pending & ATMEL_US_TXRDY) |
390 | atmel_tx_chars(port); | |
afefc415 | 391 | |
7192f92c | 392 | if (pass_counter++ > ATMEL_ISR_PASS_LIMIT) |
afefc415 | 393 | break; |
1e6c9c28 | 394 | |
afefc415 AV |
395 | status = UART_GET_CSR(port); |
396 | pending = status & UART_GET_IMR(port); | |
1e6c9c28 AV |
397 | } |
398 | return IRQ_HANDLED; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Perform initialization and enable port for reception | |
403 | */ | |
7192f92c | 404 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 AV |
405 | { |
406 | int retval; | |
407 | ||
408 | /* | |
409 | * Ensure that no interrupts are enabled otherwise when | |
410 | * request_irq() is called we could get stuck trying to | |
411 | * handle an unexpected interrupt | |
412 | */ | |
413 | UART_PUT_IDR(port, -1); | |
414 | ||
415 | /* | |
416 | * Allocate the IRQ | |
417 | */ | |
7192f92c | 418 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port); |
1e6c9c28 | 419 | if (retval) { |
7192f92c | 420 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
421 | return retval; |
422 | } | |
423 | ||
424 | /* | |
425 | * If there is a specific "open" function (to register | |
426 | * control line interrupts) | |
427 | */ | |
71f2e2b8 HS |
428 | if (atmel_open_hook) { |
429 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
430 | if (retval) { |
431 | free_irq(port->irq, port); | |
432 | return retval; | |
433 | } | |
434 | } | |
435 | ||
1e6c9c28 AV |
436 | /* |
437 | * Finally, enable the serial port | |
438 | */ | |
7192f92c HS |
439 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
440 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */ | |
afefc415 | 441 | |
7192f92c | 442 | UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */ |
afefc415 | 443 | |
1e6c9c28 AV |
444 | return 0; |
445 | } | |
446 | ||
447 | /* | |
448 | * Disable the port | |
449 | */ | |
7192f92c | 450 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 AV |
451 | { |
452 | /* | |
453 | * Disable all interrupts, port and break condition. | |
454 | */ | |
7192f92c | 455 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
456 | UART_PUT_IDR(port, -1); |
457 | ||
458 | /* | |
459 | * Free the interrupt | |
460 | */ | |
461 | free_irq(port->irq, port); | |
462 | ||
463 | /* | |
464 | * If there is a specific "close" function (to unregister | |
465 | * control line interrupts) | |
466 | */ | |
71f2e2b8 HS |
467 | if (atmel_close_hook) |
468 | atmel_close_hook(port); | |
1e6c9c28 AV |
469 | } |
470 | ||
471 | /* | |
472 | * Power / Clock management. | |
473 | */ | |
7192f92c | 474 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) |
1e6c9c28 | 475 | { |
7192f92c | 476 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 | 477 | |
1e6c9c28 AV |
478 | switch (state) { |
479 | case 0: | |
480 | /* | |
481 | * Enable the peripheral clock for this serial port. | |
482 | * This is called on uart_open() or a resume event. | |
483 | */ | |
7192f92c | 484 | clk_enable(atmel_port->clk); |
1e6c9c28 AV |
485 | break; |
486 | case 3: | |
487 | /* | |
488 | * Disable the peripheral clock for this serial port. | |
489 | * This is called on uart_close() or a suspend event. | |
490 | */ | |
7192f92c | 491 | clk_disable(atmel_port->clk); |
1e6c9c28 AV |
492 | break; |
493 | default: | |
7192f92c | 494 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
495 | } |
496 | } | |
497 | ||
498 | /* | |
499 | * Change the port parameters | |
500 | */ | |
606d099c | 501 | static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old) |
1e6c9c28 AV |
502 | { |
503 | unsigned long flags; | |
504 | unsigned int mode, imr, quot, baud; | |
505 | ||
03abeac0 AV |
506 | /* Get current mode register */ |
507 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR); | |
508 | ||
1e6c9c28 AV |
509 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
510 | quot = uart_get_divisor(port, baud); | |
511 | ||
03abeac0 AV |
512 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
513 | quot /= 8; | |
514 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
515 | } | |
1e6c9c28 AV |
516 | |
517 | /* byte size */ | |
518 | switch (termios->c_cflag & CSIZE) { | |
519 | case CS5: | |
7192f92c | 520 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
521 | break; |
522 | case CS6: | |
7192f92c | 523 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
524 | break; |
525 | case CS7: | |
7192f92c | 526 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
527 | break; |
528 | default: | |
7192f92c | 529 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
530 | break; |
531 | } | |
532 | ||
533 | /* stop bits */ | |
534 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 535 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
536 | |
537 | /* parity */ | |
538 | if (termios->c_cflag & PARENB) { | |
539 | if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */ | |
540 | if (termios->c_cflag & PARODD) | |
7192f92c | 541 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 542 | else |
7192f92c | 543 | mode |= ATMEL_US_PAR_SPACE; |
1e6c9c28 AV |
544 | } |
545 | else if (termios->c_cflag & PARODD) | |
7192f92c | 546 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 547 | else |
7192f92c | 548 | mode |= ATMEL_US_PAR_EVEN; |
1e6c9c28 AV |
549 | } |
550 | else | |
7192f92c | 551 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
552 | |
553 | spin_lock_irqsave(&port->lock, flags); | |
554 | ||
7192f92c | 555 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 556 | if (termios->c_iflag & INPCK) |
7192f92c | 557 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 558 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 559 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
560 | |
561 | /* | |
562 | * Characters to ignore | |
563 | */ | |
564 | port->ignore_status_mask = 0; | |
565 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 566 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 567 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 568 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
569 | /* |
570 | * If we're ignoring parity and break indicators, | |
571 | * ignore overruns too (for real raw support). | |
572 | */ | |
573 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 574 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 AV |
575 | } |
576 | ||
577 | // TODO: Ignore all characters if CREAD is set. | |
578 | ||
579 | /* update the per-port timeout */ | |
580 | uart_update_timeout(port, termios->c_cflag, baud); | |
581 | ||
582 | /* disable interrupts and drain transmitter */ | |
583 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
584 | UART_PUT_IDR(port, -1); /* disable all interrupts */ | |
7192f92c | 585 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); } |
1e6c9c28 AV |
586 | |
587 | /* disable receiver and transmitter */ | |
7192f92c | 588 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
589 | |
590 | /* set the parity, stop bits and data size */ | |
591 | UART_PUT_MR(port, mode); | |
592 | ||
593 | /* set the baud rate */ | |
594 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
595 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
596 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
597 | |
598 | /* restore interrupts */ | |
599 | UART_PUT_IER(port, imr); | |
600 | ||
601 | /* CTS flow-control and modem-status interrupts */ | |
602 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
603 | port->ops->enable_ms(port); | |
604 | ||
605 | spin_unlock_irqrestore(&port->lock, flags); | |
606 | } | |
607 | ||
608 | /* | |
609 | * Return string describing the specified port | |
610 | */ | |
7192f92c | 611 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 612 | { |
9ab4f88b | 613 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
614 | } |
615 | ||
616 | /* | |
617 | * Release the memory region(s) being used by 'port'. | |
618 | */ | |
7192f92c | 619 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 620 | { |
afefc415 AV |
621 | struct platform_device *pdev = to_platform_device(port->dev); |
622 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
623 | ||
624 | release_mem_region(port->mapbase, size); | |
625 | ||
626 | if (port->flags & UPF_IOREMAP) { | |
627 | iounmap(port->membase); | |
628 | port->membase = NULL; | |
629 | } | |
1e6c9c28 AV |
630 | } |
631 | ||
632 | /* | |
633 | * Request the memory region(s) being used by 'port'. | |
634 | */ | |
7192f92c | 635 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 636 | { |
afefc415 AV |
637 | struct platform_device *pdev = to_platform_device(port->dev); |
638 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
639 | ||
7192f92c | 640 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
641 | return -EBUSY; |
642 | ||
643 | if (port->flags & UPF_IOREMAP) { | |
644 | port->membase = ioremap(port->mapbase, size); | |
645 | if (port->membase == NULL) { | |
646 | release_mem_region(port->mapbase, size); | |
647 | return -ENOMEM; | |
648 | } | |
649 | } | |
1e6c9c28 | 650 | |
afefc415 | 651 | return 0; |
1e6c9c28 AV |
652 | } |
653 | ||
654 | /* | |
655 | * Configure/autoconfigure the port. | |
656 | */ | |
7192f92c | 657 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
658 | { |
659 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 660 | port->type = PORT_ATMEL; |
7192f92c | 661 | atmel_request_port(port); |
1e6c9c28 AV |
662 | } |
663 | } | |
664 | ||
665 | /* | |
666 | * Verify the new serial_struct (for TIOCSSERIAL). | |
667 | */ | |
7192f92c | 668 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
669 | { |
670 | int ret = 0; | |
9ab4f88b | 671 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
672 | ret = -EINVAL; |
673 | if (port->irq != ser->irq) | |
674 | ret = -EINVAL; | |
675 | if (ser->io_type != SERIAL_IO_MEM) | |
676 | ret = -EINVAL; | |
677 | if (port->uartclk / 16 != ser->baud_base) | |
678 | ret = -EINVAL; | |
679 | if ((void *)port->mapbase != ser->iomem_base) | |
680 | ret = -EINVAL; | |
681 | if (port->iobase != ser->port) | |
682 | ret = -EINVAL; | |
683 | if (ser->hub6 != 0) | |
684 | ret = -EINVAL; | |
685 | return ret; | |
686 | } | |
687 | ||
7192f92c HS |
688 | static struct uart_ops atmel_pops = { |
689 | .tx_empty = atmel_tx_empty, | |
690 | .set_mctrl = atmel_set_mctrl, | |
691 | .get_mctrl = atmel_get_mctrl, | |
692 | .stop_tx = atmel_stop_tx, | |
693 | .start_tx = atmel_start_tx, | |
694 | .stop_rx = atmel_stop_rx, | |
695 | .enable_ms = atmel_enable_ms, | |
696 | .break_ctl = atmel_break_ctl, | |
697 | .startup = atmel_startup, | |
698 | .shutdown = atmel_shutdown, | |
699 | .set_termios = atmel_set_termios, | |
700 | .type = atmel_type, | |
701 | .release_port = atmel_release_port, | |
702 | .request_port = atmel_request_port, | |
703 | .config_port = atmel_config_port, | |
704 | .verify_port = atmel_verify_port, | |
705 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
706 | }; |
707 | ||
afefc415 AV |
708 | /* |
709 | * Configure the port from the platform device resource info. | |
710 | */ | |
7192f92c | 711 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev) |
1e6c9c28 | 712 | { |
7192f92c | 713 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 714 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
715 | |
716 | port->iotype = UPIO_MEM; | |
a14d5273 | 717 | port->flags = UPF_BOOT_AUTOCONF; |
7192f92c | 718 | port->ops = &atmel_pops; |
a14d5273 | 719 | port->fifosize = 1; |
afefc415 AV |
720 | port->line = pdev->id; |
721 | port->dev = &pdev->dev; | |
722 | ||
723 | port->mapbase = pdev->resource[0].start; | |
724 | port->irq = pdev->resource[1].start; | |
725 | ||
75d35213 HS |
726 | if (data->regs) |
727 | /* Already mapped by setup code */ | |
728 | port->membase = data->regs; | |
afefc415 AV |
729 | else { |
730 | port->flags |= UPF_IOREMAP; | |
731 | port->membase = NULL; | |
732 | } | |
1e6c9c28 | 733 | |
7192f92c HS |
734 | if (!atmel_port->clk) { /* for console, the clock could already be configured */ |
735 | atmel_port->clk = clk_get(&pdev->dev, "usart"); | |
736 | clk_enable(atmel_port->clk); | |
737 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 738 | } |
1e6c9c28 AV |
739 | } |
740 | ||
afefc415 AV |
741 | /* |
742 | * Register board-specific modem-control line handlers. | |
743 | */ | |
71f2e2b8 | 744 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
745 | { |
746 | if (fns->enable_ms) | |
7192f92c | 747 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 748 | if (fns->get_mctrl) |
7192f92c | 749 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 750 | if (fns->set_mctrl) |
7192f92c | 751 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
752 | atmel_open_hook = fns->open; |
753 | atmel_close_hook = fns->close; | |
7192f92c HS |
754 | atmel_pops.pm = fns->pm; |
755 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
756 | } |
757 | ||
1e6c9c28 | 758 | |
749c4e60 | 759 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 760 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 761 | { |
7192f92c | 762 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
d358788f RK |
763 | barrier(); |
764 | UART_PUT_CHAR(port, ch); | |
765 | } | |
1e6c9c28 AV |
766 | |
767 | /* | |
768 | * Interrupts are disabled on entering | |
769 | */ | |
7192f92c | 770 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 771 | { |
7192f92c | 772 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 773 | unsigned int status, imr; |
1e6c9c28 AV |
774 | |
775 | /* | |
776 | * First, save IMR and then disable interrupts | |
777 | */ | |
778 | imr = UART_GET_IMR(port); /* get interrupt mask */ | |
7192f92c | 779 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 780 | |
7192f92c | 781 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
782 | |
783 | /* | |
784 | * Finally, wait for transmitter to become empty | |
785 | * and restore IMR | |
786 | */ | |
787 | do { | |
788 | status = UART_GET_CSR(port); | |
7192f92c | 789 | } while (!(status & ATMEL_US_TXRDY)); |
1e6c9c28 AV |
790 | UART_PUT_IER(port, imr); /* set interrupts back the way they were */ |
791 | } | |
792 | ||
793 | /* | |
794 | * If the port was already initialised (eg, by a boot loader), try to determine | |
795 | * the current setup. | |
796 | */ | |
7192f92c | 797 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) |
1e6c9c28 AV |
798 | { |
799 | unsigned int mr, quot; | |
800 | ||
801 | // TODO: CR is a write-only register | |
802 | // unsigned int cr; | |
803 | // | |
7192f92c HS |
804 | // cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN); |
805 | // if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) { | |
1e6c9c28 AV |
806 | // /* ok, the port was enabled */ |
807 | // } | |
808 | ||
7192f92c HS |
809 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
810 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
811 | *bits = 8; |
812 | else | |
813 | *bits = 7; | |
814 | ||
7192f92c HS |
815 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
816 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 817 | *parity = 'e'; |
7192f92c | 818 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
819 | *parity = 'o'; |
820 | ||
4d5e392c HS |
821 | /* |
822 | * The serial core only rounds down when matching this to a | |
823 | * supported baud rate. Make sure we don't end up slightly | |
824 | * lower than one of those, as it would make us fall through | |
825 | * to a much lower baud rate than we really want. | |
826 | */ | |
1e6c9c28 | 827 | quot = UART_GET_BRGR(port); |
4d5e392c | 828 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
829 | } |
830 | ||
7192f92c | 831 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 832 | { |
7192f92c | 833 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
834 | int baud = 115200; |
835 | int bits = 8; | |
836 | int parity = 'n'; | |
837 | int flow = 'n'; | |
838 | ||
afefc415 AV |
839 | if (port->membase == 0) /* Port not initialized yet - delay setup */ |
840 | return -ENODEV; | |
1e6c9c28 | 841 | |
1e6c9c28 | 842 | UART_PUT_IDR(port, -1); /* disable interrupts */ |
7192f92c HS |
843 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
844 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
845 | |
846 | if (options) | |
847 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
848 | else | |
7192f92c | 849 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
850 | |
851 | return uart_set_options(port, co, baud, parity, bits, flow); | |
852 | } | |
853 | ||
7192f92c | 854 | static struct uart_driver atmel_uart; |
1e6c9c28 | 855 | |
7192f92c HS |
856 | static struct console atmel_console = { |
857 | .name = ATMEL_DEVICENAME, | |
858 | .write = atmel_console_write, | |
1e6c9c28 | 859 | .device = uart_console_device, |
7192f92c | 860 | .setup = atmel_console_setup, |
1e6c9c28 AV |
861 | .flags = CON_PRINTBUFFER, |
862 | .index = -1, | |
7192f92c | 863 | .data = &atmel_uart, |
1e6c9c28 AV |
864 | }; |
865 | ||
7192f92c | 866 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 867 | |
afefc415 AV |
868 | /* |
869 | * Early console initialization (before VM subsystem initialized). | |
870 | */ | |
7192f92c | 871 | static int __init atmel_console_init(void) |
1e6c9c28 | 872 | { |
73e2798b | 873 | if (atmel_default_console_device) { |
7192f92c HS |
874 | add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL); |
875 | atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device); | |
876 | register_console(&atmel_console); | |
afefc415 | 877 | } |
1e6c9c28 | 878 | |
1e6c9c28 AV |
879 | return 0; |
880 | } | |
7192f92c | 881 | console_initcall(atmel_console_init); |
1e6c9c28 | 882 | |
afefc415 AV |
883 | /* |
884 | * Late console initialization. | |
885 | */ | |
7192f92c | 886 | static int __init atmel_late_console_init(void) |
afefc415 | 887 | { |
7192f92c HS |
888 | if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED)) |
889 | register_console(&atmel_console); | |
afefc415 AV |
890 | |
891 | return 0; | |
892 | } | |
7192f92c | 893 | core_initcall(atmel_late_console_init); |
afefc415 | 894 | |
1e6c9c28 | 895 | #else |
7192f92c | 896 | #define ATMEL_CONSOLE_DEVICE NULL |
1e6c9c28 AV |
897 | #endif |
898 | ||
7192f92c | 899 | static struct uart_driver atmel_uart = { |
1e6c9c28 | 900 | .owner = THIS_MODULE, |
7192f92c HS |
901 | .driver_name = "atmel_serial", |
902 | .dev_name = ATMEL_DEVICENAME, | |
903 | .major = SERIAL_ATMEL_MAJOR, | |
1e6c9c28 | 904 | .minor = MINOR_START, |
73e2798b | 905 | .nr = ATMEL_MAX_UART, |
7192f92c | 906 | .cons = ATMEL_CONSOLE_DEVICE, |
1e6c9c28 AV |
907 | }; |
908 | ||
afefc415 | 909 | #ifdef CONFIG_PM |
7192f92c | 910 | static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state) |
1e6c9c28 | 911 | { |
afefc415 | 912 | struct uart_port *port = platform_get_drvdata(pdev); |
7192f92c | 913 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
914 | |
915 | if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock()) | |
916 | enable_irq_wake(port->irq); | |
917 | else { | |
7192f92c HS |
918 | uart_suspend_port(&atmel_uart, port); |
919 | atmel_port->suspended = 1; | |
afefc415 | 920 | } |
1e6c9c28 | 921 | |
afefc415 AV |
922 | return 0; |
923 | } | |
1e6c9c28 | 924 | |
7192f92c | 925 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
926 | { |
927 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 928 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
1e6c9c28 | 929 | |
7192f92c HS |
930 | if (atmel_port->suspended) { |
931 | uart_resume_port(&atmel_uart, port); | |
932 | atmel_port->suspended = 0; | |
1e6c9c28 | 933 | } |
9b938166 AV |
934 | else |
935 | disable_irq_wake(port->irq); | |
1e6c9c28 AV |
936 | |
937 | return 0; | |
938 | } | |
afefc415 | 939 | #else |
7192f92c HS |
940 | #define atmel_serial_suspend NULL |
941 | #define atmel_serial_resume NULL | |
afefc415 | 942 | #endif |
1e6c9c28 | 943 | |
7192f92c | 944 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 945 | { |
7192f92c | 946 | struct atmel_uart_port *port; |
afefc415 | 947 | int ret; |
1e6c9c28 | 948 | |
7192f92c HS |
949 | port = &atmel_ports[pdev->id]; |
950 | atmel_init_port(port, pdev); | |
1e6c9c28 | 951 | |
7192f92c | 952 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
afefc415 AV |
953 | if (!ret) { |
954 | device_init_wakeup(&pdev->dev, 1); | |
955 | platform_set_drvdata(pdev, port); | |
956 | } | |
957 | ||
958 | return ret; | |
959 | } | |
960 | ||
7192f92c | 961 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
962 | { |
963 | struct uart_port *port = platform_get_drvdata(pdev); | |
7192f92c | 964 | struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port; |
afefc415 AV |
965 | int ret = 0; |
966 | ||
7192f92c HS |
967 | clk_disable(atmel_port->clk); |
968 | clk_put(atmel_port->clk); | |
afefc415 AV |
969 | |
970 | device_init_wakeup(&pdev->dev, 0); | |
971 | platform_set_drvdata(pdev, NULL); | |
972 | ||
973 | if (port) { | |
7192f92c | 974 | ret = uart_remove_one_port(&atmel_uart, port); |
afefc415 AV |
975 | kfree(port); |
976 | } | |
977 | ||
978 | return ret; | |
979 | } | |
980 | ||
7192f92c HS |
981 | static struct platform_driver atmel_serial_driver = { |
982 | .probe = atmel_serial_probe, | |
983 | .remove = __devexit_p(atmel_serial_remove), | |
984 | .suspend = atmel_serial_suspend, | |
985 | .resume = atmel_serial_resume, | |
afefc415 | 986 | .driver = { |
1e8ea802 | 987 | .name = "atmel_usart", |
afefc415 AV |
988 | .owner = THIS_MODULE, |
989 | }, | |
990 | }; | |
991 | ||
7192f92c | 992 | static int __init atmel_serial_init(void) |
afefc415 AV |
993 | { |
994 | int ret; | |
995 | ||
7192f92c | 996 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
997 | if (ret) |
998 | return ret; | |
999 | ||
7192f92c | 1000 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1001 | if (ret) |
7192f92c | 1002 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1003 | |
1004 | return ret; | |
1005 | } | |
1006 | ||
7192f92c | 1007 | static void __exit atmel_serial_exit(void) |
afefc415 | 1008 | { |
7192f92c HS |
1009 | platform_driver_unregister(&atmel_serial_driver); |
1010 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1011 | } |
1012 | ||
7192f92c HS |
1013 | module_init(atmel_serial_init); |
1014 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1015 | |
1016 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1017 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1018 | MODULE_LICENSE("GPL"); |