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194de561 BW |
1 | /* |
2 | * File: drivers/serial/bfin_5xx.c | |
3 | * Based on: Based on drivers/serial/sa1100.c | |
4 | * Author: Aubrey Li <aubrey.li@analog.com> | |
5 | * | |
6 | * Created: | |
7 | * Description: Driver for blackfin 5xx serial ports | |
8 | * | |
194de561 BW |
9 | * Modified: |
10 | * Copyright 2006 Analog Devices Inc. | |
11 | * | |
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, see the file COPYING, or write | |
26 | * to the Free Software Foundation, Inc., | |
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
28 | */ | |
29 | ||
30 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
31 | #define SUPPORT_SYSRQ | |
32 | #endif | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/sysrq.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/tty.h> | |
41 | #include <linux/tty_flip.h> | |
42 | #include <linux/serial_core.h> | |
43 | ||
474f1a66 SZ |
44 | #ifdef CONFIG_KGDB_UART |
45 | #include <linux/kgdb.h> | |
46 | #include <asm/irq_regs.h> | |
47 | #endif | |
48 | ||
194de561 BW |
49 | #include <asm/gpio.h> |
50 | #include <asm/mach/bfin_serial_5xx.h> | |
51 | ||
52 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
53 | #include <linux/dma-mapping.h> | |
54 | #include <asm/io.h> | |
55 | #include <asm/irq.h> | |
56 | #include <asm/cacheflush.h> | |
57 | #endif | |
58 | ||
59 | /* UART name and device definitions */ | |
60 | #define BFIN_SERIAL_NAME "ttyBF" | |
61 | #define BFIN_SERIAL_MAJOR 204 | |
62 | #define BFIN_SERIAL_MINOR 64 | |
63 | ||
64 | /* | |
65 | * Setup for console. Argument comes from the menuconfig | |
66 | */ | |
67 | #define DMA_RX_XCOUNT 512 | |
68 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
69 | ||
70 | #define DMA_RX_FLUSH_JIFFIES 5 | |
71 | ||
72 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
73 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
74 | #else | |
75 | static void bfin_serial_do_work(struct work_struct *work); | |
76 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); | |
77 | static void local_put_char(struct bfin_serial_port *uart, char ch); | |
78 | #endif | |
79 | ||
80 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); | |
81 | ||
82 | /* | |
83 | * interrupts are disabled on entry | |
84 | */ | |
85 | static void bfin_serial_stop_tx(struct uart_port *port) | |
86 | { | |
87 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
88 | ||
f4d640c9 RH |
89 | #ifdef CONFIG_BF54x |
90 | while (!(UART_GET_LSR(uart) & TEMT)) | |
91 | continue; | |
92 | #endif | |
93 | ||
194de561 BW |
94 | #ifdef CONFIG_SERIAL_BFIN_DMA |
95 | disable_dma(uart->tx_dma_channel); | |
f4d640c9 RH |
96 | #else |
97 | #ifdef CONFIG_BF54x | |
98 | /* Waiting for Transmission Finished */ | |
99 | while (!(UART_GET_LSR(uart) & TFI)) | |
100 | continue; | |
101 | /* Clear TFI bit */ | |
102 | UART_PUT_LSR(uart, TFI); | |
103 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 BW |
104 | #else |
105 | unsigned short ier; | |
106 | ||
107 | ier = UART_GET_IER(uart); | |
108 | ier &= ~ETBEI; | |
109 | UART_PUT_IER(uart, ier); | |
110 | #endif | |
f4d640c9 | 111 | #endif |
194de561 BW |
112 | } |
113 | ||
114 | /* | |
115 | * port is locked and interrupts are disabled | |
116 | */ | |
117 | static void bfin_serial_start_tx(struct uart_port *port) | |
118 | { | |
119 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
120 | ||
121 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
122 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 RH |
123 | #else |
124 | #ifdef CONFIG_BF54x | |
125 | UART_SET_IER(uart, ETBEI); | |
194de561 BW |
126 | #else |
127 | unsigned short ier; | |
128 | ier = UART_GET_IER(uart); | |
129 | ier |= ETBEI; | |
130 | UART_PUT_IER(uart, ier); | |
131 | bfin_serial_tx_chars(uart); | |
132 | #endif | |
f4d640c9 | 133 | #endif |
194de561 BW |
134 | } |
135 | ||
136 | /* | |
137 | * Interrupts are enabled | |
138 | */ | |
139 | static void bfin_serial_stop_rx(struct uart_port *port) | |
140 | { | |
141 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
f4d640c9 RH |
142 | #ifdef CONFIG_BF54x |
143 | UART_CLEAR_IER(uart, ERBFI); | |
144 | #else | |
194de561 BW |
145 | unsigned short ier; |
146 | ||
147 | ier = UART_GET_IER(uart); | |
474f1a66 SZ |
148 | #ifdef CONFIG_KGDB_UART |
149 | if (uart->port.line != CONFIG_KGDB_UART_PORT) | |
150 | #endif | |
194de561 BW |
151 | ier &= ~ERBFI; |
152 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 153 | #endif |
194de561 BW |
154 | } |
155 | ||
156 | /* | |
157 | * Set the modem control timer to fire immediately. | |
158 | */ | |
159 | static void bfin_serial_enable_ms(struct uart_port *port) | |
160 | { | |
161 | } | |
162 | ||
474f1a66 SZ |
163 | #ifdef CONFIG_KGDB_UART |
164 | static int kgdb_entry_state; | |
165 | ||
166 | void kgdb_put_debug_char(int chr) | |
167 | { | |
168 | struct bfin_serial_port *uart; | |
169 | ||
170 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
171 | uart = &bfin_serial_ports[0]; | |
172 | else | |
173 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
174 | ||
175 | while (!(UART_GET_LSR(uart) & THRE)) { | |
d5148ffa | 176 | SSYNC(); |
474f1a66 SZ |
177 | } |
178 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); | |
d5148ffa | 179 | SSYNC(); |
474f1a66 | 180 | UART_PUT_CHAR(uart, (unsigned char)chr); |
d5148ffa | 181 | SSYNC(); |
474f1a66 SZ |
182 | } |
183 | ||
184 | int kgdb_get_debug_char(void) | |
185 | { | |
186 | struct bfin_serial_port *uart; | |
187 | unsigned char chr; | |
188 | ||
189 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
190 | uart = &bfin_serial_ports[0]; | |
191 | else | |
192 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
193 | ||
194 | while(!(UART_GET_LSR(uart) & DR)) { | |
d5148ffa | 195 | SSYNC(); |
474f1a66 SZ |
196 | } |
197 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); | |
d5148ffa | 198 | SSYNC(); |
474f1a66 | 199 | chr = UART_GET_CHAR(uart); |
d5148ffa | 200 | SSYNC(); |
474f1a66 SZ |
201 | |
202 | return chr; | |
203 | } | |
204 | #endif | |
205 | ||
194de561 BW |
206 | #ifdef CONFIG_SERIAL_BFIN_PIO |
207 | static void local_put_char(struct bfin_serial_port *uart, char ch) | |
208 | { | |
209 | unsigned short status; | |
210 | int flags = 0; | |
211 | ||
212 | spin_lock_irqsave(&uart->port.lock, flags); | |
213 | ||
214 | do { | |
215 | status = UART_GET_LSR(uart); | |
216 | } while (!(status & THRE)); | |
217 | ||
218 | UART_PUT_CHAR(uart, ch); | |
219 | SSYNC(); | |
220 | ||
221 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
222 | } | |
223 | ||
224 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) | |
225 | { | |
2ac5ee47 | 226 | struct tty_struct *tty = uart->port.info->tty; |
194de561 | 227 | unsigned int status, ch, flg; |
474f1a66 SZ |
228 | #ifdef CONFIG_KGDB_UART |
229 | struct pt_regs *regs = get_irq_regs(); | |
230 | #endif | |
194de561 BW |
231 | #ifdef BF533_FAMILY |
232 | static int in_break = 0; | |
233 | #endif | |
234 | ||
235 | status = UART_GET_LSR(uart); | |
236 | ch = UART_GET_CHAR(uart); | |
237 | uart->port.icount.rx++; | |
238 | ||
474f1a66 SZ |
239 | #ifdef CONFIG_KGDB_UART |
240 | if (uart->port.line == CONFIG_KGDB_UART_PORT) { | |
241 | if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */ | |
242 | kgdb_breakkey_pressed(regs); | |
243 | return; | |
244 | } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */ | |
245 | kgdb_entry_state = 1; | |
246 | } else if (kgdb_entry_state == 1 && ch == 'q') { | |
247 | kgdb_entry_state = 0; | |
248 | kgdb_breakkey_pressed(regs); | |
249 | return; | |
250 | } else if (ch == 0x3) {/* Ctrl + C */ | |
251 | kgdb_entry_state = 0; | |
252 | kgdb_breakkey_pressed(regs); | |
253 | return; | |
254 | } else { | |
255 | kgdb_entry_state = 0; | |
256 | } | |
257 | } | |
258 | #endif | |
259 | ||
194de561 BW |
260 | #ifdef BF533_FAMILY |
261 | /* The BF533 family of processors have a nice misbehavior where | |
262 | * they continuously generate characters for a "single" break. | |
263 | * We have to basically ignore this flood until the "next" valid | |
264 | * character comes across. All other Blackfin families operate | |
265 | * properly though. | |
266 | */ | |
267 | if (in_break) { | |
268 | if (ch != 0) { | |
269 | in_break = 0; | |
270 | ch = UART_GET_CHAR(uart); | |
2ac5ee47 MF |
271 | if (bfin_revid() < 5) |
272 | return; | |
273 | } else | |
274 | return; | |
194de561 BW |
275 | } |
276 | #endif | |
277 | ||
278 | if (status & BI) { | |
279 | #ifdef BF533_FAMILY | |
280 | in_break = 1; | |
281 | #endif | |
282 | uart->port.icount.brk++; | |
283 | if (uart_handle_break(&uart->port)) | |
284 | goto ignore_char; | |
9808901b | 285 | status &= ~(PE | FE); |
2ac5ee47 MF |
286 | } |
287 | if (status & PE) | |
194de561 | 288 | uart->port.icount.parity++; |
2ac5ee47 | 289 | if (status & OE) |
194de561 | 290 | uart->port.icount.overrun++; |
2ac5ee47 | 291 | if (status & FE) |
194de561 | 292 | uart->port.icount.frame++; |
2ac5ee47 MF |
293 | |
294 | status &= uart->port.read_status_mask; | |
295 | ||
296 | if (status & BI) | |
297 | flg = TTY_BREAK; | |
298 | else if (status & PE) | |
299 | flg = TTY_PARITY; | |
300 | else if (status & FE) | |
301 | flg = TTY_FRAME; | |
302 | else | |
194de561 BW |
303 | flg = TTY_NORMAL; |
304 | ||
305 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
306 | goto ignore_char; | |
194de561 | 307 | |
2ac5ee47 MF |
308 | uart_insert_char(&uart->port, status, OE, ch, flg); |
309 | ||
310 | ignore_char: | |
311 | tty_flip_buffer_push(tty); | |
194de561 BW |
312 | } |
313 | ||
314 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
315 | { | |
316 | struct circ_buf *xmit = &uart->port.info->xmit; | |
317 | ||
318 | if (uart->port.x_char) { | |
319 | UART_PUT_CHAR(uart, uart->port.x_char); | |
320 | uart->port.icount.tx++; | |
321 | uart->port.x_char = 0; | |
322 | return; | |
323 | } | |
324 | /* | |
325 | * Check the modem control lines before | |
326 | * transmitting anything. | |
327 | */ | |
328 | bfin_serial_mctrl_check(uart); | |
329 | ||
330 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
331 | bfin_serial_stop_tx(&uart->port); | |
332 | return; | |
333 | } | |
334 | ||
335 | local_put_char(uart, xmit->buf[xmit->tail]); | |
336 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
337 | uart->port.icount.tx++; | |
338 | ||
339 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
340 | uart_write_wakeup(&uart->port); | |
341 | ||
342 | if (uart_circ_empty(xmit)) | |
343 | bfin_serial_stop_tx(&uart->port); | |
344 | } | |
345 | ||
5c4e472b AL |
346 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
347 | { | |
348 | struct bfin_serial_port *uart = dev_id; | |
349 | ||
f4d640c9 RH |
350 | #ifdef CONFIG_BF54x |
351 | unsigned short status; | |
352 | spin_lock(&uart->port.lock); | |
353 | status = UART_GET_LSR(uart); | |
354 | while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) { | |
355 | bfin_serial_rx_chars(uart); | |
356 | status = UART_GET_LSR(uart); | |
357 | } | |
358 | spin_unlock(&uart->port.lock); | |
359 | #else | |
5c4e472b AL |
360 | spin_lock(&uart->port.lock); |
361 | while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY) | |
362 | bfin_serial_rx_chars(uart); | |
363 | spin_unlock(&uart->port.lock); | |
f4d640c9 | 364 | #endif |
5c4e472b AL |
365 | return IRQ_HANDLED; |
366 | } | |
367 | ||
368 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
369 | { |
370 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 371 | |
f4d640c9 RH |
372 | #ifdef CONFIG_BF54x |
373 | unsigned short status; | |
374 | spin_lock(&uart->port.lock); | |
375 | status = UART_GET_LSR(uart); | |
376 | while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) { | |
377 | bfin_serial_tx_chars(uart); | |
378 | status = UART_GET_LSR(uart); | |
379 | } | |
380 | spin_unlock(&uart->port.lock); | |
381 | #else | |
194de561 | 382 | spin_lock(&uart->port.lock); |
5c4e472b AL |
383 | while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY) |
384 | bfin_serial_tx_chars(uart); | |
194de561 | 385 | spin_unlock(&uart->port.lock); |
f4d640c9 | 386 | #endif |
194de561 BW |
387 | return IRQ_HANDLED; |
388 | } | |
389 | ||
5c4e472b | 390 | |
194de561 BW |
391 | static void bfin_serial_do_work(struct work_struct *work) |
392 | { | |
393 | struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue); | |
394 | ||
395 | bfin_serial_mctrl_check(uart); | |
396 | } | |
194de561 BW |
397 | #endif |
398 | ||
399 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
400 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
401 | { | |
402 | struct circ_buf *xmit = &uart->port.info->xmit; | |
403 | unsigned short ier; | |
404 | int flags = 0; | |
405 | ||
406 | if (!uart->tx_done) | |
407 | return; | |
408 | ||
409 | uart->tx_done = 0; | |
410 | ||
411 | if (uart->port.x_char) { | |
412 | UART_PUT_CHAR(uart, uart->port.x_char); | |
413 | uart->port.icount.tx++; | |
414 | uart->port.x_char = 0; | |
415 | uart->tx_done = 1; | |
416 | return; | |
417 | } | |
418 | /* | |
419 | * Check the modem control lines before | |
420 | * transmitting anything. | |
421 | */ | |
422 | bfin_serial_mctrl_check(uart); | |
423 | ||
424 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
425 | bfin_serial_stop_tx(&uart->port); | |
426 | uart->tx_done = 1; | |
427 | return; | |
428 | } | |
429 | ||
430 | spin_lock_irqsave(&uart->port.lock, flags); | |
431 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
432 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
433 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
434 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
435 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
436 | set_dma_config(uart->tx_dma_channel, | |
437 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
438 | INTR_ON_BUF, | |
439 | DIMENSION_LINEAR, | |
440 | DATA_SIZE_8)); | |
441 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); | |
442 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
443 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
444 | enable_dma(uart->tx_dma_channel); | |
f4d640c9 RH |
445 | #ifdef CONFIG_BF54x |
446 | UART_SET_IER(uart, ETBEI); | |
447 | #else | |
194de561 BW |
448 | ier = UART_GET_IER(uart); |
449 | ier |= ETBEI; | |
450 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 451 | #endif |
194de561 BW |
452 | spin_unlock_irqrestore(&uart->port.lock, flags); |
453 | } | |
454 | ||
2ac5ee47 | 455 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 BW |
456 | { |
457 | struct tty_struct *tty = uart->port.info->tty; | |
458 | int i, flg, status; | |
459 | ||
460 | status = UART_GET_LSR(uart); | |
461 | uart->port.icount.rx += CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, UART_XMIT_SIZE);; | |
462 | ||
463 | if (status & BI) { | |
464 | uart->port.icount.brk++; | |
465 | if (uart_handle_break(&uart->port)) | |
466 | goto dma_ignore_char; | |
9808901b | 467 | status &= ~(PE | FE); |
2ac5ee47 MF |
468 | } |
469 | if (status & PE) | |
194de561 | 470 | uart->port.icount.parity++; |
2ac5ee47 | 471 | if (status & OE) |
194de561 | 472 | uart->port.icount.overrun++; |
2ac5ee47 | 473 | if (status & FE) |
194de561 | 474 | uart->port.icount.frame++; |
2ac5ee47 MF |
475 | |
476 | status &= uart->port.read_status_mask; | |
477 | ||
478 | if (status & BI) | |
479 | flg = TTY_BREAK; | |
480 | else if (status & PE) | |
481 | flg = TTY_PARITY; | |
482 | else if (status & FE) | |
483 | flg = TTY_FRAME; | |
484 | else | |
194de561 BW |
485 | flg = TTY_NORMAL; |
486 | ||
487 | for (i = uart->rx_dma_buf.head; i < uart->rx_dma_buf.tail; i++) { | |
488 | if (uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) | |
489 | goto dma_ignore_char; | |
2ac5ee47 | 490 | uart_insert_char(&uart->port, status, OE, uart->rx_dma_buf.buf[i], flg); |
194de561 | 491 | } |
2ac5ee47 MF |
492 | |
493 | dma_ignore_char: | |
194de561 BW |
494 | tty_flip_buffer_push(tty); |
495 | } | |
496 | ||
497 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
498 | { | |
499 | int x_pos, pos; | |
500 | int flags = 0; | |
501 | ||
502 | bfin_serial_dma_tx_chars(uart); | |
503 | ||
504 | spin_lock_irqsave(&uart->port.lock, flags); | |
505 | x_pos = DMA_RX_XCOUNT - get_dma_curr_xcount(uart->rx_dma_channel); | |
506 | if (x_pos == DMA_RX_XCOUNT) | |
507 | x_pos = 0; | |
508 | ||
509 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
510 | ||
511 | if (pos>uart->rx_dma_buf.tail) { | |
512 | uart->rx_dma_buf.tail = pos; | |
513 | bfin_serial_dma_rx_chars(uart); | |
514 | uart->rx_dma_buf.head = uart->rx_dma_buf.tail; | |
515 | } | |
516 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
517 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
518 | add_timer(&(uart->rx_dma_timer)); | |
519 | } | |
520 | ||
521 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
522 | { | |
523 | struct bfin_serial_port *uart = dev_id; | |
524 | struct circ_buf *xmit = &uart->port.info->xmit; | |
525 | unsigned short ier; | |
526 | ||
527 | spin_lock(&uart->port.lock); | |
528 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
529 | clear_dma_irqstat(uart->tx_dma_channel); | |
530 | disable_dma(uart->tx_dma_channel); | |
f4d640c9 RH |
531 | #ifdef CONFIG_BF54x |
532 | UART_CLEAR_IER(uart, ETBEI); | |
533 | #else | |
194de561 BW |
534 | ier = UART_GET_IER(uart); |
535 | ier &= ~ETBEI; | |
536 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 537 | #endif |
194de561 BW |
538 | xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1); |
539 | uart->port.icount.tx+=uart->tx_count; | |
540 | ||
541 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
542 | uart_write_wakeup(&uart->port); | |
543 | ||
544 | if (uart_circ_empty(xmit)) | |
545 | bfin_serial_stop_tx(&uart->port); | |
546 | uart->tx_done = 1; | |
547 | } | |
548 | ||
549 | spin_unlock(&uart->port.lock); | |
550 | return IRQ_HANDLED; | |
551 | } | |
552 | ||
553 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
554 | { | |
555 | struct bfin_serial_port *uart = dev_id; | |
556 | unsigned short irqstat; | |
557 | ||
558 | uart->rx_dma_nrows++; | |
559 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) { | |
560 | uart->rx_dma_nrows = 0; | |
561 | uart->rx_dma_buf.tail = DMA_RX_XCOUNT*DMA_RX_YCOUNT; | |
562 | bfin_serial_dma_rx_chars(uart); | |
563 | uart->rx_dma_buf.head = uart->rx_dma_buf.tail = 0; | |
564 | } | |
565 | spin_lock(&uart->port.lock); | |
566 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
567 | clear_dma_irqstat(uart->rx_dma_channel); | |
568 | ||
569 | spin_unlock(&uart->port.lock); | |
570 | return IRQ_HANDLED; | |
571 | } | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * Return TIOCSER_TEMT when transmitter is not busy. | |
576 | */ | |
577 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
578 | { | |
579 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
580 | unsigned short lsr; | |
581 | ||
582 | lsr = UART_GET_LSR(uart); | |
583 | if (lsr & TEMT) | |
584 | return TIOCSER_TEMT; | |
585 | else | |
586 | return 0; | |
587 | } | |
588 | ||
589 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
590 | { | |
591 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
592 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
593 | if (uart->cts_pin < 0) | |
594 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
595 | ||
596 | if (gpio_get_value(uart->cts_pin)) | |
597 | return TIOCM_DSR | TIOCM_CAR; | |
598 | else | |
599 | #endif | |
600 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
601 | } | |
602 | ||
603 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
604 | { | |
605 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
606 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
607 | if (uart->rts_pin < 0) | |
608 | return; | |
609 | ||
610 | if (mctrl & TIOCM_RTS) | |
611 | gpio_set_value(uart->rts_pin, 0); | |
612 | else | |
613 | gpio_set_value(uart->rts_pin, 1); | |
614 | #endif | |
615 | } | |
616 | ||
617 | /* | |
618 | * Handle any change of modem status signal since we were last called. | |
619 | */ | |
620 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |
621 | { | |
622 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
623 | unsigned int status; | |
624 | # ifdef CONFIG_SERIAL_BFIN_DMA | |
625 | struct uart_info *info = uart->port.info; | |
626 | struct tty_struct *tty = info->tty; | |
627 | ||
628 | status = bfin_serial_get_mctrl(&uart->port); | |
629 | if (!(status & TIOCM_CTS)) { | |
630 | tty->hw_stopped = 1; | |
631 | } else { | |
632 | tty->hw_stopped = 0; | |
633 | } | |
634 | # else | |
635 | status = bfin_serial_get_mctrl(&uart->port); | |
636 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
637 | if (!(status & TIOCM_CTS)) | |
638 | schedule_work(&uart->cts_workqueue); | |
639 | # endif | |
640 | #endif | |
641 | } | |
642 | ||
643 | /* | |
644 | * Interrupts are always disabled. | |
645 | */ | |
646 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
647 | { | |
cf686762 MF |
648 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
649 | u16 lcr = UART_GET_LCR(uart); | |
650 | if (break_state) | |
651 | lcr |= SB; | |
652 | else | |
653 | lcr &= ~SB; | |
654 | UART_PUT_LCR(uart, lcr); | |
655 | SSYNC(); | |
194de561 BW |
656 | } |
657 | ||
658 | static int bfin_serial_startup(struct uart_port *port) | |
659 | { | |
660 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
661 | ||
662 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
663 | dma_addr_t dma_handle; | |
664 | ||
665 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
666 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
667 | return -EBUSY; | |
668 | } | |
669 | ||
670 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
671 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
672 | free_dma(uart->rx_dma_channel); | |
673 | return -EBUSY; | |
674 | } | |
675 | ||
676 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
677 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
678 | ||
679 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
680 | uart->rx_dma_buf.head = 0; | |
681 | uart->rx_dma_buf.tail = 0; | |
682 | uart->rx_dma_nrows = 0; | |
683 | ||
684 | set_dma_config(uart->rx_dma_channel, | |
685 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
686 | INTR_ON_ROW, DIMENSION_2D, | |
687 | DATA_SIZE_8)); | |
688 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); | |
689 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
690 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
691 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
692 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
693 | enable_dma(uart->rx_dma_channel); | |
694 | ||
695 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
696 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
697 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
698 | add_timer(&(uart->rx_dma_timer)); | |
699 | #else | |
474f1a66 SZ |
700 | # ifdef CONFIG_KGDB_UART |
701 | if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq | |
702 | # else | |
194de561 | 703 | if (request_irq |
474f1a66 | 704 | # endif |
5c4e472b | 705 | (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
194de561 BW |
706 | "BFIN_UART_RX", uart)) { |
707 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); | |
708 | return -EBUSY; | |
709 | } | |
710 | ||
711 | if (request_irq | |
5c4e472b | 712 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
713 | "BFIN_UART_TX", uart)) { |
714 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
715 | free_irq(uart->port.irq, uart); | |
716 | return -EBUSY; | |
717 | } | |
718 | #endif | |
f4d640c9 RH |
719 | #ifdef CONFIG_BF54x |
720 | UART_SET_IER(uart, ERBFI); | |
721 | #else | |
194de561 | 722 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); |
f4d640c9 | 723 | #endif |
194de561 BW |
724 | return 0; |
725 | } | |
726 | ||
727 | static void bfin_serial_shutdown(struct uart_port *port) | |
728 | { | |
729 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
730 | ||
731 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
732 | disable_dma(uart->tx_dma_channel); | |
733 | free_dma(uart->tx_dma_channel); | |
734 | disable_dma(uart->rx_dma_channel); | |
735 | free_dma(uart->rx_dma_channel); | |
736 | del_timer(&(uart->rx_dma_timer)); | |
737 | #else | |
474f1a66 SZ |
738 | #ifdef CONFIG_KGDB_UART |
739 | if (uart->port.line != CONFIG_KGDB_UART_PORT) | |
740 | #endif | |
194de561 BW |
741 | free_irq(uart->port.irq, uart); |
742 | free_irq(uart->port.irq+1, uart); | |
743 | #endif | |
744 | } | |
745 | ||
746 | static void | |
747 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
748 | struct ktermios *old) | |
749 | { | |
750 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
751 | unsigned long flags; | |
752 | unsigned int baud, quot; | |
753 | unsigned short val, ier, lsr, lcr = 0; | |
754 | ||
755 | switch (termios->c_cflag & CSIZE) { | |
756 | case CS8: | |
757 | lcr = WLS(8); | |
758 | break; | |
759 | case CS7: | |
760 | lcr = WLS(7); | |
761 | break; | |
762 | case CS6: | |
763 | lcr = WLS(6); | |
764 | break; | |
765 | case CS5: | |
766 | lcr = WLS(5); | |
767 | break; | |
768 | default: | |
769 | printk(KERN_ERR "%s: word lengh not supported\n", | |
770 | __FUNCTION__); | |
771 | } | |
772 | ||
773 | if (termios->c_cflag & CSTOPB) | |
774 | lcr |= STB; | |
19aa6382 | 775 | if (termios->c_cflag & PARENB) |
194de561 | 776 | lcr |= PEN; |
19aa6382 MF |
777 | if (!(termios->c_cflag & PARODD)) |
778 | lcr |= EPS; | |
779 | if (termios->c_cflag & CMSPAR) | |
780 | lcr |= STP; | |
194de561 | 781 | |
2ac5ee47 MF |
782 | port->read_status_mask = OE; |
783 | if (termios->c_iflag & INPCK) | |
784 | port->read_status_mask |= (FE | PE); | |
785 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
786 | port->read_status_mask |= BI; | |
194de561 | 787 | |
2ac5ee47 MF |
788 | /* |
789 | * Characters to ignore | |
790 | */ | |
791 | port->ignore_status_mask = 0; | |
792 | if (termios->c_iflag & IGNPAR) | |
793 | port->ignore_status_mask |= FE | PE; | |
794 | if (termios->c_iflag & IGNBRK) { | |
795 | port->ignore_status_mask |= BI; | |
796 | /* | |
797 | * If we're ignoring parity and break indicators, | |
798 | * ignore overruns too (for real raw support). | |
799 | */ | |
800 | if (termios->c_iflag & IGNPAR) | |
801 | port->ignore_status_mask |= OE; | |
802 | } | |
194de561 BW |
803 | |
804 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
805 | quot = uart_get_divisor(port, baud); | |
806 | spin_lock_irqsave(&uart->port.lock, flags); | |
807 | ||
808 | do { | |
809 | lsr = UART_GET_LSR(uart); | |
810 | } while (!(lsr & TEMT)); | |
811 | ||
812 | /* Disable UART */ | |
813 | ier = UART_GET_IER(uart); | |
f4d640c9 RH |
814 | #ifdef CONFIG_BF54x |
815 | UART_CLEAR_IER(uart, 0xF); | |
816 | #else | |
194de561 | 817 | UART_PUT_IER(uart, 0); |
f4d640c9 | 818 | #endif |
194de561 | 819 | |
f4d640c9 | 820 | #ifndef CONFIG_BF54x |
194de561 BW |
821 | /* Set DLAB in LCR to Access DLL and DLH */ |
822 | val = UART_GET_LCR(uart); | |
823 | val |= DLAB; | |
824 | UART_PUT_LCR(uart, val); | |
825 | SSYNC(); | |
f4d640c9 | 826 | #endif |
194de561 BW |
827 | |
828 | UART_PUT_DLL(uart, quot & 0xFF); | |
829 | SSYNC(); | |
830 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); | |
831 | SSYNC(); | |
832 | ||
f4d640c9 | 833 | #ifndef CONFIG_BF54x |
194de561 BW |
834 | /* Clear DLAB in LCR to Access THR RBR IER */ |
835 | val = UART_GET_LCR(uart); | |
836 | val &= ~DLAB; | |
837 | UART_PUT_LCR(uart, val); | |
838 | SSYNC(); | |
f4d640c9 | 839 | #endif |
194de561 BW |
840 | |
841 | UART_PUT_LCR(uart, lcr); | |
842 | ||
843 | /* Enable UART */ | |
f4d640c9 RH |
844 | #ifdef CONFIG_BF54x |
845 | UART_SET_IER(uart, ier); | |
846 | #else | |
194de561 | 847 | UART_PUT_IER(uart, ier); |
f4d640c9 | 848 | #endif |
194de561 BW |
849 | |
850 | val = UART_GET_GCTL(uart); | |
851 | val |= UCEN; | |
852 | UART_PUT_GCTL(uart, val); | |
853 | ||
854 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
855 | } | |
856 | ||
857 | static const char *bfin_serial_type(struct uart_port *port) | |
858 | { | |
859 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
860 | ||
861 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
862 | } | |
863 | ||
864 | /* | |
865 | * Release the memory region(s) being used by 'port'. | |
866 | */ | |
867 | static void bfin_serial_release_port(struct uart_port *port) | |
868 | { | |
869 | } | |
870 | ||
871 | /* | |
872 | * Request the memory region(s) being used by 'port'. | |
873 | */ | |
874 | static int bfin_serial_request_port(struct uart_port *port) | |
875 | { | |
876 | return 0; | |
877 | } | |
878 | ||
879 | /* | |
880 | * Configure/autoconfigure the port. | |
881 | */ | |
882 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
883 | { | |
884 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
885 | ||
886 | if (flags & UART_CONFIG_TYPE && | |
887 | bfin_serial_request_port(&uart->port) == 0) | |
888 | uart->port.type = PORT_BFIN; | |
889 | } | |
890 | ||
891 | /* | |
892 | * Verify the new serial_struct (for TIOCSSERIAL). | |
893 | * The only change we allow are to the flags and type, and | |
894 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
895 | */ | |
896 | static int | |
897 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
898 | { | |
899 | return 0; | |
900 | } | |
901 | ||
902 | static struct uart_ops bfin_serial_pops = { | |
903 | .tx_empty = bfin_serial_tx_empty, | |
904 | .set_mctrl = bfin_serial_set_mctrl, | |
905 | .get_mctrl = bfin_serial_get_mctrl, | |
906 | .stop_tx = bfin_serial_stop_tx, | |
907 | .start_tx = bfin_serial_start_tx, | |
908 | .stop_rx = bfin_serial_stop_rx, | |
909 | .enable_ms = bfin_serial_enable_ms, | |
910 | .break_ctl = bfin_serial_break_ctl, | |
911 | .startup = bfin_serial_startup, | |
912 | .shutdown = bfin_serial_shutdown, | |
913 | .set_termios = bfin_serial_set_termios, | |
914 | .type = bfin_serial_type, | |
915 | .release_port = bfin_serial_release_port, | |
916 | .request_port = bfin_serial_request_port, | |
917 | .config_port = bfin_serial_config_port, | |
918 | .verify_port = bfin_serial_verify_port, | |
919 | }; | |
920 | ||
921 | static void __init bfin_serial_init_ports(void) | |
922 | { | |
923 | static int first = 1; | |
924 | int i; | |
925 | ||
926 | if (!first) | |
927 | return; | |
928 | first = 0; | |
929 | ||
930 | for (i = 0; i < nr_ports; i++) { | |
931 | bfin_serial_ports[i].port.uartclk = get_sclk(); | |
932 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; | |
933 | bfin_serial_ports[i].port.line = i; | |
934 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
935 | bfin_serial_ports[i].port.membase = | |
936 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
937 | bfin_serial_ports[i].port.mapbase = | |
938 | bfin_serial_resource[i].uart_base_addr; | |
939 | bfin_serial_ports[i].port.irq = | |
940 | bfin_serial_resource[i].uart_irq; | |
941 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
942 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
943 | bfin_serial_ports[i].tx_done = 1; | |
944 | bfin_serial_ports[i].tx_count = 0; | |
945 | bfin_serial_ports[i].tx_dma_channel = | |
946 | bfin_serial_resource[i].uart_tx_dma_channel; | |
947 | bfin_serial_ports[i].rx_dma_channel = | |
948 | bfin_serial_resource[i].uart_rx_dma_channel; | |
949 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
950 | #else | |
951 | INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work); | |
952 | #endif | |
953 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
954 | bfin_serial_ports[i].cts_pin = | |
955 | bfin_serial_resource[i].uart_cts_pin; | |
956 | bfin_serial_ports[i].rts_pin = | |
957 | bfin_serial_resource[i].uart_rts_pin; | |
958 | #endif | |
959 | bfin_serial_hw_init(&bfin_serial_ports[i]); | |
194de561 | 960 | } |
f4d640c9 | 961 | |
194de561 BW |
962 | } |
963 | ||
964 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
194de561 BW |
965 | /* |
966 | * If the port was already initialised (eg, by a boot loader), | |
967 | * try to determine the current setup. | |
968 | */ | |
969 | static void __init | |
970 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
971 | int *parity, int *bits) | |
972 | { | |
973 | unsigned short status; | |
974 | ||
975 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
976 | if (status == (ERBFI | ETBEI)) { | |
977 | /* ok, the port was enabled */ | |
978 | unsigned short lcr, val; | |
979 | unsigned short dlh, dll; | |
980 | ||
981 | lcr = UART_GET_LCR(uart); | |
982 | ||
983 | *parity = 'n'; | |
984 | if (lcr & PEN) { | |
985 | if (lcr & EPS) | |
986 | *parity = 'e'; | |
987 | else | |
988 | *parity = 'o'; | |
989 | } | |
990 | switch (lcr & 0x03) { | |
991 | case 0: *bits = 5; break; | |
992 | case 1: *bits = 6; break; | |
993 | case 2: *bits = 7; break; | |
994 | case 3: *bits = 8; break; | |
995 | } | |
f4d640c9 | 996 | #ifndef CONFIG_BF54x |
194de561 BW |
997 | /* Set DLAB in LCR to Access DLL and DLH */ |
998 | val = UART_GET_LCR(uart); | |
999 | val |= DLAB; | |
1000 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1001 | #endif |
194de561 BW |
1002 | |
1003 | dll = UART_GET_DLL(uart); | |
1004 | dlh = UART_GET_DLH(uart); | |
1005 | ||
f4d640c9 | 1006 | #ifndef CONFIG_BF54x |
194de561 BW |
1007 | /* Clear DLAB in LCR to Access THR RBR IER */ |
1008 | val = UART_GET_LCR(uart); | |
1009 | val &= ~DLAB; | |
1010 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1011 | #endif |
194de561 BW |
1012 | |
1013 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1014 | } | |
1015 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits); | |
1016 | } | |
0ae53640 RG |
1017 | #endif |
1018 | ||
1019 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
1020 | static struct uart_driver bfin_serial_reg; | |
194de561 BW |
1021 | |
1022 | static int __init | |
1023 | bfin_serial_console_setup(struct console *co, char *options) | |
1024 | { | |
1025 | struct bfin_serial_port *uart; | |
0ae53640 | 1026 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1027 | int baud = 57600; |
1028 | int bits = 8; | |
1029 | int parity = 'n'; | |
0ae53640 | 1030 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1031 | int flow = 'r'; |
0ae53640 | 1032 | # else |
194de561 | 1033 | int flow = 'n'; |
0ae53640 RG |
1034 | # endif |
1035 | # endif | |
194de561 BW |
1036 | |
1037 | /* | |
1038 | * Check whether an invalid uart number has been specified, and | |
1039 | * if so, search for the first available port that does have | |
1040 | * console support. | |
1041 | */ | |
1042 | if (co->index == -1 || co->index >= nr_ports) | |
1043 | co->index = 0; | |
1044 | uart = &bfin_serial_ports[co->index]; | |
1045 | ||
0ae53640 | 1046 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1047 | if (options) |
1048 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1049 | else | |
1050 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1051 | ||
1052 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1053 | # else |
1054 | return 0; | |
1055 | # endif | |
1056 | } | |
1057 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1058 | defined (CONFIG_EARLY_PRINTK) */ | |
1059 | ||
1060 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1061 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1062 | { | |
1063 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1064 | while (!(UART_GET_LSR(uart) & THRE)) | |
1065 | barrier(); | |
1066 | UART_PUT_CHAR(uart, ch); | |
1067 | SSYNC(); | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Interrupts are disabled on entering | |
1072 | */ | |
1073 | static void | |
1074 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1075 | { | |
1076 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
1077 | int flags = 0; | |
1078 | ||
1079 | spin_lock_irqsave(&uart->port.lock, flags); | |
1080 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1081 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1082 | ||
194de561 BW |
1083 | } |
1084 | ||
194de561 BW |
1085 | static struct console bfin_serial_console = { |
1086 | .name = BFIN_SERIAL_NAME, | |
1087 | .write = bfin_serial_console_write, | |
1088 | .device = uart_console_device, | |
1089 | .setup = bfin_serial_console_setup, | |
1090 | .flags = CON_PRINTBUFFER, | |
1091 | .index = -1, | |
1092 | .data = &bfin_serial_reg, | |
1093 | }; | |
1094 | ||
1095 | static int __init bfin_serial_rs_console_init(void) | |
1096 | { | |
1097 | bfin_serial_init_ports(); | |
1098 | register_console(&bfin_serial_console); | |
474f1a66 SZ |
1099 | #ifdef CONFIG_KGDB_UART |
1100 | kgdb_entry_state = 0; | |
1101 | init_kgdb_uart(); | |
1102 | #endif | |
194de561 BW |
1103 | return 0; |
1104 | } | |
1105 | console_initcall(bfin_serial_rs_console_init); | |
1106 | ||
1107 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1108 | #else | |
1109 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1110 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1111 | ||
1112 | ||
1113 | #ifdef CONFIG_EARLY_PRINTK | |
1114 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1115 | { | |
1116 | unsigned timeout = 0xffff; | |
1117 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1118 | ||
1119 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1120 | cpu_relax(); | |
1121 | UART_PUT_CHAR(uart, ch); | |
1122 | } | |
1123 | ||
1124 | static __init void early_serial_write(struct console *con, const char *s, | |
1125 | unsigned int n) | |
1126 | { | |
1127 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1128 | unsigned int i; | |
1129 | ||
1130 | for (i = 0; i < n; i++, s++) { | |
1131 | if (*s == '\n') | |
1132 | early_serial_putc(&uart->port, '\r'); | |
1133 | early_serial_putc(&uart->port, *s); | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | static struct __init console bfin_early_serial_console = { | |
1138 | .name = "early_BFuart", | |
1139 | .write = early_serial_write, | |
1140 | .device = uart_console_device, | |
1141 | .flags = CON_PRINTBUFFER, | |
1142 | .setup = bfin_serial_console_setup, | |
1143 | .index = -1, | |
1144 | .data = &bfin_serial_reg, | |
1145 | }; | |
1146 | ||
1147 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1148 | unsigned int cflag) | |
1149 | { | |
1150 | struct bfin_serial_port *uart; | |
1151 | struct ktermios t; | |
1152 | ||
1153 | if (port == -1 || port >= nr_ports) | |
1154 | port = 0; | |
1155 | bfin_serial_init_ports(); | |
1156 | bfin_early_serial_console.index = port; | |
1157 | #ifdef CONFIG_KGDB_UART | |
1158 | kgdb_entry_state = 0; | |
1159 | init_kgdb_uart(); | |
194de561 | 1160 | #endif |
0ae53640 RG |
1161 | uart = &bfin_serial_ports[port]; |
1162 | t.c_cflag = cflag; | |
1163 | t.c_iflag = 0; | |
1164 | t.c_oflag = 0; | |
1165 | t.c_lflag = ICANON; | |
1166 | t.c_line = port; | |
1167 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1168 | return &bfin_early_serial_console; | |
1169 | } | |
1170 | ||
1171 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ | |
194de561 BW |
1172 | |
1173 | static struct uart_driver bfin_serial_reg = { | |
1174 | .owner = THIS_MODULE, | |
1175 | .driver_name = "bfin-uart", | |
1176 | .dev_name = BFIN_SERIAL_NAME, | |
1177 | .major = BFIN_SERIAL_MAJOR, | |
1178 | .minor = BFIN_SERIAL_MINOR, | |
1179 | .nr = NR_PORTS, | |
1180 | .cons = BFIN_SERIAL_CONSOLE, | |
1181 | }; | |
1182 | ||
1183 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1184 | { | |
1185 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1186 | ||
1187 | if (uart) | |
1188 | uart_suspend_port(&bfin_serial_reg, &uart->port); | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static int bfin_serial_resume(struct platform_device *dev) | |
1194 | { | |
1195 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1196 | ||
1197 | if (uart) | |
1198 | uart_resume_port(&bfin_serial_reg, &uart->port); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int bfin_serial_probe(struct platform_device *dev) | |
1204 | { | |
1205 | struct resource *res = dev->resource; | |
1206 | int i; | |
1207 | ||
1208 | for (i = 0; i < dev->num_resources; i++, res++) | |
1209 | if (res->flags & IORESOURCE_MEM) | |
1210 | break; | |
1211 | ||
1212 | if (i < dev->num_resources) { | |
1213 | for (i = 0; i < nr_ports; i++, res++) { | |
1214 | if (bfin_serial_ports[i].port.mapbase != res->start) | |
1215 | continue; | |
1216 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1217 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1218 | platform_set_drvdata(dev, &bfin_serial_ports[i]); | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | static int bfin_serial_remove(struct platform_device *pdev) | |
1226 | { | |
1227 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); | |
1228 | ||
1229 | ||
1230 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
1231 | gpio_free(uart->cts_pin); | |
1232 | gpio_free(uart->rts_pin); | |
1233 | #endif | |
1234 | ||
1235 | platform_set_drvdata(pdev, NULL); | |
1236 | ||
1237 | if (uart) | |
1238 | uart_remove_one_port(&bfin_serial_reg, &uart->port); | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static struct platform_driver bfin_serial_driver = { | |
1244 | .probe = bfin_serial_probe, | |
1245 | .remove = bfin_serial_remove, | |
1246 | .suspend = bfin_serial_suspend, | |
1247 | .resume = bfin_serial_resume, | |
1248 | .driver = { | |
1249 | .name = "bfin-uart", | |
1250 | }, | |
1251 | }; | |
1252 | ||
1253 | static int __init bfin_serial_init(void) | |
1254 | { | |
1255 | int ret; | |
474f1a66 SZ |
1256 | #ifdef CONFIG_KGDB_UART |
1257 | struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
1258 | struct termios t; | |
1259 | #endif | |
194de561 BW |
1260 | |
1261 | pr_info("Serial: Blackfin serial driver\n"); | |
1262 | ||
1263 | bfin_serial_init_ports(); | |
1264 | ||
1265 | ret = uart_register_driver(&bfin_serial_reg); | |
1266 | if (ret == 0) { | |
1267 | ret = platform_driver_register(&bfin_serial_driver); | |
1268 | if (ret) { | |
1269 | pr_debug("uart register failed\n"); | |
1270 | uart_unregister_driver(&bfin_serial_reg); | |
1271 | } | |
1272 | } | |
474f1a66 SZ |
1273 | #ifdef CONFIG_KGDB_UART |
1274 | if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) { | |
1275 | request_irq(uart->port.irq, bfin_serial_int, | |
1276 | IRQF_DISABLED, "BFIN_UART_RX", uart); | |
1277 | pr_info("Request irq for kgdb uart port\n"); | |
1278 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); | |
d5148ffa | 1279 | SSYNC(); |
474f1a66 SZ |
1280 | t.c_cflag = CS8|B57600; |
1281 | t.c_iflag = 0; | |
1282 | t.c_oflag = 0; | |
1283 | t.c_lflag = ICANON; | |
1284 | t.c_line = CONFIG_KGDB_UART_PORT; | |
1285 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1286 | } | |
1287 | #endif | |
194de561 BW |
1288 | return ret; |
1289 | } | |
1290 | ||
1291 | static void __exit bfin_serial_exit(void) | |
1292 | { | |
1293 | platform_driver_unregister(&bfin_serial_driver); | |
1294 | uart_unregister_driver(&bfin_serial_reg); | |
1295 | } | |
1296 | ||
1297 | module_init(bfin_serial_init); | |
1298 | module_exit(bfin_serial_exit); | |
1299 | ||
1300 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1301 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1302 | MODULE_LICENSE("GPL"); | |
1303 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); |