Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
1ba7a3ee | 4 | * Copyright 2006-2007 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
474f1a66 SZ |
25 | #ifdef CONFIG_KGDB_UART |
26 | #include <linux/kgdb.h> | |
27 | #include <asm/irq_regs.h> | |
28 | #endif | |
29 | ||
194de561 BW |
30 | #include <asm/gpio.h> |
31 | #include <asm/mach/bfin_serial_5xx.h> | |
32 | ||
33 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/irq.h> | |
37 | #include <asm/cacheflush.h> | |
38 | #endif | |
39 | ||
40 | /* UART name and device definitions */ | |
41 | #define BFIN_SERIAL_NAME "ttyBF" | |
42 | #define BFIN_SERIAL_MAJOR 204 | |
43 | #define BFIN_SERIAL_MINOR 64 | |
44 | ||
45 | /* | |
46 | * Setup for console. Argument comes from the menuconfig | |
47 | */ | |
48 | #define DMA_RX_XCOUNT 512 | |
49 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
50 | ||
0aef4564 | 51 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
52 | |
53 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
54 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
55 | #else | |
194de561 | 56 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
57 | #endif |
58 | ||
59 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); | |
60 | ||
61 | /* | |
62 | * interrupts are disabled on entry | |
63 | */ | |
64 | static void bfin_serial_stop_tx(struct uart_port *port) | |
65 | { | |
66 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
0711d857 | 67 | struct circ_buf *xmit = &uart->port.info->xmit; |
1b73351c | 68 | #if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA) |
759eb040 SZ |
69 | unsigned short ier; |
70 | #endif | |
194de561 | 71 | |
f4d640c9 | 72 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 73 | cpu_relax(); |
f4d640c9 | 74 | |
194de561 BW |
75 | #ifdef CONFIG_SERIAL_BFIN_DMA |
76 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
77 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
78 | uart->port.icount.tx += uart->tx_count; | |
79 | uart->tx_count = 0; | |
80 | uart->tx_done = 1; | |
f4d640c9 RH |
81 | #else |
82 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
83 | /* Clear TFI bit */ |
84 | UART_PUT_LSR(uart, TFI); | |
85 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 | 86 | #else |
194de561 BW |
87 | ier = UART_GET_IER(uart); |
88 | ier &= ~ETBEI; | |
89 | UART_PUT_IER(uart, ier); | |
90 | #endif | |
f4d640c9 | 91 | #endif |
194de561 BW |
92 | } |
93 | ||
94 | /* | |
95 | * port is locked and interrupts are disabled | |
96 | */ | |
97 | static void bfin_serial_start_tx(struct uart_port *port) | |
98 | { | |
99 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
100 | ||
101 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
102 | if (uart->tx_done) |
103 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 RH |
104 | #else |
105 | #ifdef CONFIG_BF54x | |
106 | UART_SET_IER(uart, ETBEI); | |
194de561 BW |
107 | #else |
108 | unsigned short ier; | |
109 | ier = UART_GET_IER(uart); | |
110 | ier |= ETBEI; | |
111 | UART_PUT_IER(uart, ier); | |
194de561 | 112 | #endif |
a359cca7 | 113 | bfin_serial_tx_chars(uart); |
f4d640c9 | 114 | #endif |
194de561 BW |
115 | } |
116 | ||
117 | /* | |
118 | * Interrupts are enabled | |
119 | */ | |
120 | static void bfin_serial_stop_rx(struct uart_port *port) | |
121 | { | |
122 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
a359cca7 SZ |
123 | #ifdef CONFIG_KGDB_UART |
124 | if (uart->port.line != CONFIG_KGDB_UART_PORT) { | |
125 | #endif | |
f4d640c9 RH |
126 | #ifdef CONFIG_BF54x |
127 | UART_CLEAR_IER(uart, ERBFI); | |
128 | #else | |
194de561 BW |
129 | unsigned short ier; |
130 | ||
131 | ier = UART_GET_IER(uart); | |
132 | ier &= ~ERBFI; | |
133 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 134 | #endif |
a359cca7 SZ |
135 | #ifdef CONFIG_KGDB_UART |
136 | } | |
137 | #endif | |
194de561 BW |
138 | } |
139 | ||
140 | /* | |
141 | * Set the modem control timer to fire immediately. | |
142 | */ | |
143 | static void bfin_serial_enable_ms(struct uart_port *port) | |
144 | { | |
145 | } | |
146 | ||
474f1a66 SZ |
147 | #ifdef CONFIG_KGDB_UART |
148 | static int kgdb_entry_state; | |
149 | ||
150 | void kgdb_put_debug_char(int chr) | |
151 | { | |
152 | struct bfin_serial_port *uart; | |
153 | ||
154 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
155 | uart = &bfin_serial_ports[0]; | |
156 | else | |
157 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
158 | ||
159 | while (!(UART_GET_LSR(uart) & THRE)) { | |
d5148ffa | 160 | SSYNC(); |
474f1a66 | 161 | } |
a359cca7 SZ |
162 | |
163 | #ifndef CONFIG_BF54x | |
474f1a66 | 164 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); |
d5148ffa | 165 | SSYNC(); |
a359cca7 | 166 | #endif |
474f1a66 | 167 | UART_PUT_CHAR(uart, (unsigned char)chr); |
d5148ffa | 168 | SSYNC(); |
474f1a66 SZ |
169 | } |
170 | ||
171 | int kgdb_get_debug_char(void) | |
172 | { | |
173 | struct bfin_serial_port *uart; | |
174 | unsigned char chr; | |
175 | ||
176 | if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS) | |
177 | uart = &bfin_serial_ports[0]; | |
178 | else | |
179 | uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
180 | ||
181 | while(!(UART_GET_LSR(uart) & DR)) { | |
d5148ffa | 182 | SSYNC(); |
474f1a66 | 183 | } |
a359cca7 | 184 | #ifndef CONFIG_BF54x |
474f1a66 | 185 | UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB)); |
d5148ffa | 186 | SSYNC(); |
a359cca7 | 187 | #endif |
474f1a66 | 188 | chr = UART_GET_CHAR(uart); |
d5148ffa | 189 | SSYNC(); |
474f1a66 SZ |
190 | |
191 | return chr; | |
192 | } | |
193 | #endif | |
194 | ||
8851c71e MF |
195 | #if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO) |
196 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) | |
197 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
198 | #else | |
199 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
200 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
201 | #endif | |
202 | ||
194de561 | 203 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
204 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
205 | { | |
2ac5ee47 | 206 | struct tty_struct *tty = uart->port.info->tty; |
194de561 | 207 | unsigned int status, ch, flg; |
8851c71e | 208 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
474f1a66 SZ |
209 | #ifdef CONFIG_KGDB_UART |
210 | struct pt_regs *regs = get_irq_regs(); | |
211 | #endif | |
194de561 | 212 | |
759eb040 | 213 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
214 | UART_CLEAR_LSR(uart); |
215 | ||
216 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
217 | uart->port.icount.rx++; |
218 | ||
474f1a66 SZ |
219 | #ifdef CONFIG_KGDB_UART |
220 | if (uart->port.line == CONFIG_KGDB_UART_PORT) { | |
221 | if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */ | |
222 | kgdb_breakkey_pressed(regs); | |
223 | return; | |
224 | } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */ | |
225 | kgdb_entry_state = 1; | |
226 | } else if (kgdb_entry_state == 1 && ch == 'q') { | |
227 | kgdb_entry_state = 0; | |
228 | kgdb_breakkey_pressed(regs); | |
229 | return; | |
230 | } else if (ch == 0x3) {/* Ctrl + C */ | |
231 | kgdb_entry_state = 0; | |
232 | kgdb_breakkey_pressed(regs); | |
233 | return; | |
234 | } else { | |
235 | kgdb_entry_state = 0; | |
236 | } | |
237 | } | |
238 | #endif | |
bbf275f0 MF |
239 | |
240 | if (ANOMALY_05000230) { | |
8851c71e MF |
241 | /* The BF533 (and BF561) family of processors have a nice anomaly |
242 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 243 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
244 | * character comes across. Due to the nature of the flood, it is |
245 | * not possible to reliably catch bytes that are sent too quickly | |
246 | * after this break. So application code talking to the Blackfin | |
247 | * which sends a break signal must allow at least 1.5 character | |
248 | * times after the end of the break for things to stabilize. This | |
249 | * timeout was picked as it must absolutely be larger than 1 | |
250 | * character time +/- some percent. So 1.5 sounds good. All other | |
251 | * Blackfin families operate properly. Woo. | |
bbf275f0 MF |
252 | * Note: While Anomaly 05000230 does not directly address this, |
253 | * the changes that went in for it also fixed this issue. | |
8851c71e | 254 | * That anomaly was fixed in 0.5+ silicon. I like bunnies. |
bbf275f0 | 255 | */ |
8851c71e MF |
256 | if (anomaly_start.tv_sec) { |
257 | struct timeval curr; | |
258 | suseconds_t usecs; | |
259 | ||
260 | if ((~ch & (~ch + 1)) & 0xff) | |
261 | goto known_good_char; | |
262 | ||
263 | do_gettimeofday(&curr); | |
264 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
265 | goto known_good_char; | |
266 | ||
267 | usecs = 0; | |
268 | if (curr.tv_sec != anomaly_start.tv_sec) | |
269 | usecs += USEC_PER_SEC; | |
270 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
271 | ||
272 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
273 | goto known_good_char; | |
274 | ||
275 | if (ch) | |
276 | anomaly_start.tv_sec = 0; | |
277 | else | |
278 | anomaly_start = curr; | |
279 | ||
280 | return; | |
281 | ||
282 | known_good_char: | |
283 | anomaly_start.tv_sec = 0; | |
bbf275f0 | 284 | } |
194de561 | 285 | } |
194de561 BW |
286 | |
287 | if (status & BI) { | |
bbf275f0 | 288 | if (ANOMALY_05000230) |
8851c71e MF |
289 | if (bfin_revid() < 5) |
290 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
291 | uart->port.icount.brk++; |
292 | if (uart_handle_break(&uart->port)) | |
293 | goto ignore_char; | |
9808901b | 294 | status &= ~(PE | FE); |
2ac5ee47 MF |
295 | } |
296 | if (status & PE) | |
194de561 | 297 | uart->port.icount.parity++; |
2ac5ee47 | 298 | if (status & OE) |
194de561 | 299 | uart->port.icount.overrun++; |
2ac5ee47 | 300 | if (status & FE) |
194de561 | 301 | uart->port.icount.frame++; |
2ac5ee47 MF |
302 | |
303 | status &= uart->port.read_status_mask; | |
304 | ||
305 | if (status & BI) | |
306 | flg = TTY_BREAK; | |
307 | else if (status & PE) | |
308 | flg = TTY_PARITY; | |
309 | else if (status & FE) | |
310 | flg = TTY_FRAME; | |
311 | else | |
194de561 BW |
312 | flg = TTY_NORMAL; |
313 | ||
314 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
315 | goto ignore_char; | |
194de561 | 316 | |
2ac5ee47 MF |
317 | uart_insert_char(&uart->port, status, OE, ch, flg); |
318 | ||
319 | ignore_char: | |
320 | tty_flip_buffer_push(tty); | |
194de561 BW |
321 | } |
322 | ||
323 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
324 | { | |
325 | struct circ_buf *xmit = &uart->port.info->xmit; | |
326 | ||
327 | if (uart->port.x_char) { | |
328 | UART_PUT_CHAR(uart, uart->port.x_char); | |
329 | uart->port.icount.tx++; | |
330 | uart->port.x_char = 0; | |
194de561 BW |
331 | } |
332 | /* | |
333 | * Check the modem control lines before | |
334 | * transmitting anything. | |
335 | */ | |
336 | bfin_serial_mctrl_check(uart); | |
337 | ||
338 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
339 | bfin_serial_stop_tx(&uart->port); | |
340 | return; | |
341 | } | |
342 | ||
759eb040 SZ |
343 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
344 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
345 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
346 | uart->port.icount.tx++; | |
347 | SSYNC(); | |
348 | } | |
194de561 BW |
349 | |
350 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
351 | uart_write_wakeup(&uart->port); | |
352 | ||
353 | if (uart_circ_empty(xmit)) | |
354 | bfin_serial_stop_tx(&uart->port); | |
355 | } | |
356 | ||
5c4e472b AL |
357 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
358 | { | |
359 | struct bfin_serial_port *uart = dev_id; | |
360 | ||
f4d640c9 | 361 | spin_lock(&uart->port.lock); |
0bcfd70e | 362 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 363 | bfin_serial_rx_chars(uart); |
f4d640c9 | 364 | spin_unlock(&uart->port.lock); |
759eb040 | 365 | |
5c4e472b AL |
366 | return IRQ_HANDLED; |
367 | } | |
368 | ||
369 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
370 | { |
371 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 372 | |
f4d640c9 | 373 | spin_lock(&uart->port.lock); |
0bcfd70e | 374 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 375 | bfin_serial_tx_chars(uart); |
f4d640c9 | 376 | spin_unlock(&uart->port.lock); |
759eb040 | 377 | |
194de561 BW |
378 | return IRQ_HANDLED; |
379 | } | |
4cb4f22b | 380 | #endif |
194de561 | 381 | |
4cb4f22b | 382 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 BW |
383 | static void bfin_serial_do_work(struct work_struct *work) |
384 | { | |
385 | struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue); | |
386 | ||
387 | bfin_serial_mctrl_check(uart); | |
388 | } | |
194de561 BW |
389 | #endif |
390 | ||
391 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
392 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
393 | { | |
394 | struct circ_buf *xmit = &uart->port.info->xmit; | |
395 | unsigned short ier; | |
194de561 | 396 | |
194de561 BW |
397 | uart->tx_done = 0; |
398 | ||
1b73351c | 399 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 400 | uart->tx_count = 0; |
1b73351c SZ |
401 | uart->tx_done = 1; |
402 | return; | |
403 | } | |
404 | ||
194de561 BW |
405 | if (uart->port.x_char) { |
406 | UART_PUT_CHAR(uart, uart->port.x_char); | |
407 | uart->port.icount.tx++; | |
408 | uart->port.x_char = 0; | |
194de561 | 409 | } |
1b73351c | 410 | |
194de561 BW |
411 | /* |
412 | * Check the modem control lines before | |
413 | * transmitting anything. | |
414 | */ | |
415 | bfin_serial_mctrl_check(uart); | |
416 | ||
194de561 BW |
417 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
418 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
419 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
420 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
421 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
422 | set_dma_config(uart->tx_dma_channel, | |
423 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
424 | INTR_ON_BUF, | |
425 | DIMENSION_LINEAR, | |
2047e40d MH |
426 | DATA_SIZE_8, |
427 | DMA_SYNC_RESTART)); | |
194de561 BW |
428 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
429 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
430 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
431 | enable_dma(uart->tx_dma_channel); | |
99ee7b5f | 432 | |
f4d640c9 RH |
433 | #ifdef CONFIG_BF54x |
434 | UART_SET_IER(uart, ETBEI); | |
435 | #else | |
194de561 BW |
436 | ier = UART_GET_IER(uart); |
437 | ier |= ETBEI; | |
438 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 439 | #endif |
194de561 BW |
440 | } |
441 | ||
2ac5ee47 | 442 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 BW |
443 | { |
444 | struct tty_struct *tty = uart->port.info->tty; | |
445 | int i, flg, status; | |
446 | ||
447 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
448 | UART_CLEAR_LSR(uart); |
449 | ||
56f5de8f SZ |
450 | uart->port.icount.rx += |
451 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
452 | UART_XMIT_SIZE); | |
194de561 BW |
453 | |
454 | if (status & BI) { | |
455 | uart->port.icount.brk++; | |
456 | if (uart_handle_break(&uart->port)) | |
457 | goto dma_ignore_char; | |
9808901b | 458 | status &= ~(PE | FE); |
2ac5ee47 MF |
459 | } |
460 | if (status & PE) | |
194de561 | 461 | uart->port.icount.parity++; |
2ac5ee47 | 462 | if (status & OE) |
194de561 | 463 | uart->port.icount.overrun++; |
2ac5ee47 | 464 | if (status & FE) |
194de561 | 465 | uart->port.icount.frame++; |
2ac5ee47 MF |
466 | |
467 | status &= uart->port.read_status_mask; | |
468 | ||
469 | if (status & BI) | |
470 | flg = TTY_BREAK; | |
471 | else if (status & PE) | |
472 | flg = TTY_PARITY; | |
473 | else if (status & FE) | |
474 | flg = TTY_FRAME; | |
475 | else | |
194de561 BW |
476 | flg = TTY_NORMAL; |
477 | ||
56f5de8f SZ |
478 | for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) { |
479 | if (i >= UART_XMIT_SIZE) | |
480 | i = 0; | |
481 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) | |
482 | uart_insert_char(&uart->port, status, OE, | |
483 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 484 | } |
2ac5ee47 MF |
485 | |
486 | dma_ignore_char: | |
194de561 BW |
487 | tty_flip_buffer_push(tty); |
488 | } | |
489 | ||
490 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
491 | { | |
492 | int x_pos, pos; | |
194de561 | 493 | |
56f5de8f SZ |
494 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
495 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
496 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
497 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
498 | uart->rx_dma_nrows = 0; | |
499 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
500 | if (x_pos == DMA_RX_XCOUNT) |
501 | x_pos = 0; | |
502 | ||
503 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
56f5de8f SZ |
504 | if (pos != uart->rx_dma_buf.tail) { |
505 | uart->rx_dma_buf.head = pos; | |
194de561 | 506 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 507 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 508 | } |
0aef4564 | 509 | |
194de561 BW |
510 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; |
511 | add_timer(&(uart->rx_dma_timer)); | |
512 | } | |
513 | ||
514 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
515 | { | |
516 | struct bfin_serial_port *uart = dev_id; | |
517 | struct circ_buf *xmit = &uart->port.info->xmit; | |
518 | unsigned short ier; | |
519 | ||
520 | spin_lock(&uart->port.lock); | |
521 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 522 | disable_dma(uart->tx_dma_channel); |
0711d857 | 523 | clear_dma_irqstat(uart->tx_dma_channel); |
f4d640c9 RH |
524 | #ifdef CONFIG_BF54x |
525 | UART_CLEAR_IER(uart, ETBEI); | |
526 | #else | |
194de561 BW |
527 | ier = UART_GET_IER(uart); |
528 | ier &= ~ETBEI; | |
529 | UART_PUT_IER(uart, ier); | |
f4d640c9 | 530 | #endif |
0711d857 SZ |
531 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
532 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 533 | |
56f5de8f SZ |
534 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
535 | uart_write_wakeup(&uart->port); | |
536 | ||
1b73351c | 537 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
538 | } |
539 | ||
540 | spin_unlock(&uart->port.lock); | |
541 | return IRQ_HANDLED; | |
542 | } | |
543 | ||
544 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
545 | { | |
546 | struct bfin_serial_port *uart = dev_id; | |
547 | unsigned short irqstat; | |
0711d857 | 548 | |
194de561 BW |
549 | spin_lock(&uart->port.lock); |
550 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
551 | clear_dma_irqstat(uart->rx_dma_channel); | |
194de561 | 552 | spin_unlock(&uart->port.lock); |
0aef4564 SZ |
553 | |
554 | del_timer(&(uart->rx_dma_timer)); | |
555 | uart->rx_dma_timer.expires = jiffies; | |
556 | add_timer(&(uart->rx_dma_timer)); | |
557 | ||
194de561 BW |
558 | return IRQ_HANDLED; |
559 | } | |
560 | #endif | |
561 | ||
562 | /* | |
563 | * Return TIOCSER_TEMT when transmitter is not busy. | |
564 | */ | |
565 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
566 | { | |
567 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
568 | unsigned short lsr; | |
569 | ||
570 | lsr = UART_GET_LSR(uart); | |
571 | if (lsr & TEMT) | |
572 | return TIOCSER_TEMT; | |
573 | else | |
574 | return 0; | |
575 | } | |
576 | ||
577 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
578 | { | |
579 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
580 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
581 | if (uart->cts_pin < 0) | |
582 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
583 | ||
db288381 SZ |
584 | # ifdef BF54x |
585 | if (UART_GET_MSR(uart) & CTS) | |
586 | # else | |
194de561 | 587 | if (gpio_get_value(uart->cts_pin)) |
db288381 | 588 | # endif |
194de561 BW |
589 | return TIOCM_DSR | TIOCM_CAR; |
590 | else | |
591 | #endif | |
592 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
593 | } | |
594 | ||
595 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
596 | { | |
597 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
598 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
599 | if (uart->rts_pin < 0) | |
600 | return; | |
601 | ||
602 | if (mctrl & TIOCM_RTS) | |
db288381 SZ |
603 | # ifdef BF54x |
604 | UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS); | |
605 | # else | |
194de561 | 606 | gpio_set_value(uart->rts_pin, 0); |
db288381 | 607 | # endif |
194de561 | 608 | else |
db288381 SZ |
609 | # ifdef BF54x |
610 | UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS); | |
611 | # else | |
194de561 | 612 | gpio_set_value(uart->rts_pin, 1); |
db288381 | 613 | # endif |
194de561 BW |
614 | #endif |
615 | } | |
616 | ||
617 | /* | |
618 | * Handle any change of modem status signal since we were last called. | |
619 | */ | |
620 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |
621 | { | |
622 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
623 | unsigned int status; | |
194de561 BW |
624 | struct uart_info *info = uart->port.info; |
625 | struct tty_struct *tty = info->tty; | |
626 | ||
627 | status = bfin_serial_get_mctrl(&uart->port); | |
4cb4f22b | 628 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
194de561 BW |
629 | if (!(status & TIOCM_CTS)) { |
630 | tty->hw_stopped = 1; | |
4cb4f22b | 631 | schedule_work(&uart->cts_workqueue); |
194de561 BW |
632 | } else { |
633 | tty->hw_stopped = 0; | |
634 | } | |
194de561 BW |
635 | #endif |
636 | } | |
637 | ||
638 | /* | |
639 | * Interrupts are always disabled. | |
640 | */ | |
641 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
642 | { | |
cf686762 MF |
643 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
644 | u16 lcr = UART_GET_LCR(uart); | |
645 | if (break_state) | |
646 | lcr |= SB; | |
647 | else | |
648 | lcr &= ~SB; | |
649 | UART_PUT_LCR(uart, lcr); | |
650 | SSYNC(); | |
194de561 BW |
651 | } |
652 | ||
653 | static int bfin_serial_startup(struct uart_port *port) | |
654 | { | |
655 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
656 | ||
657 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
658 | dma_addr_t dma_handle; | |
659 | ||
660 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
661 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
662 | return -EBUSY; | |
663 | } | |
664 | ||
665 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
666 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
667 | free_dma(uart->rx_dma_channel); | |
668 | return -EBUSY; | |
669 | } | |
670 | ||
671 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
672 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
673 | ||
674 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
675 | uart->rx_dma_buf.head = 0; | |
676 | uart->rx_dma_buf.tail = 0; | |
677 | uart->rx_dma_nrows = 0; | |
678 | ||
679 | set_dma_config(uart->rx_dma_channel, | |
680 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
681 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
682 | DATA_SIZE_8, |
683 | DMA_SYNC_RESTART)); | |
194de561 BW |
684 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
685 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
686 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
687 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
688 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
689 | enable_dma(uart->rx_dma_channel); | |
690 | ||
691 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
692 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
693 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
694 | add_timer(&(uart->rx_dma_timer)); | |
695 | #else | |
a359cca7 SZ |
696 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
697 | "BFIN_UART_RX", uart)) { | |
474f1a66 | 698 | # ifdef CONFIG_KGDB_UART |
a359cca7 | 699 | if (uart->port.line != CONFIG_KGDB_UART_PORT) { |
474f1a66 | 700 | # endif |
194de561 BW |
701 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
702 | return -EBUSY; | |
a359cca7 SZ |
703 | # ifdef CONFIG_KGDB_UART |
704 | } | |
705 | # endif | |
194de561 BW |
706 | } |
707 | ||
a359cca7 | 708 | |
194de561 | 709 | if (request_irq |
5c4e472b | 710 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
711 | "BFIN_UART_TX", uart)) { |
712 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
713 | free_irq(uart->port.irq, uart); | |
714 | return -EBUSY; | |
715 | } | |
716 | #endif | |
f4d640c9 RH |
717 | #ifdef CONFIG_BF54x |
718 | UART_SET_IER(uart, ERBFI); | |
719 | #else | |
194de561 | 720 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); |
f4d640c9 | 721 | #endif |
194de561 BW |
722 | return 0; |
723 | } | |
724 | ||
725 | static void bfin_serial_shutdown(struct uart_port *port) | |
726 | { | |
727 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
728 | ||
729 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
730 | disable_dma(uart->tx_dma_channel); | |
731 | free_dma(uart->tx_dma_channel); | |
732 | disable_dma(uart->rx_dma_channel); | |
733 | free_dma(uart->rx_dma_channel); | |
734 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 735 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 736 | #else |
474f1a66 SZ |
737 | #ifdef CONFIG_KGDB_UART |
738 | if (uart->port.line != CONFIG_KGDB_UART_PORT) | |
739 | #endif | |
194de561 BW |
740 | free_irq(uart->port.irq, uart); |
741 | free_irq(uart->port.irq+1, uart); | |
742 | #endif | |
743 | } | |
744 | ||
745 | static void | |
746 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
747 | struct ktermios *old) | |
748 | { | |
749 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
750 | unsigned long flags; | |
751 | unsigned int baud, quot; | |
752 | unsigned short val, ier, lsr, lcr = 0; | |
753 | ||
754 | switch (termios->c_cflag & CSIZE) { | |
755 | case CS8: | |
756 | lcr = WLS(8); | |
757 | break; | |
758 | case CS7: | |
759 | lcr = WLS(7); | |
760 | break; | |
761 | case CS6: | |
762 | lcr = WLS(6); | |
763 | break; | |
764 | case CS5: | |
765 | lcr = WLS(5); | |
766 | break; | |
767 | default: | |
768 | printk(KERN_ERR "%s: word lengh not supported\n", | |
769 | __FUNCTION__); | |
770 | } | |
771 | ||
772 | if (termios->c_cflag & CSTOPB) | |
773 | lcr |= STB; | |
19aa6382 | 774 | if (termios->c_cflag & PARENB) |
194de561 | 775 | lcr |= PEN; |
19aa6382 MF |
776 | if (!(termios->c_cflag & PARODD)) |
777 | lcr |= EPS; | |
778 | if (termios->c_cflag & CMSPAR) | |
779 | lcr |= STP; | |
194de561 | 780 | |
2ac5ee47 MF |
781 | port->read_status_mask = OE; |
782 | if (termios->c_iflag & INPCK) | |
783 | port->read_status_mask |= (FE | PE); | |
784 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
785 | port->read_status_mask |= BI; | |
194de561 | 786 | |
2ac5ee47 MF |
787 | /* |
788 | * Characters to ignore | |
789 | */ | |
790 | port->ignore_status_mask = 0; | |
791 | if (termios->c_iflag & IGNPAR) | |
792 | port->ignore_status_mask |= FE | PE; | |
793 | if (termios->c_iflag & IGNBRK) { | |
794 | port->ignore_status_mask |= BI; | |
795 | /* | |
796 | * If we're ignoring parity and break indicators, | |
797 | * ignore overruns too (for real raw support). | |
798 | */ | |
799 | if (termios->c_iflag & IGNPAR) | |
800 | port->ignore_status_mask |= OE; | |
801 | } | |
194de561 BW |
802 | |
803 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
804 | quot = uart_get_divisor(port, baud); | |
805 | spin_lock_irqsave(&uart->port.lock, flags); | |
806 | ||
8851c71e MF |
807 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
808 | ||
194de561 BW |
809 | do { |
810 | lsr = UART_GET_LSR(uart); | |
811 | } while (!(lsr & TEMT)); | |
812 | ||
813 | /* Disable UART */ | |
814 | ier = UART_GET_IER(uart); | |
f4d640c9 RH |
815 | #ifdef CONFIG_BF54x |
816 | UART_CLEAR_IER(uart, 0xF); | |
817 | #else | |
194de561 | 818 | UART_PUT_IER(uart, 0); |
f4d640c9 | 819 | #endif |
194de561 | 820 | |
f4d640c9 | 821 | #ifndef CONFIG_BF54x |
194de561 BW |
822 | /* Set DLAB in LCR to Access DLL and DLH */ |
823 | val = UART_GET_LCR(uart); | |
824 | val |= DLAB; | |
825 | UART_PUT_LCR(uart, val); | |
826 | SSYNC(); | |
f4d640c9 | 827 | #endif |
194de561 BW |
828 | |
829 | UART_PUT_DLL(uart, quot & 0xFF); | |
830 | SSYNC(); | |
831 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); | |
832 | SSYNC(); | |
833 | ||
f4d640c9 | 834 | #ifndef CONFIG_BF54x |
194de561 BW |
835 | /* Clear DLAB in LCR to Access THR RBR IER */ |
836 | val = UART_GET_LCR(uart); | |
837 | val &= ~DLAB; | |
838 | UART_PUT_LCR(uart, val); | |
839 | SSYNC(); | |
f4d640c9 | 840 | #endif |
194de561 BW |
841 | |
842 | UART_PUT_LCR(uart, lcr); | |
843 | ||
844 | /* Enable UART */ | |
f4d640c9 RH |
845 | #ifdef CONFIG_BF54x |
846 | UART_SET_IER(uart, ier); | |
847 | #else | |
194de561 | 848 | UART_PUT_IER(uart, ier); |
f4d640c9 | 849 | #endif |
194de561 BW |
850 | |
851 | val = UART_GET_GCTL(uart); | |
852 | val |= UCEN; | |
853 | UART_PUT_GCTL(uart, val); | |
854 | ||
855 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
856 | } | |
857 | ||
858 | static const char *bfin_serial_type(struct uart_port *port) | |
859 | { | |
860 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
861 | ||
862 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
863 | } | |
864 | ||
865 | /* | |
866 | * Release the memory region(s) being used by 'port'. | |
867 | */ | |
868 | static void bfin_serial_release_port(struct uart_port *port) | |
869 | { | |
870 | } | |
871 | ||
872 | /* | |
873 | * Request the memory region(s) being used by 'port'. | |
874 | */ | |
875 | static int bfin_serial_request_port(struct uart_port *port) | |
876 | { | |
877 | return 0; | |
878 | } | |
879 | ||
880 | /* | |
881 | * Configure/autoconfigure the port. | |
882 | */ | |
883 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
884 | { | |
885 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
886 | ||
887 | if (flags & UART_CONFIG_TYPE && | |
888 | bfin_serial_request_port(&uart->port) == 0) | |
889 | uart->port.type = PORT_BFIN; | |
890 | } | |
891 | ||
892 | /* | |
893 | * Verify the new serial_struct (for TIOCSSERIAL). | |
894 | * The only change we allow are to the flags and type, and | |
895 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
896 | */ | |
897 | static int | |
898 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
899 | { | |
900 | return 0; | |
901 | } | |
902 | ||
7d01b475 GY |
903 | /* |
904 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
905 | * In other cases, disable IrDA function. | |
906 | */ | |
907 | static void bfin_set_ldisc(struct tty_struct *tty) | |
908 | { | |
909 | int line = tty->index; | |
910 | unsigned short val; | |
911 | ||
912 | if (line >= tty->driver->num) | |
913 | return; | |
914 | ||
915 | switch (tty->ldisc.num) { | |
916 | case N_IRDA: | |
917 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
918 | val |= (IREN | RPOLC); | |
919 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
920 | break; | |
921 | default: | |
922 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
923 | val &= ~(IREN | RPOLC); | |
924 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
925 | } | |
926 | } | |
927 | ||
194de561 BW |
928 | static struct uart_ops bfin_serial_pops = { |
929 | .tx_empty = bfin_serial_tx_empty, | |
930 | .set_mctrl = bfin_serial_set_mctrl, | |
931 | .get_mctrl = bfin_serial_get_mctrl, | |
932 | .stop_tx = bfin_serial_stop_tx, | |
933 | .start_tx = bfin_serial_start_tx, | |
934 | .stop_rx = bfin_serial_stop_rx, | |
935 | .enable_ms = bfin_serial_enable_ms, | |
936 | .break_ctl = bfin_serial_break_ctl, | |
937 | .startup = bfin_serial_startup, | |
938 | .shutdown = bfin_serial_shutdown, | |
939 | .set_termios = bfin_serial_set_termios, | |
940 | .type = bfin_serial_type, | |
941 | .release_port = bfin_serial_release_port, | |
942 | .request_port = bfin_serial_request_port, | |
943 | .config_port = bfin_serial_config_port, | |
944 | .verify_port = bfin_serial_verify_port, | |
945 | }; | |
946 | ||
947 | static void __init bfin_serial_init_ports(void) | |
948 | { | |
949 | static int first = 1; | |
950 | int i; | |
951 | ||
952 | if (!first) | |
953 | return; | |
954 | first = 0; | |
955 | ||
956 | for (i = 0; i < nr_ports; i++) { | |
957 | bfin_serial_ports[i].port.uartclk = get_sclk(); | |
958 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; | |
959 | bfin_serial_ports[i].port.line = i; | |
960 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
961 | bfin_serial_ports[i].port.membase = | |
962 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
963 | bfin_serial_ports[i].port.mapbase = | |
964 | bfin_serial_resource[i].uart_base_addr; | |
965 | bfin_serial_ports[i].port.irq = | |
966 | bfin_serial_resource[i].uart_irq; | |
967 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
968 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
969 | bfin_serial_ports[i].tx_done = 1; | |
970 | bfin_serial_ports[i].tx_count = 0; | |
971 | bfin_serial_ports[i].tx_dma_channel = | |
972 | bfin_serial_resource[i].uart_tx_dma_channel; | |
973 | bfin_serial_ports[i].rx_dma_channel = | |
974 | bfin_serial_resource[i].uart_rx_dma_channel; | |
975 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 BW |
976 | #endif |
977 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
4cb4f22b | 978 | INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work); |
194de561 BW |
979 | bfin_serial_ports[i].cts_pin = |
980 | bfin_serial_resource[i].uart_cts_pin; | |
981 | bfin_serial_ports[i].rts_pin = | |
982 | bfin_serial_resource[i].uart_rts_pin; | |
983 | #endif | |
984 | bfin_serial_hw_init(&bfin_serial_ports[i]); | |
194de561 | 985 | } |
f4d640c9 | 986 | |
194de561 BW |
987 | } |
988 | ||
989 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
194de561 BW |
990 | /* |
991 | * If the port was already initialised (eg, by a boot loader), | |
992 | * try to determine the current setup. | |
993 | */ | |
994 | static void __init | |
995 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
996 | int *parity, int *bits) | |
997 | { | |
998 | unsigned short status; | |
999 | ||
1000 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1001 | if (status == (ERBFI | ETBEI)) { | |
1002 | /* ok, the port was enabled */ | |
1003 | unsigned short lcr, val; | |
1004 | unsigned short dlh, dll; | |
1005 | ||
1006 | lcr = UART_GET_LCR(uart); | |
1007 | ||
1008 | *parity = 'n'; | |
1009 | if (lcr & PEN) { | |
1010 | if (lcr & EPS) | |
1011 | *parity = 'e'; | |
1012 | else | |
1013 | *parity = 'o'; | |
1014 | } | |
1015 | switch (lcr & 0x03) { | |
1016 | case 0: *bits = 5; break; | |
1017 | case 1: *bits = 6; break; | |
1018 | case 2: *bits = 7; break; | |
1019 | case 3: *bits = 8; break; | |
1020 | } | |
f4d640c9 | 1021 | #ifndef CONFIG_BF54x |
194de561 BW |
1022 | /* Set DLAB in LCR to Access DLL and DLH */ |
1023 | val = UART_GET_LCR(uart); | |
1024 | val |= DLAB; | |
1025 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1026 | #endif |
194de561 BW |
1027 | |
1028 | dll = UART_GET_DLL(uart); | |
1029 | dlh = UART_GET_DLH(uart); | |
1030 | ||
f4d640c9 | 1031 | #ifndef CONFIG_BF54x |
194de561 BW |
1032 | /* Clear DLAB in LCR to Access THR RBR IER */ |
1033 | val = UART_GET_LCR(uart); | |
1034 | val &= ~DLAB; | |
1035 | UART_PUT_LCR(uart, val); | |
f4d640c9 | 1036 | #endif |
194de561 BW |
1037 | |
1038 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1039 | } | |
1040 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits); | |
1041 | } | |
0ae53640 RG |
1042 | #endif |
1043 | ||
1044 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
1045 | static struct uart_driver bfin_serial_reg; | |
194de561 BW |
1046 | |
1047 | static int __init | |
1048 | bfin_serial_console_setup(struct console *co, char *options) | |
1049 | { | |
1050 | struct bfin_serial_port *uart; | |
0ae53640 | 1051 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1052 | int baud = 57600; |
1053 | int bits = 8; | |
1054 | int parity = 'n'; | |
0ae53640 | 1055 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1056 | int flow = 'r'; |
0ae53640 | 1057 | # else |
194de561 | 1058 | int flow = 'n'; |
0ae53640 RG |
1059 | # endif |
1060 | # endif | |
194de561 BW |
1061 | |
1062 | /* | |
1063 | * Check whether an invalid uart number has been specified, and | |
1064 | * if so, search for the first available port that does have | |
1065 | * console support. | |
1066 | */ | |
1067 | if (co->index == -1 || co->index >= nr_ports) | |
1068 | co->index = 0; | |
1069 | uart = &bfin_serial_ports[co->index]; | |
1070 | ||
0ae53640 | 1071 | # ifdef CONFIG_SERIAL_BFIN_CONSOLE |
194de561 BW |
1072 | if (options) |
1073 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1074 | else | |
1075 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1076 | ||
1077 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1078 | # else |
1079 | return 0; | |
1080 | # endif | |
1081 | } | |
1082 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1083 | defined (CONFIG_EARLY_PRINTK) */ | |
1084 | ||
1085 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1086 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1087 | { | |
1088 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1089 | while (!(UART_GET_LSR(uart) & THRE)) | |
1090 | barrier(); | |
1091 | UART_PUT_CHAR(uart, ch); | |
1092 | SSYNC(); | |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * Interrupts are disabled on entering | |
1097 | */ | |
1098 | static void | |
1099 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1100 | { | |
1101 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
1102 | int flags = 0; | |
1103 | ||
1104 | spin_lock_irqsave(&uart->port.lock, flags); | |
1105 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1106 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1107 | ||
194de561 BW |
1108 | } |
1109 | ||
194de561 BW |
1110 | static struct console bfin_serial_console = { |
1111 | .name = BFIN_SERIAL_NAME, | |
1112 | .write = bfin_serial_console_write, | |
1113 | .device = uart_console_device, | |
1114 | .setup = bfin_serial_console_setup, | |
1115 | .flags = CON_PRINTBUFFER, | |
1116 | .index = -1, | |
1117 | .data = &bfin_serial_reg, | |
1118 | }; | |
1119 | ||
1120 | static int __init bfin_serial_rs_console_init(void) | |
1121 | { | |
1122 | bfin_serial_init_ports(); | |
1123 | register_console(&bfin_serial_console); | |
474f1a66 SZ |
1124 | #ifdef CONFIG_KGDB_UART |
1125 | kgdb_entry_state = 0; | |
1126 | init_kgdb_uart(); | |
1127 | #endif | |
194de561 BW |
1128 | return 0; |
1129 | } | |
1130 | console_initcall(bfin_serial_rs_console_init); | |
1131 | ||
1132 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1133 | #else | |
1134 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1135 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1136 | ||
1137 | ||
1138 | #ifdef CONFIG_EARLY_PRINTK | |
1139 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1140 | { | |
1141 | unsigned timeout = 0xffff; | |
1142 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1143 | ||
1144 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1145 | cpu_relax(); | |
1146 | UART_PUT_CHAR(uart, ch); | |
1147 | } | |
1148 | ||
1149 | static __init void early_serial_write(struct console *con, const char *s, | |
1150 | unsigned int n) | |
1151 | { | |
1152 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1153 | unsigned int i; | |
1154 | ||
1155 | for (i = 0; i < n; i++, s++) { | |
1156 | if (*s == '\n') | |
1157 | early_serial_putc(&uart->port, '\r'); | |
1158 | early_serial_putc(&uart->port, *s); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | static struct __init console bfin_early_serial_console = { | |
1163 | .name = "early_BFuart", | |
1164 | .write = early_serial_write, | |
1165 | .device = uart_console_device, | |
1166 | .flags = CON_PRINTBUFFER, | |
1167 | .setup = bfin_serial_console_setup, | |
1168 | .index = -1, | |
1169 | .data = &bfin_serial_reg, | |
1170 | }; | |
1171 | ||
1172 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1173 | unsigned int cflag) | |
1174 | { | |
1175 | struct bfin_serial_port *uart; | |
1176 | struct ktermios t; | |
1177 | ||
1178 | if (port == -1 || port >= nr_ports) | |
1179 | port = 0; | |
1180 | bfin_serial_init_ports(); | |
1181 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1182 | uart = &bfin_serial_ports[port]; |
1183 | t.c_cflag = cflag; | |
1184 | t.c_iflag = 0; | |
1185 | t.c_oflag = 0; | |
1186 | t.c_lflag = ICANON; | |
1187 | t.c_line = port; | |
1188 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1189 | return &bfin_early_serial_console; | |
1190 | } | |
1191 | ||
1192 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ | |
194de561 BW |
1193 | |
1194 | static struct uart_driver bfin_serial_reg = { | |
1195 | .owner = THIS_MODULE, | |
1196 | .driver_name = "bfin-uart", | |
1197 | .dev_name = BFIN_SERIAL_NAME, | |
1198 | .major = BFIN_SERIAL_MAJOR, | |
1199 | .minor = BFIN_SERIAL_MINOR, | |
1200 | .nr = NR_PORTS, | |
1201 | .cons = BFIN_SERIAL_CONSOLE, | |
1202 | }; | |
1203 | ||
1204 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1205 | { | |
1206 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1207 | ||
1208 | if (uart) | |
1209 | uart_suspend_port(&bfin_serial_reg, &uart->port); | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int bfin_serial_resume(struct platform_device *dev) | |
1215 | { | |
1216 | struct bfin_serial_port *uart = platform_get_drvdata(dev); | |
1217 | ||
1218 | if (uart) | |
1219 | uart_resume_port(&bfin_serial_reg, &uart->port); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static int bfin_serial_probe(struct platform_device *dev) | |
1225 | { | |
1226 | struct resource *res = dev->resource; | |
1227 | int i; | |
1228 | ||
1229 | for (i = 0; i < dev->num_resources; i++, res++) | |
1230 | if (res->flags & IORESOURCE_MEM) | |
1231 | break; | |
1232 | ||
1233 | if (i < dev->num_resources) { | |
1234 | for (i = 0; i < nr_ports; i++, res++) { | |
1235 | if (bfin_serial_ports[i].port.mapbase != res->start) | |
1236 | continue; | |
1237 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1238 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1239 | platform_set_drvdata(dev, &bfin_serial_ports[i]); | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static int bfin_serial_remove(struct platform_device *pdev) | |
1247 | { | |
1248 | struct bfin_serial_port *uart = platform_get_drvdata(pdev); | |
1249 | ||
1250 | ||
1251 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
1252 | gpio_free(uart->cts_pin); | |
1253 | gpio_free(uart->rts_pin); | |
1254 | #endif | |
1255 | ||
1256 | platform_set_drvdata(pdev, NULL); | |
1257 | ||
1258 | if (uart) | |
1259 | uart_remove_one_port(&bfin_serial_reg, &uart->port); | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static struct platform_driver bfin_serial_driver = { | |
1265 | .probe = bfin_serial_probe, | |
1266 | .remove = bfin_serial_remove, | |
1267 | .suspend = bfin_serial_suspend, | |
1268 | .resume = bfin_serial_resume, | |
1269 | .driver = { | |
1270 | .name = "bfin-uart", | |
e169c139 | 1271 | .owner = THIS_MODULE, |
194de561 BW |
1272 | }, |
1273 | }; | |
1274 | ||
1275 | static int __init bfin_serial_init(void) | |
1276 | { | |
1277 | int ret; | |
474f1a66 SZ |
1278 | #ifdef CONFIG_KGDB_UART |
1279 | struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT]; | |
a359cca7 | 1280 | struct ktermios t; |
474f1a66 | 1281 | #endif |
194de561 BW |
1282 | |
1283 | pr_info("Serial: Blackfin serial driver\n"); | |
1284 | ||
1285 | bfin_serial_init_ports(); | |
1286 | ||
1287 | ret = uart_register_driver(&bfin_serial_reg); | |
1288 | if (ret == 0) { | |
7d01b475 | 1289 | bfin_serial_reg.tty_driver->set_ldisc = bfin_set_ldisc; |
194de561 BW |
1290 | ret = platform_driver_register(&bfin_serial_driver); |
1291 | if (ret) { | |
1292 | pr_debug("uart register failed\n"); | |
1293 | uart_unregister_driver(&bfin_serial_reg); | |
1294 | } | |
1295 | } | |
474f1a66 SZ |
1296 | #ifdef CONFIG_KGDB_UART |
1297 | if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) { | |
a359cca7 | 1298 | request_irq(uart->port.irq, bfin_serial_rx_int, |
474f1a66 SZ |
1299 | IRQF_DISABLED, "BFIN_UART_RX", uart); |
1300 | pr_info("Request irq for kgdb uart port\n"); | |
a359cca7 SZ |
1301 | #ifdef CONFIG_BF54x |
1302 | UART_SET_IER(uart, ERBFI); | |
1303 | #else | |
474f1a66 | 1304 | UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); |
a359cca7 | 1305 | #endif |
d5148ffa | 1306 | SSYNC(); |
474f1a66 SZ |
1307 | t.c_cflag = CS8|B57600; |
1308 | t.c_iflag = 0; | |
1309 | t.c_oflag = 0; | |
1310 | t.c_lflag = ICANON; | |
1311 | t.c_line = CONFIG_KGDB_UART_PORT; | |
1312 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1313 | } | |
1314 | #endif | |
194de561 BW |
1315 | return ret; |
1316 | } | |
1317 | ||
1318 | static void __exit bfin_serial_exit(void) | |
1319 | { | |
1320 | platform_driver_unregister(&bfin_serial_driver); | |
1321 | uart_unregister_driver(&bfin_serial_reg); | |
1322 | } | |
1323 | ||
1324 | module_init(bfin_serial_init); | |
1325 | module_exit(bfin_serial_exit); | |
1326 | ||
1327 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1328 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1329 | MODULE_LICENSE("GPL"); | |
1330 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1331 | MODULE_ALIAS("platform:bfin-uart"); |