Blackfin Serial Driver: macro away the IER differences between processors
[deliverable/linux.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
1ba7a3ee 4 * Copyright 2006-2007 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW
9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
474f1a66
SZ
25#ifdef CONFIG_KGDB_UART
26#include <linux/kgdb.h>
27#include <asm/irq_regs.h>
28#endif
29
194de561
BW
30#include <asm/gpio.h>
31#include <asm/mach/bfin_serial_5xx.h>
32
33#ifdef CONFIG_SERIAL_BFIN_DMA
34#include <linux/dma-mapping.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/cacheflush.h>
38#endif
39
40/* UART name and device definitions */
41#define BFIN_SERIAL_NAME "ttyBF"
42#define BFIN_SERIAL_MAJOR 204
43#define BFIN_SERIAL_MINOR 64
44
45/*
46 * Setup for console. Argument comes from the menuconfig
47 */
48#define DMA_RX_XCOUNT 512
49#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
50
0aef4564 51#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW
52
53#ifdef CONFIG_SERIAL_BFIN_DMA
54static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
55#else
194de561 56static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW
57#endif
58
59static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
60
61/*
62 * interrupts are disabled on entry
63 */
64static void bfin_serial_stop_tx(struct uart_port *port)
65{
66 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
0711d857 67 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 68
f4d640c9 69 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 70 cpu_relax();
f4d640c9 71
194de561
BW
72#ifdef CONFIG_SERIAL_BFIN_DMA
73 disable_dma(uart->tx_dma_channel);
0711d857
SZ
74 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
75 uart->port.icount.tx += uart->tx_count;
76 uart->tx_count = 0;
77 uart->tx_done = 1;
f4d640c9
RH
78#else
79#ifdef CONFIG_BF54x
f4d640c9
RH
80 /* Clear TFI bit */
81 UART_PUT_LSR(uart, TFI);
194de561 82#endif
89bf6dc5 83 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 84#endif
194de561
BW
85}
86
87/*
88 * port is locked and interrupts are disabled
89 */
90static void bfin_serial_start_tx(struct uart_port *port)
91{
92 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
93
94#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ
95 if (uart->tx_done)
96 bfin_serial_dma_tx_chars(uart);
f4d640c9 97#else
f4d640c9 98 UART_SET_IER(uart, ETBEI);
a359cca7 99 bfin_serial_tx_chars(uart);
f4d640c9 100#endif
194de561
BW
101}
102
103/*
104 * Interrupts are enabled
105 */
106static void bfin_serial_stop_rx(struct uart_port *port)
107{
108 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
89bf6dc5
MF
109#ifdef CONFIG_KGDB_UART
110 if (uart->port.line != CONFIG_KGDB_UART_PORT)
a359cca7 111#endif
f4d640c9 112 UART_CLEAR_IER(uart, ERBFI);
194de561
BW
113}
114
115/*
116 * Set the modem control timer to fire immediately.
117 */
118static void bfin_serial_enable_ms(struct uart_port *port)
119{
120}
121
474f1a66
SZ
122#ifdef CONFIG_KGDB_UART
123static int kgdb_entry_state;
124
125void kgdb_put_debug_char(int chr)
126{
127 struct bfin_serial_port *uart;
128
2ade9729
GY
129 if (CONFIG_KGDB_UART_PORT < 0
130 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ
131 uart = &bfin_serial_ports[0];
132 else
133 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
134
135 while (!(UART_GET_LSR(uart) & THRE)) {
d5148ffa 136 SSYNC();
474f1a66 137 }
a359cca7
SZ
138
139#ifndef CONFIG_BF54x
474f1a66 140 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 141 SSYNC();
a359cca7 142#endif
474f1a66 143 UART_PUT_CHAR(uart, (unsigned char)chr);
d5148ffa 144 SSYNC();
474f1a66
SZ
145}
146
147int kgdb_get_debug_char(void)
148{
149 struct bfin_serial_port *uart;
150 unsigned char chr;
151
2ade9729
GY
152 if (CONFIG_KGDB_UART_PORT < 0
153 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ
154 uart = &bfin_serial_ports[0];
155 else
156 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
157
158 while(!(UART_GET_LSR(uart) & DR)) {
d5148ffa 159 SSYNC();
474f1a66 160 }
a359cca7 161#ifndef CONFIG_BF54x
474f1a66 162 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 163 SSYNC();
a359cca7 164#endif
474f1a66 165 chr = UART_GET_CHAR(uart);
d5148ffa 166 SSYNC();
474f1a66
SZ
167
168 return chr;
169}
170#endif
171
50e2e15a 172#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF
173# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
174# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
175#else
176# define UART_GET_ANOMALY_THRESHOLD(uart) 0
177# define UART_SET_ANOMALY_THRESHOLD(uart, v)
178#endif
179
194de561 180#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW
181static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
182{
2ac5ee47 183 struct tty_struct *tty = uart->port.info->tty;
194de561 184 unsigned int status, ch, flg;
8851c71e 185 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 186
759eb040 187 status = UART_GET_LSR(uart);
0bcfd70e
MF
188 UART_CLEAR_LSR(uart);
189
190 ch = UART_GET_CHAR(uart);
194de561
BW
191 uart->port.icount.rx++;
192
474f1a66
SZ
193#ifdef CONFIG_KGDB_UART
194 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
89bf6dc5 195 struct pt_regs *regs = get_irq_regs();
474f1a66
SZ
196 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
197 kgdb_breakkey_pressed(regs);
198 return;
199 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
200 kgdb_entry_state = 1;
201 } else if (kgdb_entry_state == 1 && ch == 'q') {
202 kgdb_entry_state = 0;
203 kgdb_breakkey_pressed(regs);
204 return;
205 } else if (ch == 0x3) {/* Ctrl + C */
206 kgdb_entry_state = 0;
207 kgdb_breakkey_pressed(regs);
208 return;
209 } else {
210 kgdb_entry_state = 0;
211 }
212 }
213#endif
bbf275f0 214
50e2e15a 215 if (ANOMALY_05000363) {
8851c71e
MF
216 /* The BF533 (and BF561) family of processors have a nice anomaly
217 * where they continuously generate characters for a "single" break.
bbf275f0 218 * We have to basically ignore this flood until the "next" valid
8851c71e
MF
219 * character comes across. Due to the nature of the flood, it is
220 * not possible to reliably catch bytes that are sent too quickly
221 * after this break. So application code talking to the Blackfin
222 * which sends a break signal must allow at least 1.5 character
223 * times after the end of the break for things to stabilize. This
224 * timeout was picked as it must absolutely be larger than 1
225 * character time +/- some percent. So 1.5 sounds good. All other
226 * Blackfin families operate properly. Woo.
bbf275f0 227 */
8851c71e
MF
228 if (anomaly_start.tv_sec) {
229 struct timeval curr;
230 suseconds_t usecs;
231
232 if ((~ch & (~ch + 1)) & 0xff)
233 goto known_good_char;
234
235 do_gettimeofday(&curr);
236 if (curr.tv_sec - anomaly_start.tv_sec > 1)
237 goto known_good_char;
238
239 usecs = 0;
240 if (curr.tv_sec != anomaly_start.tv_sec)
241 usecs += USEC_PER_SEC;
242 usecs += curr.tv_usec - anomaly_start.tv_usec;
243
244 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
245 goto known_good_char;
246
247 if (ch)
248 anomaly_start.tv_sec = 0;
249 else
250 anomaly_start = curr;
251
252 return;
253
254 known_good_char:
255 anomaly_start.tv_sec = 0;
bbf275f0 256 }
194de561 257 }
194de561
BW
258
259 if (status & BI) {
50e2e15a 260 if (ANOMALY_05000363)
8851c71e
MF
261 if (bfin_revid() < 5)
262 do_gettimeofday(&anomaly_start);
194de561
BW
263 uart->port.icount.brk++;
264 if (uart_handle_break(&uart->port))
265 goto ignore_char;
9808901b 266 status &= ~(PE | FE);
2ac5ee47
MF
267 }
268 if (status & PE)
194de561 269 uart->port.icount.parity++;
2ac5ee47 270 if (status & OE)
194de561 271 uart->port.icount.overrun++;
2ac5ee47 272 if (status & FE)
194de561 273 uart->port.icount.frame++;
2ac5ee47
MF
274
275 status &= uart->port.read_status_mask;
276
277 if (status & BI)
278 flg = TTY_BREAK;
279 else if (status & PE)
280 flg = TTY_PARITY;
281 else if (status & FE)
282 flg = TTY_FRAME;
283 else
194de561
BW
284 flg = TTY_NORMAL;
285
286 if (uart_handle_sysrq_char(&uart->port, ch))
287 goto ignore_char;
194de561 288
2ac5ee47
MF
289 uart_insert_char(&uart->port, status, OE, ch, flg);
290
291 ignore_char:
292 tty_flip_buffer_push(tty);
194de561
BW
293}
294
295static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
296{
297 struct circ_buf *xmit = &uart->port.info->xmit;
298
299 if (uart->port.x_char) {
300 UART_PUT_CHAR(uart, uart->port.x_char);
301 uart->port.icount.tx++;
302 uart->port.x_char = 0;
194de561
BW
303 }
304 /*
305 * Check the modem control lines before
306 * transmitting anything.
307 */
308 bfin_serial_mctrl_check(uart);
309
310 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
311 bfin_serial_stop_tx(&uart->port);
312 return;
313 }
314
759eb040
SZ
315 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
316 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
317 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
318 uart->port.icount.tx++;
319 SSYNC();
320 }
194de561
BW
321
322 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
323 uart_write_wakeup(&uart->port);
324
325 if (uart_circ_empty(xmit))
326 bfin_serial_stop_tx(&uart->port);
327}
328
5c4e472b
AL
329static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
330{
331 struct bfin_serial_port *uart = dev_id;
332
f4d640c9 333 spin_lock(&uart->port.lock);
0bcfd70e 334 while (UART_GET_LSR(uart) & DR)
f4d640c9 335 bfin_serial_rx_chars(uart);
f4d640c9 336 spin_unlock(&uart->port.lock);
759eb040 337
5c4e472b
AL
338 return IRQ_HANDLED;
339}
340
341static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW
342{
343 struct bfin_serial_port *uart = dev_id;
194de561 344
f4d640c9 345 spin_lock(&uart->port.lock);
0bcfd70e 346 if (UART_GET_LSR(uart) & THRE)
f4d640c9 347 bfin_serial_tx_chars(uart);
f4d640c9 348 spin_unlock(&uart->port.lock);
759eb040 349
194de561
BW
350 return IRQ_HANDLED;
351}
4cb4f22b 352#endif
194de561 353
4cb4f22b 354#ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561
BW
355static void bfin_serial_do_work(struct work_struct *work)
356{
357 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
358
359 bfin_serial_mctrl_check(uart);
360}
194de561
BW
361#endif
362
363#ifdef CONFIG_SERIAL_BFIN_DMA
364static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
365{
366 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 367
194de561
BW
368 uart->tx_done = 0;
369
1b73351c 370 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 371 uart->tx_count = 0;
1b73351c
SZ
372 uart->tx_done = 1;
373 return;
374 }
375
194de561
BW
376 if (uart->port.x_char) {
377 UART_PUT_CHAR(uart, uart->port.x_char);
378 uart->port.icount.tx++;
379 uart->port.x_char = 0;
194de561 380 }
1b73351c 381
194de561
BW
382 /*
383 * Check the modem control lines before
384 * transmitting anything.
385 */
386 bfin_serial_mctrl_check(uart);
387
194de561
BW
388 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
389 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
390 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
391 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
392 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
393 set_dma_config(uart->tx_dma_channel,
394 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
395 INTR_ON_BUF,
396 DIMENSION_LINEAR,
2047e40d
MH
397 DATA_SIZE_8,
398 DMA_SYNC_RESTART));
194de561
BW
399 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
400 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
401 set_dma_x_modify(uart->tx_dma_channel, 1);
402 enable_dma(uart->tx_dma_channel);
99ee7b5f 403
f4d640c9 404 UART_SET_IER(uart, ETBEI);
194de561
BW
405}
406
2ac5ee47 407static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561
BW
408{
409 struct tty_struct *tty = uart->port.info->tty;
410 int i, flg, status;
411
412 status = UART_GET_LSR(uart);
0bcfd70e
MF
413 UART_CLEAR_LSR(uart);
414
56f5de8f
SZ
415 uart->port.icount.rx +=
416 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
417 UART_XMIT_SIZE);
194de561
BW
418
419 if (status & BI) {
420 uart->port.icount.brk++;
421 if (uart_handle_break(&uart->port))
422 goto dma_ignore_char;
9808901b 423 status &= ~(PE | FE);
2ac5ee47
MF
424 }
425 if (status & PE)
194de561 426 uart->port.icount.parity++;
2ac5ee47 427 if (status & OE)
194de561 428 uart->port.icount.overrun++;
2ac5ee47 429 if (status & FE)
194de561 430 uart->port.icount.frame++;
2ac5ee47
MF
431
432 status &= uart->port.read_status_mask;
433
434 if (status & BI)
435 flg = TTY_BREAK;
436 else if (status & PE)
437 flg = TTY_PARITY;
438 else if (status & FE)
439 flg = TTY_FRAME;
440 else
194de561
BW
441 flg = TTY_NORMAL;
442
56f5de8f
SZ
443 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
444 if (i >= UART_XMIT_SIZE)
445 i = 0;
446 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
447 uart_insert_char(&uart->port, status, OE,
448 uart->rx_dma_buf.buf[i], flg);
194de561 449 }
2ac5ee47
MF
450
451 dma_ignore_char:
194de561
BW
452 tty_flip_buffer_push(tty);
453}
454
455void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
456{
457 int x_pos, pos;
194de561 458
56f5de8f
SZ
459 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
460 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
461 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
462 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
463 uart->rx_dma_nrows = 0;
464 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW
465 if (x_pos == DMA_RX_XCOUNT)
466 x_pos = 0;
467
468 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
56f5de8f
SZ
469 if (pos != uart->rx_dma_buf.tail) {
470 uart->rx_dma_buf.head = pos;
194de561 471 bfin_serial_dma_rx_chars(uart);
56f5de8f 472 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 473 }
0aef4564 474
0a278423 475 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW
476}
477
478static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
479{
480 struct bfin_serial_port *uart = dev_id;
481 struct circ_buf *xmit = &uart->port.info->xmit;
194de561
BW
482
483 spin_lock(&uart->port.lock);
484 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 485 disable_dma(uart->tx_dma_channel);
0711d857 486 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9 487 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ
488 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
489 uart->port.icount.tx += uart->tx_count;
1b73351c 490
56f5de8f
SZ
491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&uart->port);
493
1b73351c 494 bfin_serial_dma_tx_chars(uart);
194de561
BW
495 }
496
497 spin_unlock(&uart->port.lock);
498 return IRQ_HANDLED;
499}
500
501static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
502{
503 struct bfin_serial_port *uart = dev_id;
504 unsigned short irqstat;
0711d857 505
194de561
BW
506 spin_lock(&uart->port.lock);
507 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
508 clear_dma_irqstat(uart->rx_dma_channel);
194de561 509 spin_unlock(&uart->port.lock);
0aef4564 510
0a278423 511 mod_timer(&(uart->rx_dma_timer), jiffies);
0aef4564 512
194de561
BW
513 return IRQ_HANDLED;
514}
515#endif
516
517/*
518 * Return TIOCSER_TEMT when transmitter is not busy.
519 */
520static unsigned int bfin_serial_tx_empty(struct uart_port *port)
521{
522 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
523 unsigned short lsr;
524
525 lsr = UART_GET_LSR(uart);
526 if (lsr & TEMT)
527 return TIOCSER_TEMT;
528 else
529 return 0;
530}
531
532static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
533{
534#ifdef CONFIG_SERIAL_BFIN_CTSRTS
535 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
536 if (uart->cts_pin < 0)
537 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
538
db288381
SZ
539# ifdef BF54x
540 if (UART_GET_MSR(uart) & CTS)
541# else
194de561 542 if (gpio_get_value(uart->cts_pin))
db288381 543# endif
194de561
BW
544 return TIOCM_DSR | TIOCM_CAR;
545 else
546#endif
547 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
548}
549
550static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
551{
552#ifdef CONFIG_SERIAL_BFIN_CTSRTS
553 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
554 if (uart->rts_pin < 0)
555 return;
556
557 if (mctrl & TIOCM_RTS)
db288381
SZ
558# ifdef BF54x
559 UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
560# else
194de561 561 gpio_set_value(uart->rts_pin, 0);
db288381 562# endif
194de561 563 else
db288381
SZ
564# ifdef BF54x
565 UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
566# else
194de561 567 gpio_set_value(uart->rts_pin, 1);
db288381 568# endif
194de561
BW
569#endif
570}
571
572/*
573 * Handle any change of modem status signal since we were last called.
574 */
575static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
576{
577#ifdef CONFIG_SERIAL_BFIN_CTSRTS
578 unsigned int status;
194de561
BW
579 struct uart_info *info = uart->port.info;
580 struct tty_struct *tty = info->tty;
581
582 status = bfin_serial_get_mctrl(&uart->port);
4cb4f22b 583 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
194de561
BW
584 if (!(status & TIOCM_CTS)) {
585 tty->hw_stopped = 1;
4cb4f22b 586 schedule_work(&uart->cts_workqueue);
194de561
BW
587 } else {
588 tty->hw_stopped = 0;
589 }
194de561
BW
590#endif
591}
592
593/*
594 * Interrupts are always disabled.
595 */
596static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
597{
cf686762
MF
598 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
599 u16 lcr = UART_GET_LCR(uart);
600 if (break_state)
601 lcr |= SB;
602 else
603 lcr &= ~SB;
604 UART_PUT_LCR(uart, lcr);
605 SSYNC();
194de561
BW
606}
607
608static int bfin_serial_startup(struct uart_port *port)
609{
610 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
611
612#ifdef CONFIG_SERIAL_BFIN_DMA
613 dma_addr_t dma_handle;
614
615 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
616 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
617 return -EBUSY;
618 }
619
620 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
621 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
622 free_dma(uart->rx_dma_channel);
623 return -EBUSY;
624 }
625
626 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
627 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
628
629 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
630 uart->rx_dma_buf.head = 0;
631 uart->rx_dma_buf.tail = 0;
632 uart->rx_dma_nrows = 0;
633
634 set_dma_config(uart->rx_dma_channel,
635 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
636 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH
637 DATA_SIZE_8,
638 DMA_SYNC_RESTART));
194de561
BW
639 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
640 set_dma_x_modify(uart->rx_dma_channel, 1);
641 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
642 set_dma_y_modify(uart->rx_dma_channel, 1);
643 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
644 enable_dma(uart->rx_dma_channel);
645
646 uart->rx_dma_timer.data = (unsigned long)(uart);
647 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
648 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
649 add_timer(&(uart->rx_dma_timer));
650#else
a359cca7
SZ
651 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
652 "BFIN_UART_RX", uart)) {
474f1a66 653# ifdef CONFIG_KGDB_UART
a359cca7 654 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
474f1a66 655# endif
194de561
BW
656 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
657 return -EBUSY;
a359cca7
SZ
658# ifdef CONFIG_KGDB_UART
659 }
660# endif
194de561
BW
661 }
662
663 if (request_irq
5c4e472b 664 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW
665 "BFIN_UART_TX", uart)) {
666 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
667 free_irq(uart->port.irq, uart);
668 return -EBUSY;
669 }
670#endif
f4d640c9 671 UART_SET_IER(uart, ERBFI);
194de561
BW
672 return 0;
673}
674
675static void bfin_serial_shutdown(struct uart_port *port)
676{
677 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
678
679#ifdef CONFIG_SERIAL_BFIN_DMA
680 disable_dma(uart->tx_dma_channel);
681 free_dma(uart->tx_dma_channel);
682 disable_dma(uart->rx_dma_channel);
683 free_dma(uart->rx_dma_channel);
684 del_timer(&(uart->rx_dma_timer));
75b780bd 685 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 686#else
474f1a66
SZ
687#ifdef CONFIG_KGDB_UART
688 if (uart->port.line != CONFIG_KGDB_UART_PORT)
689#endif
194de561
BW
690 free_irq(uart->port.irq, uart);
691 free_irq(uart->port.irq+1, uart);
692#endif
693}
694
695static void
696bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
697 struct ktermios *old)
698{
699 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
700 unsigned long flags;
701 unsigned int baud, quot;
0c44a86d 702 unsigned short val, ier, lcr = 0;
194de561
BW
703
704 switch (termios->c_cflag & CSIZE) {
705 case CS8:
706 lcr = WLS(8);
707 break;
708 case CS7:
709 lcr = WLS(7);
710 break;
711 case CS6:
712 lcr = WLS(6);
713 break;
714 case CS5:
715 lcr = WLS(5);
716 break;
717 default:
718 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 719 __func__);
194de561
BW
720 }
721
722 if (termios->c_cflag & CSTOPB)
723 lcr |= STB;
19aa6382 724 if (termios->c_cflag & PARENB)
194de561 725 lcr |= PEN;
19aa6382
MF
726 if (!(termios->c_cflag & PARODD))
727 lcr |= EPS;
728 if (termios->c_cflag & CMSPAR)
729 lcr |= STP;
194de561 730
2ac5ee47
MF
731 port->read_status_mask = OE;
732 if (termios->c_iflag & INPCK)
733 port->read_status_mask |= (FE | PE);
734 if (termios->c_iflag & (BRKINT | PARMRK))
735 port->read_status_mask |= BI;
194de561 736
2ac5ee47
MF
737 /*
738 * Characters to ignore
739 */
740 port->ignore_status_mask = 0;
741 if (termios->c_iflag & IGNPAR)
742 port->ignore_status_mask |= FE | PE;
743 if (termios->c_iflag & IGNBRK) {
744 port->ignore_status_mask |= BI;
745 /*
746 * If we're ignoring parity and break indicators,
747 * ignore overruns too (for real raw support).
748 */
749 if (termios->c_iflag & IGNPAR)
750 port->ignore_status_mask |= OE;
751 }
194de561
BW
752
753 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
754 quot = uart_get_divisor(port, baud);
755 spin_lock_irqsave(&uart->port.lock, flags);
756
8851c71e
MF
757 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
758
194de561
BW
759 /* Disable UART */
760 ier = UART_GET_IER(uart);
f4d640c9
RH
761#ifdef CONFIG_BF54x
762 UART_CLEAR_IER(uart, 0xF);
763#else
194de561 764 UART_PUT_IER(uart, 0);
f4d640c9 765#endif
194de561 766
f4d640c9 767#ifndef CONFIG_BF54x
194de561
BW
768 /* Set DLAB in LCR to Access DLL and DLH */
769 val = UART_GET_LCR(uart);
770 val |= DLAB;
771 UART_PUT_LCR(uart, val);
772 SSYNC();
f4d640c9 773#endif
194de561
BW
774
775 UART_PUT_DLL(uart, quot & 0xFF);
776 SSYNC();
777 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
778 SSYNC();
779
f4d640c9 780#ifndef CONFIG_BF54x
194de561
BW
781 /* Clear DLAB in LCR to Access THR RBR IER */
782 val = UART_GET_LCR(uart);
783 val &= ~DLAB;
784 UART_PUT_LCR(uart, val);
785 SSYNC();
f4d640c9 786#endif
194de561
BW
787
788 UART_PUT_LCR(uart, lcr);
789
790 /* Enable UART */
f4d640c9
RH
791#ifdef CONFIG_BF54x
792 UART_SET_IER(uart, ier);
793#else
194de561 794 UART_PUT_IER(uart, ier);
f4d640c9 795#endif
194de561
BW
796
797 val = UART_GET_GCTL(uart);
798 val |= UCEN;
799 UART_PUT_GCTL(uart, val);
800
801 spin_unlock_irqrestore(&uart->port.lock, flags);
802}
803
804static const char *bfin_serial_type(struct uart_port *port)
805{
806 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
807
808 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
809}
810
811/*
812 * Release the memory region(s) being used by 'port'.
813 */
814static void bfin_serial_release_port(struct uart_port *port)
815{
816}
817
818/*
819 * Request the memory region(s) being used by 'port'.
820 */
821static int bfin_serial_request_port(struct uart_port *port)
822{
823 return 0;
824}
825
826/*
827 * Configure/autoconfigure the port.
828 */
829static void bfin_serial_config_port(struct uart_port *port, int flags)
830{
831 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
832
833 if (flags & UART_CONFIG_TYPE &&
834 bfin_serial_request_port(&uart->port) == 0)
835 uart->port.type = PORT_BFIN;
836}
837
838/*
839 * Verify the new serial_struct (for TIOCSSERIAL).
840 * The only change we allow are to the flags and type, and
841 * even then only between PORT_BFIN and PORT_UNKNOWN
842 */
843static int
844bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
845{
846 return 0;
847}
848
7d01b475
GY
849/*
850 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
851 * In other cases, disable IrDA function.
852 */
853static void bfin_set_ldisc(struct tty_struct *tty)
854{
855 int line = tty->index;
856 unsigned short val;
857
858 if (line >= tty->driver->num)
859 return;
860
861 switch (tty->ldisc.num) {
862 case N_IRDA:
863 val = UART_GET_GCTL(&bfin_serial_ports[line]);
864 val |= (IREN | RPOLC);
865 UART_PUT_GCTL(&bfin_serial_ports[line], val);
866 break;
867 default:
868 val = UART_GET_GCTL(&bfin_serial_ports[line]);
869 val &= ~(IREN | RPOLC);
870 UART_PUT_GCTL(&bfin_serial_ports[line], val);
871 }
872}
873
194de561
BW
874static struct uart_ops bfin_serial_pops = {
875 .tx_empty = bfin_serial_tx_empty,
876 .set_mctrl = bfin_serial_set_mctrl,
877 .get_mctrl = bfin_serial_get_mctrl,
878 .stop_tx = bfin_serial_stop_tx,
879 .start_tx = bfin_serial_start_tx,
880 .stop_rx = bfin_serial_stop_rx,
881 .enable_ms = bfin_serial_enable_ms,
882 .break_ctl = bfin_serial_break_ctl,
883 .startup = bfin_serial_startup,
884 .shutdown = bfin_serial_shutdown,
885 .set_termios = bfin_serial_set_termios,
886 .type = bfin_serial_type,
887 .release_port = bfin_serial_release_port,
888 .request_port = bfin_serial_request_port,
889 .config_port = bfin_serial_config_port,
890 .verify_port = bfin_serial_verify_port,
891};
892
893static void __init bfin_serial_init_ports(void)
894{
895 static int first = 1;
896 int i;
897
898 if (!first)
899 return;
900 first = 0;
901
902 for (i = 0; i < nr_ports; i++) {
903 bfin_serial_ports[i].port.uartclk = get_sclk();
904 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
905 bfin_serial_ports[i].port.line = i;
906 bfin_serial_ports[i].port.iotype = UPIO_MEM;
907 bfin_serial_ports[i].port.membase =
908 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
909 bfin_serial_ports[i].port.mapbase =
910 bfin_serial_resource[i].uart_base_addr;
911 bfin_serial_ports[i].port.irq =
912 bfin_serial_resource[i].uart_irq;
913 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
914#ifdef CONFIG_SERIAL_BFIN_DMA
915 bfin_serial_ports[i].tx_done = 1;
916 bfin_serial_ports[i].tx_count = 0;
917 bfin_serial_ports[i].tx_dma_channel =
918 bfin_serial_resource[i].uart_tx_dma_channel;
919 bfin_serial_ports[i].rx_dma_channel =
920 bfin_serial_resource[i].uart_rx_dma_channel;
921 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561
BW
922#endif
923#ifdef CONFIG_SERIAL_BFIN_CTSRTS
4cb4f22b 924 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
194de561
BW
925 bfin_serial_ports[i].cts_pin =
926 bfin_serial_resource[i].uart_cts_pin;
927 bfin_serial_ports[i].rts_pin =
928 bfin_serial_resource[i].uart_rts_pin;
929#endif
930 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 931 }
f4d640c9 932
194de561
BW
933}
934
935#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
936/*
937 * If the port was already initialised (eg, by a boot loader),
938 * try to determine the current setup.
939 */
940static void __init
941bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
942 int *parity, int *bits)
943{
944 unsigned short status;
945
946 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
947 if (status == (ERBFI | ETBEI)) {
948 /* ok, the port was enabled */
949 unsigned short lcr, val;
950 unsigned short dlh, dll;
951
952 lcr = UART_GET_LCR(uart);
953
954 *parity = 'n';
955 if (lcr & PEN) {
956 if (lcr & EPS)
957 *parity = 'e';
958 else
959 *parity = 'o';
960 }
961 switch (lcr & 0x03) {
962 case 0: *bits = 5; break;
963 case 1: *bits = 6; break;
964 case 2: *bits = 7; break;
965 case 3: *bits = 8; break;
966 }
f4d640c9 967#ifndef CONFIG_BF54x
194de561
BW
968 /* Set DLAB in LCR to Access DLL and DLH */
969 val = UART_GET_LCR(uart);
970 val |= DLAB;
971 UART_PUT_LCR(uart, val);
f4d640c9 972#endif
194de561
BW
973
974 dll = UART_GET_DLL(uart);
975 dlh = UART_GET_DLH(uart);
976
f4d640c9 977#ifndef CONFIG_BF54x
194de561
BW
978 /* Clear DLAB in LCR to Access THR RBR IER */
979 val = UART_GET_LCR(uart);
980 val &= ~DLAB;
981 UART_PUT_LCR(uart, val);
f4d640c9 982#endif
194de561
BW
983
984 *baud = get_sclk() / (16*(dll | dlh << 8));
985 }
71cc2c21 986 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 987}
0ae53640
RG
988#endif
989
990#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
991static struct uart_driver bfin_serial_reg;
194de561
BW
992
993static int __init
994bfin_serial_console_setup(struct console *co, char *options)
995{
996 struct bfin_serial_port *uart;
0ae53640 997# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
998 int baud = 57600;
999 int bits = 8;
1000 int parity = 'n';
0ae53640 1001# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1002 int flow = 'r';
0ae53640 1003# else
194de561 1004 int flow = 'n';
0ae53640
RG
1005# endif
1006# endif
194de561
BW
1007
1008 /*
1009 * Check whether an invalid uart number has been specified, and
1010 * if so, search for the first available port that does have
1011 * console support.
1012 */
1013 if (co->index == -1 || co->index >= nr_ports)
1014 co->index = 0;
1015 uart = &bfin_serial_ports[co->index];
1016
0ae53640 1017# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
1018 if (options)
1019 uart_parse_options(options, &baud, &parity, &bits, &flow);
1020 else
1021 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1022
1023 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG
1024# else
1025 return 0;
1026# endif
1027}
1028#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1029 defined (CONFIG_EARLY_PRINTK) */
1030
1031#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1032static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1033{
1034 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1035 while (!(UART_GET_LSR(uart) & THRE))
1036 barrier();
1037 UART_PUT_CHAR(uart, ch);
1038 SSYNC();
1039}
1040
1041/*
1042 * Interrupts are disabled on entering
1043 */
1044static void
1045bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1046{
1047 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1048 int flags = 0;
1049
1050 spin_lock_irqsave(&uart->port.lock, flags);
1051 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1052 spin_unlock_irqrestore(&uart->port.lock, flags);
1053
194de561
BW
1054}
1055
194de561
BW
1056static struct console bfin_serial_console = {
1057 .name = BFIN_SERIAL_NAME,
1058 .write = bfin_serial_console_write,
1059 .device = uart_console_device,
1060 .setup = bfin_serial_console_setup,
1061 .flags = CON_PRINTBUFFER,
1062 .index = -1,
1063 .data = &bfin_serial_reg,
1064};
1065
1066static int __init bfin_serial_rs_console_init(void)
1067{
1068 bfin_serial_init_ports();
1069 register_console(&bfin_serial_console);
474f1a66
SZ
1070#ifdef CONFIG_KGDB_UART
1071 kgdb_entry_state = 0;
1072 init_kgdb_uart();
1073#endif
194de561
BW
1074 return 0;
1075}
1076console_initcall(bfin_serial_rs_console_init);
1077
1078#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1079#else
1080#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG
1081#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1082
1083
1084#ifdef CONFIG_EARLY_PRINTK
1085static __init void early_serial_putc(struct uart_port *port, int ch)
1086{
1087 unsigned timeout = 0xffff;
1088 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1089
1090 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1091 cpu_relax();
1092 UART_PUT_CHAR(uart, ch);
1093}
1094
1095static __init void early_serial_write(struct console *con, const char *s,
1096 unsigned int n)
1097{
1098 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1099 unsigned int i;
1100
1101 for (i = 0; i < n; i++, s++) {
1102 if (*s == '\n')
1103 early_serial_putc(&uart->port, '\r');
1104 early_serial_putc(&uart->port, *s);
1105 }
1106}
1107
1108static struct __init console bfin_early_serial_console = {
1109 .name = "early_BFuart",
1110 .write = early_serial_write,
1111 .device = uart_console_device,
1112 .flags = CON_PRINTBUFFER,
1113 .setup = bfin_serial_console_setup,
1114 .index = -1,
1115 .data = &bfin_serial_reg,
1116};
1117
1118struct console __init *bfin_earlyserial_init(unsigned int port,
1119 unsigned int cflag)
1120{
1121 struct bfin_serial_port *uart;
1122 struct ktermios t;
1123
1124 if (port == -1 || port >= nr_ports)
1125 port = 0;
1126 bfin_serial_init_ports();
1127 bfin_early_serial_console.index = port;
0ae53640
RG
1128 uart = &bfin_serial_ports[port];
1129 t.c_cflag = cflag;
1130 t.c_iflag = 0;
1131 t.c_oflag = 0;
1132 t.c_lflag = ICANON;
1133 t.c_line = port;
1134 bfin_serial_set_termios(&uart->port, &t, &t);
1135 return &bfin_early_serial_console;
1136}
1137
1138#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW
1139
1140static struct uart_driver bfin_serial_reg = {
1141 .owner = THIS_MODULE,
1142 .driver_name = "bfin-uart",
1143 .dev_name = BFIN_SERIAL_NAME,
1144 .major = BFIN_SERIAL_MAJOR,
1145 .minor = BFIN_SERIAL_MINOR,
2ade9729 1146 .nr = BFIN_UART_NR_PORTS,
194de561
BW
1147 .cons = BFIN_SERIAL_CONSOLE,
1148};
1149
1150static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1151{
1152 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1153
1154 if (uart)
1155 uart_suspend_port(&bfin_serial_reg, &uart->port);
1156
1157 return 0;
1158}
1159
1160static int bfin_serial_resume(struct platform_device *dev)
1161{
1162 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1163
1164 if (uart)
1165 uart_resume_port(&bfin_serial_reg, &uart->port);
1166
1167 return 0;
1168}
1169
1170static int bfin_serial_probe(struct platform_device *dev)
1171{
1172 struct resource *res = dev->resource;
1173 int i;
1174
1175 for (i = 0; i < dev->num_resources; i++, res++)
1176 if (res->flags & IORESOURCE_MEM)
1177 break;
1178
1179 if (i < dev->num_resources) {
1180 for (i = 0; i < nr_ports; i++, res++) {
1181 if (bfin_serial_ports[i].port.mapbase != res->start)
1182 continue;
1183 bfin_serial_ports[i].port.dev = &dev->dev;
1184 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1185 platform_set_drvdata(dev, &bfin_serial_ports[i]);
1186 }
1187 }
1188
1189 return 0;
1190}
1191
1192static int bfin_serial_remove(struct platform_device *pdev)
1193{
1194 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1195
1196
1197#ifdef CONFIG_SERIAL_BFIN_CTSRTS
1198 gpio_free(uart->cts_pin);
1199 gpio_free(uart->rts_pin);
1200#endif
1201
1202 platform_set_drvdata(pdev, NULL);
1203
1204 if (uart)
1205 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1206
1207 return 0;
1208}
1209
1210static struct platform_driver bfin_serial_driver = {
1211 .probe = bfin_serial_probe,
1212 .remove = bfin_serial_remove,
1213 .suspend = bfin_serial_suspend,
1214 .resume = bfin_serial_resume,
1215 .driver = {
1216 .name = "bfin-uart",
e169c139 1217 .owner = THIS_MODULE,
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1218 },
1219};
1220
1221static int __init bfin_serial_init(void)
1222{
1223 int ret;
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1224#ifdef CONFIG_KGDB_UART
1225 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
a359cca7 1226 struct ktermios t;
474f1a66 1227#endif
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1228
1229 pr_info("Serial: Blackfin serial driver\n");
1230
1231 bfin_serial_init_ports();
1232
1233 ret = uart_register_driver(&bfin_serial_reg);
1234 if (ret == 0) {
7d01b475 1235 bfin_serial_reg.tty_driver->set_ldisc = bfin_set_ldisc;
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1236 ret = platform_driver_register(&bfin_serial_driver);
1237 if (ret) {
1238 pr_debug("uart register failed\n");
1239 uart_unregister_driver(&bfin_serial_reg);
1240 }
1241 }
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1242#ifdef CONFIG_KGDB_UART
1243 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
a359cca7 1244 request_irq(uart->port.irq, bfin_serial_rx_int,
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1245 IRQF_DISABLED, "BFIN_UART_RX", uart);
1246 pr_info("Request irq for kgdb uart port\n");
a359cca7 1247 UART_SET_IER(uart, ERBFI);
d5148ffa 1248 SSYNC();
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1249 t.c_cflag = CS8|B57600;
1250 t.c_iflag = 0;
1251 t.c_oflag = 0;
1252 t.c_lflag = ICANON;
1253 t.c_line = CONFIG_KGDB_UART_PORT;
1254 bfin_serial_set_termios(&uart->port, &t, &t);
1255 }
1256#endif
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1257 return ret;
1258}
1259
1260static void __exit bfin_serial_exit(void)
1261{
1262 platform_driver_unregister(&bfin_serial_driver);
1263 uart_unregister_driver(&bfin_serial_reg);
1264}
1265
1266module_init(bfin_serial_init);
1267module_exit(bfin_serial_exit);
1268
1269MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1270MODULE_DESCRIPTION("Blackfin generic serial port driver");
1271MODULE_LICENSE("GPL");
1272MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1273MODULE_ALIAS("platform:bfin-uart");
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